JP5630294B2 - PLL circuit and semiconductor device - Google Patents

Description

  The present invention relates to a PLL circuit and a semiconductor device.

  A PLL (Phase Locked Loop) circuit is a circuit that synchronizes the phase of an output signal with the phase of a reference signal. In general, a PLL circuit includes a phase comparator, a charge pump circuit, a loop filter, a voltage controlled oscillator, and a frequency divider. The phase comparator compares the phase difference between the signal fed back from the voltage controlled oscillator via the frequency divider (frequency-divided signal obtained by frequency-dividing the output signal) and the reference signal. Then, the PLL circuit adjusts the frequency of the output signal of the voltage controlled oscillator based on the phase difference detected by the phase comparator. For example, the voltage controlled oscillator receives a control voltage adjusted based on the phase difference, and generates an output signal having a frequency corresponding to the control voltage. Thereby, the phase of the output signal is synchronized with the phase of the reference signal.

  Here, when the PLL circuit is not operating, the control voltage is maintained at, for example, 0 V (or the power supply voltage of the PLL circuit). When the PLL circuit operates, the control voltage gradually increases from 0 V to a voltage corresponding to the target frequency of the output signal. Since the control voltage at the start of the operation of the PLL circuit is 0 V (or the power supply voltage of the PLL circuit), it takes time until the oscillation frequency of the PLL circuit is stabilized.

  In order to shorten the time until the oscillation frequency of the PLL circuit is stabilized (hereinafter also referred to as a lock-up time), a PLL circuit that applies a predetermined initial voltage to a voltage controlled oscillator has been proposed (for example, Patent Document 1). . This type of PLL circuit has, for example, a voltage supply circuit connected to an input terminal (terminal that receives a control voltage) of a voltage controlled oscillator. For example, the voltage supply circuit is electrically connected to the input terminal of the voltage controlled oscillator at the start of the operation of the PLL circuit, and applies a predetermined initial voltage to the voltage controlled oscillator. Thereafter, the voltage supply circuit is electrically disconnected from the input terminal of the voltage controlled oscillator. Thereafter, the voltage controlled oscillator receives the control voltage adjusted based on the phase difference, and generates an output signal having a frequency corresponding to the control voltage.

  A PLL circuit that provides a voltage controlled oscillator with a voltage generated by a D / A converter has also been proposed (for example, Patent Document 2). For example, the D / A converter generates a voltage corresponding to the target frequency of the voltage controlled oscillator.

JP-A-6-61852 JP 2000-40959 A

  In the configuration in which the voltage supply circuit is connected to the input terminal of the voltage controlled oscillator, a current path from the voltage supply circuit to the input terminal of the voltage controlled oscillator is formed. For this reason, even if the voltage supply circuit and the input terminal of the voltage controlled oscillator are not electrically connected, there is a possibility that a leakage current of a transistor or the like in the voltage supply circuit flows to the input terminal of the voltage controlled oscillator. When the control voltage fluctuates due to a leakage current from the voltage supply circuit, the oscillation accuracy of the PLL circuit decreases. For this reason, the lock-up time becomes long. Note that the leakage current of transistors and the like increases with the miniaturization of the manufacturing process. For this reason, the leakage current flowing from the voltage supply circuit to the input terminal of the voltage controlled oscillator also increases. If the oscillation accuracy of the PLL circuit further decreases with an increase in leakage current, the PLL circuit may not function normally.

  An object of the present invention is to shorten the lock-up time while suppressing a decrease in oscillation accuracy of the PLL circuit.

In one embodiment of the present invention, a PLL circuit includes a voltage controlled oscillator that generates an output signal having a frequency corresponding to a control voltage, a frequency divider that divides the output signal, and a reference signal and the divided output signal. A phase comparator that detects a phase difference and generates a first detection signal and a second detection signal according to the phase difference, and a first switch and a second detection signal that are controlled to be turned on / off based on the first detection signal A charge pump circuit that adjusts the control voltage and a capacitive element that is charged and discharged by the charge pump circuit, and smoothes the output of the charge pump circuit to control voltage. And at least one of the first switch and the second switch is controlled to control charging / discharging of the capacitive element in an initial setting period in which an initial voltage is applied to the voltage controlled oscillator. Ri, the control voltage and a voltage supply unit for setting the initial voltage, the charge pump circuit discharges a first current source for charging the capacitor via a first switch, a capacitor through the second switch The voltage supply unit has at least one of a node between the first switch and the first current source and a node between the second switch and the second current source in the initial setting period. Then, an initial voltage is applied, and one of the first switch and the second switch disposed between the node to which the initial voltage is applied and the capacitive element is turned on, and the control voltage is set to the initial voltage .

  The lock-up time can be shortened while suppressing a decrease in the oscillation accuracy of the PLL circuit.

2 illustrates an example of a PLL circuit according to an embodiment. An example of the operation of the PLL circuit shown in FIG. 1 during the initial setting period is shown. 2 shows an example of the operation of the PLL circuit shown in FIG. 1 during a normal operation period. 3 shows an example of a PLL circuit in another embodiment. 5 shows an example of a PLL circuit when at least a part of each current source shown in FIG. 4 is composed of MOS transistors. 6 shows an example of the operation of the PLL circuit shown in FIG. 5 during the initial setting period. 6 shows an example of the operation of the PLL circuit shown in FIG. 5 during a normal operation period. 3 shows an example of a PLL circuit in another embodiment. 9 shows an example of the operation of the PLL circuit shown in FIG. 8 during the initial setting period. 3 shows an example of a PLL circuit in another embodiment. 11 shows an example of a PLL circuit that generates a voltage at the output terminal of the voltage supply unit shown in FIG. 10 by resistance division. 12 shows an example of the operation of the PLL circuit shown in FIG. 11 during the initial setting period. 12 shows an example of the operation of the PLL circuit shown in FIG. 11 during a normal operation period. 3 shows an example of a PLL circuit in another embodiment.

  Hereinafter, embodiments will be described with reference to the drawings.

  FIG. 1 shows an example of a PLL circuit 10 in one embodiment. The double circle in FIG. 1 indicates a control terminal that receives a signal for controlling on / off of the switch SW (SW1, SW2). A PLL (Phase Locked Loop) circuit 10 constitutes at least a part of a semiconductor device, for example. For example, the PLL circuit 10 includes a phase comparator PFD, a charge pump circuit CP1, a low-pass filter LPF, a voltage control oscillator VCO, a frequency divider DIV, and a voltage supply unit VS1. The PLL circuit 10 synchronizes the phase of the output signal of the frequency divider DIV (the signal obtained by dividing the output signal of the voltage control oscillator VCO) with the phase of the reference signal received by the phase comparator PFD.

  The phase comparator PFD detects the phase difference between the reference signal received at the input terminal CK and the feedback signal received at the input terminal FB. The feedback signal is, for example, an output signal of the frequency divider DIV or an output signal of the voltage control oscillator VCO. Then, the phase comparator PFD outputs a detection signal to the charge pump circuit CP1 via the output terminals UP and DN according to the phase difference between the reference signal and the feedback signal. The output terminals UP and DN are connected to, for example, the control terminal of the first switch SW1 and the control terminal of the second switch SW2 of the charge pump circuit CP1, respectively.

  For example, when the phase of the feedback signal is delayed with respect to the phase of the reference signal, the phase comparator PFD sends an up signal for increasing the frequency of the output signal of the voltage controlled oscillator VCO via the output terminal UP. Output to the charge pump circuit CP1. Further, for example, when the phase of the feedback signal is advanced with respect to the phase of the reference signal, the phase comparator PFD outputs a down signal for lowering the frequency of the output signal of the voltage control oscillator VCO to the output terminal DN. To the charge pump circuit CP1. That is, the phase comparator PFD detects a phase difference between the reference signal and the output signal of the frequency divider DIV, and generates an up signal and a down signal according to the phase difference.

  The charge pump circuit CP1 includes, for example, a first current source IS10, a first switch SW1, a second switch SW2, and a second current source IS20 connected in series between the internal power supply line and the ground line. The connection node N1 between the first switch SW1 and the second switch SW2 is connected to, for example, the input terminal VCNT of the voltage controlled oscillator VCO, the capacitive element C1 of the low-pass filter LPF, and the resistor R1. For example, the charge pump circuit CP1 adjusts the control voltage of the voltage control oscillator VCO (the voltage of the input terminal VCNT) by turning on one of the first switch SW1 and the second switch SW2.

  The first switch SW1 is controlled to be turned on / off based on, for example, an up signal received at a control terminal (double circle of the switch SW1 in the figure). The second switch SW2 is controlled to be turned on / off based on, for example, a down signal received at a control terminal (double circle of the switch SW2 in the figure). When the first switch SW1 is turned on, the first current source IS10 charges the capacitive element C1 of the low-pass filter LPF via the first switch SW1. The second current source IS20 discharges the capacitive element C1 of the low-pass filter LPF via the first switch SW1 when the second switch SW2 is turned on.

  The low-pass filter LPF has, for example, a capacitive element C1 and a resistor R1 connected in parallel between the node N1 of the charge pump circuit CP1 and the ground line. For example, the low-pass filter LPF smoothes the output of the charge pump circuit CP1 and generates a control voltage. The control voltage is input to the input terminal VCNT of the voltage control oscillator VCO. That is, the low-pass filter LPF smoothes the output of the charge pump circuit CP1 and generates a control voltage for the voltage controlled oscillator VCO.

  The voltage control oscillator VCO generates an output signal having a frequency corresponding to the control voltage received at the input terminal VCNT, and outputs the generated output signal from the output terminal SOUT. For example, the output signal of the voltage control oscillator VCO is output to the outside of the PLL circuit 10. The output signal of the voltage controlled oscillator VCO is input to the input terminal FB of the phase comparator PFD via the frequency divider DIV. Thereby, the output signal of the voltage controlled oscillator VCO is fed back to the phase comparator PFD via the frequency divider DIV.

  The frequency divider DIV is arranged between the voltage control oscillator VCO and the phase comparator PFD. For example, the frequency divider DIV divides the signal received at the input terminal CIN at a frequency dividing ratio indicated by the signal received at the input terminal DINF. Then, the frequency divider DIV outputs the frequency-divided signal from the output terminal COUT. For example, the input terminal CIN of the frequency divider DIV is connected to the output terminal SOUT of the voltage controlled oscillator VCO, and the output terminal COUT of the frequency divider DIV is connected to the input terminal FB of the phase comparator PFD.

  That is, the frequency divider DIV divides the output signal of the voltage control oscillator VCO by a predetermined frequency dividing ratio, and outputs the divided signal to the phase comparator PFD. As a result, the PLL circuit 10 allows the phase of the output signal even when the frequency of the output signal (the output signal of the voltage controlled oscillator VCO) is higher than the frequency of the reference signal (the signal received at the input terminal CK of the phase comparator PFD). Can be synchronized with the phase of the reference signal.

  For example, when the detection signal of the phase comparator PFD is invalid, the voltage supply unit VS1 controls on / off of the first switch SW1 and the second switch SW2. For example, the output terminal EN1 of the voltage supply unit VS1 is connected to the control terminal of the first switch SW1. For example, the output terminal EN2 of the voltage supply unit VS1 is connected to the control terminal of the second switch SW2.

  Here, the period in which the detection signal of the phase comparator PFD is invalid is, for example, a period in which the PLL circuit 10 is off. Alternatively, when the oscillation frequency of the PLL circuit 10 is changed, the detection signal of the phase comparator PFD may be invalidated for a predetermined time. For example, during a period when the detection signal of the phase comparator PFD is invalid, the voltage supply unit VS1 turns on the first switch SW1 and the second switch SW2, and gives an initial voltage to the voltage control oscillator VCO. That is, the voltage supply unit VS1 turns on the first switch SW1 and the second switch SW2 during an initial setting period in which an initial voltage is applied to the voltage control oscillator VCO.

  The configuration of the PLL circuit 10 is not limited to this example. For example, the PLL circuit 10 may include a selector that switches between the output signal of the phase comparator PFD and the output signal of the voltage supply unit VS1 and outputs the signal to the charge pump circuit CP1 (more specifically, the switches SW1 and SW2). Good. Further, the frequency division ratio of the frequency divider DIV may be fixed. For example, the frequency divider DIV may be configured without the input terminal DINF. Alternatively, the PLL circuit 10 may be configured without the frequency divider DIV. For example, the output signal of the voltage control oscillator VCO may be directly input to the input terminal FB of the phase comparator PFD. As a result, the output signal of the voltage controlled oscillator VCO is fed back to the phase comparator PFD without going through the frequency divider DIV.

  FIG. 2 shows an example of the operation during the initial setting period of the PLL circuit 10 shown in FIG. That is, FIG. 2 shows an example of the operation of the PLL circuit 10 when setting the initial voltage to the voltage controlled oscillator VCO. The meaning of the double circle in FIG. 2 is the same as that in FIG. The broken line in FIG. 2 indicates that the detection signal of the phase comparator PFD is invalid. For example, in the initial setting period, the output terminals UP and DN of the phase comparator PFD are set to a high impedance state.

  During the initial setting period, the voltage supply unit VS1 outputs a control signal for turning on the first switch SW1 from the output terminal EN1 to the control terminal of the first switch SW1, and also outputs a control signal for turning on the second switch SW2. To the control terminal of the second switch SW2. That is, the voltage supply unit VS1 turns on the first switch SW1 and the second switch SW2 during the initial setting period, and controls charging / discharging of the capacitive element C1.

  For example, when the voltage of the capacitive element C1 is lower than the voltage of the node N1 determined by the characteristics of each element of the charge pump circuit CP1, the current I10 flows from the first current source IS10 toward the capacitive element C1. Thereby, the capacitive element C1 is charged and the voltage of the capacitive element C1 rises. Alternatively, when the voltage of the capacitive element C1 is higher than the voltage of the node N1 determined by the characteristics of each element of the charge pump circuit CP1, a current I20 flows from the capacitive element C1 toward the second current source IS20. As a result, the capacitive element C1 is discharged, and the voltage of the capacitive element C1 decreases.

  Therefore, the voltage of the input terminal VCNT of the voltage controlled oscillator VCO (the voltage of the capacitive element C1) is the first current source IS10, the first switch SW1, the second switch connected in series between the internal power supply line and the ground line. It is stabilized at the voltage of the node N1 determined by the characteristics of the switch SW2 and the second current source IS20. Thereby, the initial voltage of the input terminal VCNT of the voltage controlled oscillator VCO is set to, for example, an intermediate voltage between the power supply voltage and the ground voltage.

  Thus, for example, when the PLL circuit is turned off, the voltage supply unit VS1 converts the voltage of the input terminal VCNT of the voltage controlled oscillator VCO to a voltage intermediate between the power supply voltage and the ground voltage (charge pump circuit CP1). Node N1 voltage determined by the characteristics of each element. Thereby, in this embodiment, the time until the voltage of the input terminal VCNT reaches the voltage corresponding to the target frequency can be shortened as compared with the configuration in which the voltage of the input terminal VCNT is maintained at the ground voltage or the power supply voltage. .

  As a result, in this embodiment, the time until the oscillation frequency of the PLL circuit 10 is stabilized (hereinafter also referred to as lock-up time) can be shortened. For example, during a period in which the PLL circuit 10 is on (a normal operation period after the initial setting period), the output terminals EN1 and EN2 of the voltage supply unit VS1 are set in a high impedance state.

  Here, for example, when it is not necessary to apply the initial voltage to the voltage controlled oscillator VCO, the voltage supply unit VS1 may turn off the first switch SW1 and the second switch SW2 during the off period of the PLL circuit 10. Further, the first current source IS10 and the second current source IS20 may be turned off during the off period of the PLL circuit 10, for example, when it is not necessary to apply an initial voltage to the voltage controlled oscillator VCO.

  FIG. 3 shows an example of the operation during the normal operation period of the PLL circuit 10 shown in FIG. FIG. 3 shows the operation of the PLL circuit 10 when the phase of the output signal of the frequency divider DIV (the signal obtained by dividing the output signal of the voltage control oscillator VCO) is advanced with respect to the phase of the reference signal. ing. The meaning of the double circle in FIG. 3 is the same as that in FIG. The broken lines in FIG. 3 indicate that the signals at the output terminals EN1 and EN2 of the voltage supply unit VS1 are invalid. For example, in the normal operation period after the initial setting period, the output terminals EN1 and EN2 of the voltage supply unit VS1 are set in a high impedance state.

  The phase comparator PFD detects in accordance with the phase difference between the reference signal received at the input terminal CK and the feedback signal received at the input terminal FB (the output signal of the frequency divider DIV or the output signal of the voltage control oscillator VCO). The signal is output to the charge pump circuit CP1 via the output terminals UP and DN.

  For example, when the phase of the feedback signal is advanced with respect to the phase of the reference signal, the phase comparator PFD outputs a down signal from the output terminal DN to the control terminal of the second switch SW2. The second switch SW2 is turned on in response to the down signal received at the control terminal. The first switch SW1 is off because the up signal for turning on the first switch SW1 is not output from the phase comparator PFD.

  For this reason, a current flows from the capacitive element C1 of the low-pass filter LPF toward the second current source IS20 of the charge pump circuit CP1, and the capacitive element C1 is discharged. Due to the discharge of the capacitive element C1, the voltage of the input terminal VCNT of the voltage controlled oscillator VCO decreases. As a result, the frequency of the output signal of the voltage controlled oscillator VCO is lowered. When the phase of the feedback signal is delayed with respect to the phase of the reference signal, the first switch SW1 is turned on and the second switch SW2 is turned off. Thereby, the capacitive element C1 is charged, and the voltage of the input terminal VCNT of the voltage controlled oscillator VCO increases. As a result, the frequency of the output signal of the voltage controlled oscillator VCO increases.

  As described above, the PLL circuit 10 controls the control voltage of the voltage control oscillator VCO according to the phase difference between the reference signal and the output signal of the frequency divider DIV (the signal obtained by dividing the output signal of the voltage control oscillator VCO). To control. Thereby, the phase of the output signal of the voltage controlled oscillator VCO is synchronized with the phase of the reference signal.

  Here, the leakage current generated in the voltage supply unit VS1 is extremely smaller than the currents of the current sources IS10 and IS20 of the charge pump circuit CP1. For this reason, during the normal operation period, the leakage current generated in the voltage supply unit VS1 is buried in the currents of the current sources IS10 and IS20 of the charge pump circuit CP1, and hardly affects the control voltage of the voltage controlled oscillator VCO. . Therefore, in this embodiment, the lockup time can be shortened without reducing the oscillation accuracy of the PLL circuit 10.

  Further, in this embodiment, the voltage supply unit VS1 is not connected to the input terminal VCNT of the voltage controlled oscillator VCO. That is, in this embodiment, the control voltage of the voltage control oscillator VCO can be set to the initial voltage without adding a transistor connected to the input terminal VCNT of the voltage control oscillator VCO. For this reason, in this embodiment, the leakage current flowing through the input terminal VCNT of the voltage controlled oscillator VCO can be reduced as compared with the configuration in which the voltage supply circuit is connected to the input terminal VCNT of the voltage controlled oscillator VCO.

  Therefore, in this embodiment, the control voltage of the voltage control transmitter VCO can be set to the initial voltage while suppressing the leakage current flowing through the input terminal VCNT of the voltage control transmitter VCO. That is, in this embodiment, the lock-up time can be shortened while suppressing the leakage current flowing through the input terminal VCNT of the voltage controlled oscillator VCO.

  As described above, in this embodiment, the voltage supply unit VS1 of the PLL circuit 10 charges and discharges the capacitive element C1 of the low-pass filter LPF via the switches SW1 and SW2 of the charge pump circuit CP1 during the initial setting period. For this reason, in this embodiment, compared with the configuration in which the voltage supply circuit is connected to the input terminal VCNT of the voltage control oscillator VCO, the influence of the leakage current of the voltage supply unit VS1 on the control voltage of the voltage control oscillator VCO is affected. Can be small. Therefore, in this embodiment, it is possible to shorten the lockup time while suppressing a decrease in the oscillation accuracy of the PLL circuit 10.

  FIG. 4 shows an example of the PLL circuit 10 in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The double circles of the current source IS (IS12, IS22) in FIG. 4 indicate control terminals that receive signals for controlling the current supply capability of the current source IS. Further, the meaning of the double circle of the switch SW (SW1, SW2) in FIG. 4 is the same as that in FIG. In the PLL circuit 10 of this embodiment, a charge pump circuit CP2 and a voltage supply unit VS2 are provided instead of the charge pump circuit CP1 and the voltage supply unit VS1 shown in FIG. Other configurations of the PLL circuit 10 are the same as those in the above-described embodiment.

  The charge pump circuit CP2 has a first current source IS12 and a second current source IS22 instead of the first current source IS10 and the second current source IS20 shown in FIG. The other configuration of the charge pump circuit CP2 is the same as that of the charge pump circuit CP1. The first current source IS12 and the second current source IS22 are controlled in current supply capability and on / off by, for example, voltages received at the respective control terminals.

  The voltage supply unit VS2 is the same as the voltage supply unit VS1 except that the current supply capability of the first current source IS12 and the second current source IS22 is controlled. For example, the output terminal ICNT1 of the voltage supply unit VS2 is connected to the control terminal of the first current source IS12. For example, the output terminal ICNT2 of the voltage supply unit VS2 is connected to the control terminal of the second current source IS22.

  For example, the voltage supply unit VS2 controls the voltage at the control terminal of the first current source IS12 and the voltage at the control terminal of the second current source IS22 during the initial setting period. Thereby, each current supply capability of 1st current source IS12 and 2nd current source IS22 is adjusted, and the voltage of node N1 is adjusted. That is, the voltage supply unit VS2 controls the current supply capability of each of the first current source IS12 and the second current source IS22 during the initial setting period, so that an arbitrary initial voltage is applied to the input terminal VCNT of the voltage control oscillator VCO. give.

  Thereby, in this embodiment, for example, the voltage corresponding to the target frequency of the voltage controlled oscillator VCO can be set as the initial voltage of the voltage controlled oscillator VCO. Therefore, in this embodiment, the lockup time can be further shortened. In this embodiment, power consumption in the initial setting period can be reduced by reducing the current supply capabilities of the first current source IS12 and the second current source IS22 in the initial setting period.

  The configuration of the PLL circuit 10 is not limited to this example. For example, the PLL circuit 10 may be configured without the frequency divider DIV. That is, the output signal of the voltage controlled oscillator VCO may be fed back to the phase comparator PFD without going through the frequency divider DIV. Alternatively, the frequency division ratio of the frequency divider DIV may be fixed.

  FIG. 5 shows an example of the PLL circuit 10 when at least a part of each of the current sources IS12 and IS22 shown in FIG. 4 is composed of MOS transistors. The meaning of the double circle in FIG. 5 is the same as that in FIG.

  The first current source IS12 includes, for example, a pMOS transistor MI1. The transistor MI1 has a source connected to the internal power supply line, a drain connected to the first switch SW1, and a gate connected to the control terminal. That is, the transistor MI1 receives the voltage output from the output terminal ICNT1 of the voltage supply unit VS2 at the gate.

  The second current source IS22 includes, for example, an nMOS transistor MI2. The transistor MI2 has a source connected to the ground line, a drain connected to the second switch SW2, and a gate connected to the control terminal. That is, the transistor MI2 receives the voltage output from the output terminal ICNT2 of the voltage supply unit VS2 at the gate.

  The on-resistances of the transistors MI1 and MI2 change according to the voltage received at the gate. Therefore, the voltage supply unit VS2 adjusts the on-resistances of the transistors MI1 and MI2 by controlling the voltage applied to the gate of the transistor MI1 and the voltage applied to the gate of the transistor MI2, respectively, during the initial setting period. Thereby, the voltage supply unit VS2 adjusts the voltage of the node N1. That is, the voltage supply unit VS2 can set the control voltage of the voltage control oscillator VCO to an arbitrary initial voltage by applying voltages to the control terminal of the first current source IS12 and the control terminal of the second current source IS22, respectively.

  Note that the configuration of the current source IS (IS12, IS22) is not limited to this example. For example, each current source IS may have a plurality of MOS transistors. Furthermore, each current source IS may have both a pMOS transistor and an nMOS transistor. Alternatively, the first current source IS12 may include an nMOS transistor instead of the pMOS transistor MI1, for example.

  FIG. 6 shows an example of the operation during the initial setting period of the PLL circuit 10 shown in FIG. The meaning of the double circle in FIG. 6 is the same as that in FIG. The meaning of the broken line in FIG. 6 is the same as that in FIG. For example, in the initial setting period, the output terminals UP and DN of the phase comparator PFD are set to a high impedance state.

  The operation of the PLL circuit 10 in the initial setting period is the same as the operation of the PLL circuit 10 described in FIG. 2 except that the voltage supply unit VS2 controls the voltages of the gates of the transistors MI1 and MI2. For example, the voltage supply unit VS2 turns on the first switch SW1 and the second switch SW2 during the initial setting period, and supplies a voltage to the control terminal of the first current source IS12 and the control terminal of the second current source IS22, respectively. Thereby, the on-resistances of the transistors MI1, MI2 of the transistor MI1, the first switch SW1, the second switch SW2, and the transistor MI2 connected in series between the internal power supply line and the ground line are adjusted. As a result, the voltage of the node N1 is adjusted, and the voltage of the input terminal VCNT of the voltage controlled oscillator VCO is adjusted.

  FIG. 7 shows an example of the operation during the normal operation period of the PLL circuit 10 shown in FIG. FIG. 7 shows the operation of the PLL circuit 10 when the phase of the output signal of the frequency divider DIV (the signal obtained by dividing the output signal of the voltage control oscillator VCO) is advanced with respect to the phase of the reference signal. ing. The meaning of the double circle in FIG. 7 is the same as that in FIG. The meaning of the broken line in FIG. 7 is the same as that in FIG. For example, in the normal operation period, the output terminals EN1 and EN2 of the voltage supply unit VS2 are set to a high impedance state.

  The operation of the PLL circuit 10 during the normal operation period is the same as the operation of the PLL circuit 10 described in FIG. 3 except that the voltage supply unit VS2 applies voltages to the gates of the transistors MI1 and MI2. For example, in the normal operation period, the voltage supply unit VS2 applies a voltage that makes the current supply capability of the first current source IS12 a predetermined capability to the control terminal of the first current source IS12, and the current of the second current source IS22. A voltage that makes the supply capacity a predetermined capacity is applied to the control terminal of the second current source IS22. Thereby, during the normal operation period, the PLL circuit 10 operates in the same manner as the operation described in FIG.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Furthermore, in this embodiment, by controlling the voltage of the control terminal of the first current source IS12 and the voltage of the control terminal of the second current source IS22, the control voltage of the voltage control oscillator VCO is set to an arbitrary initial voltage (for example, , The voltage corresponding to the target frequency of the voltage controlled oscillator VCO). Thereby, in this embodiment, the lock-up time can be further shortened. In this embodiment, power consumption in the initial setting period can be reduced by reducing the current supply capabilities of the first current source IS12 and the second current source IS22 in the initial setting period.

  FIG. 8 shows an example of the PLL circuit 10 according to another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The meaning of the double circle in FIG. 8 is the same as that in FIG. The PLL circuit 10 of this embodiment has a voltage supply unit VS3 instead of the voltage supply unit VS1 shown in FIG. Other configurations of the PLL circuit 10 are the same as those in the embodiment described with reference to FIGS.

  In this embodiment, the first switch SW1 and the second switch SW2 of the charge pump circuit CP1 have, for example, a pMOS transistor MS1 and an nMOS transistor MS2, respectively. The transistor MS1 has a source connected to the first current source IS10, a drain connected to the drain of the transistor MS2, and a gate connected to the control terminal. The transistor MS2 has a source connected to the second current source IS20, a drain connected to the drain of the transistor MS1, and a gate connected to the control terminal. That is, the drains of the transistors MS1 and MS2 are connected to the node N1.

  The configuration of the switch SW (SW1, SW2) is not limited to this example. For example, each switch SW may have a plurality of MOS transistors. Furthermore, each switch SW may have both a pMOS transistor and an nMOS transistor. Alternatively, the first switch SW1 may include, for example, an nMOS transistor instead of the pMOS transistor MS1. Each switch SW may be configured without including a MOS transistor.

  The voltage supply unit VS3 is the same as the voltage supply unit VS1 except that the on-resistance of the first switch SW1 and the on-resistance of the second switch SW2 are respectively controlled during the initial setting period. For example, the output terminal SCNT1 of the voltage supply unit VS3 is connected to the control terminal of the first switch SW1. For example, the output terminal SCNT2 of the voltage supply unit VS3 is connected to the control terminal of the second switch SW2.

  For example, the voltage supply unit VS3 controls the voltage of the control terminal of the first switch SW1 and the voltage of the control terminal of the second switch SW2 during the initial setting period. As a result, the on-resistance of the first switch SW1 and the on-resistance of the second switch SW2 are adjusted, and the voltage of the node N1 is adjusted.

  That is, the voltage supply unit VS3 supplies the adjustment voltage to the control terminal of the first switch SW1 and the control terminal of the second switch SW2 during the initial setting period, thereby reducing the on-resistance of the first switch SW1 and the second switch SW2. Each is controlled, and the control voltage of the voltage controlled oscillator VCO is set to the initial voltage.

  The configuration of the PLL circuit 10 is not limited to this example. For example, the PLL circuit 10 may be configured without the frequency divider DIV. That is, the output signal of the voltage controlled oscillator VCO may be fed back to the phase comparator PFD without going through the frequency divider DIV. Alternatively, the frequency division ratio of the frequency divider DIV may be fixed.

  FIG. 9 shows an example of the operation during the initial setting period of the PLL circuit 10 shown in FIG. The meaning of the double circle in FIG. 9 is the same as that in FIG. The meaning of the broken line in FIG. 9 is the same as that in FIG. For example, in the initial setting period, the output terminals UP and DN of the phase comparator PFD are set to a high impedance state.

  The operation of the PLL circuit 10 in the initial setting period is the same as the operation of the PLL circuit 10 described in FIG. 2 except that the voltage supply unit VS3 controls the voltages of the gates of the transistors MS1 and MS2. For example, the voltage supply unit VS3 supplies adjustment voltages to the gates of the transistors MS1 and MS2, respectively, during the initial setting period. That is, the transistor MS1 receives the adjustment voltage output from the output terminal SCNT1 of the voltage supply unit VS3 at the gate, and the transistor MS2 receives the adjustment voltage output from the output terminal SCNT2 of the voltage supply unit VS3 at the gate.

  The on-resistance of the transistors MS1 and MS2 changes according to the voltage received at the gate. Therefore, the on-resistance of the transistors MS1 and MS2 of the first current source IS10, the transistor MS1, the transistor MS2, and the second current source IS20 connected in series between the internal power supply line and the ground line is controlled by the voltage supply unit VS3. Each is adjusted. As a result, the voltage of the node N1 is adjusted, and the voltage of the input terminal VCNT of the voltage controlled oscillator VCO is adjusted.

  That is, the voltage supply unit VS3 arbitrarily controls the input terminal VCNT of the voltage controlled oscillator VCO by controlling the voltage of the control terminal of the first switch SW1 and the voltage of the control terminal of the second switch SW2 during the initial setting period. Gives the initial voltage. Thereby, in this embodiment, for example, the voltage corresponding to the target frequency of the voltage controlled oscillator VCO can be set as the initial voltage of the voltage controlled oscillator VCO. Therefore, in this embodiment, the lockup time can be further shortened.

  The operation of the PLL circuit 10 during the normal operation period is the same as the operation of the PLL circuit 10 described with reference to FIG. For example, in the normal operation period, the output terminals SCNT1 and SCNT2 of the voltage supply unit VS3 are set in a high impedance state. As a result, the phase comparator PFD causes the first switch SW1 and the second switch according to the phase difference between the reference signal and the output signal of the frequency divider DIV (the signal obtained by dividing the output signal of the voltage control oscillator VCO). SW2 ON / OFF can be controlled.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Furthermore, in this embodiment, by controlling the voltage of the control terminal of the first switch SW1 and the voltage of the control terminal of the second switch SW2, respectively, the control voltage of the voltage control oscillator VCO is set to an arbitrary initial voltage (for example, voltage Voltage corresponding to the target frequency of the control oscillator VCO). Further, in this embodiment, by increasing the on-resistance of the first switch SW1 and the second switch SW2 in the initial setting period, the current in the initial setting period flowing in the first switch SW1 and the second switch SW2 is reduced. it can. As a result, in this embodiment, power consumption during the initial setting period can be reduced.

  FIG. 10 shows an example of the PLL circuit 10 in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The meaning of the double circle in FIG. 10 is the same as that in FIG. The PLL circuit 10 of this embodiment has a voltage supply unit VS4 instead of the voltage supply unit VS2 shown in FIG. Other configurations of the PLL circuit 10 are the same as those in the embodiment described with reference to FIGS.

  For example, the voltage supply unit VS4 supplies an initial voltage to the voltage control oscillator VCO using the voltage output from the output terminal VR during the initial setting period. For example, the output terminal VR of the voltage supply unit VS4 is connected to a connection node N2 between the first current source IS12 and the first switch SW1. The output terminals EN1 and EN2 of the voltage supply unit VS4 are connected to the control terminal of the first switch SW1 and the control terminal of the second switch SW2, respectively. The output terminals EN3 and EN4 of the voltage supply unit VS4 are connected to the control terminal of the first current source IS12 and the control terminal of the second current source IS22, respectively.

  For example, in the initial setting period, the voltage supply unit VS4 turns on the first switch SW1, turns off the second switch SW2, and turns off the first current source IS12 and the second current source IS22. As a result, the voltage at the output terminal VR of the voltage supply unit VS4 is applied to the input terminal VCNT of the voltage controlled oscillator VCO.

  The output terminal VR may be connected to the connection node N3 between the second current source IS22 and the second switch SW2 without being connected to the node N2 of the charge pump circuit CP2. In this case, the voltage supply unit VS4 turns off the first switch SW1, turns on the second switch SW2, and turns off the first current source IS12 and the second current source IS22 during the initial setting period. That is, the voltage supply unit VS4 is arranged between the node connected to the output terminal VR and the capacitive element C1 of the low-pass filter LPF among the first switch SW1 and the second switch SW2 during the initial setting period. Turn on the switch.

  Here, for example, the voltage of the output terminal VR is generated by resistance division as shown in FIG. Note that the voltage of the output terminal VR may be given by a method other than resistance division (for example, a voltage generated by a band gap circuit). In this embodiment, the first current source IS12 and the second current source IS22 may be configured to be turned on / off by the voltages of the output terminals EN3 and EN4 of the voltage supply unit VS4. That is, the current supply capability of the first current source IS12 and the second current source IS22 may not be controlled by the voltages of the output terminals EN3 and EN4 of the voltage supply unit VS4.

  The configuration of the PLL circuit 10 is not limited to this example. For example, the PLL circuit 10 may be configured without the frequency divider DIV. That is, the output signal of the voltage controlled oscillator VCO may be fed back to the phase comparator PFD without going through the frequency divider DIV. Alternatively, the frequency division ratio of the frequency divider DIV may be fixed.

  FIG. 11 shows an example of the PLL circuit 10 that generates the voltage of the output terminal VR of the voltage supply unit VS4 shown in FIG. 10 by resistance division. The meaning of the double circle in FIG. 11 is the same as that in FIG.

  The voltage supply unit VS4 includes a voltage generation unit VG1 that supplies a voltage to the output terminal VR. The voltage generator VG1 includes, for example, a resistor R10, switches SW10 and SW20, and a resistor R20 that are connected in series between the internal power supply line and the ground line. In FIG. 11, in order to make the drawing easier to see, a description of a control terminal that receives a signal for controlling on / off of the switches SW10 and SW20 is omitted.

  The output terminal VR is connected to a connection node between the switch SW10 and the switch SW20. Therefore, for example, when the switches SW10 and SW20 are turned on, the voltage of the output terminal VR is set to a voltage divided by the on-resistance of the resistor R10 and the switch SW10 and the on-resistance of the switch SW20 and the resistor R10. For example, when the on resistances of the switches SW10 and SW20 are small, the voltage at the output terminal VR is set to a voltage divided by the resistors R10 and R20.

  The configuration of the voltage supply unit VS4 is not limited to this example. For example, the terminal that is not connected to the resistor R20 of the switch SW20 is not connected to the node N2 of the charge pump circuit CP2, but may be connected to the connection node N3 between the second current source IS22 and the second switch SW2. Good. In this case, the voltage supply unit VS4 turns on the first switch SW1 and the second switch SW2 and turns off the first current source IS12 and the second current source IS22 during the initial setting period. For example, the voltage generation unit VG1 may be provided outside the voltage supply unit VS4.

  FIG. 12 shows an example of the operation during the initial setting period of the PLL circuit 10 shown in FIG. The meaning of the double circle in FIG. 12 is the same as in FIG. The meaning of the broken line in FIG. 12 is the same as that in FIG. For example, in the initial setting period, the output terminals UP and DN of the phase comparator PFD are set to a high impedance state. Also, the broken line current sources IS12 and IS22 in FIG. 12 indicate that the current sources IS12 and IS22 are off.

  During the initial setting period, the voltage supply unit VS4 turns on the switches SW10 and SW20 of the voltage generation unit VG1, and outputs the voltage divided by the resistors R10 and R20 to the output terminal VR. In the initial setting period, the voltage supply unit VS4 turns on the first switch SW1, turns off the second switch SW2, and turns off the first current source IS12 and the second current source IS22. As a result, the voltage divided by the resistors R10 and R20 (the voltage at the output terminal VR) is applied to the input terminal VCNT of the voltage controlled oscillator VCO.

  For example, when the voltage of the capacitive element C1 is lower than the voltage of the output terminal VR, a current I30 flows from the output terminal VR toward the capacitive element C1. Thereby, the capacitive element C1 is charged and the voltage of the capacitive element C1 rises. Alternatively, when the voltage of the capacitive element C1 is higher than the voltage of the output terminal VR, a current I30 flows from the capacitive element C1 toward the output terminal VR. As a result, the capacitive element C1 is discharged, and the voltage of the capacitive element C1 decreases.

  That is, the voltage supply unit VS4 turns on at least one of the first switch SW1 and the second switch SW2 during the initial setting period, and controls charging / discharging of the capacitive element C1. Due to charging / discharging of the capacitive element C1, the voltage of the input terminal VCNT of the voltage controlled oscillator VCO (the voltage of the capacitive element C1) is stabilized at the voltage of the output terminal VR.

  In this way, the voltage supply unit VS4 sets the control voltage of the voltage control oscillator VCO to the voltage (initial voltage) of the output terminal VR during the initial setting period. Therefore, also in the PLL circuit 10 of this embodiment, the lockup time can be shortened. For example, in the configuration shown in FIG. 12, by increasing the resistances R10 and R20, the current of the voltage generation unit VG1 can be reduced, and the power consumption can be reduced. For example, in the normal operation period, the output terminals EN1, EN2, and VR of the voltage supply unit VS4 are set in a high impedance state.

  FIG. 13 shows an example of the operation during the normal operation period of the PLL circuit 10 shown in FIG. FIG. 13 shows the operation of the PLL circuit 10 when the phase of the output signal of the divider DIV (the signal obtained by dividing the output signal of the voltage control oscillator VCO) is advanced with respect to the phase of the reference signal. ing. The meaning of the double circle in FIG. 13 is the same as that in FIG. The broken lines in FIG. 13 indicate that the signals at the output terminals EN1, EN2, and VR of the voltage supply unit VS4 are invalid. For example, in the normal operation period, the output terminals EN1, EN2, and VR of the voltage supply unit VS4 are set in a high impedance state.

  The operation of the PLL circuit 10 in the normal operation period is the same as the operation of the PLL circuit 10 described in FIG. 7 except that the output terminal VR of the voltage supply unit VS4 is set to a high impedance state. For example, in the normal operation period, the voltage supply unit VS4 turns off the switches SW10 and SW20 of the voltage generation unit VG1 and sets the output terminal VR to a high impedance state. Thereby, in the normal operation period, the PLL circuit 10 operates in the same manner as the operation described with reference to FIGS. In this embodiment, since the output terminal VR of the voltage supply unit VS4 is connected to the input terminal VCNT of the voltage control transmitter VCO via the first switch SW1, the leakage current of the voltage supply unit VS4 is voltage controlled transmission. The influence on the control voltage of the VCO can be reduced.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, in this embodiment, the voltage generated by the voltage generator VG1 is set as the initial voltage of the voltage controlled oscillator VCO. Thereby, in this embodiment, the initial voltage of the voltage controlled oscillator VCO can be easily generated regardless of the characteristics of each element of the charge pump circuit CP2.

  FIG. 14 shows an example of the PLL circuit 10 in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The meaning of the double circle in FIG. 14 is the same as that in FIG. In the PLL circuit 10 of this embodiment, a selection unit SEL is provided in the PLL circuit 10 shown in FIG. 10, and a voltage supply unit VS5 is provided instead of the voltage supply unit VS4. Other configurations of the PLL circuit 10 are the same as those in the embodiment described with reference to FIGS. In FIG. 14, in order to make the drawing easier to see, each switch SW (SW10, SW11, SW12, SW20, SW21, SW22) in the voltage supply unit VS5 (more specifically, the voltage generation unit VG2) is turned on / off. The description of the control terminal that receives the signal for controlling is omitted.

  The voltage supply unit VS5 has a voltage generation unit VG2 instead of the voltage generation unit VG1. The other configuration of the voltage supply unit VS5 is the same as that of the voltage supply unit VS4. For example, the voltage supply unit VS5 sets the voltage of the output terminal VR based on the signal received from the selection unit SEL. The voltage of the output terminal VR is generated by the voltage generator VG2.

  The voltage generator VG2 includes, for example, a variable resistor disposed between the internal power supply line and the output terminal VR, and a variable resistor disposed between the output terminal VR and the ground line. The variable resistor has, for example, a plurality of pairs in which resistors and switches are connected in series. For example, in the voltage generator VG2, a pair of the resistor R10 and the switch SW10, a pair of the resistor R11 and the switch SW11, and a pair of the resistor R12 and the switch SW12 are connected in parallel between the internal power supply line and the output terminal VR. Has been. Further, a pair of the switch SW20 and the resistor R20, a pair of the switch SW21 and the resistor R21, and a pair of the switch SW22 and the resistor R22 are connected in parallel between the output terminal VR and the ground line. The number of resistors and switch pairs is not limited to this example.

  The voltage generated by the voltage generator VG2 (the voltage at the output terminal VR) changes, for example, the ratio between the resistance between the internal power supply line and the output terminal VR and the resistance between the output terminal VR and the ground line By doing so, it is set variably. For example, the resistance between the internal power supply line and the output terminal VR is variably set by changing the combination of the resistors R10, R11, and R12 in the voltage generation unit VG2. Further, the resistance between the output terminal VR and the ground line is variably set by changing the combination of the resistors R20, R21, and R22 in the voltage generator VG2.

  The combination of the resistors R10, R11, and R12 is changed by controlling on / off of the switches SW10, SW11, and SW12. Further, the combination of the resistors R10, R11, and R12 is changed by controlling on / off of the switches SW20, SW21, and SW22. That is, the voltage of the output terminal VR is variably set by controlling on / off of the switches SW10, SW11, SW12, SW20, SW21, and SW22.

  The frequency divider DIV is arranged between the voltage control oscillator VCO and the phase comparator PFD. For example, the frequency divider DIV divides the signal received at the input terminal CIN at a frequency dividing ratio indicated by the signal received at the input terminal DINF. Then, the frequency divider DIV outputs the frequency-divided signal from the output terminal COUT. For example, the input terminal CIN of the frequency divider DIV is connected to the output terminal SOUT of the voltage controlled oscillator VCO, and the output terminal COUT of the frequency divider DIV is connected to the input terminal FB of the phase comparator PFD.

  That is, the frequency divider DIV divides the output signal of the voltage control oscillator VCO by a predetermined frequency dividing ratio, and outputs the divided signal to the phase comparator PFD. As a result, the PLL circuit 10 allows the phase of the output signal even when the frequency of the output signal (the output signal of the voltage controlled oscillator VCO) is higher than the frequency of the reference signal (the signal received at the input terminal CK of the phase comparator PFD). Can be synchronized with the phase of the reference signal.

  For example, the selection unit SEL generates a signal indicating a combination of resistors (R10-R12, R20-R22) in the voltage generation unit VG2 based on the frequency division ratio indicated by the signal received at the input terminal SINF. For example, the input terminal SINF of the selection unit SEL is connected to the input terminal DINF of the frequency divider DIV. Note that the selection unit SEL may receive a signal indicating the target frequency of the output signal of the voltage controlled oscillator VCO instead of the signal indicating the frequency division ratio.

  The signal indicating the combination of the resistors (R10-R12, R20-R22) in the voltage generator VG2 is a signal indicating whether each switch SW10, SW11, SW12, SW20, SW21, SW22 is turned on or off, for example. . This signal is output from each of the output terminals RESL1 to RESL6 of the selection unit SEL, for example.

  For example, when the frequency of the output signal of the PLL circuit 10 (output signal of the voltage controlled oscillator VCO) is high, the frequency division ratio of the frequency divider DIV is larger than when the frequency of the output signal of the PLL circuit 10 is low. Is set. Therefore, the voltage at the output terminal VR is high when the frequency division ratio of the frequency divider DIV is small (for example, when the frequency division ratio is 3), for example, when the frequency division ratio of the frequency divider DIV is small (for example, It is set higher than when the circumferential ratio is 2.

  Therefore, for example, when the division ratio indicated by the signal received at the input terminal SINF is large, the selection unit SEL outputs a signal indicating a combination of resistors (R10-R12, R20-R22) that increase the voltage at the output terminal VR. Output from the output terminals RESL1-RESL6. For example, when the division ratio indicated by the signal received at the input terminal SINF is small, the selection unit SEL outputs a signal indicating a combination of resistors (R10-R12, R20-R22) that reduce the voltage at the output terminal VR. Output from the output terminals RESL1-RESL6.

  Thereby, the voltage supply unit VS5 can appropriately set the voltage of the output terminal VR based on the signal received from the selection unit SEL, for example, in the initial setting period. The operation of the PLL circuit 10 in the initial setting period is the same as that of the PLL circuit 10 described in FIG. 12 except that the voltage supply unit VS5 sets the voltage of the output terminal VR based on the signal received from the selection unit SEL. Same as operation. For example, in the initial setting period, the voltage supply unit VS5 turns on the first switch SW1, turns off the second switch SW2, and turns off the first current source IS12 and the second current source IS22. The operation of the PLL circuit 10 during the normal operation period is the same as the operation of the PLL circuit 10 described with reference to FIG. 13 except that a phase difference between the signal divided by the frequency divider DIV and the reference signal is detected. The same.

  The configuration of the voltage supply unit VS5 is not limited to this example. For example, the output terminal VR may be connected to the node N3 without being connected to the node N2 of the charge pump circuit CP2. In this case, the voltage supply unit VS5 turns off the first switch SW1, turns on the second switch SW2, and turns off the first current source IS12 and the second current source IS22 during the initial setting period.

  For example, the terminal of the switches SW20, SW21, and SW22 that is not connected to the resistors R20, R21, and R22 may be connected to the node N3 without being connected to the node N2. In this case, the voltage supply unit VS5 turns on the first switch SW1 and the second switch SW2 and turns off the first current source IS12 and the second current source IS22 during the initial setting period. For example, the voltage generation unit VG2 may be provided outside the voltage supply unit VS5. Alternatively, the voltage at the output terminal VR may be variably generated by a method other than resistance division.

  Further, the PLL circuit 10 may be configured by omitting the frequency divider DIV. That is, the output signal of the voltage controlled oscillator VCO may be fed back to the phase comparator PFD without going through the frequency divider DIV. Alternatively, the frequency division ratio of the frequency divider DIV may be fixed. In these cases, the selection unit SEL outputs, for example, a signal indicating a combination of resistors (R10-R12, R20-R22) in the voltage generation unit VG2 as an output signal of the PLL circuit 10 (an output signal of the voltage control oscillator VCO). It generates according to the target frequency. Further, in the PLL circuit 10 described with reference to FIGS. 4 to 9, the initial voltage (initial voltage of the control voltage) of the input terminal VCNT of the voltage control oscillator VCO may be set variably.

  For example, the voltage supply unit VS2 shown in FIG. 6 adjusts the voltages of the control terminals of the current sources IS12 and IS22 in accordance with the target frequency of the output signal of the voltage control oscillator VCO, whereby the on-resistance of the transistor MI1. And the ratio of the on-resistance of the transistor MI2. Thereby, the initial voltage of the input terminal VCNT of the voltage controlled oscillator VCO is set variably. Further, for example, the voltage supply unit VS3 illustrated in FIG. 9 adjusts the voltage of the control terminals of the switches SW1 and SW2 according to the target frequency of the output signal of the voltage control oscillator VCO, thereby turning on the transistor MS1. The ratio between the resistance and the on-resistance of the transistor MS2 is adjusted. Thereby, the initial voltage of the input terminal VCNT of the voltage controlled oscillator VCO is set variably.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Furthermore, in this embodiment, the initial voltage applied to the input terminal VCNT of the voltage controlled oscillator VCO can be variably set, so that it is appropriate for the target frequency of the output signal of the PLL circuit 10 (output signal of the voltage controlled oscillator VCO). Such an initial voltage can be applied to the input terminal VCNT of the voltage controlled oscillator VCO. Thereby, in this embodiment, even when the frequency of the output signal of the PLL circuit 10 is changed, the lockup time can be shortened.

The invention described in the above embodiments is organized and disclosed as an appendix.
(Appendix 1)
A voltage controlled oscillator that generates an output signal having a frequency according to the control voltage;
A frequency divider for dividing the output signal;
A phase comparator that detects a phase difference between a reference signal and the divided output signal, and generates a first detection signal and a second detection signal according to the phase difference;
A charge pump circuit for adjusting the control voltage, comprising: a first switch whose on / off is controlled based on the first detection signal; and a second switch whose on / off is controlled based on the second detection signal; ,
A low-pass filter that includes a capacitive element that is charged and discharged by the charge pump circuit, and that generates the control voltage by smoothing the output of the charge pump circuit;
During an initial setting period in which an initial voltage is applied to the voltage controlled oscillator, at least one of the first switch and the second switch is turned on to control charging / discharging of the capacitive element, thereby changing the control voltage to the initial voltage. And a voltage supply unit to be set.
(Appendix 2)
The charge pump circuit
A first current source controlled by a voltage received by the first control terminal and charging the capacitive element via the first switch;
A second current source controlled by a voltage received by the second control terminal and discharging the capacitive element via the second switch;
The voltage supply unit turns on the first switch and the second switch during the initial setting period, and supplies the control voltage to the first control terminal and the second control terminal, respectively. The PLL circuit according to appendix 1, wherein the PLL circuit is set to an initial voltage.
(Appendix 3)
The first current source includes a MOS transistor that receives a voltage of the first control terminal at a gate;
The second current source has a MOS transistor that receives the voltage of the second control terminal at the gate,
The voltage supply unit controls the voltage of the first control terminal and the voltage of the second control terminal, respectively, during the initial setting period, so that the respective MOS transistors of the first current source and the second current source 3. The PLL circuit according to appendix 2, wherein the on-resistance is controlled and the control voltage is set to the initial voltage.
(Appendix 4)
The voltage supply unit applies a first adjustment voltage to a terminal that receives a signal for controlling on / off of the first switch and a signal for controlling on / off of the second switch during the initial setting period. The PLL circuit according to appendix 1, wherein an on-resistance of the first switch and the second switch is controlled by applying a second adjustment voltage to a terminal, and the control voltage is set to the initial voltage.
(Appendix 5)
The first switch includes a MOS transistor that receives the first adjustment voltage at a gate;
The PLL circuit according to claim 4, wherein the second switch includes a MOS transistor that receives the second adjustment voltage at a gate.
(Appendix 6)
The charge pump circuit includes a first current source that charges the capacitive element via the first switch, and a second current source that discharges the capacitive element via the second switch;
In the initial setting period, the voltage supply unit includes the initial voltage at least one of a node between the first switch and the first current source and a node between the second switch and the second current source. A voltage is applied, and one of the first switch and the second switch that is disposed between the node to which the initial voltage is applied and the capacitive element is turned on, and the control voltage is set to the initial voltage. The PLL circuit according to supplementary note 1, characterized by:
(Appendix 7)
The PLL circuit according to claim 6, wherein the voltage supply unit variably sets the initial voltage according to a target frequency of the voltage controlled oscillator.
(Appendix 8)
The PLL circuit according to any one of appendices 1 to 5, wherein the voltage supply unit variably sets the initial voltage according to a target frequency of the voltage controlled oscillator.
(Appendix 9)
The charge pump circuit
A first current source controlled by a voltage received by the first control terminal and charging the capacitive element via the first switch;
A second current source controlled by a voltage received by the second control terminal and discharging the capacitive element via the second switch;
The voltage supply unit turns on the first switch and the second switch during the initial setting period, and the voltages of the first control terminal and the second control terminal according to a target frequency of the voltage controlled oscillator. The PLL circuit according to claim 1, wherein the initial voltage of the control voltage is variably set.
(Appendix 10)
In the initial setting period, the voltage supply unit includes a voltage at a terminal that receives a signal for controlling on / off of the first switch according to a target frequency of the voltage controlled oscillator, and on / off of the second switch. The ratio of the on-resistance of the first switch to the on-resistance of the second switch is adjusted by adjusting the voltage of the terminal that receives the signal for controlling the control, and the initial voltage of the control voltage is variably set. The PLL circuit according to appendix 1, wherein:
(Appendix 11)
A PLL circuit that generates an output signal having a frequency based on the reference signal;
The PLL circuit includes:
A voltage controlled oscillator that generates the output signal having a frequency according to a control voltage;
A frequency divider for dividing the output signal;
A phase comparator that detects a phase difference between the reference signal and the divided output signal and generates a first detection signal and a second detection signal according to the phase difference;
A charge pump circuit for adjusting the control voltage, comprising: a first switch whose on / off is controlled based on the first detection signal; and a second switch whose on / off is controlled based on the second detection signal; ,
A low-pass filter that includes a capacitive element that is charged and discharged by the charge pump circuit, and that generates the control voltage by smoothing the output of the charge pump circuit;
During an initial setting period in which an initial voltage is applied to the voltage controlled oscillator, at least one of the first switch and the second switch is turned on to control charging / discharging of the capacitive element, thereby changing the control voltage to the initial voltage. A semiconductor device comprising: a voltage supply unit to be set.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Further, any person having ordinary knowledge in the technical field should be able to easily come up with any improvements and modifications, and there is no intention to limit the scope of the embodiments having the invention to those described above. It is also possible to rely on suitable improvements and equivalents within the scope disclosed in.

  DESCRIPTION OF SYMBOLS 10 ... PLL circuit; C1 ... Capacitance element; CP1, CP2 ... Charge pump circuit; DIV ... Divider; IS10, IS12, IS20, IS22 ... Current source; LPF ... Low pass filter; MI1, MI2, MS1, MS2 ... MOS transistor PFD, phase comparator, R1, R10-R12, R20-R22, resistance, SEL, selection unit, SW1, SW2, SW10-SW12, SW20-SW22, switch, VG1, VG2, voltage supply unit, VS1-VS5,. Voltage supply

Claims (3)

A voltage controlled oscillator that generates an output signal having a frequency according to the control voltage;
A frequency divider for dividing the output signal;
A phase comparator that detects a phase difference between the reference signal and the divided output signal, and generates a first detection signal and a second detection signal according to the phase difference;
A charge pump circuit for adjusting the control voltage, comprising: a first switch whose on / off is controlled based on the first detection signal; and a second switch whose on / off is controlled based on the second detection signal; ,
A low-pass filter that includes a capacitive element that is charged and discharged by the charge pump circuit, and that generates the control voltage by smoothing the output of the charge pump circuit;
During an initial setting period in which an initial voltage is applied to the voltage controlled oscillator, at least one of the first switch and the second switch is turned on to control charging / discharging of the capacitive element, thereby changing the control voltage to the initial voltage. A voltage supply unit to be set,
The charge pump circuit includes a first current source that charges the capacitive element via the first switch, and a second current source that discharges the capacitive element via the second switch;
In the initial setting period, the voltage supply unit includes the initial voltage at least one of a node between the first switch and the first current source and a node between the second switch and the second current source. A voltage is applied, and one of the first switch and the second switch that is disposed between the node to which the initial voltage is applied and the capacitive element is turned on, and the control voltage is set to the initial voltage. A PLL circuit characterized by that. The PLL circuit according to claim 1, wherein the voltage supply unit variably sets the initial voltage according to a target frequency of the voltage controlled oscillator. A PLL circuit that generates an output signal having a frequency based on the reference signal;
The PLL circuit includes:
A voltage controlled oscillator that generates the output signal having a frequency according to a control voltage;
A frequency divider for dividing the output signal;
A phase comparator that detects a phase difference between the reference signal and the divided output signal and generates a first detection signal and a second detection signal according to the phase difference;
A charge pump circuit for adjusting the control voltage, comprising: a first switch whose on / off is controlled based on the first detection signal; and a second switch whose on / off is controlled based on the second detection signal; ,
A low-pass filter that includes a capacitive element that is charged and discharged by the charge pump circuit, and that generates the control voltage by smoothing the output of the charge pump circuit;
During an initial setting period in which an initial voltage is applied to the voltage controlled oscillator, at least one of the first switch and the second switch is turned on to control charging / discharging of the capacitive element, thereby changing the control voltage to the initial voltage. A voltage supply unit to be set,
The charge pump circuit includes a first current source that charges the capacitive element via the first switch, and a second current source that discharges the capacitive element via the second switch;
In the initial setting period, the voltage supply unit includes the initial voltage at least one of a node between the first switch and the first current source and a node between the second switch and the second current source. A voltage is applied, and one of the first switch and the second switch that is disposed between the node to which the initial voltage is applied and the capacitive element is turned on, and the control voltage is set to the initial voltage. A semiconductor device.

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