JP5624579B2 - オンチップルータ - Google Patents

オンチップルータ Download PDF

Info

Publication number
JP5624579B2
JP5624579B2 JP2012067923A JP2012067923A JP5624579B2 JP 5624579 B2 JP5624579 B2 JP 5624579B2 JP 2012067923 A JP2012067923 A JP 2012067923A JP 2012067923 A JP2012067923 A JP 2012067923A JP 5624579 B2 JP5624579 B2 JP 5624579B2
Authority
JP
Japan
Prior art keywords
router
packet
output port
header
hop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2012067923A
Other languages
English (en)
Japanese (ja)
Other versions
JP2013201552A (ja
JP2013201552A5 (enExample
Inventor
野 徹 佐
野 徹 佐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2012067923A priority Critical patent/JP5624579B2/ja
Priority to US13/598,389 priority patent/US20130250954A1/en
Publication of JP2013201552A publication Critical patent/JP2013201552A/ja
Publication of JP2013201552A5 publication Critical patent/JP2013201552A5/ja
Application granted granted Critical
Publication of JP5624579B2 publication Critical patent/JP5624579B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00Routing or path finding of packets in data switching networks
    • H04L45/02Topology update or discovery
    • H04L45/06Deflection routing, e.g. hot-potato routing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
JP2012067923A 2012-03-23 2012-03-23 オンチップルータ Expired - Fee Related JP5624579B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2012067923A JP5624579B2 (ja) 2012-03-23 2012-03-23 オンチップルータ
US13/598,389 US20130250954A1 (en) 2012-03-23 2012-08-29 On-chip router and multi-core system using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012067923A JP5624579B2 (ja) 2012-03-23 2012-03-23 オンチップルータ

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2014124443A Division JP5847887B2 (ja) 2014-06-17 2014-06-17 オンチップルータ及びそれを用いたマルチコアシステム

Publications (3)

Publication Number Publication Date
JP2013201552A JP2013201552A (ja) 2013-10-03
JP2013201552A5 JP2013201552A5 (enExample) 2014-03-20
JP5624579B2 true JP5624579B2 (ja) 2014-11-12

Family

ID=49211770

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012067923A Expired - Fee Related JP5624579B2 (ja) 2012-03-23 2012-03-23 オンチップルータ

Country Status (2)

Country Link
US (1) US20130250954A1 (enExample)
JP (1) JP5624579B2 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150103822A1 (en) * 2013-10-15 2015-04-16 Netspeed Systems Noc interface protocol adaptive to varied host interface protocols
US10061531B2 (en) 2015-01-29 2018-08-28 Knuedge Incorporated Uniform system wide addressing for a computing system
US10027583B2 (en) 2016-03-22 2018-07-17 Knuedge Incorporated Chained packet sequences in a network on a chip architecture
US10346049B2 (en) * 2016-04-29 2019-07-09 Friday Harbor Llc Distributed contiguous reads in a network on a chip architecture
US20170118312A1 (en) * 2017-01-09 2017-04-27 Mediatek Inc. Packet Header Deflation For Network Virtualization
US10541934B1 (en) * 2017-12-11 2020-01-21 Xilinx, Inc . Systems and methods for frame buffering and arbitration in a network

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5475680A (en) * 1989-09-15 1995-12-12 Gpt Limited Asynchronous time division multiplex switching system
US6687247B1 (en) * 1999-10-27 2004-02-03 Cisco Technology, Inc. Architecture for high speed class of service enabled linecard
KR100429904B1 (ko) * 2002-05-18 2004-05-03 한국전자통신연구원 차등화된 QoS 서비스를 제공하는 라우터 및 그것의고속 IP 패킷 분류 방법
US8228908B2 (en) * 2006-07-11 2012-07-24 Cisco Technology, Inc. Apparatus for hardware-software classification of data packet flows
JP2008027153A (ja) * 2006-07-20 2008-02-07 Ricoh Co Ltd 情報処理プログラム、情報処理装置および情報処理方法
EP2009554A1 (en) * 2007-06-25 2008-12-31 Stmicroelectronics SA Method for transferring data from a source target to a destination target, and corresponding network interface
WO2010022767A1 (en) * 2008-08-26 2010-03-04 Telefonaktiebolaget Lm Ericsson (Publ) Packet forwarding in a network
JPWO2010104033A1 (ja) * 2009-03-09 2012-09-13 日本電気株式会社 プロセッサ間通信システム及び通信方法、ネットワークスイッチ、及び並列計算システム
WO2010137572A1 (ja) * 2009-05-25 2010-12-02 日本電気株式会社 ネットワークオンチップとネットワークルーティング方法とシステム

Also Published As

Publication number Publication date
US20130250954A1 (en) 2013-09-26
JP2013201552A (ja) 2013-10-03

Similar Documents

Publication Publication Date Title
US8937958B2 (en) Router and many-core system
US8601423B1 (en) Asymmetric mesh NoC topologies
US8848703B2 (en) On-chip router and multi-core system using the same
US8638665B2 (en) Router, information processing device having said router, and packet routing method
US20140177470A1 (en) Memory Sharing in a Network Device
CN104662525B (zh) 并行计算机、节点装置以及并行计算机的控制方法
US20150103822A1 (en) Noc interface protocol adaptive to varied host interface protocols
JP2013201552A (ja) オンチップルータ及びそれを用いたマルチコアシステム
CN109698788A (zh) 流量转发方法和流量转发装置
US9306844B2 (en) Zero-cycle router for networks on-chip
CN112491715B (zh) 路由装置及片上网络的路由设备
US11310169B2 (en) Network-on-chip topology generation
JP5847887B2 (ja) オンチップルータ及びそれを用いたマルチコアシステム
US8812787B2 (en) Router and many-core system
US9413654B2 (en) System, relay device, method, and medium
EP2405362B1 (en) A connection arrangement
CN108431790B (zh) 用于高速迁移(EXTRA)NoC的路由器的专用SSR管线级
JP6586374B2 (ja) 通信装置、経路管理サーバ、通信方法、および仮想ポート割当方法
CN117278507A (zh) 一种缓存器、缓存器系统及数据处理方法
CN100401718C (zh) 一种数据帧组播复制的方法及系统
US20160112318A1 (en) Information processing system, method, and information processing apparatus
JP2020005017A (ja) 動的可変容量メモリ装置及び記憶容量動的可変方法
Sahu Bidirectional Network-on-Chip Router Implementation Using VHDL
JP2005045681A (ja) スイッチネットワーク装置及びその転送制御方法
Wang et al. An innovative routing scheme to reduce communication delay in DMesh networks

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140204

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20140204

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20140404

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140418

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140617

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20140902

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140926

LAPS Cancellation because of no payment of annual fees