JP5616305B2 - Transmitter - Google Patents

Description

  The present invention relates to low power consumption of a transmitter.

  In a transmitter of a portable communication terminal device represented by a mobile phone (hereinafter referred to as “mobile terminal”), the output power of a transmission output signal (hereinafter referred to as “transmission output power”) has a wide variable width and low It is required to be power consumption. The low power consumption is indispensable for extending the battery of the mobile terminal, and it is important to keep the average power consumption low in the usage state of the mobile terminal that changes every moment. Further, since the power consumption is the product of the current consumption and the power supply voltage, reducing the current consumption means that the power consumption is reduced.

  For example, the transmitter described in Patent Document 1 is a power adjustment type transmitter. In this transmitter, as a means for reducing current consumption, a plurality of modulators arranged in parallel can be operated or not operated without changing the amplitude of the input baseband signal. The transmission output power is realized. In the method of changing the amplitude of the baseband signal in order to realize the desired transmission output power, the current flowing through the mixer cannot be reduced. However, according to the method of adjusting the transmission output power in Patent Document 1, the current consumption is small. The transmission output power can be adjusted with. Thereby, the power consumption calculated | required by the product of a power supply voltage and current consumption can also be reduced.

  Incidentally, the transmitter described in Patent Document 1 includes a baseband unit, an IQ quadrature modulator, a bandpass filter, a power amplifier (PA), an antenna, a power detector, and an interface circuit. The baseband unit includes a digital signal processing unit, a digital / analog converter (DA converter), a low-pass filter, and an analog / digital converter (AD converter). The IQ quadrature modulator includes a voltage controlled oscillation circuit (VCO), a frequency divider, two mixers, and an addition node.

  The two mixers are configured as follows. That is, the signal from the low-pass filter of the baseband part is input to four mixer cells connected in parallel to the mixer via the effective signal input part of the IQ quadrature modulator. Then, the sum of the currents output from each mixer cell is supplied to four transistors using the local oscillator signal from the local oscillator input unit as the other input via the current mirror. The outputs of the four transistors are output from two high frequency output units.

  Here, in the mixer of Patent Document 1, transmission output power is obtained by connecting or disconnecting each mixer cell by a switch connecting the four mixer cells in accordance with a signal from the control input unit. Can be adjusted. Thereby, the transmission output power can be adjusted with less current consumption than the method of adjusting the transmission output power by changing the amplitude of the baseband signal. That is, the average power consumption of the mixer itself can be kept low.

  Next, the power consumption of the frequency divider that drives the two mixers in Patent Document 1 will be described. The frequency divider is often realized by a CML (Current Mode Logic) circuit in a high-frequency circuit. FIG. 12 is a specific example when the divide-by-2 circuit is realized by a CML circuit. The CML circuit shown in FIG. 12 includes N-type MOS (Metal Oxide Semiconductor) transistors 901, 902, and 903, a load resistor 904, and a constant current source 900. This CML circuit receives high-frequency differential signals LOP and LON having a frequency twice as high as the carrier wave frequency, inputs differential outputs LOIP and LOIN having the same frequency as the carrier wave frequency, and these differential outputs are each 90 degrees in phase. Output differential outputs LOQP and LOQN.

  Here, the differential outputs LOIP and LOIN are input to one of the two mixers, and the differential outputs LOQP and LOQN are input to the other mixer. When the frequency divider is realized by the divide-by-2 circuit of FIG. 12, the capacitive load of the transistor in each mixer that is the output destination of each of the output LOIP, LOIN, LOQP, and LOQN of the divide-by-2 is CL. When the resistance value of the load resistor 904 of the two-frequency divider is R, the time constant composed of CL and R is R · CL. When the mixer circuit is composed of MOS transistors, the dominant factor of the capacitive load CL is proportional to the area of the gate formed by the gate oxide film of the MOS transistor. Here, the mathematical expression is simplified by ignoring the parasitic capacitance of the drain of the transistor 902, the parasitic capacitance of the gate of the transistor 903, the parasitic effect of the wiring, and the like in FIG.

  Assuming that the frequency of the carrier wave is fc, and the time constant R · CL needs to be smaller than the period 1/2 · π · fc, the selection range of the resistance value R satisfies the following expression (1): .

  Next, assuming that the output amplitudes of the outputs LOIP, LOIN, LOQP, and LOQN need to be V0 at a single-ended peak-to-peak value, the current value I0 of the constant current source 900 takes the above equation (1) into consideration, The following formula (2) is satisfied.

   From the above formulas (1) and (2), it can be seen that the current consumption in the frequency divider increases in proportion to the capacitive load CL of the transistors in the mixer.

Japanese Patent No. 4047274

However, when a conventional transmitter is realized by a CMOS (Complementary Metal Oxide Semiconductor) circuit, it is possible to suppress the average power consumption of the mixer itself, but it is a carrier wave signal for driving the mixer. The power consumption of the frequency divider that generates the high-frequency signal is irrelevant to the transmission output power, and there is a problem that the average power remains high.
The present invention has been made in view of the above problems, and by reducing the power consumption of both the mixer and the frequency divider according to the desired transmission output power, it is more average than the conventional transmitter. An object of the present invention is to provide a transmitter with low power consumption.

In order to solve the above problem, an aspect of the present invention includes K mixer cells (K is a natural number of 2 or more) arranged in parallel, and baseband signals are respectively transmitted to the K mixer cells. An input mixer, a frequency divider configured to output carrier wave signals to the K mixer cells and including N (N is a natural number of K ≧ N) frequency divider cells; and the mixer And a control circuit for outputting a control signal for setting an operating state of the frequency divider, and a phase detector for detecting a phase relationship between output signals of the N frequency divider cells. The number N of the frequency divider cells is smaller than the number K of the mixer cells, and the K mixer cells and the N frequency divider cells are connected one-to-one or one-to-one. and, the control circuit, the peripheral and the mixer cells connected to each other The operation state is set independently from the frequency divider cell, and the mixer cell adjusts the phase of the input baseband signal according to the detection result of the phase detector. It is a transmitter.

According to this configuration, when the transmission output power is lowered from the maximum, the frequency divider cell paired with the mixer cell constituting the mixer is deactivated together with the mixer, so that the desired transmission output power can be obtained. Accordingly, power consumption in the frequency divider can be suppressed.
According to another aspect of the present invention, there are K mixer cells (K is a natural number of 2 or more) arranged in parallel, and a baseband signal is input to each of the K mixer cells. Output a carrier wave signal to the K mixer cells, a frequency divider composed of N frequency divider cells (N is a natural number of K ≧ N), the mixer and the frequency divider A control circuit for outputting a control signal for setting an operating state of the detector, and a phase detector for detecting a phase relationship between output signals of the N frequency divider cells, and the frequency division The frequency divider cell is composed of (2 ^ L) frequency dividers in which L frequency dividers are connected in series with L stages (L is a natural number of 2 or more), and output signals of a plurality of frequency dividers (L-1) divide-by-2 divider phase detectors for detecting the phase relationship between 1) Among the two frequency divider phase detectors, the two frequency divider phase detectors in the M-th stage (M is a natural number of 2 or more) are the N frequency divider cells arranged in parallel. The phase relationship between the output signals of the M-th frequency divider in each of the N frequency divider cells is detected, and the (M + 1) -th stage of the second frequency divider in each of the N frequency divider cells is In accordance with the detection result of the two-frequency divider phase detector, the phase of the input signal is rotated forward or inverted, and the control circuit includes the mixer cell and the frequency divider cell connected to each other. And the mixer cell adjusts the phase of the input baseband signal according to the detection result of the phase detector.
According to this configuration, it is possible to stably obtain a desired transmission output power.
In another aspect of the present invention, the number N of frequency divider cells and the number K of mixer cells are the same, and the K mixer cells and the N frequency divider cells are the same. Is a one-to-one connection.

In another aspect of the present invention, the number N of the frequency divider cells is smaller than the number K of the mixer cells, and the K mixer cells and the N frequency divider cells include: The transmitter is connected in a one-to-one or one-to-multiple manner.
In another aspect of the present invention, the phase detector may be configured such that the frequency divider is based on the phase of the output signal from one frequency divider cell of the N frequency divider cells. It is a transmitter characterized by detecting the phase relationship of (N-1) frequency divider cells other than cells.

According to this configuration, it is possible to stably obtain a desired transmission output power.
In another aspect of the present invention, the N frequency divider cells have a normal or inverted phase relationship between output signals of the N frequency divider cells, and the phase detector The transmitter is characterized by detecting the phase relationship between normal rotation and inversion.
According to another aspect of the present invention, the mixer cell is a transmitter characterized in that the phase of the input baseband signal is rotated or inverted according to the detection result of the phase detector. is there.

  According to another aspect of the present invention, the frequency divider includes a frequency divider constituted by a (2 ^ L) frequency divider in which two frequency dividers are connected in series with L stages (L is a natural number of 2 or more). It comprises a frequency divider cell and (L−1) two frequency divider phase detectors for detecting the phase relationship between the output signals of a plurality of frequency dividers. Among the frequency divider phase detectors, the M-th phase detector (M is a natural number of 2 or more) is the M-th phase in each of the N frequency divider cells arranged in parallel. The phase divider between the output signals of the two frequency dividers is detected, and the (M + 1) -th stage of the two frequency dividers in each of the N frequency divider cells is the M-th frequency divider. According to the detection result of the phase detector, the transmitter is characterized in that the phase of the input signal is rotated forward or inverted.

According to this configuration, it is possible to stably obtain a desired transmission output power.
In another aspect of the present invention, a first mixer having the mixer to which an in-phase (I) baseband signal is input and a second mixer having the mixer to which a quadrature (Q) baseband signal is input. a mixer, a first carrier wave signal inputted to the first mixer, the second is inputted to the mixer the first carrier wave signal and a phase to generate a 90-degree different from the second carrier wave signal A transmitter comprising: an IQ frequency divider having the frequency divider; and an adder for adding the output signal of the first mixer and the output signal of the second mixer. It is.

  According to this configuration, when the transmission output power is lowered from the maximum, the frequency divider cell paired with the mixer cell constituting the mixer is deactivated together with the mixer, so that the desired transmission output power can be obtained. Accordingly, power consumption in the frequency divider can be suppressed.

  According to one aspect of the present invention, when the transmission output power is reduced from the maximum, the frequency divider cell paired with the mixer cell constituting the mixer is deactivated together with the mixer. Depending on the transmission output power, power consumption in the frequency divider can be suppressed.

It is a figure which shows an example of a structure of the IQ orthogonal modulation type transmitter which concerns on one Embodiment of this invention. It is an example of the structure of the mixer which concerns on one Embodiment of this invention. It is an example of the structure of the frequency divider which concerns on one Embodiment of this invention. It is a figure which shows an example of a structure of IQ orthogonal modulation type | mold transmitter in order to demonstrate transmission output power. It is a figure shown about an example of the polarity of the output signal of a frequency divider. It is a figure which shows an example about a part of structure of the IQ orthogonal modulation type transmitter which concerns on one Embodiment of this invention. It is a figure which shows an example of a structure of the phase detector in the IQ orthogonal modulation type transmitter which concerns on one Embodiment of this invention. It is a figure shown about an example of the polarity of the input and output of a phase detector in the IQ quadrature modulation type transmitter which concerns on one Embodiment of this invention. It is an example of the circuit diagram of the mixer which concerns on one Embodiment of this invention. It is a figure shown about an example of a structure of the frequency divider concerning one Embodiment of this invention. It is an example of the structure of the 2 frequency divider in the frequency divider which concerns on one Embodiment of this invention. This is a specific example when the divide-by-2 circuit is realized by a CML circuit.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing referred to in the following description, the same parts as those in other drawings are denoted by the same reference numerals. All transistors used in the configuration described below are N-type MOS transistors.
(First embodiment)
[Circuit configuration]
(IQ quadrature modulation transmitter)
FIG. 1 is a diagram illustrating a configuration example of an IQ quadrature modulation transmitter according to the present embodiment. An IQ quadrature modulation transmitter shown in FIG. 1 includes a baseband unit 20, an IQ quadrature modulator 30, a control circuit 5000, a bandpass filter 9, a power amplifier 10 (PA), an antenna 11, and power. It comprises a detector 12, an interface circuit 14, and a phase detector 15. The baseband unit 20 includes a digital signal processing unit 1, a digital / analog converter 3 (DA converter), a low-pass filter 4, and an analog / digital converter 13 (AD converter).

The IQ quadrature modulator 30 includes a voltage controlled oscillation circuit 7 (VCO), a frequency divider 50, two mixers 5, 5 ′, and an addition node 8.
The differential output from the frequency divider 50 is connected to the high-frequency differential input of the mixer 5 (high-frequency differential inputs 1201 and 1301 in FIG. 2 to be described later. Similarly, the difference from the frequency divider 50 is The dynamic output is connected to a high-frequency differential input (high-frequency differential inputs 1201 and 1301 in FIG. 2 to be described later) of the mixer 5 ′ The configurations of the mixers 5 and 5 ′ and the frequency divider 50 are as follows. This will be described in detail later.

  Further, the control circuit 5000 receives the transmission power setting from the interface circuit 14, and operates or operates the plurality of divider cells in the divider 50 and the plurality of mixer cells of the mixers 5, 5 ′. Control the inactive state. Specifically, the control circuit 5000 sends an operation or non-operation control signal to the mixers 5, 5 ′ and the frequency divider 50 according to the transmission power setting from the interface circuit 14 according to a preset control table. Send.

(Operation of control circuit)
Here, the operation of the control circuit 5000 will be described. FIG. 2 is an example of a circuit diagram of the mixer 5 (5 ′) according to the present embodiment. However, in FIG. 2, in order to explain only the operation of the control circuit 5000, the circuit portion to which the output signal from the phase detector 15 is input is omitted.

The mixer 5 (5 ′) according to the present embodiment includes K (K is a natural number of 2 or more) mixer cells 1601 to 160K.
The mixer cell 1601 includes an NMOS 1011 for converting each of the baseband inputs 1100 and 1101 from voltage to current, a resistor 1001, a cascode transistor 1021, and a transistor that performs frequency conversion according to the high-frequency differential inputs 1201 and 1301. 1031, a transistor 1041 for setting the gate voltage of the cascode transistor 1021 to the bias voltage Vb or the ground according to the operation / non-operation control signal 1501, and an inverting logic element 1050.

The operation / non-operation control signal 1501 is a control signal for setting the operation state of the mixer 5 (5 ′) in FIG. 2, and is input from the control circuit 5000 (FIG. 1) to the mixer 5 (5 ′). The When the operation / non-operation control signal 1501 is logically high, a bias voltage Vb is input to the gate of the cascode transistor 1021, and the mixer cell 1601 is appropriately biased (operation state). On the other hand, when the operation / non-operation control signal 1501 is logically low, the ground voltage is input to the gate of the cascode transistor 1021, and the voltage at the connection point between the resistor 1001 and the transistor 1011 becomes equal to the ground voltage. Thereby, the electric current which flows into the mixer cell 1601 becomes zero, and the operation | movement is stopped (non-operation). The operation of the mixer cells 1602 to 160K is the same.
Further, the frequency divider 50 according to the present embodiment includes N (N is a natural number of K ≧ N) frequency divider cells 50 ′. FIG. 3 is a diagram illustrating a configuration example of a frequency divider (frequency divider cell) 50 ′. The frequency divider 50 ′ of FIG. 3 generates a high frequency signal for driving the mixer of FIG.

The frequency divider 50 ′ shown in FIG. 3 has a configuration of a frequency divider having N-type MOS transistors 101, 102, 103, a load resistor 104, and a constant current source 100, as in FIG. Similar to FIG. 2, a cascode transistor 1020, a transistor 1040 for setting the gate voltage of the cascode transistor 1020 to the bias voltage Vb or the ground according to the operation / non-operation control signal 1500, and an inverting logic element 1050 are added. It is a thing.
Also, the differential outputs LOIP and LOIN of the frequency divider 50 ′ of FIG. 3 are connected to the high frequency differential inputs 1201 and 1301 of FIG. Similarly, the differential outputs LOQP and LOQN are also connected to the high-frequency differential inputs 1201 and 1301 in FIG. 2 (the same applies to the high-frequency differential inputs 1202 to 120K and 1302 to 130K). That is, the frequency divider 50 ′ connected to the mixer cell 1601 also stops its operation by setting the current flowing between its power supply and ground to zero in accordance with the operation / non-operation control signal 1500. Specifically, when the operation / non-operation control signal 1500 is logically high, the constant current source 100 passes a predetermined current, and when the operation / non-operation control signal 1500 is logically low, the constant current source 100 By setting the current of zero to zero, setting of operation or non-operation is realized.

  Also, the mixer cells 1602 to 160K in the mixer of FIG. 2 have the same structure as the mixer cell 1601. That is, the mixer cells 1602 to 160K include resistors 1002 to 100K, transistors 1012 to 101K, 1022 to 102K, 1032 to 103K, 1042 to 104K, and an inverting logic element 1050. The operation / non-operation control signals 1501 to 150K input to the mixer cells 1601 to 160K are independently controlled by the control circuit 5000. The high-frequency differential inputs 1201 to 120K and 1301 to 130K are connected to N frequency divider cells in a one-to-one or multiple-to-one manner. Here, K ≧ N. The N frequency divider cells are realized by installing N frequency dividers 50 ′ shown in FIG. 3, for example.

By setting a part of the K mixer cells to the non-operating state by the control circuit, a desired transmission output power can be realized without changing the amplitude of the baseband signal. In the method of changing the amplitude of the baseband signal in order to achieve a desired transmission output power, the current flowing through the mixer cannot be reduced. On the other hand, as in the present embodiment, the amplitude of the baseband signal is reduced. With the method of adjusting the transmission output power without changing it, the transmission output power can be adjusted with little current consumption.
Furthermore, by controlling the frequency divider cell connected to the mixer cell set to non-operation so as to be non-operational, it is possible to reduce current consumed unnecessarily in the frequency divider cell. it can. Therefore, the power consumption required by the product of the power supply voltage and the current consumption can also be reduced.

[Power consumption in frequency divider]
Next, power consumption in the frequency divider 50 of the present embodiment will be described. In the following description, the number N of frequency divider cells 50 ′ constituting the frequency divider 50 is assumed to be the same as the number K of mixer cells for simplicity. Note that the transistors 1031 to 103K in FIG. 2 to which the high frequency signal is input from the frequency divider 50 ′ in FIG. 3 are four transistors that receive the local oscillator signal from the local oscillator input unit described in Patent Document 1. Equivalent to.

In the mixer according to the present embodiment (FIG. 2) and the mixer described in Patent Literature 1, when the same current is output, the sum of currents from each mixer cell is obtained through the current mirror in Patent Literature 1. When the sum of the gate areas of the four input transistors is S0, the sum of the gate areas of the transistors 1031 to 103K in FIG. 2 is S0.
Here, it is assumed that all the MOS transistors have the same type, the same gate length, and the same high-frequency signal frequency. In Patent Document 1, the current mirror and the four transistors connected to the current mirror are configured in two stages from the ground, whereas in the mixer of FIG. 2 according to the present embodiment, the resistor 1001, the transistor 1011, 1021 and 1031 are constituted by multistage connection. However, for simplicity, this point is not considered in terms of power consumption.

  Here, assuming that the mixer cells 1601 to 160K are the same, the area of the transistor 1030 is represented by S0 / K. This indicates that the capacitive load value of the transistor 1031 of FIG. 2 according to the present embodiment is CL / K with respect to the capacitive load value CL of the gates of the four transistors of Patent Document 1. At this time, if the two-frequency divider 50 ′ of FIG. 3 is connected to the mixer cell 1601 of FIG. 2 in a one-to-one relationship, the current value I0x of the constant current source 100 is expressed by the following equation (3). Indicated by

   Here, it is assumed that the high-frequency signal output amplitude of the frequency divider output is a single-ended peak-to-peak value, V0 is required, and the frequency of the transmission carrier wave is fc. Further, a relationship of I0 = K · I0x is established between the current value I0 of the constant current source of the two-frequency divider that drives the mixer of Patent Document 1 and the current value I0x.

  In the present embodiment, the divide-by-2 also operates / non-operates in accordance with the operation / non-operation of the mixer cell. Therefore, when the transmission output power when the K mixer cells and the N (= K) frequency divider cells operate is the maximum, in this embodiment, the constant current source 100 of the two dividers is used. The current value is the same as in Patent Document 1. On the other hand, in a situation where the transmission output power is very small, only one of the K mixer cells of FIG. 2 operates and only one of the K frequency divider cells operates. The current value of the constant current source 100 is I0x. Compared with Patent Document 1, the current consumption is 1 / K, that is, the power consumption is 1 / K.

As described above, in the present embodiment, it is possible to reduce the power consumption of the mixer and the frequency divider according to the desired transmission output power.
In place of the mixer shown in FIG. 2, a high-frequency input transistor and a baseband input transistor are installed in each mixer cell, and another mixer that can control operation / non-operation of the mixer cell independently is provided. May be used. In this case as well, the average power consumption of the transmitter can be reduced.

[Transmission output power]
By the way, if it is going to implement | achieve the frequency divider arrange | positioned in parallel by simply installing two or more CML type | mold dividers, a desired transmission output power may not be obtained for the following reasons. .
FIG. 4 is a diagram illustrating a configuration example of a transmitter including frequency divider cells 2000 and 2001, mixer cells 2002 and 2003, and an addition node 2004. Each of the frequency divider cells 2000 and 2001 is a frequency divider cell having a configuration similar to that of the frequency divider (2 divider) 50 ′ shown in FIG. 3, and the mixer cells 2002 and 2003 are respectively The mixer cells have the same configuration as 1601 and 1602 shown in FIG.

  The phase relationship between the polarities of the differential output signals L1P and L1N of the frequency divider cell 2000 and the polarities of the differential output signals L2P and L2N of the frequency divider cell 2001 is one of the combinations shown in FIG. . Here, “L1” indicates the polarity of L1P-L1N, and “L2” indicates the polarity of L2P-L2N. In FIG. 5, in-phase means a phase difference of 0 degree, and inversion means a phase difference of 180 degrees.

  3 is stopped by the control signal from the control circuit 5000, the current supply from the constant current source 100 is stopped. Therefore, the output signals LOIP, LOIN, LOQP, and LOQN are It becomes the power supply voltage VDD. When the frequency divider 50 'transitions from the stopped state to the operating state, these output signals aim at Vdd-I * R / 2 which is in a balanced state. Here, the current value of the constant current source 100 is I. However, a subtle difference in voltage generated between the output signals LOIP and LOIN on the way to the equilibrium state due to manufacturing variation between MOS transistors or the like is positive due to the so-called cross-coupled configuration formed by the two transistors 103. Due to the feedback action, one voltage goes to the high voltage Vdd during normal operation, and the other goes to the low voltage Vdd-I * R. This is the initial value of the output voltage when transitioning from the stopped state to the operating state.

  The initial values of the voltages of the output signals LOQP and LOQN are uniquely determined if the polarities of the output signals LOIP and LOIN are determined. In the subsequent operation state, the voltage is not fixed to the equilibrium state, the high voltage, or the low voltage, and the high voltage and the low voltage are alternately output in a half cycle of the input high-frequency signal. Thus, since the initial value of the output when transitioning from the stopped state to the operating state cannot be controlled, the frequency dividers 2000 and 2001 using such a divide-by-2 frequency divider cell as the frequency divider cell. The outputs of the frequency dividers 2000 and 2001 indicate one of the phase relationships in FIG.

  The differential outputs O1P and O1N and O2P and O2N of the mixer cells 2002 and 2003 in FIG. 4 are expressed by the following equation (4). Here, BP1−BN1 which is the difference between the baseband signals BP1 and BN1 of the input differential input signal is defined as B.

  When OP-ON, which is the difference between the differential output signals OP and ON from the addition node 2004, is O, O is expressed by the following equation (5).

  Therefore, when the phase relationship shown in FIG. 5 is inverted, L1 = −1 * L2, so that the output of the addition node 2004 becomes zero and a desired output cannot be obtained. Thus, for example, if the polarities of the outputs of the two frequency dividers (frequency divider cells) 2000 and 2001 are determined uncorrelated and randomly, the probability of obtaining a desired transmission output power is ½. is there.

  As described above, if the phases of the outputs of the plurality of frequency divider cells arranged in parallel are determined uncorrelated and randomly, a desired transmission output power may not be obtained. In the transmitter according to the above, by providing the phase detector 15, a desired transmission output power can be stably obtained.

(Phase detector)
FIG. 6 is a diagram showing an example of the configuration of the peripheral portion of the phase detector 15 in the IQ quadrature modulation type transmitter of the present embodiment shown in FIG. 6 shows the configuration of the frequency divider 50, the mixer 5 (or the mixer 5 ′), the adder node 8, and the phase detector 15 of the IQ orthogonal modulation type transmitter of FIG.
The frequency divider 50 includes N frequency divider cells 3101, 3102,..., 310N arranged in parallel, and the mixer 5 is connected in parallel as shown in FIG. , And 160K mixer cells 1601, 1602,..., 160K. The phase detector 15 detects the phase relationship between the outputs of the other frequency divider cells 3102 to 310N with reference to the phase of the output signal of the frequency divider cell 3101.

  The phase detector 15 outputs (N−1) phase detection results corresponding to the phase relationship of the outputs of the frequency divider cells 3102 to 310N. This detection result is input to the mixer cells 1602 to 160K connected to the frequency divider cells 3102 to 310N. In each of the mixer cells 1602 to 160K, the phase of the signal output from the frequency divider cell is the same as that of the frequency divider cell 3101 in accordance with the signal indicating the phase detection result from the phase detector 15. Adjust so that

  Thereby, even if the phase of the output signal from the frequency divider cells 3101 to 310N is determined uncorrelated and randomly, the signal output from the mixer cells 1601 to 160K and added at the addition node 8 is A desired transmission output power is always obtained.

(Configuration of phase detector)
When the polarity of the output signal from the frequency divider cells 3102 to 310N is only positive or negative when the frequency divider cell 3101 of FIG. 6 is used as a reference, the phase detector 15 is shown in FIG. This can be realized by providing (N−1) phase detector cells.
The phase detector cell of FIG. 7 includes two transistors 401a and 401b to which a signal AP input from a terminal 410 and a signal AN input from a terminal 411 are input, a signal from the transistors 401a and 401b, and a terminal 412. From the four transistors 402a, 402b, 402c, 402d, the load resistors 403a, 403b, the constant current source 400, and the transistors 402a to 402d that receive the signal BP input from the terminal 413 and the signal BN input from the terminal 413. The limiter 430 to which the differential signals QP and QN are input.

  Specifically, the signal AP input from the terminal 410 is input to the gate of the transistor 401a, and the signal AN input from the terminal 411 is input to the gate of the transistor 401b. The constant current source 400 is connected to the sources of the transistors 401a and 401b. The drain of the transistor 401a is connected to the sources of the transistors 402a and 402b, and the drain of the transistor 401b is connected to the sources of the transistors 402c and 402d.

  Further, the signal BP from the terminal 412 is input to the gates of the transistors 402a and 402d, and the signal BN from the terminal 413 is input to the transistors 402b and 402c. The drains of the transistors 402a and 402c are connected to the load resistor 403a, and the drains of the transistors 402b and 402d are connected to the load resistor 403b. Further, the differential signal QP output from the transistors 402 a and 402 c and the differential signal QN output from the transistors 402 b and 402 d are input to the limiter 430.

  The limiter 430 outputs a ground voltage signal when the differential signals QP and QN are low, and outputs a power supply voltage signal of the limiter 430 when the differential signals QP and QN are low. It is. A signal obtained by logically inverting the output of the limiter 430 by the inverting logic element 431 becomes the output of the phase detector cell of FIG. A differential output signal from the frequency divider cell 3101 shown in FIG. 6 is input to the terminal 410 and the terminal 411, and the frequency divider cell 3102 shown in FIG. 6 is input to the terminal 412 and the terminal 413. A differential output signal output from any of .about.310N is input.

  Here, the polarities of the differential output signals input from the terminals 410 to 413 are as shown in FIG. In FIG. 8, “A” indicates the polarity of the differential input signal AP-AN, and “B” indicates the polarity of the differential input signal BP-BN. “Q” indicates the polarity of the differential signal QP-QN. “OUTN” indicates the polarity of the output signal from the limiter 430. “OUT” indicates the polarity of the output signal of the phase detector cell.

(Configuration of mixer cell)
FIG. 9 is an example of a circuit diagram of the mixer 5 (5 ′) according to the present embodiment. Specifically, the configuration shown in FIG. 9 is obtained by adding a circuit portion to which an output signal from the phase detector 15 is input to the configuration of the mixer 5 (5 ′) shown in FIG.

  In addition to the configuration of FIG. 2, the mixer cells 1602 to 160K of the mixer 5 (5 ′) include terminals 2112 to 211K to which an output signal from the phase detector 15 is input, and N-type MOS transistors 2012 to 201K. , N-type MOS transistors 2022 to 202K and an inverting logic element 2040. Terminals 1100 and 1101 are terminals to which baseband signals are input, and terminals 1201 to 120K and 1301 to 130K are signals from frequency divider cells 3101 to 310N connected to mixer cells 1601 to 160K, respectively. Is a terminal to which is input.

  A signal from the phase detector 15 is input to the terminals 2112 to 211K. For example, in the mixer cell 1602, a signal input to the terminal 2112 is input to each gate of the pair of transistors 2012, while a signal input to the terminal 2112 is inverted by the inverting logic element 2040. Thus, the gates of the pair of transistors 2022 are connected so as to be input. The sources of the pair of transistors 2012 and 2022 are connected to the drains of the pair of N-type MOS transistors 1022, respectively. The other mixer cells 1603 to 160K have the same configuration.

Here, when the detection result of the phase detector 15 is “in phase”, since the detection result signal is high, the transistors 2012 to 201K are respectively connected to the differential pairs formed of the transistors 1012 to 101K. Passing current flows. When the detection result of the phase detector 15 is “inverted”, since the detection result signal is low, the transistors 2022 to 202K each have a current passing through the differential pair constituted by the transistors 1012 to 101K. Flowing.
By the operation as described above, the phase normal rotation / inversion relationship between the frequency divider cells 3101 to 310N is corrected, and a desired transmission output power can be realized in the mixer cells 1601 to 160K. That is, the transmission output power of the addition node 8 is obtained by performing the above phase correction operation by the phase detector 15 in all of the mixer cells 1602, 1603,..., 160K except the mixer cell 1601 serving as a reference. Can obtain a desired signal.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.
(Configuration of frequency divider and phase detector)
FIG. 10 is a diagram illustrating an example of the configuration of the frequency divider 50 according to the present embodiment. The frequency divider 50 according to the present embodiment has two frequency divider cells 500 and 600, and the number N of frequency divider cells arranged in parallel is N = 2. Each of these frequency divider cells has a number L = 3 of the two frequency dividers connected in series. That is, the frequency divider cell 500 includes three divide-by-two units 501, 502, and 503, and the frequency divider cell 600 includes three divide-by-two units 601, 602, and 603. The frequency divider 50 according to the present embodiment is also configured to include two phase detectors 701 and 702.

  At this time, the frequency division numbers of the frequency divider cells 500 and 600 are respectively 2 ^ 3 = 8. The phase detectors 701 and 702 can be realized with the same configuration as in FIG. Further, each of the two frequency dividers 501, 502, 503, and 601 can be realized by a configuration similar to that in FIG. 3 (a configuration in which there is no input from the phase detectors 701 and 702). Other divide-by-two 602 and 603 can be realized by divide-by-2 shown in the same configuration as in FIG.

(Configuration of the two frequency dividers 602 and 603)
In addition to the configuration of FIG. 3, the divide-by-2 shown in FIG. 11 includes a terminal 4110 to which an output signal from the phase detector 701 or 702 is input, transistors 4010 and 4011, transistors 4020 and 4021, and an inversion. And a logic element 4040.
That is, the outputs of the phase detectors 701 and 702 in FIG. 10 are input to the terminal 4110. When this input signal is high, the current that has passed through the transistor 101 flows to the transistors 4010 and 4011. On the other hand, when the input signals from the phase detectors 701 and 702 are low, the current passing through the transistor 101 flows to the transistors 4020 and 4021. Therefore, compared to when the input signals from the phase detectors 701 and 702 are high. The polarity of the output signal of the frequency dividers 602 and 603 is inverted.

  Returning to FIG. 10, the phase detector 701 detects normal rotation / inversion of the frequency dividers 501 and 601, and outputs the detection result to the frequency divider 602. This ensures that the phase relationship between the divide-by-2 502 and the divide-by-2 602 is either normal or inverted. Subsequently, the phase detector 702 detects the normal phase inversion / inversion of the frequency dividers 502 and 602, and outputs the detection result to the frequency divider 603. This ensures that the phase relationship between the ½ divider 503 and the ½ divider 603 is either normal or inverted.

The frequency divider 50 shown in FIG. 6 forms the frequency divider 50 as shown in FIG. 10, so that the frequency divider 50 shown in FIG. 10 is used as a reference, as in the first embodiment. In this case, the polarity of the output signal from the frequency divider 603 is generated only in positive or negative. As a result, a desired signal can be obtained as the transmission output power of the addition node 8 in FIG.
While the embodiments of the present invention have been described above, the scope of the present invention is not limited to the illustrated and described exemplary embodiments, and provides the same effects as those intended by the present invention. All embodiments are also included. Further, the scope of the invention can be defined by any desired combination of particular features among all the disclosed features.

1 Digital signal processor 3 Digital / analog converter (DA converter)
4 Low-pass filter 5, 5 'Mixer 7 Voltage controlled oscillator (VCO)
8 Addition node 9 Band pass filter 10 Power amplifier 11 Antenna 12 Power detector 13 Analog / digital converter (AD converter)
14 interface circuit 15 phase detector 20 baseband unit 30 IQ quadrature modulator 50 frequency divider 50 ′ frequency divider (frequency divider cell)
100 Constant current source 101, 102, 103 Transistor 104 Load resistance 400 Constant current source 401a, 401b Transistor 402a, 402b, 402c, 402d Transistor 403a, 403b Load resistance 410, 411, 412, 413 Terminal 430 Limiter 431 Inverting logic element 500, 600 Frequency divider cell 501, 502, 503 2 Divider 601, 602, 603 2 Divider 701, 702 Phase detector 900 Constant current source 901, 902, 903 Transistor 904 Load resistor 1001 to 100K Resistor 1011 to 101K Transistor 1021-102K Cascode transistor 1031-103K Transistor 1041-104K Transistor 1050 Inverting logic element 1100, 1101 Baseband input 12 1-120K high-frequency differential input 1301-130K high-frequency differential input 1400, 1401 RF output 1500 operation / non-operation control signal 1501-150K operation / non-operation control signal 1601-160K mixer cell 2000, 2001 frequency divider cell 2002 , 2003 Mixer cell 2004 Addition node 2012-201K transistor 2022-202K transistor 2040 Inverting logic element 2112-211K terminal 3101-310N Frequency divider cell 4010, 4011 transistor 4020, 4021 transistor 4040 Inverting logic element 4110 terminal 5000 Control circuit L1P , L1N differential output signal L2P, L2N differential output signal O1P, O1N differential output signal O2P, O2N differential output signal LOP, LON high frequency differential signal LOIP, LOIN Differential output signal LOQP, LOQN Differential output signal QP, QN Differential output signal Vb Bias voltage VDD Power supply voltage

Claims (8)

A mixer composed of K (K is a natural number of 2 or more) mixer cells arranged in parallel, and a baseband signal is input to each of the K mixer cells;
Outputting a carrier wave signal to the K mixer cells, and a frequency divider composed of N frequency divider cells (N is a natural number of K ≧ N);
A control circuit for outputting a control signal for setting an operating state of the mixer and the frequency divider;
A phase detector for detecting a phase relationship of respective output signals of the N frequency divider cells;
Including
The number N of the frequency divider cells is smaller than the number K of the mixer cells, and the K mixer cells and the N frequency divider cells are connected in a one-to-one or one-to-multiple manner. ,
The control circuit sets an operation state independently of the mixer cell and the frequency divider cell connected to each other,
The transmitter, wherein the mixer cell adjusts the phase of the input baseband signal according to a detection result of the phase detector. A mixer composed of K (K is a natural number of 2 or more) mixer cells arranged in parallel, and a baseband signal is input to each of the K mixer cells;
Outputting a carrier wave signal to the K mixer cells, and a frequency divider composed of N frequency divider cells (N is a natural number of K ≧ N);
A control circuit for outputting a control signal for setting an operating state of the mixer and the frequency divider;
A phase detector for detecting a phase relationship of respective output signals of the N frequency divider cells;
Including
The frequency divider includes a frequency divider cell constituted by a (2 ^ L) frequency divider in which two frequency dividers are connected in series in L stages (L is a natural number of 2 or more), and a plurality of frequency dividers Comprising (L-1) divide-by-2 phase detectors for detecting the phase relationship between the output signals of the detectors,
Of the (L-1) number of the two-divider phase detectors, the M-th stage (M is a natural number of 2 or more) of the two-frequency divider phase detectors is the N frequency components arranged in parallel. Detecting the phase relationship between the output signals of the M-divider in the M-th stage in each of the frequency cells;
The two frequency dividers in the (M + 1) th stage in each of the N frequency frequency divider cells change the phase of the input signal according to the detection result of the Mth frequency divider phase detector. Forward or reverse,
The control circuit sets an operation state independently of the mixer cell and the frequency divider cell connected to each other,
The transmitter, wherein the mixer cell adjusts the phase of the input baseband signal according to a detection result of the phase detector. The number N of the frequency divider cells is the same as the number K of the mixer cells, and the K mixer cells and the N frequency divider cells are connected in a one-to-one relationship. 3. A transmitter as claimed in claim 2 , characterized in that The number N of the frequency divider cells is smaller than the number K of the mixer cells, and the K mixer cells and the N frequency divider cells are connected in a one-to-one or one-to-multiple manner. The transmitter according to claim 2 . The phase detector has (N−1) non-frequency divider cells other than the frequency divider cell on the basis of the phase of the output signal from one of the N frequency divider cells. The transmitter according to any one of claims 1 to 4 , wherein the phase relationship of the frequency divider cell is detected. In the N frequency divider cells, the phase relationship between the output signals of the N frequency divider cells is normal or inverted, and the phase detector has the normal or inverted phase relationship. transmitter according to claim 1, any one of 5, wherein the detecting. The transmitter according to claim 6 , wherein the mixer cell performs normal rotation or inversion of a phase of the input baseband signal according to a detection result of the phase detector. A first mixer having the mixer to which an in-phase (I) baseband signal is input;
A second mixer having the mixer to which a quadrature (Q) baseband signal is input;
The frequency division for generating a first carrier wave signal input to the first mixer and a second carrier wave signal input to the second mixer and having a phase different from that of the first carrier wave signal by 90 degrees. An IQ frequency divider having a counter;
An adder for adding the output signal of the first mixer and the output signal of the second mixer;
The transmitter according to claim 1, comprising:

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