JP5602791B2 - Transmitter - Google Patents

Description

  The present invention relates to a transmitter designed to reduce power consumption, and more specifically, by reducing power consumption of both a mixer and a frequency divider according to a desired transmission output power. The present invention relates to an IQ orthogonal modulation type transmitter in which average power consumption is kept lower than that of a conventional transmitter.

  In recent years, in a transmitter of a portable communication terminal device represented by a mobile phone (hereinafter referred to as “mobile terminal”), the output power of a transmission output signal (hereinafter referred to as “transmission output power”) has a wide variable width. There is a demand for low power consumption. The low power consumption is indispensable for extending the battery of the mobile terminal, and it is important to keep the average power consumption low in the usage state of the mobile terminal that changes every moment. Further, since the power consumption is the product of the current consumption and the power supply voltage, reducing the current consumption means that the power consumption is reduced.

  For example, the transmitter described in Patent Document 1 is a power adjustment type transmitter. In this transmitter, as a means for reducing current consumption, a plurality of modulators arranged in parallel can be operated or not operated without changing the amplitude of the input baseband signal. The transmission output power is realized. In the method of changing the amplitude of the baseband signal in order to achieve the desired transmission output power, the current flowing through the mixer cannot be reduced. However, according to the transmission output power adjustment method described in Patent Document 1, The transmission output power can be adjusted with low current consumption. Thereby, the power consumption calculated | required by the product of a power supply voltage and current consumption can also be reduced.

  By the way, the transmitter described in Patent Document 1 described above includes a baseband unit, an IQ quadrature modulator, a bandpass filter, a power amplifier (PA), an antenna, a power detector, and an interface circuit. The baseband unit includes a digital signal processing unit, a digital / analog converter (DA converter), a low-pass filter, and an analog / digital converter (AD converter). The IQ quadrature modulator includes a voltage controlled oscillation circuit (VCO), a frequency divider, two mixers, and an addition node.

  The two mixers are configured as follows. In other words, the signal from the low-pass filter in the baseband part is input to four mixer cells connected in parallel to the mixer via the effective signal input part of the IQ quadrature modulator. Then, the sum of the currents output from each mixer cell is supplied to four transistors using the local oscillator signal from the local oscillator input unit as the other input via the current mirror. The outputs of the four transistors are output from two high frequency output units.

  Here, in the mixer of Patent Document 1 described above, transmission is performed by connecting or disconnecting each mixer cell with a switch connecting the four mixer cells in accordance with a signal from the control input unit. Output power can be adjusted. Thereby, the transmission output power can be adjusted with less current consumption than the method of adjusting the transmission output power by changing the amplitude of the baseband signal. That is, the average power consumption of the mixer itself can be kept low.

Next, the power consumption of the frequency divider that drives the two mixers in Patent Document 1 will be described. The frequency divider is often realized by a CML (Current Mode Logic) circuit in a high-frequency circuit.
FIG. 6 is a circuit configuration diagram in the case where a conventional divide-by-2 circuit is realized by a CML circuit. The CML circuit shown in FIG. 6 includes N-type MOS (Metal Oxide Semiconductor) transistors 901, 902, and 903, a load resistor 904, and a constant current source 900. This CML circuit receives high-frequency differential signals LOP and LON having a frequency twice the carrier wave frequency as input, differential outputs LOIP and LOIN having the same frequency as the carrier wave frequency, and each of these differential outputs and a 90-degree phase. Output differential outputs LOQP and LOQN.

  Here, the differential outputs LOIP and LOIN are input to one of the two mixers, and the differential outputs LOQP and LOQN are input to the other mixer. When the frequency divider is realized by the divide-by-2 shown in FIG. 6, the capacitive load of the transistor in each mixer, which is the output destination of each of the outputs LOIP, LOIN, LOQP, LOQN of the divide-by-2, is obtained. If CL is R and the resistance value of the load divider 904 of the two-frequency divider is R, the time constant composed of CL and R is R · CL. When the mixer circuit is composed of MOS transistors, the dominant factor of the capacitive load CL is proportional to the area of the gate formed by the gate oxide film of the MOS transistor.

Note that the mathematical formula is simplified by ignoring the parasitic capacitance of the drain of the transistor 902, the parasitic capacitance of the gate of the transistor 903, the parasitic effect of the wiring, and the like shown in FIG.
Assuming that the frequency of the carrier wave is fc and the time constant R · CL needs to be smaller than the period ½ · π · fc, the selection range of the resistance value R is given by the following equation (1): Fulfill.

  Next, assuming that the output amplitude of the outputs LOIP, LOIN, LOQP, and LOQN is V0 at a single-ended peak-to-peak value, the current value I0 of the constant current source 900 takes the above equation (1) into consideration, The following formula (2) is satisfied.

  From the above formulas (1) and (2), it can be seen that the current consumption in the frequency divider increases in proportion to the capacitive load CL of the transistors in the mixer.

Japanese translation of PCT publication No. 2004-534472 (Patent No. 4047274)

  However, when the conventional transmitter is realized by a complementary metal oxide semiconductor (CMOS) circuit, it is possible to suppress the average power consumption of the mixer itself, but it is a carrier wave signal for driving the mixer. The power consumption of the frequency divider that generates the high-frequency signal is irrelevant to the transmission output power, and there is a problem that the average power remains high.

  The present invention has been made in view of such problems, and its object is to reduce the power consumption of both the mixer and the frequency divider according to the desired transmission output power. Another object of the present invention is to provide an IQ quadrature modulation type transmitter in which average power consumption is kept lower than that of a conventional transmitter.

The present invention has been made to achieve such an object, and the invention according to claim 1 is directed to K mixer cells (K is a natural number of 2 or more) arranged in parallel (2002, 2002). , 2003, 2003 '), and a carrier wave signal is output to the K mixer cells and a mixer (5, 5') to which baseband signals are respectively input. , N (N is a natural number with K ≧ N) frequency divider cells (2000) composed of frequency divider cells (2000, 2001), and for setting the operating states of the mixer and the frequency divider A control circuit (5000) for outputting the control signals of the N frequency divider cells, a phase detector (15) for detecting the phase relationship between the output signals of the N frequency divider cells, and a signal input to the frequency divider cells. N-1 capacitive elements (C4) installed in the section N−1 switches (SW1) for connecting / disconnecting or not connecting / connecting the capacitive element according to the operation / non-operation of the frequency divider cell, and the control circuit is connected to each other The mixer cell and the frequency divider cell are set to operate independently, and the mixer cell adjusts the phase of the input baseband signal according to the detection result of the phase detector. It is characterized by doing. (Fig. 1, Fig. 5)
The invention according to claim 2 is the invention according to claim 1, wherein the number N of the frequency divider cells and the number K of the mixer cells are the same, and the K mixer cells. And the N frequency divider cells are connected in a one-to-one relationship.

The invention according to claim 3 is the invention according to claim 1, wherein the number N of the frequency divider cells is smaller than the number K of the mixer cells, and the K mixer cells and the The N frequency divider cells are connected in a one-to-one or one-to-multiple manner.
According to a fourth aspect of the present invention, in the first, second or third aspect of the present invention, the first mixer having the mixer to which the in-phase (I) baseband signal (BIP1, BIN1) is input. 2002, 2003), a second mixer (2002 ′, 2003 ′) having the mixer to which quadrature (Q) baseband signals (BQP1, BQN1) are inputted, and a first mixer inputted to the first mixer. 1 carrier wave signal (LIP1, LIN1, LIP2, LIN2) and a second carrier wave signal (LQP1, LQN1, LQP2, LQN2) which is input to the second mixer and is 90 degrees out of phase with the first high frequency signal. An IQ frequency divider (2000, 2001) having the frequency divider to be generated, and an adder (2004) for adding the output signal of the first mixer and the output signal of the second mixer Characterized in that it comprises and. (Figs. 4 and 5)

  According to the present invention, when the transmission output power is reduced from the maximum, the frequency divider cell paired with the mixer cell constituting the mixer is deactivated together with the mixer, so that the desired transmission output power can be obtained. Accordingly, power consumption in the frequency divider can be suppressed.

1 is a circuit configuration diagram of an IQ quadrature modulation type transmitter according to the present invention. FIG. It is a circuit block diagram which shows an example of the mixer in the transmitter which concerns on this invention. It is a circuit block diagram of the frequency divider in the transmitter which concerns on this invention. It is a circuit block diagram of the IQ orthogonal modulation type transmitter comprised by a frequency divider cell, a mixer cell, and an addition node. It is another circuit block diagram of the IQ orthogonal modulation type transmitter comprised by a frequency divider cell, a mixer cell, and an addition node. It is a circuit block diagram at the time of implement | achieving the conventional 2 frequency divider by the CML circuit.

Embodiments of the present invention will be described below with reference to the drawings.
In each drawing referred to in the following description, the same parts as those in other drawings are denoted by the same reference numerals. All transistors used in the configuration described below are N-type MOS transistors.
FIG. 1 is a circuit configuration diagram of an IQ quadrature modulation type transmitter according to the present invention. An IQ quadrature modulation type transmitter shown in FIG. 1 includes a baseband unit 20, an IQ quadrature modulator 30, a control circuit 5000, a bandpass filter 9, a power amplifier (PA) 10, an antenna 11, a power detector 12, and an interface. The circuit 14 and the phase detector 15 are comprised.

  The baseband unit 20 is connected to an IQ quadrature modulator 30, and the IQ quadrature modulator 30 is connected to the control circuit 5000, the bandpass filter 9, the phase detector 15, and the interface circuit 14. The power amplifier (PA) 10 is connected to the bandpass filter 9, and the antenna 11 is connected to the power amplifier (PA) 10. The power detector 12 is connected to the baseband unit 20 and the power amplifier (PA) 10, and the interface circuit 14 is also connected to the baseband unit 20 and the control circuit 5000.

  That is, the transmitter of the present invention includes at least K (K is a natural number of 2 or more) mixer cells arranged in parallel, and a baseband signal is input to each of the K mixer cells. 5, 5 ′, a carrier wave signal is output to K mixer cells, and a frequency divider 50 including N frequency divider cells (N is a natural number where K ≧ N), 5 ′ and a control circuit 5000 that outputs a control signal for setting the operating state of the frequency divider 50, a phase detector 15 that detects the phase relationship between the output signals of the N frequency divider cells, It has.

  The baseband unit 20 includes a digital signal processing unit (DSP) 1, a digital / analog converter 3 (DAC: DA converter), a low-pass filter 4, and an analog / digital converter 13 (ADC: AD converter). The digital signal processing unit (DSP) 1 is connected to a digital / analog converter 3 and an analog / digital converter 13, and the digital / analog converter 3 is connected to a low-pass filter 4. Each low-pass filter 4 is connected to the mixers 5 and 5 ′ constituting the IQ quadrature modulator 30, and the analog / digital converter 13 is connected to the power detector 12.

  The IQ quadrature modulator 30 includes a voltage controlled oscillation circuit (VCO) 7, a frequency divider 50, two mixers 5, 5 ′, and an addition node 8, and the voltage controlled oscillation circuit (VCO) 7 is The frequency divider 50 is connected to the two mixers 5, 5 ′ and the addition node 8. The addition node 8 is connected to the two mixers 5 and 5 ′ and the band pass filter 9, and the two mixers 5 and 5 ′ are connected to the phase detector 15 and the control circuit 5000, respectively. .

  The differential output from the frequency divider 50 is connected to a high-frequency differential input (high-frequency differential inputs 1201 and 1301 in FIG. 2 described later) of the mixer 5. Similarly, the differential output from the frequency divider 50 is connected to a high frequency differential input (high frequency differential inputs 1201 and 1301 in FIG. 2 described later) of the mixer 5 '. The configurations of the mixers 5 and 5 'and the frequency divider 50 will be described later.

  Further, the control circuit 5000 receives the transmission power setting from the interface circuit 14, and the frequency divider cells inside the frequency divider 50 and the mixer cells of the mixers 5 and 5 ′ Control the operating or non-operating state. Specifically, the control circuit 5000 sends an operation or non-operation control signal to the mixers 5, 5 ′ and the frequency divider 50 according to the transmission power setting from the interface circuit 14 according to a preset control table. Send.

Hereinafter, the operation of the control circuit 5000 will be described.
FIG. 2 is a circuit configuration diagram showing an example of a mixer in the transmitter according to the present invention. However, in FIG. 2, in order to explain only the operation of the control circuit 5000, the circuit portion to which the output signal from the phase detector 15 is input is omitted.
The mixers 5 and 5 ′ shown in FIG. 2 include K mixer cells 1601 to 160K (K is a natural number of 2 or more). The mixer cell 1601 includes an NMOS 1011 for converting each of the baseband inputs 1100 and 1101 from voltage to current, a resistor 1001, a cascode transistor 1021, and a transistor that performs frequency conversion according to the high-frequency differential inputs 1201 and 1301. 1031, a transistor 1041 for setting the gate voltage of the cascode transistor 1021 to the bias voltage Vb or the ground according to the operation / non-operation control signal 1501, and an inverting logic element 1050.

  The operation / non-operation control signal 1501 is a control signal for setting the operation state of the mixer 5 (5 ′) shown in FIG. 2, and is supplied from the control circuit 5000 shown in FIG. 1 to the mixer 5 (5 ′). Is input. When the operation / non-operation control signal 1501 is logically high, a bias voltage Vb is input to the gate of the cascode transistor 1021, and the mixer cell 1601 is appropriately biased (operation state).

On the other hand, when the operation / non-operation control signal 1501 is logically low, the ground voltage is input to the gate of the cascode transistor 1021, and the voltage at the connection point between the resistor 1001 and the transistor 1011 becomes equal to the ground voltage.
Thereby, the electric current which flows into the mixer cell 1601 becomes zero, and the operation | movement is stopped (non-operation). The operation of the mixer cells 1602 to 160K is the same.

FIG. 3 is a circuit configuration diagram of the frequency divider cell 50 ′ in the transmitter according to the present invention. The frequency divider 50 of FIG. 1 can be configured by using N frequency divider cells 50 ′ (N is a natural number of K ≧ N). The frequency divider 50 generates a high-frequency signal for driving the mixers 5 and 5 ′ shown in FIG.
The frequency divider cell 50 ′ shown in FIG. 3 has a configuration of a frequency divider having N-type MOS transistors 101, 102, 103, a load resistor 104, and a constant current source 100, as in FIG. 2, a cascode transistor 1020, a transistor 1040 for setting the gate voltage of the cascode transistor 1020 to the bias voltage Vb or the ground according to the operation / non-operation control signal 1500, and an inverting logic element 1050 are added. It has been done.

Further, the differential outputs LOIP and LOIN of the frequency divider cell 50 ′ shown in FIG. 3 are connected to the high frequency differential inputs 1201 and 1301 shown in FIG. Similarly, the differential outputs LOQP and LOQN are also connected to the high-frequency differential inputs 1201 and 1301 shown in FIG. 2 (the same applies to the high-frequency differential inputs 1202 to 120K and 1302 to 130K).
That is, the frequency divider cell 50 ′ connected to the mixer cell 1601 also stops its operation by setting the current flowing between its power supply and ground to zero in response to the operation / non-operation control signal 1500. Specifically, when the operation / non-operation control signal 1500 is logically high, the constant current source 100 passes a predetermined current, and when the operation / non-operation control signal 1500 is logically low, the constant current source 100 By setting the current of zero to zero, setting of operation or non-operation is realized.

Further, the mixer cells 1602 to 160K in the mixer shown in FIG. 2 have the same structure as the mixer cell 1601. That is, the mixer cells 1602 to 160K are composed of resistors 1002 to 100K, transistors 1012 to 101K, 1022 to 102K, 1032 to 103K, 1042 to 104K, and an inverting logic element 1050.
The operation / non-operation control signals 1501 to 150K input to the mixer cells 1601 to 160K are independently controlled by the control circuit 5000. The high-frequency differential inputs 1201 to 120K and 1301 to 130K are connected to N frequency divider cells in a one-to-one or multiple-to-one manner. That is, the number N of the frequency divider cells 50 ′ is smaller than the number K of the mixer cells 1601 to 160K, and a pair of K frequency divider cells 1601 to 160K and N frequency divider cells 50 ′. One or a plurality of pairs are connected.

Here, K ≧ N. The N frequency divider cells can be realized by installing N frequency divider cells 50 ′ shown in FIG. 3, for example.
By setting a part of the K mixer cells to the non-operating state by the control circuit 5000, a desired transmission output power can be realized without changing the amplitude of the baseband signal. In the method of changing the amplitude of the baseband signal in order to achieve a desired transmission output power, the current flowing through the mixers 5 and 5 ′ cannot be reduced. If the transmission output power is adjusted without changing the amplitude of the transmission output power, the transmission output power can be adjusted with less current consumption.

Further, the frequency divider cell 50 ′ connected to the mixer cells 1601 to 160K set to non-operation is controlled so as to be non-operational, so that it is unnecessarily consumed in the frequency divider cell 50 ′. Current can be reduced. Therefore, the power consumption required by the product of the power supply voltage and the current consumption can also be reduced.
Next, power consumption in the frequency divider 50 of the transmitter according to the present invention will be described. In the following description, for simplicity, the number N of frequency divider cells 50 ′ constituting the frequency divider 50 will be described as being the same as the number K of mixer cells 1601 to 160K. That is, the number N of the frequency divider cells 50 ′ is the same as the number K of the mixer cells 1601 to 160K, and the K mixer cells 1601 to 160K and the N frequency divider cells 50 ′ are one. Connected in a one-to-one relationship.

Note that the transistors 1031 to 103K shown in FIG. 2 to which a high frequency signal is inputted from the frequency divider cell 50 ′ shown in FIG. 3 receive the local oscillator signal from the local oscillator input unit described in Patent Document 1 described above. It corresponds to four transistors as inputs.
In the case of outputting the same current in the mixers 5 and 5 ′ shown in FIG. 2 and the mixer described in Patent Document 1 described above, the current from each mixer cell is passed through the current mirror in Patent Document 1 described above. When the total gate area of the four transistors to which the total current is input is S0, the total gate area of the transistors 1031 to 103K shown in FIG. 2 is S0.

  Here, it is assumed that all the MOS transistors have the same type, the same gate length, and the same high-frequency signal frequency. In Patent Document 1 described above, the current mirror and the four transistors connected to the current mirror are configured in two stages from the ground, while the mixers 5 and 5 ′ in the transmitter according to the present invention have resistances. 1001 and transistors 1011, 1021, 1031 are constituted by multistage connection. However, for simplicity, this point is not considered in terms of power consumption.

  Here, if the mixer cells 1601 to 160K are the same, the area of the transistor 1031 is represented by S0 / K. This indicates that the capacitive load value of the transistor 1031 shown in FIG. 2 according to the present invention is CL / K with respect to the capacitive load value CL of the gates of the four transistors of Patent Document 1 described above. ing. At this time, assuming that the frequency divider (2 divider) cell 50 ′ shown in FIG. 3 is connected to the mixer cell 1601 shown in FIG. The current value I0x is expressed by the following formula (3).

  Here, it is assumed that the high frequency signal output amplitude of the output of the divide-by-2 is a single-ended peak / peak value and V0 is required, and the frequency of the transmission carrier wave is fc. Further, a relationship of I0 = K · I0x is established between the current value I0 of the constant current source of the two-frequency divider that drives the mixer of Patent Document 1 described above and the current value I0x.

  In the present invention, the divide-by-2 is also operated / not operated in accordance with the operation / non-operation of the mixer cells 1601 to 160K. Therefore, when the transmission output power when the K mixer cells 1601 to 160K and the N (= K) frequency divider cells 50 ′ operate is the maximum, in the present invention, the constant of the two dividers is set. The current value of the current source 100 is the same as that in Patent Document 1 described above. On the other hand, the transmission output power is very small, only one of the K mixer cells 1601 to 160K shown in FIG. 2 operates, and only one of the K frequency divider cells 50 ′. In such a situation, the current value of the constant current source 100 is I0x. Compared with Patent Document 1 described above, the current consumption is 1 / K, that is, the power consumption is 1 / K.

As described above, in the present invention, it is possible to reduce the power consumption of the mixer and the frequency divider according to the desired transmission output power.
In place of the mixers 5 and 5 'shown in FIG. 2, a high-frequency input transistor and a baseband input transistor are provided for each mixer cell, and the mixer cells can be controlled to operate / non-operate independently. Other mixers may be used. In this case as well, the average power consumption of the transmitter can be reduced.

  By the way, in the present invention, when switching the operation / non-operation of the K frequency divider cells 50 ′ connected to the voltage controlled oscillator (VCO) 7 shown in FIG. In some cases, the oscillation frequency (fvco) of the voltage controlled oscillator 7 may change instantaneously as the capacitance generated at the output of 7 changes slightly. This instantaneous change in fvco causes an instantaneous change in the transmission output signal frequency, which may prevent correct communication as a transmitter. Therefore, it is preferable to install a circuit that corrects a minute change in capacitance associated with switching between operation / non-operation of the frequency divider cell 50 '.

FIG. 4 is a circuit configuration diagram of an IQ quadrature modulation type transmitter including a frequency divider cell, a mixer cell, and an addition node.
This IQ orthogonal modulation type transmitter includes frequency divider cells 2000 and 2001, mixer cells 2002, 2002 ′, 2003, 2003 ′ and an addition node (adder) 2004, and frequency divider cell 2000 Are connected to mixer cell 2002 and mixer cell 2002 ′, frequency divider cell 2001 is connected to mixer cell 2003 and mixer cell 2003 ′, and summing node 2004 is connected to mixer cell 2002, 2002 ′, 2003, 2003 ′.

  That is, the transmitter shown in FIG. 4 receives first mixers 2002 and 2003 having mixers to which in-phase (I) baseband signals BIP1 and BIN1 are input, and quadrature (Q) baseband signals BQP1 and BQN1. Second mixers 2002 ′ and 2003 ′ having the mixer, first carrier wave signals LIP1, LIN1, LIP2 and LIN2 input to the first mixer, and input to the second mixer, IQ frequency dividers 2000 and 2001 having frequency dividers that generate second carrier wave signals LQP1, LQN1, LQP2, and LQN2 that are 90 degrees out of phase with the high-frequency signal, the output signal of the first mixer, and the second And an adding unit 2004 for adding the output signals of the mixer.

  Each of the frequency divider cells 2000 and 2001 is a frequency divider cell having the same configuration as the frequency divider (two-frequency divider) cell 50 ′ shown in FIG. Reference numerals 2002 ′ and 2003 ′ denote mixer cells having the same configuration as 1601 and 1602 shown in FIG. Here, the oscillation frequency of the voltage controlled oscillator 7 is equal to twice the transmission carrier frequency (fc) because the frequency divider cell 50 'has a frequency division number of two.

  When the frequency divider cells 2000 and 2001 and the mixers 2002, 2003, 2002 ′ and 2003 ′ are in operation, a large transmission output power can be obtained, and the frequency divider cell 2000 and the mixers 2002 and 2002 can be obtained. When 'is in the operating state, a small transmission output power can be obtained. The differential high frequency signal input to the frequency divider cells 2000 and 2001 is the output of the voltage controlled oscillator 7. Therefore, four transistors 101 of the frequency divider 50 ′ are connected to one of the differential outputs of the voltage controlled oscillator 7, and the frequency divider cell 50 ′ is connected to the other of the differential outputs of the voltage controlled oscillator 7. The four transistors 101 are connected.

  The capacitance appearing at the gate terminal of the transistor 101 is expressed by Equation (4) when the transistor 101 operates in the saturation region, and is expressed by Equation (5) when it operates in the triode region.

  Here, W is the gate width. L is the gate length. Cox is a gate capacitance per unit area. Cov is an overlap capacitance between the gate poly and the source or drain region.

  It is assumed that transistor 101 operates in the saturation region when frequency divider cell 50 'is in operation. In addition, when the frequency divider cell 50 'is inactive, the transistor 101 is assumed to operate in the region between the three electrodes. In this case, when the frequency divider cells 2000 and 2001 capable of obtaining a large transmission output are in an operating state, four transistors 101 are connected to each differential high frequency signal output from the voltage controlled oscillator 7. The capacity load is expressed by equation (6).

  Further, when only the frequency divider cell 2000 capable of obtaining a small transmission output is in an operating state, the capacitive load appearing in each differential high frequency signal of the output of the voltage controlled oscillator 7 is expressed by Expression (7). .

  Therefore, when the state changes from a large transmission output to a small transmission output, that is, when the frequency divider cell 2001 is switched from the operating state to the non-operating state, the change in the capacitive load on each high-frequency signal output from the voltage controlled oscillator 7 Is expressed by Expression (7) -Expression (6) = Expression (8).

  Although not shown in FIG. 1, the voltage-controlled oscillator 7 normally operates as part of a PLL (Phase Locked Loop). Here, when the oscillation frequency of the voltage controlled oscillator 7 is an LC resonance type oscillator, it is expressed by the equation (9).

  Here, L is an inductance. C1 is a variable capacitor, and is adjusted to a capacitor that realizes a desired oscillation frequency by a feedback operation of the PLL. C2 is a fixed capacitance component. C3 is an input capacitance of the frequency divider cell 50 ', and its value changes depending on the operation / non-operation of the frequency divider cell 50'.

  When the total capacitance value C1 + C2 + C3 changes instantaneously, the oscillation frequency of the voltage controlled oscillator 7 changes in accordance with the change in capacitance, and a deviation from a desired frequency occurs. After that, the capacitance of C1 is adjusted by the feedback operation of the PLL, and after a predetermined time has elapsed, it returns to the desired oscillation frequency and stabilizes. The time required for the operation of adjusting the capacitance value of C1 is longer as the capacitance load change ΔC shown in Equation (8) is larger, and is longer as the PLL loop bandwidth is narrower. While the capacitance of C1 is being adjusted, the oscillation frequency of the voltage controlled oscillator 7 remains deviated from a desired frequency, and communication as a transmitter may not be performed correctly.

FIG. 5 is another circuit configuration diagram of an IQ quadrature modulation type transmitter composed of a frequency divider cell, a mixer cell, and an addition node, in which a change in capacity is corrected.
That is, the transmitter shown in FIG. 5 is composed of K mixer cells 2002, 2002 ′, 2003, 2003 ′ arranged in parallel (K is a natural number of 2 or more), and is based on K mixer cells. Carrier wave signals are output to the mixers 5 and 5 ′ to which the band signals are respectively input and K mixer cells, and N (N is a natural number of K ≧ N) frequency divider cells 2000 and 2001. The frequency divider 50, the control circuit 5000 that outputs a control signal for setting the operation state of the mixer and the frequency divider, and the phase relationship between the output signals of the N frequency divider cells. The phase detector 15 to detect, the N−1 capacitive elements C4 installed in the signal input section of the frequency divider cell, and the capacitive elements connected / not connected according to the operation / non-operation of the frequency divider cell. N-1 switches connected or not connected / connected The control circuit sets the operation state independently of the mixer cell and the frequency divider cell connected to each other, and the mixer cell is input according to the detection result of the phase detector. Adjust the phase of the baseband signal.

  By installing the correction capacitor element C4 shown in FIG. 5, this instantaneous change in frequency can be prevented. The switch SW1 is on when both the frequency divider cells 2000 and 2001 capable of obtaining a large transmission output are in an operating state, and only the frequency divider cell 2000 capable of obtaining a small transmission output is in an operating state. It is off when there is. Further, the capacitance value of C4 is equal to the value of the change ΔC of the capacitive load in the equation (8). As a result, there is no change in the capacitive load generated at the output of the voltage controlled oscillator 7 at the moment of switching between the small transmission output state and the large transmission output state.

In FIG. 5, the correction capacitor element is realized by a pure capacitor element, but it is also possible to realize this by using a MOS transistor or another element that provides an equivalent effect.
Although the IQ quadrature modulation type transmitter of the present invention has been described above, the technical scope of the present invention is not limited to the illustrated and described exemplary embodiments, and is intended by the present invention. All embodiments that provide the same effect are also included. Further, the technical scope of the present invention may be constituted by any desired combination of specific features among all the disclosed features.

1 Digital signal processor 3 Digital / analog converter (DA converter)
4 Low-pass filter 5, 5 'Mixer 7 Voltage controlled oscillation circuit (VCO)
8 Addition node 9 Band pass filter 10 Power amplifier 11 Antenna 12 Power detector 13 Analog / digital converter (AD converter)
14 interface circuit 15 phase detector 20 baseband unit 30 IQ quadrature modulator 50 frequency divider 50 ′ frequency divider (frequency divider cell)
DESCRIPTION OF SYMBOLS 100 Constant current source 101,102,103 Transistor 104 Load resistance 900 Constant current source 901,902,903 Transistor 904 Load resistance 1001-100K Resistance 1011-101K Transistor 1021-102K Cascode transistor 1031-103K Transistor 1041-104K Transistor 1050 Inversion logic Element 1100, 1101 Baseband input 1201-120K High-frequency differential input 1301-130K High-frequency differential input 1400, 1401 RF output 1500 Operation / non-operation control signal 1501-150K Operation / non-operation control signal 1601-160K Mixer cell 2000, 2001 Frequency divider cell 2002, 2003, 2002 ′, 2003 ′ Mixer cell 2004 Addition node 5000 Control circuit LOP LON High-frequency differential signal LOIP, LOIN Differential output signal LOQP, LOQN Differential output signal Vb Bias voltage SW1 Switch C4 Capacitance element BIP1, BIN1 In-phase (I) baseband signal BQP1, BQN1 Quadrature (Q) baseband signal LIP1, LIN1 , LIP2, LIN2 First carrier wave signal LQP1, LQN1, LQP2, LQN2 Second carrier wave signal

Claims (4)

A mixer composed of K (K is a natural number of 2 or more) mixer cells arranged in parallel, and a baseband signal is input to each of the K mixer cells;
Outputting a carrier wave signal to the K mixer cells, and a frequency divider composed of N frequency divider cells (N is a natural number of K ≧ N);
A control circuit for outputting a control signal for setting an operating state of the mixer and the frequency divider;
A phase detector for detecting a phase relationship of respective output signals of the N frequency divider cells;
N-1 capacitive elements installed in the signal input section of the frequency divider cell;
N−1 switches for connecting / disconnecting or non-connecting / connecting the capacitive element according to the operation / non-operation of the frequency divider cell,
The control circuit sets an operation state independently of the mixer cell and the frequency divider cell connected to each other,
The transmitter, wherein the mixer cell adjusts the phase of the input baseband signal according to a detection result of the phase detector.   The number N of the frequency divider cells and the number K of the mixer cells are the same, and the K mixer cells and the N frequency divider cells are connected one-to-one. The transmitter according to claim 1.   The number N of the frequency divider cells is smaller than the number K of the mixer cells, and the K mixer cells and the N frequency divider cells are connected in a one-to-one or one-to-multiple manner. The transmitter according to claim 1. A first mixer having the mixer to which an in-phase (I) baseband signal is input;
A second mixer having the mixer to which a quadrature (Q) baseband signal is input;
The frequency divider that generates a first carrier wave signal input to the first mixer and a second carrier wave signal that is input to the second mixer and that is 90 degrees out of phase with the first high-frequency signal. An IQ frequency divider comprising:
4. The transmitter according to claim 1, further comprising: an adder that adds the output signal of the first mixer and the output signal of the second mixer. 5.

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