JP2014096614A - Transmitter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transmitter that keeps average power consumption lower than conventional transmitters by achieving reduction in power consumption of both a mixer and a frequency divider according to desired transmission output power.SOLUTION: A transmitter includes: mixer cells 2002, 2002', 2003, and 2003' that are disposed in parallel; frequency divider cells 2000 and 2001; an addition node 2004; a phase detector; a capacitance adjustment voltage generating circuit 2006 generating a capacitance adjustment voltage; and a switch SW1 controlling the connection between the capacitance adjustment voltage and the frequency divider cell 2001. By connecting/disconnecting the capacitance adjustment voltage according to operation/non-operation of the frequency divider, the change in capacitance of a high-frequency signal node is compensated.

Description

  The present invention relates to a transmitter designed to reduce power consumption, and more specifically, by reducing power consumption of both a mixer and a frequency divider according to a desired transmission output power. The present invention relates to an IQ quadrature modulation type transmitter in which the average power consumption is kept lower than that of a conventional transmitter.

  In recent years, in a transmitter of a portable communication terminal device represented by a mobile phone (hereinafter referred to as “mobile terminal”), the output power of a transmission output signal (hereinafter referred to as “transmission output power”) has a wide variable width. There is a demand for low power consumption. The low power consumption is indispensable for extending the battery of the mobile terminal, and it is important to keep the average power consumption low in the usage state of the mobile terminal that changes every moment. Further, since the power consumption is the product of the current consumption and the power supply voltage, reducing the current consumption means that the power consumption is reduced.

  For example, the transmitter described in Patent Document 1 is a power adjustment type transmitter. In this transmitter, as a means for reducing current consumption, a plurality of modulators arranged in parallel can be operated or not operated without changing the amplitude of the input baseband signal. The transmission output power is realized. In the method of changing the amplitude of the baseband signal in order to achieve the desired transmission output power, the current flowing through the mixer cannot be reduced. However, according to the transmission output power adjustment method described in Patent Document 1, The transmission output power can be adjusted with low current consumption. Thereby, the power consumption calculated | required by the product of a power supply voltage and a consumption current can also be reduced.

  By the way, the transmitter described in Patent Document 1 described above includes a baseband unit, an IQ quadrature modulator, a bandpass filter, a power amplifier (PA), an antenna, a power detector, and an interface circuit. The baseband unit includes a digital signal processing unit, a digital / analog converter (DA converter), a low-pass filter, and an analog / digital converter (AD converter). The IQ quadrature modulator includes a voltage controlled oscillation circuit (VCO), a frequency divider, two mixers, and an addition node. In the IQ quadrature modulation, “I” indicates an in-phase component of the waveform, and “Q” indicates a quadrature component.

  The two mixers are configured as follows. In other words, the signal from the low-pass filter in the baseband part is input to four mixer cells connected in parallel to the mixer via the effective signal input part of the IQ quadrature modulator. Then, the sum of the currents output from each mixer cell is supplied to four transistors using the local oscillator signal from the local oscillator input unit as the other input via the current mirror. The outputs of the four transistors are output from two high frequency output units.

  Here, in the mixer of Patent Document 1 described above, transmission is performed by connecting or disconnecting each mixer cell with a switch connecting the four mixer cells in accordance with a signal from the control input unit. Output power can be adjusted. Thereby, the transmission output power can be adjusted with less current consumption than the method of adjusting the transmission output power by changing the amplitude of the baseband signal. That is, the average power consumption of the mixer itself can be kept low.

Next, the power consumption of the frequency divider that drives the two mixers in Patent Document 1 will be described. The frequency divider is often realized by a CML (Current Mode Logic) circuit in a high-frequency circuit.
FIG. 14 is a circuit configuration diagram in the case where a conventional divide-by-2 divider is realized by a CML circuit. The CML circuit shown in FIG. 14 includes N-type MOS (Metal Oxide Semiconductor) transistors 901, 902, and 903, a load resistor 904, and a constant current source 900. This CML circuit receives high-frequency differential signals LOP and LON having a frequency twice the carrier wave frequency as input, differential outputs LOIP and LOIN having the same frequency as the carrier wave frequency, and each of these differential outputs and a 90-degree phase. Output differential outputs LOQP and LOQN.

  Here, the differential outputs LOIP and LOIN are input to one of the two mixers, and the differential outputs LOQP and LOQN are input to the other mixer. When the frequency divider is realized by the divide-by-2 shown in FIG. 14, the capacitive load of the transistor in each mixer, which is the output destination of each of the outputs LOIP, LOIN, LOQP, and LOQN of the divide-by-2, is obtained. If CL is R and the resistance value of the load divider 904 of the two-frequency divider is R, the time constant composed of CL and R is R · CL. When the mixer circuit is composed of MOS transistors, the dominant factor of the capacitive load CL is proportional to the area of the gate formed by the gate oxide film of the MOS transistor.

Here, the mathematical expression is simplified by ignoring the parasitic capacitance of the drain of the transistor 902, the parasitic capacitance of the gate of the transistor 903, and the parasitic effect of the wiring shown in FIG.
Assuming that the frequency of the carrier wave is fc and the time constant R · CL needs to be smaller than the period ½ · π · fc, the selection range of the resistance value R is given by the following equation (1): Fulfill.

  Next, assuming that the output amplitude of the outputs LOIP, LOIN, LOQP, and LOQN is V0 at a single-ended peak-to-peak value, the current value I0 of the constant current source 900 takes the above equation (1) into consideration, The following formula (2) is satisfied.

  From the above formulas (1) and (2), it can be seen that the current consumption in the frequency divider increases in proportion to the capacitive load CL of the transistors in the mixer.

Japanese translation of PCT publication No. 2004-534472 (Patent No. 4047274)

  However, when the conventional transmitter is realized by a complementary metal oxide semiconductor (CMOS) circuit, it is possible to suppress the average power consumption of the mixer itself, but it is a carrier wave signal for driving the mixer. The power consumption of the frequency divider that generates the high-frequency signal is irrelevant to the transmission output power, and there is a problem that the average power remains high.

  The present invention has been made in view of such problems, and its object is to reduce the power consumption of both the mixer and the frequency divider according to the desired transmission output power. Another object of the present invention is to provide an IQ quadrature modulation type transmitter in which average power consumption is kept lower than that of a conventional transmitter.

  The present invention has been made to achieve such an object, and the invention according to claim 1 is directed to K mixer cells (K is a natural number of 2 or more) arranged in parallel (2002, 2002). , 2003, 2003 '), and a carrier wave signal is output to the K mixer cells and a mixer (5, 5') to which baseband signals are respectively input. , N (N is a natural number with K ≧ N) frequency divider cells (2000) composed of frequency divider cells (2000, 2001), and for setting the operating states of the mixer and the frequency divider A control circuit (5000) for outputting the control signals of the N frequency divider cells, a phase detector (15) for detecting the phase relationship between the output signals of the N frequency divider cells, and a signal input to the frequency divider cells. The capacitance adjustment voltage connected to the transistor A capacity adjustment voltage generation circuit (2006) to be formed, and N-1 switches (SW1) for disconnecting / connecting the capacity adjustment voltage according to the operation / non-operation of the frequency divider cell, The control circuit (5000) sets the operation state of the mixer cell and the frequency divider cell connected to each other independently, and the mixer cell is set according to the detection result of the phase detector. The phase of the input baseband signal is adjusted. (Fig. 1, Fig. 6 and Fig. 7)

  According to a second aspect of the present invention, in the first aspect of the present invention, the capacitance adjustment voltage generation circuit (2006) includes a constant current source (42) that supplies a temperature-dependent current, and the frequency component. A constant voltage (Vc) is generated and output using a transistor (46) that is the same type as the input transistor (101) of the peripheral cell.

  According to a third aspect of the present invention, in the first aspect of the invention, the frequency divider cell (60 ') converts a plurality of input voltage signals corresponding to a plurality of frequency bands into current signals. Current signals output from all the VI converters, including VI converters (70, 80) and one IV converter (90) that converts the current signal into an output voltage signal while dividing the frequency. Are connected to the IV converter in common and select one VI converter for passing the current signal and the input voltage signal in accordance with the frequency band of the RF modulation signal to be output. To output signals in a plurality of frequency bands. (FIGS. 10, 11, and 12)

  According to a fourth aspect of the present invention, in the third aspect of the present invention, the VI converter receives the input voltage signal and converts the input voltage signal into the current signal, and the difference. A constant current source (100) that is a tail current of a dynamic pair; a DC addition circuit (71) that generates and adds an input DC voltage of the differential pair; and a node that connects the differential pair and the constant current source; The switch includes a switch (SW1) connected to the capacitance adjustment voltage, and the switch is disconnected / connected according to the operation / non-operation of the frequency divider cell. (Fig. 12)

  According to a fifth aspect of the present invention, in the third aspect of the present invention, the DC addition circuit (71) includes a constant current source and a plurality of resistors, and the constant current source is provided in the VI converter. When a current flows through the constant current source, the DC voltage is generated and applied so that the operating state of the input differential pair in the VI converter is appropriate. When no current flows through the constant current source, a value close to the power supply voltage is generated so that the input differential pair in the VI converter is turned on in a linear region. (Fig. 13)

  According to a sixth aspect of the present invention, in the first or third aspect of the present invention, the number N of the frequency divider cells and the number K of the mixer cells are the same, and the K number of mixed cells is the same. And the N frequency divider cells are connected in a one-to-one relationship.

  The invention according to claim 7 is the invention according to claim 1 or 3, wherein the number N of the frequency divider cells is smaller than the number K of the mixer cells, and the K mixer cells. And the N frequency divider cells are connected in a one-to-one or one-to-multiple manner.

  The invention according to claim 8 is the first mixer having the mixer to which the in-phase (I) baseband signal (BIP1, BIN1) is inputted in the invention according to any one of claims 1 to 7. (2002, 2003), a second mixer (2002 ′, 2003 ′) having the mixer to which a quadrature (Q) baseband signal (BQP1, BQN1) is input, and input to the first mixer A first carrier wave signal (LIP1, LIN1, LIP2, LIN2) and a second carrier wave signal (LQP1, LQN1, LQP2, LQN2) that is input to the second mixer and is 90 degrees out of phase with the first high frequency signal; An IQ frequency divider (2000, 2001) having the frequency divider for generating the signal, and an adder for adding the output signal of the first mixer and the output signal of the second mixer ( Characterized in that it comprises a 004) and. (Figs. 4 and 5)

  According to the present invention, when the transmission output power is reduced from the maximum, the frequency divider cell paired with the mixer cell constituting the mixer is deactivated together with the mixer, so that the desired transmission output power can be obtained. Accordingly, power consumption in the frequency divider can be suppressed.

1 is a circuit configuration diagram of an IQ quadrature modulation type transmitter according to the present invention. FIG. It is a circuit block diagram which shows an example of the mixer in the transmitter which concerns on this invention. It is a circuit block diagram of the frequency divider cell in the transmitter which concerns on this invention. FIG. 4 is a circuit configuration diagram of an IQ quadrature modulation type transmitter composed of a frequency divider cell, a mixer cell, and an addition node shown in FIG. 3. It is a figure showing the relationship between the capacity | capacitance which appears in the gate terminal of a MOS transistor, and bias conditions. It is another circuit block diagram of the frequency divider cell in the transmitter which concerns on this invention. FIG. 7 is another circuit configuration diagram of the IQ quadrature modulation type transmitter including the frequency divider cell, the mixer cell, and the addition node illustrated in FIG. 6. FIG. 8 is a circuit configuration diagram of the capacitance adjustment voltage generation circuit shown in FIG. 7. It is a circuit block diagram of the resistance ladder cell shown in FIG. It is a circuit block diagram of the IQ orthogonal modulation type transmitter corresponding to the several frequency band comprised by a frequency divider cell, a mixer cell, and an addition node. It is a circuit block diagram of the frequency divider corresponding to the several frequency band which concerns on this invention. It is another circuit block diagram of the frequency divider corresponding to the several frequency band which concerns on this invention. FIG. 10 is a circuit configuration diagram of the DC addition circuit shown in FIG. 9. It is a circuit block diagram at the time of implement | achieving the conventional 2 frequency divider by the CML circuit.

Embodiments of the present invention will be described below with reference to the drawings.
In each drawing referred to in the following description, the same parts as those in other drawings are denoted by the same reference numerals. All transistors used in the configuration described below are N-type MOS transistors.
FIG. 1 is a circuit configuration diagram of an IQ quadrature modulation type transmitter according to the present invention. An IQ quadrature modulation type transmitter shown in FIG. 1 includes a baseband unit 20, an IQ quadrature modulator 30, a control circuit 5000, a bandpass filter 9, a power amplifier (PA) 10, an antenna 11, a power detector 12, and an interface. The circuit 14 and the phase detector 15 are comprised.

  The baseband unit 20 is connected to an IQ quadrature modulator 30, and the IQ quadrature modulator 30 is connected to the control circuit 5000, the bandpass filter 9, the phase detector 15, and the interface circuit 14. The power amplifier (PA) 10 is connected to the bandpass filter 9, and the antenna 11 is connected to the power amplifier (PA) 10. The power detector 12 is connected to the baseband unit 20 and the power amplifier (PA) 10, and the interface circuit 14 is also connected to the baseband unit 20 and the control circuit 5000.

  That is, the transmitter of the present invention includes at least K (K is a natural number of 2 or more) mixer cells arranged in parallel, and a baseband signal is input to each of the K mixer cells. 5, 5 ′, a carrier wave signal is output to K mixer cells, and a frequency divider 50 including N frequency divider cells (N is a natural number where K ≧ N), 5 ′ and a control circuit 5000 that outputs a control signal for setting the operating state of the frequency divider 50, a phase detector 15 that detects the phase relationship between the output signals of the N frequency divider cells, It has.

  The baseband unit 20 includes a digital signal processing unit (DSP) 1, a digital / analog converter 3 (DAC: DA converter), a low-pass filter 4, and an analog / digital converter 13 (ADC: AD converter). The digital signal processing unit (DSP) 1 is connected to a digital / analog converter 3 and an analog / digital converter 13, and the digital / analog converter 3 is connected to a low-pass filter 4. Each low-pass filter 4 is connected to the mixers 5 and 5 ′ constituting the IQ quadrature modulator 30, and the analog / digital converter 13 is connected to the power detector 12.

  The IQ quadrature modulator 30 includes a voltage controlled oscillation circuit (VCO) 7, a frequency divider 50, two mixers 5, 5 ′, and an addition node 8, and the voltage controlled oscillation circuit (VCO) 7 is The frequency divider 50 is connected to the two mixers 5, 5 ′ and the addition node 8. The addition node 8 is connected to the two mixers 5 and 5 ′ and the band pass filter 9, and the two mixers 5 and 5 ′ are connected to the phase detector 15 and the control circuit 5000, respectively. .

  The differential output from the frequency divider 50 is connected to a high-frequency differential input (high-frequency differential inputs 1201 and 1301 in FIG. 2 described later) of the mixer 5. Similarly, the differential output from the frequency divider 50 is connected to a high frequency differential input (high frequency differential inputs 1201 and 1301 in FIG. 2 described later) of the mixer 5 '. The configurations of the mixers 5 and 5 'and the frequency divider 50 will be described later.

  Further, the control circuit 5000 receives the transmission power setting from the interface circuit 14, and the frequency divider cells inside the frequency divider 50 and the mixer cells of the mixers 5 and 5 ′ Control the operating or non-operating state. Specifically, the control circuit 5000 sends an operation or non-operation control signal to the mixers 5, 5 ′ and the frequency divider 50 according to the transmission power setting from the interface circuit 14 according to a preset control table. Send.

That is, the control circuit 5000 sets the operation state of the mixer cells 1601 to 160K and the frequency divider cell 50 ′ that are connected to each other independently, and the mixer cells 1601 to 160K detect the phase detector 15. The phase of the input baseband signal is adjusted according to the result.
Hereinafter, the operation of the control circuit 5000 will be described.
FIG. 2 is a circuit configuration diagram showing an example of a mixer in the transmitter according to the present invention. However, in FIG. 2, in order to explain only the operation of the control circuit 5000, the circuit portion to which the output signal from the phase detector 15 is input is omitted.

  1 includes K mixer cells 1601 to 160K (K is a natural number of 2 or more). The mixer cell 1601 includes an NMOS 1011 for converting each of the baseband inputs 1100 and 1101 from voltage to current, a resistor 1001, a cascode transistor 1021, and a transistor that performs frequency conversion according to the high-frequency differential inputs 1201 and 1301. 1031, a transistor 1041 for setting the gate voltage of the cascode transistor 1021 to the bias voltage Vb or the ground according to the operation / non-operation control signal 1501, and an inverting logic element 1050.

  The operation / non-operation control signal 1501 is a control signal for setting the operation state of the mixer 5 (5 ′) shown in FIG. 2, and is supplied from the control circuit 5000 shown in FIG. 1 to the mixer 5 (5 ′). Is input. When the operation / non-operation control signal 1501 is logically high, a bias voltage Vb is input to the gate of the cascode transistor 1021, and the mixer cell 1601 is appropriately biased (operation state).

On the other hand, when the operation / non-operation control signal 1501 is logically low, the ground voltage is input to the gate of the cascode transistor 1021, and the voltage at the connection point between the resistor 1001 and the transistor 1011 becomes equal to the ground voltage.
Thereby, the electric current which flows into the mixer cell 1601 becomes zero, and the operation | movement is stopped (non-operation). The operation of the mixer cells 1602 to 160K is the same.

FIG. 3 is a circuit configuration diagram of a frequency divider cell in the transmitter according to the present invention. The frequency divider 50 of FIG. 1 can be configured by using N frequency divider cells 50 ′ (N is a natural number of K ≧ N). The frequency divider 50 generates a high-frequency signal for driving the mixers 5 and 5 ′ shown in FIG.
The frequency divider cell 50 ′ shown in FIG. 3 has a frequency divider configuration having N-type MOS transistors 101, 102, 103, a load resistor 104, and a constant current source 100, as in FIG. 2, a cascode transistor 1020, a transistor 1040 for setting the gate voltage of the cascode transistor 1020 to the bias voltage Vb or the ground according to the operation / non-operation control signal 1500, and an inverting logic element 1050 are added. It has been done.

Further, the differential outputs LOIP and LOIN of the frequency divider cell 50 ′ shown in FIG. 3 are connected to the high frequency differential inputs 1201 and 1301 shown in FIG. Similarly, the differential outputs LOQP and LOQN are also connected to the high-frequency differential inputs 1201 and 1301 shown in FIG. 2 (the same applies to the high-frequency differential inputs 1202 to 120K and 1302 to 130K).
That is, the frequency divider cell 50 ′ connected to the mixer cell 1601 also stops its operation by setting the current flowing between its power supply and ground to zero in response to the operation / non-operation control signal 1500. Specifically, when the operation / non-operation control signal 1500 is logically high, the constant current source 100 passes a predetermined current, and when the operation / non-operation control signal 1500 is logically low, the constant current source 100 By setting the current of zero to zero, setting of operation or non-operation is realized.

Further, the mixer cells 1602 to 160K in the mixer shown in FIG. 2 have the same structure as the mixer cell 1601. That is, the mixer cells 1602 to 160K are composed of resistors 1002 to 100K, transistors 1012 to 101K, 1022 to 102K, 1032 to 103K, 1042 to 104K, and an inverting logic element 1050.
The operation / non-operation control signals 1501 to 150K input to the mixer cells 1601 to 160K are independently controlled by the control circuit 5000. The high-frequency differential inputs 1201 to 120K and 1301 to 130K are connected to N frequency divider cells in a one-to-one or multiple-to-one manner. That is, the number N of the frequency divider cells 50 ′ is smaller than the number K of the mixer cells 1601 to 160K, and a pair of K frequency divider cells 1601 to 160K and N frequency divider cells 50 ′. One or a plurality of pairs are connected.

Here, K ≧ N. The N frequency divider cells can be realized by installing N frequency divider cells 50 ′ shown in FIG. 3, for example.
By setting a part of the K mixer cells to the non-operating state by the control circuit 5000, a desired transmission output power can be realized without changing the amplitude of the baseband signal. In the method of changing the amplitude of the baseband signal in order to achieve a desired transmission output power, the current flowing through the mixers 5 and 5 ′ cannot be reduced. If the transmission output power is adjusted without changing the amplitude of the transmission output power, the transmission output power can be adjusted with less current consumption.

Further, the frequency divider cell 50 ′ connected to the mixer cells 1601 to 160K set to non-operation is controlled so as to be non-operational, so that it is unnecessarily consumed in the frequency divider cell 50 ′. Current can be reduced. Therefore, the power consumption required by the product of the power supply voltage and the current consumption can also be reduced.
Next, power consumption in the frequency divider 50 of the transmitter according to the present invention will be described. In the following description, for simplicity, the number N of frequency divider cells 50 ′ constituting the frequency divider 50 will be described as being the same as the number K of mixer cells 1601 to 160K. That is, the number N of the frequency divider cells 50 ′ is the same as the number K of the mixer cells 1601 to 160K, and the K mixer cells 1601 to 160K and the N frequency divider cells 50 ′ are one. Connected in a one-to-one relationship.

Note that the transistors 1031 to 103K shown in FIG. 2 to which a high frequency signal is inputted from the frequency divider cell 50 ′ shown in FIG. 3 receive the local oscillator signal from the local oscillator input unit described in Patent Document 1 described above. It corresponds to four transistors as inputs.
In the case of outputting the same current in the mixers 5 and 5 ′ shown in FIG. 2 and the mixer described in Patent Document 1 described above, the current from each mixer cell is passed through the current mirror in Patent Document 1 described above. When the total gate area of the four transistors to which the total current is input is S0, the total gate area of the transistors 1031 to 103K shown in FIG. 2 is S0.

  Here, it is assumed that all the MOS transistors have the same type, the same gate length, and the same high-frequency signal frequency. In Patent Document 1 described above, the current mirror and the four transistors connected to the current mirror are configured in two stages from the ground, while the mixers 5 and 5 ′ in the transmitter according to the present invention have resistances. 1001 and transistors 1011, 1021, 1031 are constituted by multistage connection. However, for simplicity, this point is not considered in terms of power consumption.

  Here, if the mixer cells 1601 to 160K are the same, the area of the transistor 1031 is represented by S0 / K. This indicates that the capacitive load value of the transistor 1031 shown in FIG. 2 according to the present invention is CL / K with respect to the capacitive load value CL of the gates of the four transistors of Patent Document 1 described above. ing. At this time, assuming that the frequency divider (2 divider) cell 50 ′ shown in FIG. 3 is connected to the mixer cell 1601 shown in FIG. The current value I0x is expressed by the following formula (3).

  Here, it is assumed that the high frequency signal output amplitude of the output of the divide-by-2 is a single-ended peak / peak value and V0 is required, and the frequency of the transmission carrier wave is fc. Further, a relationship of I0 = K · I0x is established between the current value I0 of the constant current source of the two-frequency divider that drives the mixer of Patent Document 1 described above and the current value I0x.

  In the present invention, the divide-by-2 is also operated / not operated in accordance with the operation / non-operation of the mixer cells 1601 to 160K. Therefore, when the transmission output power when the K mixer cells 1601 to 160K and the N (= K) frequency divider cells 50 ′ operate is the maximum, in the present invention, the constant of the two dividers is set. The current value of the current source 100 is the same as that in Patent Document 1 described above. On the other hand, the transmission output power is very small, only one of the K mixer cells 1601 to 160K shown in FIG. 2 operates, and only one of the K frequency divider cells 50 ′. In such a situation, the current value of the constant current source 100 is I0x. Compared with Patent Document 1 described above, the current consumption is 1 / K, that is, the power consumption is 1 / K.

As described above, in the present invention, it is possible to reduce the power consumption of the mixer and the frequency divider according to the desired transmission output power.
In place of the mixers 5 and 5 'shown in FIG. 2, a high-frequency input transistor and a baseband input transistor are provided for each mixer cell, and the mixer cells can be controlled to operate / non-operate independently. Other mixers may be used. In this case as well, the average power consumption of the transmitter can be reduced.

  By the way, in the present invention, when switching the operation / non-operation of the K frequency divider cells 50 ′ connected to the voltage controlled oscillator (VCO) 7 shown in FIG. In some cases, the oscillation frequency (fvco) of the voltage controlled oscillator 7 may change instantaneously as the capacitance generated at the output of 7 changes slightly. This instantaneous change in fvco causes an instantaneous change in the transmission output signal frequency, which may prevent correct communication as a transmitter. Therefore, it is preferable to install a circuit that corrects a minute change in capacitance associated with switching between operation / non-operation of the frequency divider cell 50 '.

  FIG. 4 is a circuit configuration diagram of an IQ orthogonal modulation type transmitter including the frequency divider cell, the mixer cell, and the addition node shown in FIG. This IQ orthogonal modulation type transmitter includes frequency divider cells 2000 and 2001, mixer cells 2002, 2002 ′, 2003, 2003 ′ and an addition node (adder) 2004, and frequency divider cell 2000 Are connected to mixer cell 2002 and mixer cell 2002 ′, frequency divider cell 2001 is connected to mixer cell 2003 and mixer cell 2003 ′, and summing node 2004 is connected to mixer cell 2002, 2002 ′, 2003, 2003 ′.

  That is, the transmitter shown in FIG. 4 receives first mixers 2002 and 2003 having mixers to which in-phase (I) baseband signals BIP1 and BIN1 are input, and quadrature (Q) baseband signals BQP1 and BQN1. Second mixers 2002 ′ and 2003 ′ having the mixer, first carrier wave signals LIP1, LIN1, LIP2 and LIN2 input to the first mixer, and input to the second mixer, IQ frequency dividers 2000 and 2001 having frequency dividers that generate second carrier wave signals LQP1, LQN1, LQP2, and LQN2 that are 90 degrees out of phase with the high-frequency signal, the output signal of the first mixer, and the second And an adding unit 2004 for adding the output signals of the mixer.

  Each of the frequency divider cells 2000 and 2001 is a frequency divider cell having the same configuration as the frequency divider (two-frequency divider) cell 50 ′ shown in FIG. Reference numerals 2002 ′ and 2003 ′ denote mixer cells having the same configuration as 1601 and 1602 shown in FIG. Here, the oscillation frequency of the voltage controlled oscillator 7 is equal to twice the transmission carrier frequency (fc) because the frequency divider cell 50 'has a frequency division number of two.

  When the frequency divider cells 2000 and 2001 and the mixers 2002, 2003, 2002 ′ and 2003 ′ are in operation, a large transmission output power can be obtained, and the frequency divider cell 2000 and the mixers 2002 and 2002 can be obtained. When 'is in the operating state, a small transmission output power can be obtained. The differential high frequency signal input to the frequency divider cells 2000 and 2001 is the output of the voltage controlled oscillator 7. Therefore, four transistors 101 of the frequency divider 50 ′ are connected to one of the differential outputs of the voltage controlled oscillator 7, and the frequency divider cell 50 ′ is connected to the other of the differential outputs of the voltage controlled oscillator 7. The four transistors 101 are connected.

FIG. 5 is a diagram showing the relationship between the capacitance appearing at the gate terminal of the MOS transistor and the bias condition. The capacitance appearing at the gate terminal of the transistor 101 can be represented by the sum of the gate-drain capacitance CGD and the gate-source capacitance CGS, and the bias condition (gate-source voltage VGS) is changed according to the curve shown in FIG. Dependent.
In particular, the capacitance appearing at the gate terminal of the transistor 101 is expressed by Equation (4) when the transistor 101 operates in the saturation region, and is expressed by Equation (5) when it operates in the triode region.

2/3 · W · L · Cox + 2 · W · Cov (4)
W ・ L ・ Cox + 2 ・ W ・ Cov (5)
Here, W is the gate width. L is the gate length. Cox is a gate capacitance per unit area. Cov is an overlap capacitance between the gate poly and the source or drain region.
When the frequency divider cell 50 'is in operation, the transistor 101 operates in the saturation region, and when the frequency divider cell 50' is inactive, the transistor 101 operates in the tripolar region. .

  Further, when the frequency divider cell 50 'is in the operating state and the input amplitude reaches a peak, the transistor 101 operates near the triode region. This is particularly noticeable when the power supply voltage is low due to low power consumption and the drain-source voltage is low. In many cases, the frequency divider cell 50 ′ has linearity. Not important and not a problem.

In that case, when the frequency divider cell 50 ′ is in the operating state, the capacitance appearing at the gate terminal of the transistor 101 approaches formula (4) to formula (5), and reaches the value in the curve region shown in FIG. Become.
On the other hand, when the frequency divider cell 50 ′ is in a non-operating state and the potentials of the drain terminal and the source terminal are increased and brought close to the potential of the gate terminal, the capacitance appearing at the gate terminal is The equation (5) approaches the equation (4), and the values in the curve region shown in FIG. 5 are obtained.

In the following, for simplicity of explanation, it is assumed that the transistor 101 operates in the saturation region when the frequency divider cell 50 ′ is in the operating state. Further, it is assumed that the transistor 101 operates in the region between the three electrodes when the frequency divider cell 50 ′ is in a non-operating state.
In this case, when the frequency divider cells 2000 and 2001 capable of obtaining a large transmission output are in an operating state, four transistors 101 are connected to each differential high frequency signal output from the voltage controlled oscillator 7. The capacity load is expressed by equation (6).

8/3 · W · L · Cox + 8 · W · Cov (6)
Further, when only the frequency divider cell 2000 capable of obtaining a small transmission output is in an operating state, the capacitive load appearing in each differential high frequency signal of the output of the voltage controlled oscillator 7 is expressed by Expression (7). .

10/3 · W · L · Cox + 8 · W · Cov (7)
Therefore, when the state changes from a large transmission output to a small transmission output, that is, when the frequency divider cell 2001 is switched from the operating state to the non-operating state, the change in the capacitive load on each high-frequency signal output from the voltage controlled oscillator 7 Is expressed by Expression (7) -Expression (6) = Expression (8).

10/3 · W · L · Cox + 8 · W · Cov
-8/3 · W · L · Cox + 8 · W · Cov
= 2/3 · W · L · Cox (8)
Although not shown in FIG. 1, the voltage-controlled oscillator 7 normally operates as part of a PLL (Phase Locked Loop). Here, when the oscillation frequency of the voltage controlled oscillator 7 is an LC resonance type oscillator, it is expressed by the equation (9).

1 / (2π√L (C1 + C2 + C3)) (9)
Here, L is an inductance. C1 is a variable capacitor, and is adjusted to a capacitor that realizes a desired oscillation frequency by a feedback operation of the PLL. C2 is a fixed capacitance component. C3 is an input capacity of the frequency divider cell 50 ′, and its value changes depending on the operation / non-operation of the frequency divider cell 50 ′.

  When the total capacitance value C1 + C2 + C3 changes instantaneously, the oscillation frequency of the voltage controlled oscillator 7 changes in accordance with the change in capacitance, and a deviation from a desired frequency occurs. After that, the capacitance of C1 is adjusted by the feedback operation of the PLL, and after a predetermined time has elapsed, it returns to the desired oscillation frequency and stabilizes. The time required for the operation of adjusting the capacitance value of C1 is longer as the capacitance load change ΔC shown in Equation (8) is larger, and is longer as the PLL loop bandwidth is narrower. While the capacitance of C1 is being adjusted, the oscillation frequency of the voltage controlled oscillator 7 remains deviated from a desired frequency, and communication as a transmitter may not be performed correctly.

  FIG. 6 is another circuit configuration diagram of the frequency divider cell in the transmitter according to the present invention, in which the change in capacitance is corrected. The frequency divider cell 60 ′ shown in FIG. 6 has the same structure as the frequency divider cell 50 ′ shown in FIG. 3, but the drain terminal and source of the N-type MOS transistor 101 according to the operation / non-operation control signal 1500. A switch SW1 for disconnecting / connecting the capacitance adjustment voltage Vc is added to the terminal.

  That is, the frequency divider cell 60 ′ includes VI converters 70 and 80 that convert a plurality of input voltage signals corresponding to a plurality of frequency bands into current signals, and an output voltage signal while frequency dividing the current signal. One IV converter 90 for conversion, and current signals output from all VI converters are shared and connected to the IV converter, and a set of current signals is set according to the frequency band of the RF modulation signal to be output. By selecting a VI converter for passing a current signal and an input voltage signal, signals in a plurality of frequency bands are output from one output terminal.

  The VI converter receives an input voltage signal and converts it into a current signal, an input differential pair 101, a constant current source 100 that is a tail current of the differential pair, and an input DC voltage of the differential pair. A DC adding circuit 71 to be added, a node connecting the differential pair and the constant current source, and a switch SW1 connected with a capacitance adjustment voltage are connected. The switch SW1 is disconnected according to the operation / non-operation of the frequency divider cell. /Connecting.

FIG. 7 is another circuit configuration diagram of the IQ quadrature modulation type transmitter composed of the frequency divider cell, the mixer cell, and the addition node shown in FIG. is there.
That is, the transmitter shown in FIG. 7 is composed of K mixer cells 2002, 2002 ′, 2003, and 2003 ′ (K is a natural number of 2 or more) arranged in parallel, and is based on the K mixer cells. Carrier wave signals are output to mixers 5 and 5 ′ to which band signals are respectively input and K mixer cells, and N (N is a natural number of K ≧ N) frequency divider cells 2000 and 2005. The frequency divider cell 2005 includes a capacitance adjustment voltage generation circuit 2006 that generates a capacitance adjustment voltage Vc that is input to the frequency divider cell 2001 when the frequency divider cell 2005 is not operating.

The frequency divider cell 2000 is a frequency divider cell having a configuration similar to that of the frequency divider (2 divider) cell 50 ′ shown in FIG. 3, and the frequency divider cell 2005 is shown in FIG. This is a frequency divider cell having the same configuration as the frequency divider (2 divider) cell 60 ′ shown.
By inputting the capacitance adjustment voltage Vc from the capacitance adjustment voltage generation circuit 2006 shown in FIG. 7 to the frequency divider cell 2005, the above-described instantaneous change in frequency can be prevented. The switch SW1 shown in FIG. 6 is in an off state when in an operation state where a large transmission output can be obtained, and is in an on state when in a non-operation state where a small transmission output can be obtained.

The drain of transistor 101 when the capacitance value appearing at the gate terminal of transistor 101 is equal to the capacitance value appearing at the gate terminal during operation when frequency divider cell 60 'shown in FIG. In the following text, the voltage of the terminal and the source terminal is Vevn.
In the capacitance adjustment voltage generation circuit, by generating the capacitance adjustment voltage Vc so that Vc = Vevn, the capacitance generated in the output of the voltage controlled oscillator 7 at the moment of switching between the small transmission output state and the large transmission output state The load does not change.

As described above, when the frequency divider cell 60 is in a non-operating state, the potential at the drain terminal and the source terminal of the transistor 101 is applied from an external circuit, so that the capacitance appearing at the gate terminal can be reduced. Can be equal.
Next, the capacity adjustment voltage generation circuit will be described.
FIG. 8 is a circuit configuration diagram of the capacitance adjustment voltage generation circuit shown in FIG. The capacitance adjustment voltage generation circuit 2006 includes a resistance ladder cell 41, a constant current source 42, a control circuit 43 that outputs a switch selection signal 430 input to the resistance ladder cell 41, and a bias that determines the current value of the constant current source 42. A band gap 44 that outputs 440, a buffer 45, an N-type MOS transistor 46, and a resistor 47 are included.

In other words, the capacity adjustment voltage generation circuit 2006 uses the constant current source 42 that supplies a temperature-dependent current and the transistor 46 that is the same type as the input transistor 101 of the frequency divider cell, to generate a constant voltage (Vc). Generate and output.
FIG. 9 is a circuit configuration diagram of the resistance ladder cell shown in FIG. 8 and shows a pair of the resistance 4101 and the switch SW_m of the resistance ladder cell 41. The resistor ladder cell 41 is configured by connecting n pairs of resistors and switches shown in FIG. 9 in series. Also, all the n resistors 4101 of the resistor ladder cell 41 have the same value, which is Rx. The uppermost resistor-switch pair, that is, the switch of the pair connected to the power supply voltage is SW_1, and the m-th pair of switches connected in series is numbered sequentially as SW_m.
When the power supply voltage is represented by VDD and the switch that is turned on in the resistance ladder cell 41 by the control circuit 43 is SW_m, the input voltage Vcx of the buffer 45 follows the equation (10).

Vcx = VDD−Idc · m · Rx (10)
The buffer 45 is a negative operational amplifier connected to a general operational amplifier, and obtains an output voltage by multiplying the input voltage by one. The N-type MOS transistor 46 is diode-connected, that is, connected so that the gate voltage and the drain voltage have the same potential. When the resistance 47 is sufficiently large, Vc is approximately given by Vcx−Vth. However, Vth represents the threshold voltage of the N-type MOS transistor 46.
Accordingly, the capacitance adjustment voltage Vc output from the capacitance adjustment voltage generation circuit 2006 follows the equation (11).

VDD-Idc.m.Rx-Vth (11)
On the other hand, since the capacitance adjustment voltage Vc is required to be Vevn, the resistance value Rx and the constant current Idc are set so that the equation (11) becomes equal to Vevn.

Even if Vevn fluctuates due to individual variations in manufacturing or changes in temperature, the switch turned on in the resistance ladder cell 41 is changed by the control circuit 43 to change m in the equation (11). At any time, equation (11) can be made equal to Vevn.
However, by using the same type of transistor as the transistor 101 in FIG. 6 as the N-type MOS transistor 46, it is possible to change the equation (V) without changing m with respect to individual variations in manufacturing and fluctuations in Vevn due to temperature changes. The value given in 11) can be made to follow.

Parameters such as the threshold voltage of MOS transistors vary from individual to individual, with various values centered on ideal design values, and also vary with temperature changes. These parameters can be expected to vary in roughly the same trend.
For example, when the threshold voltage of the transistor 101 in FIG. 6 is increased, the potential difference between the drain and the source when the drain current flows through the transistor 101 in the operating state is decreased, and the voltage of the source terminal is increased. Accordingly, the capacitance appearing at the gate terminal of the transistor 101 at that time shifts to the right on the triode region side in the curved region shown in FIG. On the other hand, when the threshold voltage Vth of the N-type MOS transistor 42 in FIG. 8 is increased, the capacitance adjustment voltage Vc is decreased from the equation (11).

That is, the potential difference between the gate and the source in the non-operating state of the transistor 101 in FIG. 6 increases. Accordingly, the capacitance appearing at the gate terminal of the transistor 101 at that time shifts to the right on the triode region side in the curved region shown in FIG.
Thus, even if Vevn varies due to the variation of the threshold voltage of the N-type MOS transistor, Vc given by equation (11) also varies in the same tendency.

  Also, for individual variations in resistance values and temperature changes, if the current flowing through the constant current source is generated by a certain reference voltage and resistance, the same type of resistance can be used within the same chip. Therefore, the product of the resistance value and the current can be expected to be constant. This is a generally used technique, and applies to the current Idc of the constant current source 42 generated by the band gap 44 shown in FIG. 8 and the resistance Rx of the resistance ladder 41. The relationship between the current of the constant current source 100 and the resistor 104 in FIG.

In addition to the above, the temperature dependence of the capacitance adjustment voltage Vc is further increased by giving the temperature dependence of the bias 440 applied to the constant current source 42 in the band gap 44 in FIG. By adjusting, it is possible to follow the variation of Vevn due to the temperature change more accurately.
Next, a description will be given of a circuit configuration and operation in a case where a change in capacity is corrected in a transmitter corresponding to a plurality of frequency bands (bands).

FIG. 10 is another circuit configuration diagram of an IQ orthogonal modulation type transmitter composed of a frequency divider cell, a mixer cell, and an addition node, corresponding to a plurality of frequency bands (bands), and The capacitance change is corrected.
The transmitter shown in FIG. 10 outputs RF modulation signals in frequency bands of band A and band B, and K (K is a natural number of 2 or more) mixer cells 2002, 2002 ′, and 2003 arranged in parallel. , 2003 ′, and the carrier wave signals are output to the mixers 5 and 5 ′ in which the baseband signals are respectively input to the K mixer cells and the K mixer cells, and N (N is K ≧≧). N natural number) IV converter cells 3000 and 3001, VI converter cells 3002 and 3002 ′ for converting a high-frequency signal A corresponding to band A into a current signal, and a high-frequency signal B corresponding to band B as a current signal It comprises a VI converter cell 3003, 3003 ′ to be converted, and a capacity adjustment voltage generation circuit 3006 for generating a capacity adjustment voltage Vc to be input to the VI converter cells 3002 ′ and 3003 ′.

The IV converter cell 3000 is connected to the VI converter cell 3002 and the VI converter cell 3004, and the IV converter cell 3001 is connected to the VI converter cell 3003 and the VI converter cell 3005.
When the IV converter cells 3000 and 3001 and the VI converter cells 3002 and 3002 ′ are in an operating state and the VI converter cells 3003 and 3003 ′ are in an inactive state, a large transmission output power of an RF modulation signal of band A is obtained. When only IV converter cell 3000 and VI converter cell 3002 are in operation, and IV converter cell 3001, VI converter cell 3002 ′ and VI converter cells 3003, 3003 ′ are inactive, A small transmission output power of the band A RF modulation signal can be obtained.

  When the IV converter cells 3000 and 3001 and the VI converter cells 3003 and 3003 ′ are in operation and the VI converter cells 3002 and 3002 ′ are inactive, a large transmission output power of the band B RF modulation signal is obtained. When only the IV converter cell 3000 and the VI converter cell 3003 are in operation, and the IV converter cell 3001, VI converter cell 3003 ′ and the VI converter cells 3002, 3002 ′ are inactive, A small transmission output power of the band B RF modulation signal can be obtained.

FIG. 11 is a circuit configuration diagram of a frequency divider corresponding to a plurality of frequency bands according to the present invention, and shows a circuit configuration of an IV converter 70 and two VI converters 80 and 90 in the transmitter according to the present invention. ing.
The IV converter cells 3000 and 3001 have a circuit configuration similar to that of the IV converter 70, the VI converter cell 3002 has a circuit configuration similar to that of the VI converter 80, and the VI converter cell 3003 includes a VI converter. The circuit configuration is the same as 90. Each circuit configuration in which the IV converter 70 is connected to the VI converter 80 or the VI converter 90 is the same circuit configuration as the frequency divider 50 ′ shown in FIG. When the VI converter 80 is in a non-operating state, no current flows through the constant current source 810. When the VI converter 90 is not operating, no current flows through the constant current source 910.

FIG. 12 is another circuit configuration diagram of a frequency divider corresponding to a plurality of frequency bands according to the present invention, and shows an IV converter 70 and two VI converters 80 ′ and 90 ′ in the transmitter according to the present invention. The circuit configuration is shown.
The IV converter 70 has the same circuit configuration as the IV converter 70 in FIG. 11, the VI converter cell 3002 ′ has the same circuit configuration as the VI converter 80 ′, and the VI converter cell 3003 ′ The circuit configuration is the same as that of the VI converter 90 ′. Each circuit configuration in which the IV converter 70 is connected to the VI converter 80 ′ or the VI converter 90 ′ is a circuit configuration in which the switch SW1 connected to the drain voltage of the transistor 101 is deleted from the frequency divider 60 shown in FIG. Be the same. When the VI converter 80 ′ is inactive, no current flows through the constant current source 820. When the VI converter 90 ′ is inactive, no current flows through the constant current source 920.

The VI converters 80 ′ and 90 ′ have DC addition circuits 81 and 91 at their input units, respectively, remove DC components of the input high-frequency signal, and add appropriate DC voltages. The DC addition circuit is not specified in the input sections of the VI converters 80 and 90 and the frequency divider cells 50 and 50 ′ described above, but may be provided.
Therefore, the carrier frequency of band A is obtained by dividing the high frequency signal A by 2, and the carrier frequency of band B is obtained by dividing the high frequency signal B by 2.

The switch SW1 is in an off state when it is in an operating state where a large transmission output can be obtained, and is in an on state when it is in a non-operating state where a small transmission output can be obtained regardless of the band of the RF modulation signal to be output. .
Next, a DC voltage applied to the gate terminals of the transistors 821 and 921 will be described.

  FIG. 13 is a circuit configuration diagram of the DC addition circuit shown in FIG. 9 and shows a circuit configuration of the DC addition circuit 71. The DC addition circuit 71 includes a constant current source 713 that generates a DC voltage, resistors 711 and 712, a capacitor 715 that removes DC components of the input high-frequency signals LOP ′ and LON ′, and a high-frequency signal from which the DC components have been removed. The resistor 714 supplies the DC voltage Vdc.

The DC addition circuit 71 has the same circuit configuration as the DC addition circuit 91 and the DC addition circuit 91 in the VI converter 80 ′ shown in FIG.
That is, the DC addition circuit 71 includes a constant current source and a plurality of resistors. The constant current source operates / not operates according to the operation / non-operation of the VI converter, and when a current flows through the constant current source, When a DC voltage is generated and applied so that the operating state of the input differential pair in the VI converter is appropriate and no current flows through the constant current source, the input differential pair in the VI converter is turned on in the linear region. A value close to the power supply voltage is generated.

  When the VI converter is in an operating state, a constant current flows through the constant current source 713 in the DC addition circuit 71 associated therewith, and the current flows through the resistors 711 and 712. At this time, the current of the current source 713 and the values of the resistors 711 and 712 are set as the DC voltage Vdc so that the input transistor of the VI converter is in an appropriate operation state. When the VI converter is in a non-operating state, no current flows through the constant current source 713 in the accompanying bias circuit 71, and the DC voltage Vdc becomes a high potential close to the power supply voltage.

  Therefore, the DC voltage input to the gate terminal of the transistor 821 is given an appropriate potential in an operation state in which a large transmission output of the RF modulation signal of band A can be obtained, and the band of the RF modulation signal to be output is given. Regardless, in a non-operating state where a small transmission output can be obtained, a high potential close to the power supply voltage is applied. The DC voltage input to the gate terminal of the transistor 921 is given an appropriate potential in an operation state in which a large transmission output of the band B RF modulation signal can be obtained, regardless of the band of the output RF modulation signal. In a non-operating state in which a small transmission output can be obtained, a high potential close to the power supply voltage is given.

  In an operation state in which a small transmission output of the RF modulation signal of band A can be obtained, the capacitance adjustment voltage Vc is connected to the source terminal of the transistor 821 only through the switch SW1. The capacitance adjustment voltage Vc is connected to the drain voltage of the transistor 821 through the switch SW1 and the transistor 921. At this time, the DC voltage applied to the gate terminal of the transistor 921 is a high potential, and the high-frequency signal B is not input. Therefore, the transistor 921 is in an on state.

  In an operation state in which a small transmission output of the band B RF modulation signal can be obtained, the capacitance adjustment voltage Vc is connected to the source terminal of the transistor 921 only through the switch SW1. The capacitance adjustment voltage Vc is connected to the drain voltage of the transistor 921 through the switch SW1 and the transistor 821. At this time, the DC voltage supplied to the gate terminal of the transistor 821 is a high potential, and the high-frequency signal A is not input. Therefore, the transistor 821 is in an on state.

  When the VI converter 80 ′ or the VI converter 90 ′ is in an operating state, if the load capacity of each drain terminal of the transistors 821 and 921 is large, characteristic degradation such as a decrease in the limit frequency that can be divided occurs. . However, as described above, the switch SW1 is not connected to the drain terminals of the transistors 821 and 921, and the transistor 921 functions as the switch for the transistor 821 and the transistor 821 functions as the switch for the transistor 921. The effect of not adding an extra load capacity in the state is obtained.

  Although the IQ quadrature modulation type transmitter of the present invention has been described above, the technical scope of the present invention is not limited to the illustrated and described exemplary embodiments, and is intended by the present invention. All embodiments that provide the same effect are also included. Further, the technical scope of the present invention may be constituted by any desired combination of specific features among all the disclosed features.

1 Digital signal processor 3 Digital / analog converter (DA converter)
4 Low-pass filter 5, 5 'Mixer 7 Voltage controlled oscillation circuit (VCO)
8 Addition node 9 Band pass filter 10 Power amplifier 11 Antenna 12 Power detector 13 Analog / digital converter (AD converter)
14 interface circuit 15 phase detector 20 baseband unit 30 IQ quadrature modulator 40 capacity adjustment voltage generation circuit (capacitance adjustment voltage generation circuit cell)
41 resistor ladder cell 42 constant current source 43 control circuit 44 band gap 45 buffer 46 N-type MOS transistor 47 resistor 410 resistor ladder 4101 resistor 4102 switch 50 frequency divider 50 ′ frequency divider (frequency divider cell)
60 'frequency divider (frequency divider cell)
100, 810, 910, 820, 920 Constant current source 101, 102, 103, 811, 911, 821, 921 Transistor 104 Load resistance 900 Constant current source 901, 902, 903 Transistor 904 Load resistance 1001-100K Resistance 1011-101K Transistor 1021 to 102K Cascode transistors 1031 to 103K Transistors 1041 to 104K Transistor 1050 Inverting logic elements 1100 and 1101 Baseband inputs 1201 to 120K High frequency differential inputs 1301 to 130K High frequency differential inputs 1400 and 1401 RF outputs 1500 Operation / non-operation control signal 1501 ~ 150K operation / non-operation control signal 1601 ~ 160K mixer cell 2000, 2001, 2005 frequency divider cell 2002, 2003, 2002 ', 2003 'mixer cell 2004 addition node 2006 capacity adjustment voltage generation circuit 3000, 3001 IV converter cell 3002, 3002', 3003, 3003 'VI converter cell 70 IV converter 80, 90, 80', 90 'VI converter 71 DC additional circuit 711, 712 Resistor 713 Constant current source 714 Resistor 715 Capacitor 81, 91 DC additional circuit cell 5000 Control circuit LOP, LON High frequency differential signal LOIP, LOIN Differential output signal LOQP, LOQN Differential output signal Vb Bias voltage SW1 switch BIP1, BIN1 In-phase (I) baseband signal BQP1, BQN1 Quadrature (Q) baseband signal LIP1, LIN1, LIP2, LIN2 First carrier wave signal LQP1, LQN1, LQP2, LQN2 Second carrier wave signal

Claims (8)

A mixer composed of K (K is a natural number of 2 or more) mixer cells arranged in parallel, and a baseband signal is input to each of the K mixer cells;
Outputting a carrier wave signal to the K mixer cells, and a frequency divider composed of N frequency divider cells (N is a natural number of K ≧ N);
A control circuit for outputting a control signal for setting an operating state of the mixer and the frequency divider;
A phase detector for detecting a phase relationship of respective output signals of the N frequency divider cells;
A capacitance adjustment voltage generation circuit for generating a capacitance adjustment voltage connected to the signal input transistor of the frequency divider cell;
N−1 switches that disconnect / connect the capacitance adjustment voltage according to the operation / non-operation of the frequency divider cell;
The control circuit sets an operation state independently of the mixer cell and the frequency divider cell connected to each other,
The transmitter, wherein the mixer cell adjusts the phase of the input baseband signal according to a detection result of the phase detector.   The capacitance adjustment voltage generation circuit generates and outputs a constant voltage using a constant current source that supplies a temperature-dependent current and a transistor that is the same type as the input transistor of the frequency divider cell. The transmitter of claim 1, characterized in that: The frequency divider cell includes a VI converter that converts a plurality of input voltage signals corresponding to a plurality of frequency bands into current signals, and one IV that converts the current signals into output voltage signals while dividing the frequency. Including a converter,
The current signals output from all the VI converters are shared and connected to the IV converter, and the VI converter and the input that pass a set of the current signals according to the frequency band of the RF modulation signal to be output The transmitter according to claim 1, wherein a signal of a plurality of frequency bands is output from one output terminal by selecting a voltage signal.   The VI converter generates an input differential pair that receives the input voltage signal and converts it into the current signal, a constant current source that is a tail current of the differential pair, and an input DC voltage of the differential pair. And a switch connecting the capacitance adjusting voltage to the node connecting the differential pair and the constant current source, the switch depending on the operation / non-operation of the frequency divider cell. 4. The transmitter according to claim 3, wherein the transmitter is disconnected / connected.   The DC additional circuit includes a constant current source and a plurality of resistors. The constant current source operates / inactivates according to the operation / non-operation of the VI converter, and when a current flows through the constant current source When a DC voltage is generated and applied so that the operating state of the input differential pair in the VI converter becomes appropriate, and no current flows through the constant current source, the input differential in the VI converter 4. The transmitter according to claim 3, wherein the transmitter generates a value close to the power supply voltage so that the pair is turned on in a linear region.   The number N of the frequency divider cells and the number K of the mixer cells are the same, and the K mixer cells and the N frequency divider cells are connected one-to-one. The transmitter according to claim 1 or 3.   The number N of the frequency divider cells is smaller than the number K of the mixer cells, and the K mixer cells and the N frequency divider cells are connected in a one-to-one or one-to-multiple manner. The transmitter according to claim 1, wherein: A first mixer having the mixer to which an in-phase (I) baseband signal is input;
A second mixer having the mixer to which a quadrature (Q) baseband signal is input;
The frequency divider that generates a first carrier wave signal input to the first mixer and a second carrier wave signal that is input to the second mixer and that is 90 degrees out of phase with the first high-frequency signal. An IQ frequency divider comprising:
The transmitter according to claim 1, further comprising: an adder that adds the output signal of the first mixer and the output signal of the second mixer.

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