JP5608350B2 - Selective silicide formation method and semiconductor device - Google Patents

Description

The present invention relates to a selective silicide formation method and a semiconductor device.

  In order to obtain a transistor having a low operating voltage and good performance, miniaturization based on a scaling law is performed. When the gate length, gate width, and thickness of the gate insulating film of the transistor are reduced due to miniaturization, parasitic resistance such as electric resistance of the gate electrode and electric resistance of the diffusion layer increases. In order to overcome this situation, a silicide containing a metal such as titanium (Ti) or cobalt (Co) is formed on the surface of the gate electrode or the diffusion layer to lower the electric resistance.

  A salicide technique for forming silicide in a self-aligned manner with respect to a gate electrode or a diffusion layer is also known (for example, Patent Document 1).

Japanese Patent Laid-Open No. 10-144625

  However, generally, in order to form silicide, a high temperature treatment of 600 ° C. to 800 ° C. is necessary.

  In addition, the salicide technology has an advantage that the silicide can be formed in a self-aligned manner with respect to the gate electrode and the diffusion layer, so that there is an advantage that the processing can be simplified, but the unreacted material remaining on the silicon oxide film without being silicided. It is necessary to dissolve and remove the metal film with a chemical solution, which increases the number of wet cleaning steps.

The present invention has been made in view of the above circumstances, and a selective silicide formation method capable of forming silicide at a lower temperature without increasing the wet cleaning process, and the selective formation method. Provided is a semiconductor device formed by using a silicide formation method.

In order to solve the above-described problem, a selective silicide formation method according to the first aspect of the present invention is a silicide formation method in which silicide is formed on a substrate on which silicon and silicon oxide are exposed. The temperature of the substrate is set to 400 ° C. or higher, a manganese organic compound gas is supplied onto the surface of the substrate where the silicon and the silicon oxide are exposed, and the silicon exposed on the surface of the substrate is Manganese silicide is selectively formed, and a manganese oxide film is formed on the silicon oxide .

A selective silicide formation method according to a second aspect of the present invention is a silicide formation method for forming silicide on a substrate having silicon and silicon oxide exposed on the surface, wherein the temperature of the substrate is as 400 ° C. or higher, by supplying a manganese organic compound gas onto the surface of the substrate between the silicon and the silicon oxide is exposed, selectively manganese metal on the silicon exposed on the surface of the substrate The substrate is heated at a temperature of 400 ° C. or more, the metal manganese is reacted with the silicon exposed on the surface of the substrate, the silicon is converted into manganese silicide, and the silicon oxide is formed. A manganese oxide film is formed thereon .

A semiconductor device according to a third aspect of the present invention includes a silicon substrate, an element isolation region formed in the silicon substrate and defining an element region on a surface of the silicon substrate, and containing the silicon oxide, and the element region A source diffusion layer and a drain diffusion layer formed therein, and a gate electrode formed on the element region between the source diffusion layer and the drain diffusion layer and electrically insulated from the element region; wherein the source diffusion layer, and a portion of the drain diffusion layer, viewed contains manganese silicided regions, manganese oxide layer is formed on the isolation region.

According to the present invention, a selective silicide forming method capable of forming a silicide at a lower temperature without increasing the wet cleaning step, and the selective silicide forming method are used. A semiconductor device can be provided.

Sectional drawing which shows roughly an example of the film-forming apparatus which can implement the formation method of the silicide which concerns on 1st Embodiment of this invention Sectional drawing which shows an example of the formation method of the silicide which concerns on 1st Embodiment of this invention The top view which shows roughly an example of the film-forming system which can implement the formation method of the silicide which concerns on 2nd Embodiment of this invention Sectional drawing which shows roughly an example of the heat processing apparatus which can implement the formation method of the silicide which concerns on 2nd Embodiment of this invention Sectional drawing which shows an example of the formation method of the silicide which concerns on 2nd Embodiment of this invention Sectional drawing which shows the semiconductor device which concerns on 3rd Embodiment of this invention

  Embodiments of the present invention will be described below with reference to the accompanying drawings. In this description, the same parts are denoted by the same reference symbols throughout the drawings to be referred to.

(First embodiment)
The first embodiment is a silicide formation method for forming a silicide on a substrate having silicon and silicon oxide exposed on the surface, wherein the silicon exposed on the surface of the substrate is selectively and directly formed. This is an example of silicidation.

(Device configuration)
FIG. 1 is a cross-sectional view schematically showing an example of a film forming apparatus capable of performing the silicide forming method according to the first embodiment of the present invention. In this example, as an example of a film forming apparatus, a thermal CVD apparatus that forms a film on a substrate to be processed, for example, a semiconductor wafer (hereinafter referred to as a wafer) using a thermal CVD method is illustrated. The film forming apparatus is not limited to a thermal CVD apparatus.

  As shown in FIG. 1, the thermal CVD apparatus 10 has a processing chamber 11. A mounting table 12 for mounting the wafer W horizontally is provided in the processing chamber 11. In the mounting table 12, a heater 12a, which is a temperature adjusting means for the wafer W, is provided. The heater 12a is provided with a temperature measuring means (not shown), for example, a thermocouple, for controlling the temperature. The mounting table 12 is provided with three lifter pins 12c (only two are shown for convenience) that can be moved up and down by a lifting mechanism 12b. The wafer W is moved up and down using the lifter pins 12c, and the wafer W is transferred between the wafer transfer means (not shown) and the mounting table 12.

  One end of an exhaust pipe 13 is connected to the bottom of the processing chamber 11, and an exhaust device 14 is connected to the other end of the exhaust pipe 13. A transfer port 15 that is opened and closed by a gate valve G is formed on the side wall of the processing chamber 11.

  A gas shower head 16 facing the mounting table 12 is provided on the ceiling of the processing chamber 11. The gas shower head 16 includes a gas chamber 16a, and the gas supplied to the gas chamber 16a is supplied into the processing chamber 11 through a plurality of gas discharge holes 16b.

  The gas shower head 16 is connected to a source gas supply piping system 17 for introducing a source gas, for example, a gas containing a manganese organic compound, into the gas chamber 16a.

The source gas supply piping system 17 includes a source gas supply path 17a. A raw material reservoir 18 is connected upstream of the raw material gas supply path 17a. The raw material reservoir 18 stores a manganese raw material, for example, a manganese organic compound. In this example, a cyclopentadienyl manganese organic compound, for example, (EtCp) ₂ Mn (bisethylcyclopentadienyl manganese) 18a is stored in a liquid state as the manganese organic compound. (EtCp) ₂ Mn is a manganese precursor. A bubbling mechanism 19 is connected to the raw material reservoir 18.

The bubbling mechanism 19 includes, for example, a bubbling gas reservoir 19a in which bubbling gas is stored, a bubbling gas supply pipe 19b that guides the bubbling gas to the raw material reservoir 18, and a bubbling that flows in the bubbling gas supply pipe 19b. A mass flow controller (MFC) 19c for adjusting the flow rate of the working gas and a valve 19d are included. Examples of the bubbling gas include argon (Ar) gas, hydrogen (H ₂ ) gas, and nitrogen (N ₂ ) gas. One end of the bubbling gas supply pipe 19b is disposed in the raw material liquid stored in the raw material storage section 18, in this example, (EtCp) ₂ Mn. By blowing the bubbling gas from the bubbling gas supply pipe 19b, the raw material liquid is bubbled and vaporized. The vaporized source gas, (EtCp) ₂ Mn, which is vaporized in this example, is supplied to the gas chamber 16a via the source gas supply path 17a and the valve 17b that opens and closes the source gas supply path 17a. The bubbling gas is also used as a carrier gas.

  Note that the method of supplying the source gas is not limited to the bubbling method in which the source liquid is bubbled and vaporized as described above, and the so-called liquid that feeds the source liquid to the vaporizer and vaporizes the source liquid using the vaporizer. It is also possible to use a feeding method.

  A preflow line 20 connected to the exhaust device 14 is connected between the valve 17 b and the raw material reservoir 18. The preflow line 20 is provided with a valve 20a. Until the bubbling flow rate of the source gas is stabilized, the valve 17b is closed and the valve 20a is opened, so that the source gas flows through the preflow line 20. When the bubbling flow rate is stable and the supply timing of the source gas is reached, the valve 20a is closed and the valve 17b is opened, so that the source gas flows into the source gas supply path 17a.

  A purge mechanism 21 is connected between the valve 17b and the gas chamber 16a.

The purge mechanism 21 flows through, for example, a purge gas storage unit 21a in which a purge gas is stored, a purge gas supply pipe 21b that guides the purge gas to the source gas supply path 17a, and a purge gas supply pipe 21b. It includes a mass flow controller (MFC) 21c that adjusts the flow rate of the purge gas, and valves 21d and 21e. The valve 21d is provided between the purge gas reservoir 21a and the mass flow controller 21c, and the valve 21e is provided between the source gas supply path 17a and the mass flow controller 21c. Examples of the purge gas include argon (Ar) gas, hydrogen (H ₂ ) gas, and nitrogen (N ₂ ) gas. When purging the inside of the source gas supply path 17a, the inside of the gas chamber 16a, and the inside of the processing chamber 11, the valve 17b is closed and the valves 21d and 21e are opened so that the purge gas is supplied to the source gas supply path. It is made to flow through 17a through the purge gas supply pipe 21b. The purge gas can also be used as a bubbling gas for the source gas. That is, the bubbling gas reservoir 19a and the purge gas reservoir 21a may have a common configuration.

  The control unit 23 controls the thermal CVD apparatus 10. The control unit 23 includes a process controller 23a, a user interface 23b, and a storage unit 23c. The user interface 23 b includes a keyboard on which a process manager manages command input to manage the thermal CVD apparatus 10, a display that visualizes and displays the operating status of the thermal CVD apparatus 10, and the like. The storage unit 23c stores a recipe in which a control program, drive condition data, and the like for realizing the processing by the thermal CVD apparatus 10 are controlled by the process controller 23a. The recipe is called from the storage unit 23c according to an instruction from the user interface 23b as necessary, and the thermal CVD apparatus 10 is controlled by causing the process controller 23a to execute the recipe. For example, a recipe stored in a computer-readable storage medium such as a CD-ROM, a hard disk, or a flash memory may be used, or may be transmitted from another device at any time via a dedicated line, for example. It is also possible to use it.

(Method of forming silicide)
Next, a method for forming silicide using the thermal CVD apparatus 10 will be described.

  2A and 2B are cross-sectional views showing an example of a silicide formation method according to the first embodiment of the present invention. FIG. 2A shows a point in time when the MOSFET is formed on the silicon substrate 101 as the wafer W.

As shown in FIG. 2A, an element isolation region 102 is formed on the surface of a p-type or n-type silicon substrate 101 that is a wafer W. The element isolation region 102 is formed as an insulator containing silicon oxide, and defines an element region 103 in which an active region such as a source diffusion layer and a drain diffusion layer of a MOSFET is formed on the surface of the silicon substrate 101. An example of an insulator containing silicon oxide used for the element isolation region 102 is silicon dioxide (CVD-SiO ₂ ) formed by a CVD method. In the element region 103, a source diffusion layer 104s and a drain diffusion layer 104d having a conductivity type opposite to that of the silicon substrate 101 are formed. The element region 103 between the source diffusion layer 104s and the drain diffusion layer 104d functions as a channel. On this channel, a gate electrode 105 containing silicon formed so as to be electrically insulated from the element region 103 is formed. In this example, the gate insulating film 106 is formed over the channel, and the gate electrode 105 is formed over the gate insulating film 106. In this example, the gate insulating film 106 is made of an insulator containing silicon oxide. An example of an insulator containing silicon oxide used for the gate insulating film 106 is silicon dioxide (Thermal-SiO ₂ ) formed by oxidizing the silicon substrate 101 using a thermal oxidation method. An example of the gate electrode 105 containing silicon is doped polysilicon doped in n-type or p-type. A sidewall insulating film 107 is formed on the sidewall of the gate electrode 105. The sidewall insulating film 107 in this example is made of an insulator containing silicon oxide. An example of an insulator containing silicon oxide used for the sidewall insulating film 107 is silicon dioxide (CVD-SiO ₂ ) formed by a CVD method.

  Thus, FIG. 2A shows a silicon substrate 101 with silicon and silicon oxide exposed on the surface.

  Next, the silicon substrate 101 in the state shown in FIG. 2A is carried into the processing chamber 11 of the thermal CVD apparatus 10 shown in FIG. 1, and the silicon substrate 101 is placed on the mounting table 12. Next, the silicon substrate 101 is heated to a film formation temperature of 400 ° C. or higher using the heater 12a. Next, when the temperature of the silicon substrate 101 reaches the deposition temperature, a manganese organic compound gas is supplied onto the surface of the silicon substrate 101 where silicon and silicon oxide are exposed, as shown in FIG. 2B. Next, the silicon substrate 101 is maintained at the deposition temperature for a predetermined deposition time, and the supply of the manganese organic compound gas is continued. Thereby, the silicon exposed on the surface of the silicon substrate 101, in this example, the exposed surfaces of the silicon substrate 101, the source diffusion layer 104s, the drain diffusion layer 104d, and the gate electrode 105 are selectively and directly silicided into manganese. Is done. Thus, a manganese silicided region (manganese silicide layer) 108 is formed in the source diffusion layer 104s, the drain diffusion layer 104d, and the gate electrode 105. In addition, a manganese oxide film 109 is formed on the silicon oxide exposed on the surface of the silicon substrate 101, in this example, on the exposed surfaces of the element isolation region 102 and the sidewall insulating film 107.

(Processing conditions)
As in this example, the following conditions can be exemplified as an example of processing conditions when silicon is directly converted to manganese silicide using a manganese organic compound gas.

Manganese organic compound gas: (EtCp) ₂ Mn gas
Carrier gas: H ₂ gas
(EtCp) ₂ Mn / H ₂ flow ratio = 7 sccm / 25 sccm
Deposition temperature: 400 ° C or higher
Deposition pressure: 133Pa
Deposition time: 10 min
(advantage)
According to the silicide forming method according to the first embodiment, a manganese organic compound gas is supplied onto the silicon substrate 101 where silicon and silicon oxide are exposed on the surface, and exposed on the surface of the silicon substrate 101. The silicon thus obtained is silicided selectively and directly. At this time, a manganese oxide film 109 is formed on the silicon oxide exposed on the surface of the silicon substrate 101. The manganese oxide film 109 is an insulator. For this reason, even if the manganese oxide film 109 is formed on the exposed surface of the silicon oxide, in this example, the exposed surface of the element isolation region 102 and the exposed surface of the sidewall insulating film 107, the manganese oxide film 109 remains. The gate electrode 105, the source diffusion layer 104s, and the drain diffusion layer 104d are not electrically short-circuited. Moreover, the manganese oxide film 109 has a self-limit phenomenon that when the film thickness reaches a certain value, the film thickness does not increase any more. For example, the thickness of the manganese oxide film 109 that can be formed under the above processing conditions is extremely thin, such as about 2 to 7 nm. For this reason, even if the manganese oxide film 109 remains on the silicon substrate 101, the influence on the structure of the semiconductor device itself, for example, the influence of locally increasing the film thickness of the element isolation region 102 and the sidewall insulating film 107, etc. Is also small. For this reason, the manganese oxide film 109 formed simultaneously with the manganese silicide layer 108 does not need to be removed.

  Therefore, according to the first embodiment, there is no need to dissolve and remove the unreacted metal film remaining on the silicon oxide film and the like without being silicified as in the prior art, for example, a wet cleaning process. The advantage that the manganese silicide layer 108 can be formed without increasing the thickness can be obtained.

  Furthermore, according to the silicide forming method according to the first embodiment, when the silicon exposed on the surface of the silicon substrate 101 is selectively and directly silicided, the film forming temperature is lowered to 400 ° C. or more. can do. Even when the deposition temperature is lowered to 400 ° C. or higher, the manganese silicide layer 108 can be formed on the silicon substrate 101, the source diffusion layer 104 s, the drain diffusion layer 104 d, and the gate electrode 105.

  As described above, according to the first embodiment, the manganese silicide layer 108 is formed at a lower temperature than the conventional case where the high temperature treatment of 600 ° C. to 800 ° C. is required to form the manganese silicide layer 108. be able to.

  Therefore, according to the first embodiment, when the manganese silicide layer 108 is formed, it is possible to save energy necessary for increasing the temperature, and for example, it is advantageous to reduce the manufacturing cost of the semiconductor device. it can.

  In the first embodiment, the gate electrode 105 is formed using doped polysilicon. Then, the resistance of the gate electrode 105 was reduced by making the silicide of the gate electrode 105 using doped polysilicon into manganese silicide. However, it is considered to use metal for the gate electrode 105 in order to further reduce the resistance of the gate electrode 105. When metal is used for the gate electrode 105, it is important that the process performed after forming the gate electrode 105 be performed at a lower temperature in order to reduce thermal damage to the gate electrode 105. .

  In this respect, in the first embodiment, since the silicidation process of the source diffusion layer 104s and the drain diffusion layer 104d performed after the gate electrode 105 is formed can be reduced in temperature, it is advantageous for the gate electrode 105 to be a metal electrode. It is.

  As described above, according to the first embodiment, it is possible to obtain a silicide formation method capable of forming silicide at a lower temperature without increasing the wet cleaning process.

(Modification 1)
In the first embodiment, after silicon is selectively converted into manganese silicide, the temperature of the silicon substrate 101 is set to 400 ° C. or higher to heat-treat the silicon substrate 101 so that the manganese silicide layer 108 is crystallized or crystal grains are grown. Anyway.

  According to the first modified example, the manganese silicide layer 108 is single-crystallized or crystal grains are grown, so that the resistance value is decreased due to the increase in the manganese silicide layer 108, or the single-crystallize or crystal grains are formed. It is possible to obtain an advantage that the sheet resistance can be further reduced due to the increase.

(Modification 2)
In the first embodiment, the manganese oxide film 109 is formed simultaneously with the manganese silicide layer 108. In order to reduce the thickness of the manganese oxide film 109, the temperature of the silicon substrate 101 is set in advance on the surface of the silicon substrate 101 before the manganese organic compound gas is supplied onto the surface of the silicon substrate 101. It is preferable to anneal the silicon substrate 101 at a temperature equal to or higher than the temperature at which the organic compound gas is supplied, i. By this annealing, the silicon substrate 101 can be degassed, in particular, moisture (for example, H ₂ O or OH) can be evaporated. In particular, by evaporating the water from the silicon oxide, it is possible to reduce the substance that makes the manganese organic compound manganese oxide from the silicon oxide. For this reason, the thickness of the manganese oxide film 109 formed on the surface of the silicon oxide can be further reduced.

  According to the second modification, the thickness of the manganese oxide film 109 can be further reduced, thereby further reducing the influence of locally increasing the film thickness of the element isolation region 102 and the sidewall insulating film 107. The advantage that it can be obtained.

  The second modification can also be effectively applied to a second embodiment described later.

(Second Embodiment)
The second embodiment is a silicide forming method for forming a silicide on a substrate having silicon and silicon oxide exposed on the surface, wherein metal manganese is selectively deposited on the silicon exposed on the surface of the substrate. In this example, the metal manganese is reacted with silicon to silicide silicon.

(Device configuration)
FIG. 3 is a plan view schematically showing an example of a film forming system capable of performing the silicide forming method according to the second embodiment of the present invention. This example illustrates a film forming system that performs a film forming process on a substrate to be processed, for example, a wafer, as an example of a film forming system, but the substrate to be processed is not limited to a wafer.

  As shown in FIG. 3, the film forming system 30 includes a processing unit 40 that performs processing on the wafer W, a loading / unloading unit 50 that loads the wafer W into and out of the processing unit 40, and a control unit that controls the film forming system 30. 60. The film forming system 30 according to this example is a cluster tool type (multi-chamber type) film forming system.

  In this example, the processing unit 40 includes two processing chambers (PM) for processing the wafer W (processing chambers 41a and 41b). Each of these processing chambers 41a and 41b is configured so that the inside thereof can be depressurized to a predetermined degree of vacuum. In the processing chamber 41a, the CVD film forming process of the manganese film is performed as the film forming process on the wafer W, and the heat treatment is performed on the wafer W on which the manganese film is formed in the processing chamber 41b. The processing chambers 41a and 41b are connected to one transfer chamber (TM) 42 via gate valves G1 and G2.

  The loading / unloading unit 50 includes a loading / unloading chamber (LM) 51. The carry-in / out chamber 51 is configured to be capable of adjusting the inside to atmospheric pressure or almost atmospheric pressure, for example, slightly positive pressure with respect to the outside atmospheric pressure. In this example, the plane shape of the carry-in / out chamber 51 is a rectangle having a long side when viewed from the plane and a short side orthogonal to the long side. The long side of the rectangle is adjacent to the processing unit 40. The loading / unloading chamber 51 includes a load port (LP) to which the carrier C in which the wafer W is accommodated is attached. In this example, three load ports 52 a, 52 b, and 52 c are provided on the long side of the loading / unloading chamber 51 facing the processing unit 40. In this example, the number of load ports is three, but the number is not limited to these, and the number is arbitrary. Each of the load ports 52a to 52c is provided with a shutter (not shown). When a wafer C storing or empty carrier C is attached to these load ports 52a to 52c, the shutter (not shown) is released. The inside of the carrier C and the inside of the carry-in / out chamber 51 are communicated with each other while preventing the outside air from entering. An orienter (ORT) 53 for aligning the orientation of the wafer W taken out from the carrier C is provided at the position of the short side of the rectangle.

  Between the processing unit 40 and the loading / unloading unit 50, a load lock chamber (LLM), in this example, two load lock chambers 46a and 46b are provided. Each of the load lock chambers 46a and 46b is configured to be able to switch the inside to a predetermined degree of vacuum and atmospheric pressure or almost atmospheric pressure. The load lock chambers 46a and 46b are connected to one side of the loading / unloading chamber 51 opposite to the side where the load ports 52a to 52c are provided via the gate valves G3 and G4, and are transferred via the gate valves G5 and G6. It is connected to two sides of the chamber 42 other than the two sides to which the processing chambers 41a and 41b are connected. The load lock chambers 46a and 46b communicate with the loading / unloading chamber 51 by opening the corresponding gate valve G3 or G4, and are blocked from the loading / unloading chamber 51 by closing the corresponding gate valve G3 or G4. The corresponding gate valve G5 or G6 is opened to communicate with the transfer chamber 42, and the corresponding gate valve G5 or G6 is closed to be shut off from the transfer chamber 42.

  A loading / unloading mechanism 55 is provided inside the loading / unloading chamber 51. The loading / unloading mechanism 55 performs loading / unloading of the wafer W with respect to the carrier C, loading / unloading of the wafer W with respect to the orienter 53, and loading / unloading of the wafer W with respect to the load lock chambers 46a and 46b. The carry-in / out mechanism 55 includes, for example, two multi-joint arms 56 a and 56 b and is configured to be able to travel on a rail 57 extending along the longitudinal direction of the carry-in / out chamber 51. Hands 58a and 58b are attached to the tips of the articulated arms 56a and 56b. The wafer W is placed on the hand 58a or 58b, and the above-described loading / unloading of the wafer W is performed.

  The transfer chamber 42 is configured as a vacuum capable structure, for example, a vacuum container. Inside the transfer chamber 42, a transfer mechanism 44 for transferring the wafer W to and from the processing chambers 41a and 41b and the load lock chambers 46a and 46b is provided, and the transfer chamber 44 is shielded from the atmosphere. The wafer W is transferred. The transport mechanism 44 is disposed substantially at the center of the transport chamber 42. The transport mechanism 44 has, for example, a plurality of transfer arms that can rotate and extend. In this example, for example, there are two transfer arms 44a and 44b. Holders 45a and 45b are attached to the ends of the transfer arms 44a and 44b. The wafer W is held by the holder 45a or 45b, and as described above, the wafer W is transferred to the processing chambers 41a and 41b and the load lock chambers 46a and 46b.

  The control unit 60 controls the film forming system 30. The control unit 60 includes a process controller 60a, a user interface 60b, and a storage unit 60c. The user interface 60 b includes a keyboard on which the process manager manages command input to manage the film forming system 30, a display that visualizes and displays the operating status of the film forming system 30, and the like. The storage unit 60c stores a recipe in which a control program, drive condition data, and the like for realizing the processing by the film forming system 30 is controlled by the process controller 60a. The recipe is called from the storage unit 60c according to an instruction from the user interface 60b as necessary, and the film forming system 30 is controlled by causing the process controller 60a to execute the recipe. For example, a recipe stored in a computer-readable storage medium such as a CD-ROM, a hard disk, or a flash memory may be used, or may be transmitted from another device at any time via a dedicated line, for example. It is also possible to use it.

  In the film forming system 30, for example, the thermal CVD apparatus 10 shown in FIG. 1 can be used as the film forming apparatus including the processing chamber 41 a that performs the CVD film forming process of the manganese film.

  Moreover, the heat processing apparatus provided with the processing chamber 41b which performs heat processing can use the heat processing apparatus 70 shown in FIG. 4, for example.

  As shown in FIG. 4, the heat treatment apparatus 70 includes a processing chamber 41b. A mounting table 72 for mounting the wafer W horizontally is provided in the processing chamber 41b. In the mounting table 72, a heater 72a serving as a temperature control unit for the wafer W is provided. The mounting table 72 is provided with three lifter pins 72c (only two are shown for convenience) that can be moved up and down by a lifting mechanism (not shown). The wafer W is lifted and lowered by the lifter pins 72c. The wafer W is transferred between the transfer means and the mounting table 72.

  One end of an exhaust pipe 73 is connected to the bottom of the processing chamber 41b, and an exhaust device 74 is connected to the other end of the exhaust pipe 73. A transfer port 75 that is opened and closed by a gate valve G2 is formed on the side wall of the processing chamber 41b.

  A gas discharge hole 76 facing the mounting table 72 is provided in the ceiling portion of the processing chamber 41b. For example, a processing gas supply piping system 77 for introducing a processing gas into the processing chamber 41b is connected to the gas discharge hole.

The processing gas supply mechanism 77 includes, for example, a processing gas storage unit 77a in which processing gas is stored, a supply pipe 77b that guides the processing gas to the processing chamber 41b, and a mass flow controller that adjusts the flow rate of the processing gas flowing in the supply pipe 77b. (MFC) 77c and valves 77d and 77e. The valve 77d is provided between the processing gas reservoir 77a and the mass flow controller 77c, and the valve 77e is provided between the supply pipe 77b and the mass flow controller 77c. Examples of the processing gas include argon (Ar) gas, hydrogen (H ₂ ) gas, and nitrogen (N ₂ ) gas. For pressure control, a pressure gauge is installed in the processing chamber 41b, and a pressure control valve is provided in the exhaust device 74, but the illustration is omitted here.

(Method of forming silicide)
Next, a method for forming silicide using the film forming system 30 will be described.

  5A to 5C are cross-sectional views showing an example of a silicide forming method according to the second embodiment of the present invention. FIG. 5A shows a point in time when the MOSFET is formed on the silicon substrate 101 as the wafer W, and FIG. 5A shows the same state as that shown in FIG. 2A. That is, FIG. 5A shows the silicon substrate 101 with silicon and silicon oxide exposed on the surface.

  Next, the silicon substrate 101 in the state shown in FIG. 5A is carried into the processing chamber 41a of the film forming system 30 shown in FIG. The thermal CVD apparatus provided with the processing chamber 41a is the same apparatus as the thermal CVD apparatus 10 described with reference to FIG. Therefore, referring to FIG. 1, the silicon substrate 101 in the state shown in FIG. 5A is carried into the processing chamber 11 of the thermal CVD apparatus 10 shown in FIG. 1, and the silicon substrate 101 is placed on the mounting table 12. Placed on. Next, the silicon substrate 101 is heated to a film formation temperature of 400 ° C. or higher using the heater 12a. Next, when the temperature of the silicon substrate 101 reaches the film formation temperature, as shown in FIG. 5B, a manganese organic compound gas is supplied onto the surface of the silicon substrate 101 where silicon and silicon oxide are exposed. Next, the silicon substrate 101 is maintained at the deposition temperature for a predetermined deposition time, and the supply of the manganese organic compound gas is continued. As a result, the manganese film 110 is selectively formed on the silicon exposed on the surface of the silicon substrate 101, in this example, on the silicon substrate 101, the source diffusion layer 104s, the drain diffusion layer 104d, and the gate electrode 105. As an example of processing conditions for selectively forming the manganese film 110 on silicon using a manganese organic compound gas as in this example, the following conditions can be exemplified.

(Processing conditions)
Manganese organic compound gas: (EtCp) ₂ Mn gas
Carrier gas: H ₂ gas
(EtCp) ₂ Mn / H ₂ flow ratio = 7 sccm / 25 sccm
Deposition temperature: 400 ° C or higher
Deposition pressure: 133Pa
Deposition time: 10 min
Next, the silicon substrate 101 on which the manganese film 110 is formed is unloaded from the processing chamber 41a of the film forming system 30 shown in FIG. 3 to the transfer chamber 42 using the transfer mechanism 44 without being exposed to the atmosphere. Further, the silicon substrate 101 is carried into the processing chamber 41b from the transfer chamber 42 of the film forming system 30 shown in FIG. 3 using the transfer mechanism 44 without being exposed to the atmosphere. The silicon substrate 101 in the state shown in FIG. 5B is mounted on the mounting table 72 of the heat treatment apparatus 70 shown in FIG. Next, using the heater 72a, the temperature of the silicon substrate 101 is set to 400 ° C. or higher, and the silicon substrate 101 on which the manganese film 110 is formed is heat-treated. As an example of the heat treatment conditions, the following conditions can be exemplified.

(Heat treatment conditions)
Processing atmosphere: Ar
Heat treatment temperature: 400 ° C or higher
Heat treatment pressure: 133Pa
Heat treatment time: 10-30 min
5C, the silicon exposed on the surface of the silicon substrate 101, in this example, the exposed surfaces of the silicon substrate 101, the source diffusion layer 104s, the drain diffusion layer 104d, and the gate electrode 105 are selectively formed. Manganese silicide. Thus, a manganese silicided region (manganese silicide layer) 108 is formed in the source diffusion layer 104s, the drain diffusion layer 104d, and the gate electrode 105. Further, similarly to the first embodiment, a manganese oxide film 109 is formed on the silicon oxide exposed on the surface of the silicon substrate 101, in this example, on the exposed surfaces of the element isolation region 102 and the sidewall insulating film 107. The

(advantage)
According to the silicide forming method according to the second embodiment, a manganese organic compound gas is supplied onto the silicon substrate 101 where silicon and silicon oxide are exposed on the surface, and exposed on the surface of the silicon substrate 101. A manganese film 110 is selectively formed on the deposited silicon. Thereafter, the silicon substrate 101 on which the manganese film 110 is formed is heat-treated, and silicon exposed on the surface of the silicon substrate 101 is converted into manganese silicide.

  Also in the second embodiment, the same advantages as those of the embodiment of the table 1 can be obtained.

(Third embodiment)
The third embodiment is an example of a semiconductor device formed by using the silicide formation method according to the first embodiment or the silicide formation method according to the second embodiment.

  6A to 6G are cross-sectional views schematically showing some examples of the semiconductor device according to the third embodiment of the present invention.

(First example)
As shown in FIG. 6A, the semiconductor device according to the first example is a MOSFET.

As shown in FIG. 6A, the MOSFET includes an n-type or p-type silicon substrate 101 and an element isolation region containing silicon oxide that is formed in the silicon substrate 101 and defines an element region 103 on the surface of the silicon substrate 101. 102 and a source diffusion layer 104s and a drain diffusion layer 104d having a conductivity type opposite to that of the silicon substrate 101 formed in the element region 103, and on the element region 103 between the source diffusion layer 104s and the drain diffusion layer 104d. A gate electrode 105a formed electrically through the gate insulating film 106a, for example, and a side wall insulating film 107 formed on the side wall of the gate electrode 105a are provided. In the first example, the element isolation region 102 and the sidewall insulating film 107 are made of silicon oxide, for example, silicon dioxide (CVD-SiO ₂ ) formed using a CVD method.

Furthermore, in the first example, the gate insulating film 106a is made of silicon oxide, for example, silicon dioxide (Thermal-SiO ₂ ) formed by oxidizing the silicon substrate 101, and the gate electrode 105a is made of silicon, for example, , N-type or p-type doped polysilicon.

  Then, a manganese silicided region (MnSix: manganese silicide layer 108) formed in the source diffusion layer 104s, the drain diffusion layer 104d, and the gate electrode 105a according to the first embodiment or the second embodiment. ) Is included.

  A manganese oxide film (MnOx) 109 is formed on the element isolation region 102 and the sidewall insulating film 107.

  By using the silicide formation method according to the first embodiment or the second embodiment, as shown in FIG. 6A, a manganese silicide layer is formed on the source diffusion layer 104s, the drain diffusion layer 104d, and the gate electrode 105a. A MOSFET in which the sheet resistance of the source diffusion layer 104s, the drain diffusion layer 104d, and the gate electrode 105a is reduced can be formed.

(Second example)
As shown in FIG. 6B, the MOSFET according to the second example is different from the MOSFET according to the first example shown in FIG. 6A in that the gate insulating film 106b has a higher dielectric constant than silicon oxide. It is formed using an insulating film (high-k). Examples of the high dielectric constant insulating film include hafnium oxide (HfOx), hafnium silicon oxide (HfSiOx), and zirconium oxide (ZrOx).

  As described above, in the silicide formation method according to the first embodiment or the second embodiment, the manganese silicide layer 108 is formed on the MOSFET using the high dielectric constant insulating film as the gate insulating film 106b. You can also

(Third example)
As shown in FIG. 6C, the MOSFET according to the third example is different from the MOSFET according to the second example shown in FIG. 6B in that the gate electrode 105b is made of metal (metal) and doped polysilicon (poly-Si). And a manganese silicide layer 108 is formed in the vicinity of the surface of the doped polysilicon layer.

  As described above, in the silicide formation method according to the first embodiment or the second embodiment, manganese is used for a MOSFET using a structure in which a metal and doped polysilicon are stacked on the gate electrode 105b. A silicide layer 108 can also be formed.

(Fourth example)
As shown in FIG. 6D, the MOSFET according to the fourth example differs from the MOSFET according to the third example shown in FIG. 6C in that the gate insulating film 106c is formed using a manganese oxide film (MnOx). There is.

  As described above, in the silicide formation method according to the first embodiment or the second embodiment, the manganese silicide layer 108 may be formed on the MOSFET using the manganese oxide film as the gate insulating film 106c. it can.

(Fifth example)
As shown in FIG. 6E, the MOSFET according to the fifth example is different from the MOSFET according to the second example shown in FIG. 6B in that the gate electrode 105c is all made into manganese silicide.

  As described above, in the silicide formation method according to the first embodiment or the second embodiment, the gate electrode 105c can be entirely made into manganese silicide.

(Sixth example)
As shown in FIG. 6F, the MOSFET according to the sixth example is different from the MOSFET according to the fifth example shown in FIG. 6E in that the gate electrode 105d is entirely converted to manganese silicide, and the gate is formed from the upper surface of the gate electrode 105d. This is because the amount of manganese is reduced toward the insulating film 106b. That is, manganese-rich manganese silicide is formed on the upper surface of the gate electrode 105d. The manganese content gradually decreases from the upper surface of the gate electrode 105d toward the gate insulating film 106b, and silicon-rich manganese silicide is formed in a region where the gate electrode 105d and the gate insulating film 106b are in contact with each other.

  As described above, in the silicide formation method according to the first embodiment or the second embodiment, the gate electrode 105d is entirely converted into manganese silicide, and the gate electrode 105d is moved from the upper surface toward the gate insulating film 106b. MOSFETs in which the manganese content is gradually reduced can also be formed.

(Seventh example)
As shown in FIG. 6G, the MOSFET according to the seventh example differs from the MOSFET according to the fifth example shown in FIG. 6E in that the gate insulating film 106c is formed using a manganese oxide film (MnOx). There is.

  As described above, in the silicide formation method according to the first embodiment or the second embodiment, the gate electrode 105c is entirely converted to manganese silicide with respect to the MOSFET using the manganese oxide film as the gate insulating film 106c. You can also

  Although the present invention has been described according to some embodiments, the present invention is not limited to the above-described embodiments, and can be appropriately modified without departing from the spirit of the invention.

For example, in the above embodiment, as the manganese organic compound gas, a cyclopentadienyl-based manganese organic compound, for example, a gas of (EtCp) ₂ Mn [= Mn (C ₂ H ₅ C ₅ H ₄ ) ₂ ] is used. It was. However, the cyclopentadienyl-based manganese organic compound is not limited to (EtCp) ₂ Mn, and is selected from at least one of the following cyclopentadienyl-based manganese organic compounds to be gasified. Is also possible.

(EtCp) ₂ Mn [= Mn (C ₂ H ₅ C ₅ H ₄ ) ₂ ]
_{Cp 2 Mn [= Mn (C} 5 H 5) 2]
(MeCp) ₂ Mn [= Mn (CH ₃ C ₅ H ₄ ) ₂ ]
_{(I-PrCp) 2 Mn [} = Mn (C 3 H 7 C 5 H 4) 2]
MeCpMn (CO) ₃ [= (CH ₃ C ₅ H ₄ ) Mn (CO) ₃ ]
_{(T-BuCp) 2 Mn [} = Mn (C 4 H 9 C 5 H 4) 2]
_{Mn (DMPD) (EtCp) [} = Mn (C 7 H 11 C 2 H 5 C 5 H 4)], and _{((CH 3) 5 Cp)} 2 Mn [= Mn ((CH 3) 5 C 5 H 4 ₂ ]
Further, in the above embodiment, as a carrier gas for supplying the cyclopentadienyl system manganese organic compound gas, but with H ₂ gas, any inert gas such as Ar gas or N ₂ gas It is also possible to use these.

  In addition to the cyclopentadienyl manganese organic compound, the following organic compounds can be used as the manganese organic compound.

CH ₃ Mn (CO) ₅
Mn (DPM) ₂ [= Mn (C ₁₁ H ₁₉ O ₂ ) ₂ ]
Mn (DPM) ₃ [= Mn (C ₁₁ H ₁₉ O ₂ ) ₃ ]
Mn (acac) ₂ [= Mn (C ₅ H ₇ O ₂ ) ₂ ]
Mn (acac) ₃ [= Mn (C ₅ H ₇ O ₂ ) ₃ ]
Mn (hfac) ₂ [= Mn (C ₅ HF ₆ O ₂ ) ₂ ]
_{Mn (iPr-AMD) 2)} [= Mn (C 3 H 7 NC (CH 3) NC 3 H 7) 2]
_{Mn (tBu-AMD) 2)} [= Mn (C 4 H 9 NC (CH 3) NC 4 H 9) 2]
In addition, the present invention can be variously modified without departing from the gist thereof.

  DESCRIPTION OF SYMBOLS 101 ... Silicon substrate, 102 ... Element isolation region, 103 ... Element region, 104s ... Source diffusion layer, 104d ... Drain diffusion layer, 105 ... Gate electrode, 106 ... Gate insulating film, 107 ... Side wall insulating film, 108 ... Manganese silicide layer 109 ... Manganese oxide film, 110 ... Manganese film.

Claims (11)

A method of forming a silicide, wherein a silicide is formed on a substrate having silicon and silicon oxide exposed on a surface,
The substrate temperature is set to 400 ° C. or higher, and a manganese organic compound gas is supplied onto the surface of the substrate where the silicon and the silicon oxide are exposed,
A selective silicide formation method , wherein the silicon exposed on the surface of the substrate is selectively converted into manganese silicide, and a manganese oxide film is formed on the silicon oxide . After selectively siliciding the silicon only with manganese,
2. The selective silicide formation method according to claim 1, wherein the temperature of the substrate is set to 400 ° C. or more, and the substrate is heat-treated to crystallize or grow crystal grains of the manganese silicide. A method of forming a silicide, wherein a silicide is formed on a substrate having silicon and silicon oxide exposed on a surface,
Selected as above temperature 400 ° C. of the substrate, by supplying a manganese organic compound gas onto the surface of the substrate between the silicon and the silicon oxide is exposed on the silicon exposed on the surface of the substrate Metal manganese is formed,
The substrate was heat-treated the temperature of the substrate as 400 ° C. or higher, said metal permanganate is reacted with the exposed silicon on the surface of the substrate, the silicon and manganese silicide, manganese oxide on the silicon oxide A selective silicide formation method comprising forming a film . The step of forming the metal manganese and the step of siliciding the silicon into a manganese and forming a manganese oxide film on the silicon oxide are continuously performed without being exposed to the atmosphere. Item 4. The selective silicide formation method according to Item 3. Before supplying manganese organic compound gas onto the surface of the substrate,
The substrate is annealed at a temperature equal to or higher than the temperature at which manganese organic compound gas is supplied onto the surface of the substrate, and the substrate on which silicon and silicon oxide are exposed is degassed. The selective silicide formation method according to any one of claims 1 to 4, wherein: 6. The selective silicide formation method according to claim 1, wherein the manganese organic compound gas is a cyclopentadienyl manganese organic compound gas. Carrier gas when supplying the cyclopentadienyl manganese organic compound gas,
The selective silicide formation method according to claim 6, which is selected from H ₂ gas, Ar gas, and N ₂ gas. The cyclopentadienyl manganese organic compound gas is
(EtCp) ₂ Mn [= Mn (C ₂ H ₅ C ₅ H ₄ ) ₂ ]
_{Cp 2 Mn [= Mn (C} 5 H 5) 2]
(MeCp) ₂ Mn [= Mn (CH ₃ C ₅ H ₄ ) ₂ ]
_{(I-PrCp) 2 Mn [} = Mn (C 3 H 7 C 5 H 4) 2]
MeCpMn (CO) ₃ [= (CH ₃ C ₅ H ₄ ) Mn (CO) ₃ ]
_{(T-BuCp) 2 Mn [} = Mn (C 4 H 9 C 5 H 4) 2]
_{Mn (DMPD) (EtCp) [} = Mn (C 7 H 11 C 2 H 5 C 5 H 4)], and _{((CH 3) 5 Cp)} 2 Mn [= Mn ((CH 3) 5 C 5 H 4 ₂ ]
CH ₃ Mn (CO) ₅
Mn (DPM) ₂ [= Mn (C ₁₁ H ₁₉ O ₂ ) ₂ ]
Mn (DPM) ₃ [= Mn (C ₁₁ H ₁₉ O ₂ ) ₃ ]
Mn (acac) ₂ [= Mn (C ₅ H ₇ O ₂ ) ₂ ]
Mn (acac) ₃ [= Mn (C ₅ H ₇ O ₂ ) ₃ ]
Mn (hfac) ₂ [= Mn (C ₅ HF ₆ O ₂ ) ₂ ]
_{Mn (iPr-AMD) 2)} [= Mn (C 3 H 7 NC (CH 3) NC 3 H 7) 2]
_{Mn (tBu-AMD) 2)} [= Mn (C 4 H 9 NC (CH 3) NC 4 H 9) 2]
The selective silicide formation method according to claim 6 or 7, wherein the gas is selected from a gas containing at least one of the following. A silicon substrate;
An element isolation region containing silicon oxide formed in the silicon substrate and defining an element region on a surface of the silicon substrate;
A source diffusion layer and a drain diffusion layer formed in the element region;
A gate electrode formed on the element region between the source diffusion layer and the drain diffusion layer and electrically insulated from the element region;
The source diffusion layer, and a portion of the drain diffusion layer, see contains manganese silicided regions,
A semiconductor device, wherein a manganese oxide film is formed on the element isolation region . The gate electrode comprises silicon;
The semiconductor device according to claim 9, wherein the gate electrode containing silicon includes a manganese silicide region. 11. The semiconductor device according to claim 9, wherein the gate insulating film that electrically insulates the element region from the gate electrode is a manganese oxide film.

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