JP5599121B1 - Game machine - Google Patents

Abstract

The present invention provides a gaming machine that can suitably prevent fraud that interferes with transmission and reception of control information.
Based on control information received from the first control means, and first control means for transmitting the generated control information one by one at a predetermined transmission interval for each configuration data via the communication means. Second control means for performing control, and when there is no control information to be transmitted, by generating specific control information, the first control means over a plurality of control information transmission periods The configuration data is transmitted without interruption at the transmission interval. Further, the second control means is caused to detect a state where the reception interval of the configuration data exceeds the predetermined determination time as a communication error, and sets the predetermined determination time to be twice or more of the transmission interval.
[Selection] Figure 10

Description

  The present invention relates to a technique for preventing illegal acts of gaming machines.

  A gaming machine such as a slot machine or a pachinko machine may be composed of a plurality of control boards in order to distribute the control burden. In these gaming machines, the control boards are connected to each other by a signal line, and a command is transmitted from one control board to the other control board, so that the processes executed by each control board are interlocked and executed by each control board. It realizes that the processing becomes the operation of an integrated gaming machine.

  For example, the gaming machine described in Patent Document 1 has a game content that gives a predetermined profit to a player when a predetermined role continuously wins in a game. In such a gaming machine, The winning itself is controlled by the main control board, and the profit granting by the continuous winning of the predetermined role is controlled by the sub control board. Specifically, every time a winning occurs, the main control board transmits a command notifying the occurrence of winning and the type of winning to the sub control board. The sub-control board counts the number of consecutive winnings in a predetermined combination based on the command transmitted from the main control means, and counts when receiving a command indicating that the predetermined combination has not been won. When the counted number of winnings reaches a predetermined value, the player is given a predetermined profit.

  In addition, the gaming machine described in Patent Document 2 includes a means for detecting a communication error on a control board that receives a command. Specifically, the gaming machine described in Patent Document 2 includes a command data storage unit that stores a regular command in advance on a control board on the receiving side, and compares the received command with data stored in the command data storage unit. . According to such a configuration, when the received command is altered or missing, it does not match when collated with the data stored in the command data storage unit, so that it can be detected as a communication error.

JP 2012-081176 A JP 2001-058067 A

  By the way, in recent years, fraudulent acts that obstruct command communication have prevailed against the gaming machine described in Patent Document 1. For example, in the gaming machine described in Patent Document 1, even if the consecutive winning of the predetermined role is interrupted, if the communication of the command indicating that the predetermined role has not been won is interrupted, the continuous winning of the predetermined role is continued. If it is, the sub-control board can be misidentified, so that it is easy to obtain a profit by consecutive winning of a predetermined role. Specifically, when a predetermined combination is not won, a command indicating that the predetermined combination has not been won is transmitted / received by intentionally radiating radio waves to the communication path between the main control board and the sub-control board. Interfering can be mentioned. In addition, the reception function of the sub control board is instantaneously malfunctioned by a method such as instantaneously shorting the power supply of the sub control board at the moment when the command indicating that the predetermined role is not won is transmitted. A method is also mentioned.

  If such illegal acts are left unattended, it will cause a great deal of damage to the hall where the gaming machine is installed. Since the error detection method described in Patent Document 2 can detect command alteration / missing, such an illegal act can be detected as a communication error. However, in the conventional gaming machine, even when a command alteration or disappearance is detected, no strict response is performed. This is because the control information modification or loss may occur spontaneously even when the communication means is operating normally. This is because the player who plays the game correctly is disadvantaged.

  An object of this invention is to provide the game machine which can solve the said problem.

  The inventor conducted intensive studies to solve the above problem, and found that when the communication of the command (control information) is hindered by the illegal action, the command is relatively largely lost. This is because control information is transferred in units of a predetermined configuration data in a communication circuit provided between control boards. In a naturally occurring communication error, a unit of configuration data is generated by a framing error at the time of data transfer. In contrast to the inability to receive, in the case of the above fraudulent acts, it is considered that a failure occurs in the communication circuit for a longer time than a naturally occurring one, and it is likely that a plurality of configuration data cannot be received continuously. . The inventor has focused on the fact that the configuration data is transmitted at regular intervals via the communication circuit, and has reached the present invention.

The present invention is based on the first control means disposed on the first substrate and transmitting control information, and the control information disposed on the second substrate and received from the first control means. A game machine comprising: second control means for performing control; and communication means for transferring data from the first control means to the second control means using predetermined configuration data as a transfer unit, The first control means includes control information generation means for generating the control information, and transmission means configured to transmit the configuration data one by one at a predetermined transmission interval via the communication means, The control information generated by the control information generating means is transmitted by the transmitting means in units of the configuration data, and the communication means is disposed on the first substrate, and the first control The configuration data sent by the means A first communication circuit that outputs to the outside of the first substrate, and a second communication that is disposed on the second substrate and that receives the configuration data from the first communication circuit via a signal line. and a circuit, said second control means, every time the interrupt that is configured to generate at predetermined intervals, and transmits the read signal to the second communication circuit, is input to the second communication circuit said receiving means configuration data for receiving the configuration data by executing a data acquisition processing for capturing from said second communication circuit, the reception interval in which the receiving means receives the configuration data, predetermined judgment that First communication error detection means for detecting a state exceeding the time as a first communication error, wherein the control information generation means performs specific control when the control information to be transmitted by the transmission means does not exist. Generating information and transmitting means , By transmitting the specific control information, the configuration data is periodically transmitted over the transmission interval over a plurality of transmission periods of the control information, and the predetermined determination time is determined by the transmission unit. The length of the configuration data is at least twice as long as the transmission interval, and the second communication circuit temporarily stores the configuration data input from the first communication circuit until it is captured by the receiving means. The FIFO circuit can store and hold a plurality of the configuration data at the same time, and when the read signal is received , the FIFO circuit sequentially fetches the configuration data from the previously stored configuration data. A gaming machine characterized by being a circuit to be operated.

  Even in the case of a communication error that occurs spontaneously or in the case of a communication error due to fraudulent activity, the configuration data reception interval will be longer than normal due to failure to receive the configuration data. When it is caused by fraud, it is often impossible to continuously receive a plurality of pieces of configuration data, so that the reception interval of the configuration data is longer than that naturally occurring. For this reason, in the present invention, by setting the determination time, which is a determination criterion for the first communication error, to an appropriate length, and eliminating a reception interval that occurs due to a spontaneous communication error, Only a communication error caused by an illegal act can be detected as the first communication error.

  In particular, in the present invention, if the communication is normally performed, the configuration data is always transmitted at a constant transmission interval. Therefore, the first communication error detection unit can be enabled over a plurality of control information reception periods. As a result, communication errors caused by fraud can be monitored without interruption. Further, in such a configuration, even when the entire configuration data constituting one control information is lost, the second control means can detect it as the first communication error.

  By the way, in this configuration, when the other processing contents of the second control unit temporarily increase and the data fetching process of the second control unit is extended, the second communication circuit has not fetched the data. Before the configuration data is fetched, the next configuration data may reach the second communication circuit. In such a case, in the communication circuit of the existing gaming machine, the newly received unacquired configuration data is overwritten, and the retained unacquired configuration data is discarded. As described above, when the second control unit misses a part of the configuration data of the control information due to the extension of the data fetching process, the control information received from the first control unit cannot be processed normally. Even if the data fetching process is postponed, the configuration data is not missed unless the control information is transmitted from the first control means. Because the configuration data is transmitted without interruption at the transmission interval, if the existing communication circuit is adopted, the configuration data will be missed every time the data acquisition process is extended. Information cannot be processed normally.

  On the other hand, in this configuration, by storing a plurality of configuration data in the FIFO circuit provided in the second communication circuit, the next configuration is stored in the second communication circuit before unprocessed configuration data is captured. Even if the data arrives, the configuration data that has not been captured is not discarded. For this reason, according to this configuration, even when the data acquisition process is extended, the second control unit does not miss the configuration data.

  As a specific configuration of the present invention, the first communication error detecting unit determines whether or not the receiving unit has received the configuration data every time the data fetching process is executed. A confirmation means, and the reception state confirmation means comprises a non-reception number counting means for counting the number of times of continuous determination that the configuration data has not been received. A configuration is proposed in which when the number of times corresponding to a predetermined determination time is reached, the first communication error is detected. In such a configuration, the first communication error detection means can be suitably realized.

  Further, in this configuration, it is proposed that the second control unit includes a second communication error detection unit that detects an abnormality in the content of the configuration data received by the reception unit as a second communication error. The Here, the “abnormality of the contents of the configuration data” detected as the second communication error includes an abnormality of the control information detected based on the error detection code included in the control information. In addition, the configuration data received from the first control means is collated with a pre-stored regular data pattern, and the status where the received configuration data does not match the regular data pattern is indicated as a second communication error. It can also be detected.

  In such a configuration, not only when the configuration data of the control information is lost, but also when the configuration data of the control information is altered, it can be controlled as a communication error. As described above, in the present invention, even when the data fetching process is extended by the second control unit, the second control unit does not miss the configuration data. There is no possibility that the spillover is detected as a second communication error.

  In the present invention, the second control means includes an error counting means for counting the number of times the second communication error is detected by the second communication error detecting means, and the error counting means when a predetermined condition is satisfied. Error processing when the initialization means for initialization and the first communication error detection means detect the first communication error, or when the number of counts of the error count means reaches a predetermined number of detections A configuration including an error processing execution means for executing is proposed.

  In such a configuration, by performing error processing based on detection of the first communication error and the second communication error, it becomes possible to more reliably control communication errors caused by fraudulent acts. . Here, in the second communication error, it is not possible to distinguish between a communication error caused by fraud and a spontaneous communication error. In this configuration, the error counting unit and the initialization unit are set as appropriate, and error processing is executed only when a second communication error is detected at a frequency that cannot occur due to a spontaneous communication error. Evil can be eliminated.

  As described above, according to the present invention, it becomes possible to detect only a communication error that is considered to be caused by fraud as the first communication error. Therefore, strict countermeasures are taken based on the detection of the first communication error. Even if it is taken, there is no penalty for a player who is playing correctly. In particular, in the present invention, since the configuration data is transmitted from the first control means at regular intervals, it is possible to constantly monitor the occurrence of the first communication error, and thereby strictly control fraud. Is possible. Furthermore, in the present invention, since a plurality of configuration data can be temporarily stored and held in the FIFO circuit of the second communication circuit, even if the data fetching process by the second control means is extended, a problem occurs. There is no. Therefore, in the gaming machine of the present invention, it is possible to appropriately control fraudulent acts that interfere with communication of control information.

FIG. 3 is a perspective view of the slot machine 1 according to the first embodiment. 2 is a perspective view showing an outline of the slot machine 1 with a front door 3 opened. FIG. 3 is a block diagram showing a control circuit of the slot machine 1. FIG. It is a chart explaining the contents of a command. 3 is a block diagram showing a control circuit related to communication between a main control board 14 and a sub control board 15. FIG. It is a flowchart which shows the control content of a main control process. It is a flowchart which shows the control content of a command transmission process. (A) is a flowchart showing the control contents of the sub-control process, (B) is a flowchart showing the control contents of the communication error process, and (C) is a flowchart showing the control contents of the data fetch process. is there. (A) is a timing chart showing a case where communication error processing is executed, and (B) is a timing chart showing a case where communication error processing is not executed. (A) is a timing chart showing a case where a command is normally received, and (B) is a timing chart showing a case where a severe communication error is detected. It is a timing chart which shows the case where a minor communication error is detected. (A) is a timing chart which shows the case where execution of a data acquisition process is extended in an Example, (B) is a timing chart which shows the case where execution of a data acquisition process is extended in a comparative example. is there. It is a flowchart which shows the control content of a communication error detection process. It is a flowchart which shows the control content of the communication error detection process following FIG.

Embodiments of the present invention are described according to the following examples.
In the following embodiments, the first board according to the present invention corresponds to the main control board 14, and the second board according to the present invention corresponds to the sub-control board 15. The first control means according to the present invention corresponds to the main microcomputer 30 of the main control board 14, and the second control means according to the present invention corresponds to the sub microcomputer 40 of the sub control board 15. To do. The first communication circuit according to the present invention corresponds to the parallel communication circuit 33 of the main control board 14, and the second communication circuit according to the present invention corresponds to the parallel communication circuit 41 of the sub control board 15. The control information according to the present invention corresponds to a command transmitted from the main control board 14 to the sub control board 15.

  In this embodiment, the present invention is applied to a slot machine. As shown in FIGS. 1 and 2, the housing 2 of the slot machine 1 is opened forward and is covered by the front door 3 from the front. As shown in FIG. 1, a visual recognition window 4 for visually recognizing three reels 9 disposed inside the housing 2 is provided at the center of the front door 3. A horizontally long rectangular liquid crystal display 10 is disposed above the viewing window 4. Further, on the front side of the front door 3, various switches such as bet switches 5 a and 5 b, a start switch 6, a stop switch 7, and a checkout switch 8 used for game operation are disposed below the viewing window 4. The front door 3 is provided with a plurality of speakers 11 and effect lamps 12 at appropriate positions.

  In addition, as shown in FIG. 2, the main control board 14 and the sub control board 15 are installed inside the housing 2 in a state where the main control board 14 and the sub control board 15 are housed in the case. The main control board 14 and the sub control board 15 constitute a control device of the slot machine 1, and commands (in one direction) from the main control board 14 to the sub control board 15 via the signal line 16 connecting the boards. Control information) is transmitted. Inside the housing 2, a power box 19 including a power-on switch 18 and a hopper unit 20 are disposed below the reel 9. A front door opening detection sensor 22 that detects opening of the front door 3 is provided on the right side of the housing 2. The front door opening detection sensor 22 is disposed so as to face the reflecting plate 23 provided on the front door 3 and optically detects the opening of the front door 3.

Next, a control circuit for controlling the operation of the slot machine 1 will be described with reference to FIG.
The main control board 14 controls the progress of the game, and includes a main microcomputer 30, a random number generation circuit 31, a latch circuit 32, and a parallel communication circuit 33. The main microcomputer 30 includes a CPU, a RAM, a ROM, an I / O port, and the like. Is input to the I / O port of the main microcomputer 30. Signals are sent from the main microcomputer 30 to the motor for driving the reel 9 via the I / O port, the motor for driving the hopper unit 20, and the external signal output board 24 for transmitting signals to the outside of the machine. Is output. The main microcomputer 30 transmits various commands to the sub-control board 15 via the parallel communication circuit 33. The command transmitted from the main control board 14 to the sub control board 15 is sent only in one direction, and no command is sent from the sub control board 15 to the main control board 14. The main microcomputer 30 generates an interrupt to the CPU at intervals of 1.8 milliseconds. A command transmission process, which will be described later, is executed every time this interrupt occurs. In the RAM of the main microcomputer 30, a storage area as a transmission buffer 34 (see FIG. 5) for temporarily storing commands to be transmitted is secured in advance. The CPU of the main microcomputer 30 generates a command and stores the generated command in the transmission buffer 34. The transmission buffer 34 can store a plurality of commands. The main microcomputer 30 transmits commands in the order stored in the transmission buffer 34.

  The sub-control board 15 controls effects relating to games in accordance with commands received from the main control board 14, and includes a sub-microcomputer 40, a parallel communication circuit 41, a random number generation circuit 42, and a latch circuit 43. A sound control circuit 44, an image control circuit 45, and an LED drive circuit 46. The sub microcomputer 40 includes a CPU, a RAM, a ROM, an I / O port, and the like. The ROM of the sub-microcomputer 40 stores fixed data relating to a wide variety of effect patterns. The RAM of the sub microcomputer 40 is provided with a reception buffer 47 (see FIG. 5) for receiving a command transmitted from the main control board 14. The parallel communication circuits 33 and 41 of the main control board 14 and the sub control board 15 are interconnected by the signal line 16, and a command transmitted from the main control board 14 is transmitted to the parallel communication circuits 33 of both the control boards 14 and 15. , 41 to the reception buffer 47. The CPU of the sub microcomputer 40 generates interrupts at intervals of 1.2 milliseconds. Each time this interrupt occurs, a command is acquired from the parallel communication circuit 41 to the reception buffer 47. Then, the CPU of the sub-microcomputer 40 executes a process corresponding to the acquired command. Specifically, by outputting a signal from the I / O port to the sound control circuit 44, the sound control circuit 44 outputs a sound from the speaker, and outputs a signal from the I / O port to the image control circuit 45. Thus, the image control circuit 45 outputs an image to the liquid crystal display 10 and outputs a signal from the I / O port to the LED drive circuit 46, whereby the LED drive circuit 46 turns on the effect lamp.

  In this embodiment, information that can specify the state of the slot machine 1 is output from the main control board 14 and the sub control board 15 to the external signal output board 24. The external signal output board 24 outputs a signal necessary for an external device such as a computer installed in order to centrally manage the operating status of the gaming machine in a game hall or the like. In this embodiment, the number of game media inserted, the number of game media paid out, a signal indicating that a bonus has occurred, an error has occurred, etc. are transmitted from the main control board 14 via the external signal output board 24. Output to an external device. In this embodiment, the sub-control board 15 can also output various signals to an external device via the external signal output board 24.

  FIG. 4A shows a data format of a command transmitted from the main control board 14 to the sub control board 15. This command corresponds to control information according to the present invention. As shown in FIG. 4A, the command is 5-byte data in which 5 pieces of 1-byte configuration data form one set. That is, the command is meaningful by a plurality of configuration data. The configuration data constituting the command includes a communication unit for normally performing communication and a data unit for storing information of the main control board 14. Specifically, as shown in FIG. 4B, the configuration data “ST” at the head of the command constitutes a communication unit, and a fixed value indicating the head of the command is stored. The second and third configuration data “DATA1” and “DATA2” constitute a data part, and store values corresponding to the type and contents of the command. The fourth component data “CH” stores a checksum that is an error detection code. Specifically, the configuration data “CH” stores the lower 1 byte when “DATA1” and “DATA2” are added. The fifth configuration data “EN” configures the communication unit, and stores a fixed value indicating the end of the command.

  FIG. 4C shows a specific example of the data portion of the command (“DATA1” and “DATA2”). In the figure, “h” means a hexadecimal number. In this embodiment, a plurality of types of commands including an internal winning command, a left reel stop command, a middle reel stop command, a right reel stop command, a winning determination command, a power-on command, a door command, and an active command are sent from the main control board 14. Transmit to the control board 15. The internal winning command is a command that can specify the lottery result of the winning lottery process, and is transmitted when the start switch 6 is operated and the winning lottery process is executed. The left reel stop command is a command that can specify the stop position of the left reel, and is transmitted when the left reel stops. The middle reel stop command is a command that can specify the stop position of the middle reel, and is transmitted when the middle reel stops. The right reel stop command is a command that can specify the stop position of the right reel, and is transmitted when the right reel stops. The winning determination command is a command that can specify the presence / absence of a winning and the type of winning, and is transmitted when all the reels are stopped and the stop symbol determining process is performed. The power-on command is transmitted when the supply of power to the main control board 14 is started and the initial setting at the start-up in the main control board 14 is completed. The door command is a command indicating the detection state of the front door opening detection sensor 22, that is, ON (open state) / OFF (closed state), when the power is turned on, at the end of one game (after the game is over, the bet of the next game). Sent when the detection state of the front door opening detection sensor 22 changes (ON to OFF, OFF to ON) until the setting of the number can be started). The active command is a command that can specify whether or not an error has occurred in the main control board 14 and the type of error. Here, commands other than the active command are generated and transmitted according to the progress of the game and the operating state of the switch and sensor, whereas the active command is generated and transmitted regularly during the period when these commands are not transmitted. Sent. That is, the active command corresponds to specific control information according to the present invention.

  FIG. 5 is a block diagram showing a control circuit related to communication between the main control board 14 and the sub control board 15. In the present embodiment, the command is transmitted from the main control board 14 to the sub control board 15 at a predetermined time interval in a predetermined order for each configuration data. As a method of transferring the configuration data from the main control board 14 to the sub control board 15, a method (parallel communication) in which one (1 byte) of configuration data is transmitted in parallel through a plurality of signal lines 16 is used.

  Specifically, the main microcomputer 30 outputs the configuration data stored in the transmission buffer 34 from the data bus terminal 35 every time the above-described interruption of 1.8 milliseconds is performed. The data bus terminal 35 of the main microcomputer 30 and the data bus terminal 36 of the parallel communication circuit 33 are connected via a data bus 37 on the main control board 14. The parallel communication circuit 33 of the main control board 14 is for outputting one piece of configuration data inputted to the data bus terminal 36 from the connection terminal 38 to the outside of the board simultaneously in parallel. When one piece of configuration data is input to the data bus terminal 36, the parallel communication circuit 33 of the main control board 14 outputs the configuration data from the connection terminal 38 to the eight signal lines 16 in parallel without delay. At the same time, a strobe signal as a trigger is output from the control signal line 16.

  Data output from the main control board 14 is input to the connection terminal 48 of the parallel communication circuit 41 of the sub control board 15 through the signal line 16. When one piece of configuration data is input to the connection terminal 48, the parallel communication circuit 41 of the sub-control board 15 sequentially stores the input data in the FIFO circuit 50. The FIFO circuit 50 stores and holds a plurality of received configuration data and outputs them according to the order of reception. Specifically, the FIFO circuit 50 includes a plurality of registers 51 for storing configuration data, and a write pointer 52 as storage means for designating the order of the plurality of registers 51 for storing configuration data. When outputting the configuration data, the read pointer 53, which is a storage means for designating the output order of the configuration data stored in the plurality of registers 51, and the input / output data when the configuration data is stored and output And a selector 54 for selecting the register 51 to be operated.

  More specifically, when the FIFO circuit 50 receives one piece of configuration data transmitted by the main control board 14, the selector 54 refers to the write pointer 52 and follows the address stored in the write pointer 52. The register 51 is selected, and the configuration data is stored in the selected register 51. After the configuration data is stored, the contents of the write pointer 52 and the read pointer 53 are updated. On the other hand, when the FIFO circuit 50 receives the read signal from the sub microcomputer 40, the selector 54 refers to the read pointer 53, selects the register 51 according to the address stored in the read pointer 53, and selects the selected register 51. Is output from the data bus terminal 55. At this time, when a plurality of pieces of configuration data are stored in the FIFO circuit 50, one piece of configuration data stored first is selected and output. After the configuration data is output, the contents of the write pointer 52 and the read pointer 53 are updated. If no configuration data is stored when the read signal is received, the FIFO circuit 50 outputs a signal indicating no data from the data bus terminal 55 to the sub microcomputer 40. Since the FIFO circuit 50 can be realized by an existing circuit configuration, the detailed circuit configuration will not be described.

  The sub-microcomputer 40 transmits a read signal to the FIFO circuit 50 each time the above-described 1.2 millisecond intervals are interrupted, and fetches the configuration data transmitted from the main control board 14 from the parallel communication circuit 41. Process. When the configuration data is input from the FIFO circuit 50 to the data bus terminal 57 of the sub microcomputer 40 via the data bus 56 on the sub control board 15 by this data fetching process, the sub microcomputer 40 is connected to the RAM. The configuration data input to the reception buffer 47, which is a storage area secured in the memory, is stored.

  In this way, data transmitted by the main microcomputer 30 in units of configuration data is transferred by the parallel communication circuits 33 and 41 of both control boards 14 and 15 and the signal line 16, and is received by the reception buffer 47 of the sub microcomputer 40. Are received in units of configuration data. That is, in this embodiment, the parallel communication circuits 33 and 41 and the signal line 16 correspond to the communication means according to the present invention, and the parallel communication circuits 33 and 41 of the main control board 14 and the sub control board 15 are the present invention. Respectively corresponding to the first communication circuit and the second communication circuit. The reception buffer 47 of the sub-microcomputer 40 constitutes reception means according to the present invention.

FIG. 6 shows the control contents of the main control processing that constitutes the main routine in the control contents of the CPU of the main control board 14. Details of steps S100 to S108 executed in the main control process are as follows.
S100: Wait until a predetermined number (the number of medals required to execute one game) is set.
S101: Wait until the start switch 6 is operated.
S102: When the start switch 6 is operated, the latch circuit 32 extracts the random number generated by the random number generation circuit 31. It is determined whether or not winning of the winning combination is allowed based on the extracted random number value.
S103: The rotation of each reel 9 is started, and when the reel 9 reaches a predetermined rotation speed, the operation of the stop switch 7 is validated.
S104: Wait until the player operates the stop switch 7.
S105: When the player operates the stop switch 7, the reel 9 corresponding to the operated stop switch 7 stops rotating.
S106: Wait until all the reels 9 stop rotating.
S107: It is determined whether or not the display result derived by the reel 9 is in a predetermined mode. Specifically, it is determined whether or not the combination of symbols displayed on the winning line matches the combination of symbols determined as a predetermined winning combination. Is determined.
S108: A process according to the determination result of the stop symbol determination process is performed. Specifically, when it is determined that a winning has occurred, the number of payouts corresponding to the winning is added to the credit, and when the credit exceeds a predetermined number (50), the surplus medal is paid out. put out.

  FIG. 7 shows the contents of command transmission processing executed by the CPU of the main microcomputer 30. This command transmission process is executed every time the aforementioned interrupt occurs, that is, at an interval of 1.8 milliseconds. In the command transmission process, first, it is determined whether or not all the configuration data constituting the command has been transmitted, that is, whether or not the command is being transmitted (S200). If it is determined that the command is being transmitted, the process proceeds to step S203. If it is determined that the command is not being transmitted, the process proceeds to step S201. In step S201, it is determined whether or not the transmission buffer 34 is empty. If it is determined that the transmission buffer 34 is empty, an active command is generated and stored in the transmission buffer 34 (S202). If the process proceeds to S203 and it is determined that the transmission buffer 34 is not empty, the process proceeds to step S203 as it is. In step S203, one byte (configuration data) of the command stored in the transmission buffer 34 is output from the data bus terminal 35, and is output to the sub-control board 15 via the parallel communication circuit 33, and command transmission processing is performed. finish.

  Thus, the CPU of the main microcomputer 30 generates a command according to the progress of the game according to the execution state of the main control process, and stores it in the transmission buffer 34. Further, the CPU of the main microcomputer 30 determines whether or not the detection state of the front door opening detection sensor 22 has changed every time the above-described interrupt occurs, and generates a door command when the change has occurred, and sends it to the transmission buffer 34. Store. Then, when the transmission buffer 34 becomes empty, the CPU of the main microcomputer 30 generates an active command and stores it in the transmission buffer 34 to transmit the command to the sub-control board 15 without interruption. Data is always transmitted to the sub-control board 15 at intervals of 1.8 milliseconds. That is, the control information generation means according to the present invention is mainly realized by the main control process and the command transmission process. Further, the transmission means according to the present invention is mainly realized by the above step S203.

  FIG. 8A shows the control contents of the CPU of the sub-microcomputer 40 and the control contents of the sub-control processing constituting the main routine. As shown in FIG. 8A, in such sub-control processing, the CPU of the sub-microcomputer 40 has received a predetermined number (5) of configuration data, that is, has received one command. Whether or not one command has been received, processing corresponding to the received command is executed (S302). For example, when an internal winning command is received, an effect based on the result of the combination lottery process is started. Specifically, the left reel corresponding image, the middle reel corresponding image, and the right reel corresponding image are displayed on the liquid crystal display 10. When a left reel stop command, middle reel stop command, and right reel stop command are received, an effect corresponding to each reel is performed. Specifically, when a left reel stop command is received, the left reel corresponding image is deleted. If the winning combination corresponding to the result of the winning lottery process is not realized based on the stop position, the effect started based on the reception of the internal winning command is stopped. When the winning determination command is received, the effect started based on the reception of the internal winning command is ended. Furthermore, when there is a prize, an effect is executed according to the type of prize. When a power-on command is received, if no communication error has occurred at the time of reception, the sub-control board 15 executes an initialization process. Further, when a door command indicating opening of the front door 3 is received, a notification that the front door 3 is open is notified. Specifically, the fact is displayed on the liquid crystal display 10. In addition, when an active command indicating an error state is received, notification is performed in such a manner that the type of error can be specified. Specifically, an error code corresponding to the type of error is displayed on the liquid crystal display 10.

  FIG. 8B shows the control content of the communication error process executed by the CPU of the sub microcomputer 40. This communication error process corresponds to the error process according to the present invention, and is executed when a communication error described later is detected. Specifically, in such communication error processing, a communication error display indicating the occurrence of a communication error is displayed on the liquid crystal display 10 (S401), and it is determined whether or not an error cancellation condition is satisfied (S402). Then, the communication error display (S401) is continued until it is determined that the error cancellation condition is satisfied. While this communication error display (S401) continues, no other image is displayed on the liquid crystal display 10. In this embodiment, when the power is turned on again and the front door 3 is opened, an error cancellation condition for ending the communication error process is set. Specifically, the initialization process is executed only when the power-on command and the door command are received and the door command indicates that the front door 3 is opened, and the communication error process is completed by the initialization. To do. In other words, during the execution of the communication error process, even if only the power-on command is received, the initialization process is not performed and the communication error process is not terminated. In this embodiment, since the error cancellation condition is configured in this way, the locked front door 3 must be opened when the communication error process is terminated. For this reason, when communication error processing is executed due to fraud, it is possible to prevent a person who has performed fraud from canceling communication error processing. In addition, even if a fraudster can open the front door 3, it is obviously unnatural that someone other than the attendant of the game hall opens the front door 3 during business hours. Because it attracts the attention of third parties, including attendants at the amusement hall, it is possible to realize early detection of fraud.

  FIG. 8C shows the control contents of the data fetching process executed by the CPU of the sub microcomputer 40. Specifically, in this data fetching process, first, a read signal is transmitted from the sub microcomputer 40 to the FIFO circuit 50 of the parallel communication circuit 41 (S501), and whether or not configuration data is received from the FIFO circuit 50. Is determined (S502). If it is determined that the configuration data has been received from the FIFO circuit 50, the configuration data is stored in the reception buffer 47 (S503), and the data fetching process is terminated. On the other hand, when it is determined that the configuration data has not been received, that is, when the configuration data is not stored in the FIFO circuit 50, the data fetching process is terminated as it is. This data fetching process is executed every time the aforementioned interrupt occurs. That is, the data fetching process is normally executed at intervals of 1.2 milliseconds. However, when the processing load of other interrupt processing increases in the CPU of the sub microcomputer 40, the execution of the data fetching process may be postponed and the execution interval may exceed 1.2 milliseconds.

  The CPU of the sub-microcomputer 40 executes a communication error detection process every time the aforementioned interrupt occurs. In the communication error detection process, a communication error is detected based on data received from the main control board 14, and the communication error process is executed according to the content of the detected communication error. That is, the communication error detection process realizes the first communication error detection process and the second communication error detection process according to the present invention. Specifically, in the communication error detection process, whether or not the CPU of the sub-microcomputer 40 has received new configuration data (new configuration data) at an interval of 1.2 milliseconds at which an interrupt occurs. And the number of times of continuous determination that new configuration data has not been received is counted, thereby monitoring the configuration data reception interval. As described above, the configuration data is always transmitted from the main control board 14 at intervals of 1.8 milliseconds, and the transmitted configuration data is captured by the reception buffer 47 at intervals of 1.2 milliseconds by the data capturing process. For this reason, when communication is normally performed, new configuration data is confirmed in the reception buffer 47 at least once (2.4 milliseconds) in the communication error detection process. In other words, in the communication error detection process, when the reception of new configuration data cannot be confirmed continuously twice or more, the communication is not normally performed.

  In this embodiment, the communication error detection process detects a case where the reception of the configuration data cannot be confirmed continuously three times or more as a severe communication error. The case where reception of configuration data cannot be confirmed three or more times consecutively corresponds to a state where configuration data has not been received for 3.6 milliseconds, and two pieces of configuration data to be received at 1.8 millisecond intervals. This is a case where continuous reception was not possible. Most communication errors that occur spontaneously cannot receive the configuration data independently. Therefore, if the configuration data cannot be received in succession two times, there is a very high possibility that it is caused by fraud. For this reason, in this embodiment, when such a severe communication error is detected, the communication error process is immediately executed. That is, the severe communication error corresponds to the first communication error according to the present invention, and the determination time of 3.6 milliseconds for detecting the severe communication error corresponds to the predetermined determination time according to the present invention. To do.

  On the other hand, in this embodiment, a case where the checksum (error detection code) of the command does not match is detected as a minor communication error. Specifically, when the CPU of the sub-microcomputer 40 receives the configuration data “CH” in which the checksum is stored, the checksum is checked, and if the checksum does not match, it is detected as a minor communication error. Even if only one piece of configuration data that should be received from the main control board 14 side at intervals of 1.8 milliseconds cannot be received, a checksum error can occur, so this minor communication error is caused by fraud. It may be possible, but it may have occurred spontaneously. For this reason, in this embodiment, simply detecting a minor communication error does not execute communication error processing, and if a minor communication error is repeated at a frequency that is not considered to be a spontaneous occurrence, Communication error processing is to be executed. Specifically, as shown in FIG. 9A, the CPU of the sub-microcomputer 40 counts the number of minor communication errors detected as an error count, and performs communication error processing when the error count reaches three times. At the same time, the detection interval of the minor communication error is measured by a timer, and as shown in FIG. 9B, when the minor communication error is not detected for a predetermined time, the error count is initialized (0 times). That is, the minor communication error corresponds to the second communication error according to the present invention. The error count corresponds to the error counting means according to the present invention, and three error counts correspond to the predetermined number of detections according to the present invention. The timer constitutes initialization means for error counting means according to the present invention.

Next, the execution mode of the communication error detection process will be described using a timing chart.
FIG. 10A is a timing chart when the winning determination command and the active command are normally transmitted and received. In such an example, the main control board 14 transmits a winning determination command and an active command at intervals of 1.8 milliseconds for each configuration data. On the other hand, when the sub control board 15 executes the data fetching process and the communication error detection process at intervals of 1.2 milliseconds and confirms new configuration data in the reception buffer 47, the sub-control board 15 sets the reception count to the initial value “5”. If the configuration data cannot be confirmed, 1 is subtracted from the reception count. This reception count is used to count the number of times that the reception of new configuration data cannot be continuously confirmed in the communication error detection process. When this reception count is “2”, a severe communication error occurs. That is, this reception count constitutes the non-reception frequency counting means according to the present invention. In the example of FIG. 10A, since the configuration data is normally received, the reception count does not become 2 or less, and the communication error process is not executed.

  FIG. 10B is a timing chart when a severe communication error is detected. In such an example, although the winning determination command and the active command are transmitted from the main control board 14, two component data (“05” and “01”) of the winning determination command are continuously received for some reason. Does not reach 47. In this case, the sub-control board 15 determines that there is no new configuration data (Err) in the reception buffer 47 at the timing (T2, T4) at which two configuration data that have not arrived should be received, and the reception count is subtracted. Is done. For this reason, in such an example, the reception count is subtracted to “2” at time T4 in the figure, resulting in a severe communication error, and communication error processing is executed at time T5 in the figure.

  FIG. 11 is a timing chart when a minor communication error is detected. In such an example, although the winning determination command and the active command are transmitted from the main control board 14, the winning buffer determination command and the active command configuration data (“05”, “08”) are received by one unit for some reason. Does not reach 47. In this case, the sub-control board 15 determines that there is no new configuration data (Err) in the reception buffer 47 at the timing (T2, T10) at which the two configuration data that have not arrived should be received. For this reason, in such an example, when the configuration data “CH” storing the checksum is received at time T5 in the figure, the checksum check result does not match, resulting in a minor communication error and an error count. Is added to 1 and a timer for measuring a predetermined time is activated. At time T13 in the figure, a minor communication error occurs again due to a checksum mismatch, the error count is incremented to 2, and the timer is reset to the initial setting to start measuring a predetermined time from the beginning. To do. In this example, a minor communication error is detected before the timer expires the predetermined time, so the error count is 2. However, if the timer expires before the minor communication error is detected, the error count Is reset to zero.

  As described above, in this embodiment, the CPU of the sub-microcomputer 40 determines whether or not new configuration data has been received at regular intervals (1.2 millisecond intervals), and continuously receives configuration data. The configuration data reception interval is monitored by counting the number of times it is determined that the configuration data has not been detected, and a serious communication error is detected when the configuration data reception interval exceeds twice the configuration data transmission interval. As described above, such a severe communication error is not a spontaneous communication error, but is highly likely to be a communication error caused by fraud. Therefore, based on the detection of such a severe communication error, it is severe. Even if the communication error process is executed, the player who is playing the game correctly is not disturbed. Therefore, according to the slot machine 1 of the present embodiment, it is possible to appropriately control fraudulent acts that interfere with command communication.

  In this embodiment, the main microcomputer 30 generates and sends an active command when no command is present in the transmission buffer 34, so that the configuration data is always sent at intervals of 1.8 milliseconds. Therefore, the sub-microcomputer 40 has an advantage that the communication error detection process can be constantly executed to monitor fraud without interruption.

  In the present embodiment, the sub microcomputer 40 detects a case where the command checksums do not match as a minor communication error, and if this minor communication error is detected at a certain frequency or more, the same communication as the severe communication error is detected. Perform error handling. Minor communication errors may be caused by fraud and may occur spontaneously. Thus, communication error processing is performed only when the detection frequency exceeds a certain frequency. If executed, the communication error process can be executed only when it is considered that the communication error is caused by an illegal act, and an illegal act that cannot be detected as a severe communication error can be appropriately controlled. Further, since the minor communication error is detected based on the contents of the configuration data, the modification of the configuration data that cannot be detected by the severe communication error can be detected and controlled by the minor communication error.

  FIG. 12A is a timing chart showing how the configuration data is received when the data fetching process is extended by the sub-microcomputer 40 in this embodiment. In such an example, the main control board 14 transmits a winning determination command at intervals of 1.8 milliseconds for each configuration data. Each configuration data transmitted by the main control board 14 is stored in the FIFO circuit 50 of the sub control board 15 without delay. The configuration data stored in the FIFO circuit 50 is taken into the reception buffer 47 from the FIFO circuit 50 by the data taking process of the sub microcomputer 40. Here, the data fetching process is basically executed at an interval of 1.2 milliseconds. In this example, the load on the CPU of the sub microcomputer 40 is temporarily increased, so that T1 to T1 in the figure. The execution interval of the data fetching process is about 3 milliseconds until T2. Then, two pieces of configuration data (“05”, “01”) are transmitted from the main control board 14 between T1 and T2. At this time, since a plurality of configuration data can be stored in the FIFO circuit 50, the previous configuration data “05” is not discarded even after the second configuration data “01” is transmitted, and the FIFO circuit 50 is not discarded. Two pieces of configuration data are stored and held. When the sub microcomputer 40 transmits a read signal to the FIFO circuit 50 at time T2 in the figure, the configuration data “05” stored in advance is input from the FIFO circuit 50 to the sub microcomputer 40. The configuration data “05” is stored in the reception buffer 47. The remaining configuration data “01” is fetched from the FIFO circuit 50 in the next data fetching process (T3 in the figure) and stored in the reception buffer 47. As described above, in this embodiment, even when the data fetching process is extended, the constituent data of the winning determination command is received by the sub microcomputer 40 without being lost by the action of the FIFO circuit.

  FIG. 12B is a timing chart showing a case where the data fetching process is extended in the comparative example in which a simple latch circuit is provided in the parallel communication circuit 41 instead of the FIFO circuit. In this comparative example, as in FIG. 12A, the main control board 14 transmits a winning determination command at intervals of 1.8 milliseconds for each configuration data. In the comparative example, each configuration data transmitted by the main control board 14 is stored in the latch circuit of the sub control board 15 without delay, not in the FIFO circuit. Here, since only the latest configuration data inputted from the main control board 14 can be stored and held in the latch circuit, from the main control board 14 while the data fetching process is extended as shown by T1 to T2 in the figure. When two pieces of configuration data (“05”, “01”) are transmitted, the configuration data “05” stored earlier is stored when the second configuration data “01” is stored in the latch circuit. Discarded from the latch circuit. For this reason, in this comparative example, the winning determination command transmitted by the main control board 14 is received by the sub-microcomputer 40 in a state where some of the configuration data “05” is missing, and at the time T5 in FIG. As a result, a minor communication error is detected, and an error count is added to 1.

  As is apparent from a comparison between FIGS. 12A and 12B, in the present embodiment, before the sub microcomputer 40 fetches the previous configuration data, the following configuration is made from the main control board 14. Even when data is transmitted, there is an advantage that the sub-microcomputer 40 can receive the command configuration data without being missed by the function of the FIFO circuit 50. Missing configuration data not only makes the received command unexecutable, but can also be detected as a minor communication error, so if the number of spontaneous minor communication errors caused by missing configuration data increases, As described above, it is difficult to discriminate between minor communication errors due to fraud and naturally occurring minor communication errors based on the frequency of occurrence, and it is difficult to control fraudulent acts. Can be prevented appropriately, and this problem can be avoided.

Next, the control process of the communication error detection process will be described.
FIGS. 13 and 14 are flowcharts showing the control contents of the communication error detection process executed by the CPU of the sub microcomputer 40. In the communication error detection process, the CPU of the sub microcomputer 40 first subtracts the reception count (S601), and then determines whether or not the reception count is 1 (S602). If it is determined that the reception count is 1, the communication error process (see FIG. 8B) is executed (S603), and the communication error detection process is terminated. If it is determined in step S602 that the reception count is not 1, if the timer for resetting the error count is not 0, 1 is subtracted from the timer (S700), and new configuration data is stored in the reception buffer 47. It is determined whether or not (S701). If it is determined that there is no new configuration data in the reception buffer 47, the process proceeds to step S708. If it is determined that there is configuration data in the reception buffer 47, the reception count is set to the initial value “5” (S702). The process proceeds to step S703. In step S703, it is determined whether the configuration data of the reception buffer 47 is the configuration data “CH” of the fourth byte of the command. If it is determined that the configuration data is not the configuration data “CH” of the fourth byte, step S708 is performed. Migrate to On the other hand, if it is determined that the configuration data is “CH” in the fourth byte, it is determined whether or not the checksum matches the data portion received immediately before (S704). If it is determined that the checksums match, the process proceeds to step S708. If it is determined that the checksums do not match, 1 is added to the error count (S705), and the process proceeds to step S706. In step S706, it is determined whether or not the error count is 3. If it is determined that the error count is 3, communication error processing (see FIG. 8B) based on three minor communication error detections is executed (S710), and the communication error detection processing is terminated. On the other hand, if it is determined in step S706 that the error count is not 3, an initial value (predetermined time) is set in the timer (S707), and the process proceeds to step S708. In step S708, it is determined whether or not the timer is 0, that is, whether or not the measurement of the set time has expired. If it is determined that the timer is not 0, the communication error detection process is terminated and the timer is 0. If it is determined that there is an error, the error counter is initialized to 0 (S709), and the communication error detection process is terminated.

  In the control content of the communication error detection process, the first communication error detection means according to the present invention is mainly realized by steps S601, S602, S702, and S703. The second communication error detection means according to the present invention is mainly realized by steps S703 and S704. Also, the reception status confirmation means according to the present invention is mainly realized by step S701. Further, the non-reception frequency counting means according to the present invention is mainly realized by steps S601 and S702. Further, the error counting means according to the present invention is mainly realized by step S705. The initialization means according to the present invention is mainly realized by steps S700, S707, S708, and S709. The error processing execution means according to the present invention is mainly realized by steps S603 and S710.

  Note that the gaming machine of the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, in the above embodiment, the present invention is applied to a slot machine, but the present invention can be similarly applied to a gaming machine such as a pachinko machine. In the above embodiment, the present invention is applied to the communication between the main control board and the sub control board of the slot machine, but the present invention is limited to the communication between the main control board and the sub control board. is not. The present invention is particularly effective for a configuration in which control information is transmitted in one direction from the first control unit to the second control unit. However, the present invention has a configuration in which control information is transmitted in both directions. Is also applicable.

  In the above embodiment, the communication means of the present invention is constituted by the parallel communication circuits 33 and 41 of both control boards 14 and 15 and the signal line 16. However, the communication means of the present invention is a serial communication system. It can also be configured by a communication circuit. In the above embodiment, both control boards 14 and 15 are directly connected via the signal line 16. However, the communication means of the present invention includes a relay board that relays between the control boards 14 and 15. You can also In this case, the configuration data is transmitted from the main control board 14 to the relay board by the parallel communication system, and is transmitted from the relay board to the sub-control board 15 by the serial communication system. You can also

  In the above embodiment, the control information (command) is 5-byte data, and each control information is divided into 1-byte unit data and transmitted. However, the control information according to the present invention has a variable length. Alternatively, the size of the control information and the configuration data may be equalized, and the control information may be transmitted as one configuration data without being divided. In the above embodiment, the predetermined determination time according to the present invention is set to twice (3.6 milliseconds) the transmission interval of configuration data (1.8 milliseconds), and two pieces of configuration data are continuously transmitted. In this case, the predetermined determination time according to the present invention should be set to a length that can sufficiently eliminate a spontaneous communication error. In some cases, the value may be set to a value other than twice the transmission interval of the configuration data.

  In the above embodiment, when a severe communication error (first communication error) is detected, a communication error is displayed on the liquid crystal display 10. However, the contents of error processing and the release conditions according to the present invention are appropriately set. It can be set. In the above embodiment, when a minor communication error (second communication error) is detected at a high frequency, communication error processing (error processing) is executed. In the present invention, a minor communication error is detected. A lighter error process than the communication error process may be executed once or at a low frequency.

  In the above embodiment, the timer for resetting the error count (error counting means) is initialized every time a minor communication error is detected. However, when the second minor communication error is detected, the timer is initialized. Instead, the error count may be initialized when the timer expires the predetermined time before detecting the third minor communication error. Further, instead of expiration of the timer measurement, an error count may be initialized when a predetermined command is received a predetermined number of times.

  In the above embodiment, the case where the checksum of the command does not match is detected as a minor detection error, but instead of or in addition to the checksum check, the configuration data having a fixed value is included in the command. It may be determined whether the value is normal. Specifically, in any of the commands of the above-described embodiment, a fixed value “AA (hexadecimal number)” is stored in the head configuration data “ST” in any command, and the fifth configuration The data “EN” stores a fixed value “BB (hexadecimal number)”. For this reason, for example, when the CPU of the sub microcomputer 40 receives the configuration data of the first byte, it determines whether the received configuration data is “AA”, thereby generating a communication error. It can be detected. In addition, when the configuration data “AA” is received, the occurrence of a communication error can also be detected by determining whether the configuration data received fifth from the configuration data is “BB”. .

1 slot machine (game machine)
2 housing 3 front door 4 viewing window 5a, 5b bet switch 6 start switch 7 stop switch 8 settlement switch 9 reel 10 liquid crystal display 11 speaker 12 presentation lamp 14 main control board (first board)
15 Sub-control board (second board)
16 Signal line 18 Power-on switch 19 Power supply box 20 Hopper unit 22 Front door open detection sensor 23 Reflector 30 Main microcomputer (first control means)
40 Microcomputer for sub (second control means)
33 Parallel communication circuit (first communication circuit)
47 Receive buffer 41 Parallel communication circuit (second communication circuit)
50 FIFO circuit

Claims (5)

A first control means disposed on the first substrate for transmitting control information;
A second control unit disposed on the second substrate and performing control based on the control information received from the first control unit;
A gaming machine comprising communication means for transferring data from the first control means to the second control means as a unit of transfer of predetermined configuration data,
The first control means includes
Control information generating means for generating the control information, and transmission means configured to transmit the configuration data one by one at a predetermined transmission interval via the communication means,
The control information generated by the control information generating means is transmitted in units of the configuration data by the transmitting means,
The communication means includes
A first communication circuit disposed on the first substrate and outputting the configuration data transmitted by the first control means to the outside of the first substrate;
A second communication circuit disposed on the second substrate and receiving the configuration data from the first communication circuit via a signal line;
The second control means includes
Each time the configured interrupt to occur at predetermined intervals, and transmits the read signal to the second communication circuit, capturing the configuration data input to said second communication circuit from the second communication circuit receiving means for receiving the configuration data by executing a data acquisition processing,
A first communication error detecting means for detecting, as a first communication error, a state in which a reception interval at which the receiving means receives the configuration data exceeds a predetermined determination time;
The control information generation means generates specific control information when the control information to be transmitted by the transmission means does not exist,
The transmission means periodically transmits the configuration data at the transmission interval over a transmission period of a plurality of the control information by transmitting the specific control information,
The predetermined determination time is at least twice as long as the transmission interval of the configuration data by the transmission means,
Further, the second communication circuit includes a FIFO circuit that temporarily stores and holds the configuration data input from the first communication circuit until it is captured by the receiving unit.
The FIFO circuit is capable of storing and holding a plurality of the configuration data at the same time, and when receiving the read signal , the FIFO circuit is a circuit that causes the reception means to sequentially take in the configuration data stored previously. Gaming machine.   The first control unit divides the control information generated by the control information generation unit into a plurality of the configuration data, and transmits the plurality of configuration data one by one at the transmission interval by the transmission unit. The gaming machine according to claim 1, wherein: The first communication error detecting means is
A reception state confirmation unit that determines whether or not the reception unit has received the configuration data each time the data fetching process is executed;
The reception state confirmation means comprises an unreception count counting means for counting the number of times of continuous determination that the configuration data has not been received;
3. The first communication error according to claim 1 , wherein the first communication error is detected when the number of counts of the unreceived number counting means reaches a number corresponding to the predetermined determination time. Game machines. It said second control means according to claim 1 to claim 3, characterized in that it comprises a second communication error detecting means for detecting an abnormality of the contents of the configuration data received by the receiving means as the second communication error The gaming machine according to any one of the above. The second control means includes
Error counting means for counting the number of times the second communication error is detected by the second communication error detecting means;
Initialization means for initializing the error counting means upon establishment of a predetermined condition;
Error processing execution means for executing error processing when the first communication error detection means detects the first communication error or when the number of counts of the error counting means reaches a predetermined number of detections; The gaming machine according to claim 4 , further comprising:

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