JP5598114B2 - Arithmetic unit - Google Patents

Description

  The present invention relates to an arithmetic unit.

  Among processors used in supercomputers, there are processors equipped with arithmetic units as shown in FIGS.

  The arithmetic unit shown in FIG. 8 includes four arithmetic units p0 to p3 capable of executing ALU processing, MUL processing, and LDST processing, and for each instruction input to the instruction buffer, an arithmetic unit pX ( X = 0 to 3) is a unit that operates a plurality of times. Note that the ALU processing is addition processing, logical operation processing, and the like. Further, the MUL system process is a multiplication process or the like, and the LDST system process is a load process or a store process.

  More specifically, the control path of this arithmetic unit changes a specific process and an operand (register in a register file to be read / written) to each arithmetic unit pX capable of executing and executing various processes. However, it is a unit (circuit) that can be performed a plurality of times (for a plurality of cycles). Then, the scheduler of this arithmetic unit fetches the instruction in the instruction buffer every cycle, and the arithmetic unit pX not executing the processing (or completing the processing in the current cycle) starts the operation for a plurality of cycles. As a result, it is a unit that controls the control path.

  Similarly to the arithmetic unit of FIG. 8, the arithmetic unit shown in FIG. 9 is also a unit in which the arithmetic unit pX (X = 0 to 7) operates a plurality of times for each instruction input to the instruction buffer. . However, this arithmetic unit is not an arithmetic unit having all processing functions (FIG. 8), but arithmetic units p0 to p7 having only a single processing function (operators p0 to p3 capable of only ALU processing, MUL It is a unit including arithmetic units p4 and p5 capable of performing only system processing and arithmetic units p6 and p7) capable of performing only LDST system processing.

JP 2004-38751 A

J. et al. L. Hennessy, D.C. A. By JL Hennessy and DA Patterson, "Computer Architecture: A Quantitative Approach" (USA), 2nd edition, Morgan Kaufmann Publishers, 1996, Appendix B Vector Processor (Appendix B Vector Processors)

  The functions required of the scheduler of an arithmetic unit (FIG. 9) in which each arithmetic unit has only a single processing function are basically free (processing) that can be an instruction issue destination. Is not being executed / processing is completed in the current cycle). Therefore, this arithmetic unit is easy to design and manufacture a scheduler. However, this arithmetic unit has a disadvantage that a register file with a large number of ports is required, that is, a circuit scale must be increased.

  Further, the function required for the scheduler of the arithmetic unit (FIG. 8) in which each arithmetic unit has all the processing functions is only a function for specifying an empty arithmetic unit. Therefore, this arithmetic unit is also easy to design and manufacture the scheduler. In addition, since this arithmetic unit requires a relatively small number of ports in its register file, this arithmetic unit is less than the configuration of FIG. 9 from the viewpoint of reducing the manufacturing cost and power consumption of the arithmetic unit. It is better to adopt the configuration of FIG.

  However, since the usage frequency of the ALU processing function is usually higher than the usage frequency of the other processing functions, when the configuration of FIG. 8 is adopted, the use of the LDST processing function or the MUL processing function of a certain arithmetic unit is used. An arithmetic unit having a low frequency, that is, an arithmetic unit having a circuit that is not efficiently used is obtained.

  If the number of circuits that are not efficiently used can be reduced, the manufacturing cost and power consumption of the arithmetic unit can be reduced. Accordingly, as shown in FIG. 10, the arithmetic unit includes arithmetic units p0 and p1 capable of executing ALU processing and MUL processing, and p2 and p3 capable of executing ALU processing and LDST processing. It is conceivable to be provided.

  However, in the arithmetic unit adopting this configuration, there arises a problem that does not occur in the arithmetic unit (FIG. 8) in which each arithmetic unit has all processing functions.

  Specifically, in the configuration shown in FIG. 8, each instruction is issued to an empty pipeline (part consisting of an arithmetic unit and a circuit in a control path for operating it multiple times). If a scheduler is installed, it is possible to realize an arithmetic unit in which each pipeline functions efficiently (the unused time of each pipeline is short).

  On the other hand, the configuration shown in FIG. 10 cannot realize an arithmetic unit in which each pipeline functions efficiently if a scheduler having only such a level of instruction issue function is used. ing.

  Specifically, for each instruction, the scheduler of the arithmetic unit in FIG. 10 searches for an empty pipeline having a function to process (execute) the instruction in a predetermined order, and the instruction is searched for the searched pipeline. For ALU instructions, search for empty pipelines in the order of pipelines p0, p1, p2, and p3. For MUL instructions, search for empty pipelines in the order of pipelines p0 and p1. For the LDST instruction, it is assumed that an empty pipeline is searched in the order of pipelines p2 and p3.

  Then, in the instruction buffer of the arithmetic unit having such a configuration, an ALU instruction vadd that needs to be added eight times, a MUL instruction vmul that needs to be multiplied eight times, and a load process eight times Consider a case where an LDST instruction vload that needs to be executed and a MUL instruction vmul that needs to be multiplied eight times are input in this order.

  In this case, as shown in FIG. 11, after the first instruction vadd is issued to the pipeline p0, the instructions vmul and vload are sequentially issued to the pipelines p1 and p2. Therefore, when the fourth instruction vmul is fetched by the scheduler, only the pipeline p3 that cannot process the MUL instruction is free. Since the pipeline that can process the MUL instruction is free in the ninth cycle, the fourth instruction vmul is issued to the pipeline p0 in the ninth cycle.

That the series of instructions described above are processed in this manner means that each pipeline is not efficiently used in this arithmetic unit. This is because these instructions, as shown in FIG. 12, first issue the first instruction vadd to the pipeline p3, and then sequentially execute the instructions to the pipelines p1, p2, and p0. This is because if vmul, vload, and vmul are issued, they can be issued for each cycle.

  As described above, the configuration shown in FIG. 10 cannot realize an arithmetic unit in which each pipeline functions efficiently if a scheduler having a relatively simple configuration is used. It is extremely difficult to design a scheduler that can determine that instructions in the instruction buffer should be issued to each pipeline in the order shown in FIG. Moreover, such a scheduler must be large in circuit scale.

  Therefore, the problem with the disclosed technology is that it is an arithmetic unit that can be manufactured at low cost with multiple pipelines that perform multi-cycle operation, and each pipeline can be efficiently operated without having a scheduler with a complicated configuration. It is to provide an arithmetic unit that can be operated in an automatic manner.

  In order to solve the above problems, an arithmetic unit according to an aspect of the disclosed technology includes one or more first pipelines having a first type process execution function and a second type process execution function, and a first type A plurality of pipelines that perform a multi-cycle operation, including one or more second pipelines having a seed processing execution function and a third type processing execution function, and a second pipe that is ready to start a new process And a control circuit having a function of taking over a first type loop process that has already been started by a first pipeline and that is completed by executing the first type process a plurality of times.

  If the above configuration is adopted, it is an arithmetic unit that can be manufactured at low cost with multiple pipelines that perform multi-cycle operation, and each pipeline can be efficiently operated without having a complicated scheduler. It is possible to realize an arithmetic unit that can be operated automatically.

The schematic block diagram of the arithmetic unit which concerns on embodiment. Explanatory drawing of the control information memorize | stored in the control information register | resistor of an arithmetic unit. The flowchart of the instruction issue process which a scheduler performs. Explanatory drawing of the control content by a scheduler. Explanatory drawing of the control content by a scheduler. Explanatory drawing of the control content by a scheduler. The schematic block diagram of the arithmetic unit provided with several existing pipelines which have all the processing functions. Explanatory drawing of a modification example of an existing arithmetic unit having a plurality of pipelines having a single processing function Explanatory drawing of the modification / improvement example of the arithmetic unit provided with the some pipeline which has the existing all processing function. The schematic block diagram of the arithmetic unit provided with the some pipeline which has the existing single processing function. Explanatory drawing of the structure which it is desirable to employ | adopt about an arithmetic unit. The figure for demonstrating the problem which may arise when the structure of FIG. 10 is employ | adopted. Explanatory drawing for demonstrating the problem which may arise when the structure of FIG. 10 is employ | adopted.

First, the outline of the arithmetic unit 10 according to the embodiment will be described with reference to FIGS. 1 and 2. Of these drawings, FIG. 1 is a schematic configuration diagram of the arithmetic unit 10, and FIG. 2 is an explanation of control information stored in the control information register 21 _X (X = 0 to 3) of the arithmetic unit 10. FIG.

  As shown in FIG. 1, the arithmetic unit 10 according to the embodiment includes an instruction buffer 11, a scheduler 12, a control path 13, and a data path 14.

  The data path 14 is a unit (functional block, circuit) that actually performs various processes on data. The data path 14 includes a register file 25 and four arithmetic units p0 to p4.

  The register file 25 includes a plurality of registers (in the present embodiment, eight 64-bit registers) and a plurality of registers (in the present embodiment, 32 64-bit registers) having a plurality of read ports and a plurality of write ports (not shown). It is an aggregate.

  The arithmetic units p0 and p1 are both units (hereinafter also referred to as MUL type arithmetic units) capable of executing ALU processing (addition processing, logical operation processing, etc.) and MUL processing (multiplication processing, etc.). . The arithmetic units p2 and p3 are both units (hereinafter also referred to as LDST type arithmetic units) capable of executing ALU processing and LDST processing (load processing, store processing, etc.).

  Each arithmetic unit pX (X = 0 to 3) in the data path 14 is a unit that completes one process during one cycle (an instruction issue cycle of the scheduler 12 described later). Each computing unit pX is a unit that can perform only one process in one cycle (a unit that cannot simultaneously execute a plurality of processes). For convenience of illustration, FIG. 1 shows the calculation result of each calculator pX outside the register file 25, but the data path 14 indicates that the calculation result of each calculator pX is a specific value in the register file 25. It is stored in the register.

  The instruction buffer 11 is a buffer (a kind of FIFO memory) for storing instructions received by the arithmetic unit 10 in time series.

  The scheduler 12 reads (fetches) the first instruction (the instruction received in the past in the past) in the buffer 11 for each cycle, and processes the contents corresponding to the read instruction to the data path 14 (and the control path 13). The unit to be started. Although details of the scheduler 12 will be described later, an instruction received by the arithmetic unit 10 (an instruction processed by the scheduler 12) is, in principle, an instruction that can be executed by operating a certain arithmetic unit pX a plurality of times. More specifically, the instruction received by the arithmetic unit 10 is, in principle, an instruction that can be executed by repeating an addition process or the like (a process that can be executed by any of the arithmetic units pX) a plurality of times while changing its operand. ing.

The control path 13 is a unit that controls the data path 14 based on control information (details will be described later) given from the scheduler 12. The control path 13 includes four control information registers 21 _{0 to} 21 ₃ , four instruction update circuits 22 _{0 to} 22 ₃ , and four two-input multiplexers 23 ₀ to 23.
23 ₃ , and four three-input multiplexers 24 _{0 to} 24 ₃ .

Each control information register 21 _X (X = 0 to 3) provided in the control path 13 includes control information having a configuration as shown in FIG. 2, that is, arithmetic unit control information, operand information, the current number of loops, and the like. This is a register for storing control information (32-bit information in this embodiment).

This control information is information in which the scheduler 12 sets an initial value and the instruction update circuit 22 _X periodically updates the contents (at the time of transition to the next cycle).

Specifically, the arithmetic unit control information in the control information on the control information register 21 _X is information supplied to the arithmetic unit pX in order to specify the processing (type of processing) to be performed in the next cycle (see FIG. 1). Operand information is information including designation information (src0, src1, dst in FIG. 2) of some registers in the register file 25 that should be read / written in the type of processing designated by the arithmetic unit control information. is there. As schematically shown in FIG. 1, the operand information on each control information register 21 _X is, for example, register designation information for outputting data to the arithmetic unit pX (in FIG. 1, those corresponding to src0 and src1) Only the two arrows) are supplied to the register file 25.

The current loop count (FIG. 2) is an instruction update circuit for determining whether or not the control information on the control information register 21 _X needs to be updated (it is also necessary to make the arithmetic unit pX function in the next cycle). 22 _X is information to be referred to. Note that the processing performed by the instruction update circuit 22 _X when the arithmetic unit pX needs to function in the next cycle is performed after changing the operand information and the current loop count for the control information read from the control information register 21 _X. This is a process of outputting (resetting to the control information register 21 _X ).

Each 2-input multiplexer 23 _X in the control path 13 (FIG. 1) enables the scheduler 12 to set control information in the control information register 21 _X and update the control information by the instruction update circuit 22 _X. It is a provided multiplexer.

Each three-input multiplexer 24 _X is controlled by the instruction update circuit 22 _X using the control information register 21 _X.
Is a multiplexer provided so that the control information set in can be set in another control information register 21 _Y (Y ≠ X; details will be described later).

And Aru circuit configuration shown in FIG. 1 as apparent from (connection form between the other components), 3-input multiplexer 24 ₀ is control information updated about LDST ALUs p2 or p3 (i.e., the instruction updating circuit 22 _2, 22 ₃ of the output), which is assumed to be set in the control information register 21 _0. The 3-input multiplexer 24 ₁ can also set updated control information related to the LDST arithmetic unit p2 or p3 in the control information register 21 ₁ .

Then, the three-input multiplexers 24 ₂ and 24 ₃ respectively send the updated control information (outputs of the instruction update circuits 22 ₀ and 22 ₁ ) related to the MUL arithmetic units p0 or p1 to the control information registers 21 ₂ and 21 ₃ . It can be set.

Based on the above, the configuration and operation of the arithmetic unit 10 will be described in more detail below. In the following description, the part composed of the control information register 21 _X , the instruction update circuit 22 _X , the arithmetic unit pX, etc. [the part consisting of the arithmetic unit pX and the configuration for operating the arithmetic unit pX multiple times] , Written as pipeline pX. Further, the pipelines p0 and p1 (that is, the pipeline including the MUL arithmetic units p0 and p1) are denoted as MUL pipelines p0 and p1, and the pipelines p2 and p3 are denoted as LDST pipelines. They are expressed as p2 and p3.

FIG. 3 shows a flowchart of instruction issue processing executed by the scheduler 12 to issue one instruction on the instruction buffer 11 to any pipeline pX. This instruction issue processing is performed by the scheduler 12 in principle (except when the step S105 is executed).
This process starts every cycle. Although there are various other issuance restrictions such as register interference, it is assumed that only resource contention exists for the sake of simplicity in this processing flow.

  That is, since the predetermined timing has come, the scheduler 12 that has started the instruction issuing process first reads out the first instruction (the instruction received in the past) on the instruction buffer 11 (step S101).

  Next, the scheduler 12 checks whether or not the pipeline pX that can issue the read instruction is empty in order of priority assigned in advance to each pipeline pX for each instruction type (step S102). Note that “the pipeline pX is free” means that a new process can be started in the next cycle (the process in which the pipeline pX is not performing or the pipeline pX is being executed is the current cycle). It ends with). A pipeline pX that can issue an instruction (see FIG. 1) is an ALU instruction (addition instruction, logical operation instruction, etc.), which is a pipeline p0 to p3, and a MUL instruction (multiplication). (Instructions, etc.) refers to pipelines p0, p1, and LDST instructions (load instructions, store instructions, etc.) refer to pipelines p2, p3.

If there is a pipeline pX that can issue the read instruction (step S103; YES), the scheduler 12 issues an instruction to the pipeline pX (step S108). More specifically, the scheduler 12 sets the control information (see FIG. 2) according to the read instruction in the control information register 21 _X of the pipeline pX that has been found free by the process of step S102. This processing is performed in step S108.

  Then, the scheduler 12 that has finished the process of step S108 once ends the process of FIG. 3 and the timing to start the process of FIG. 3 is reached (one cycle has passed and the next instruction on the instruction buffer 11 is It is in a state of waiting for the timing to be processed.

  On the other hand, when there is no pipeline pX that can issue the read instruction (step S103; NO), the scheduler 12 determines whether or not the process takeover enabling condition is satisfied (step S104).

  Here, the process takeover enabling condition is that when the read instruction is a MUL instruction, “there is an empty LDST pipeline and a MUL pipeline executing ALU processing” (LDST pipeline) at least one of p2 and p3 is free, and at least one of the MUL pipelines p0 and p1 is executing ALU processing). When the read instruction is an LDST instruction, “There is an empty MUL pipeline and an LDST pipeline executing ALU processing” (at least one of the MUL pipelines p0 and p1 is empty). And at least one of the LDST pipelines p2 and p3 is executing ALU processing ”.

  If the process takeover condition is satisfied, the scheduler 12 executes one pipeline executing ALU processing (MUL pipeline when processing a MUL instruction, and LDST processing when processing an LDST instruction. (Pipeline) is specified as the processing takeover source pipeline, and one available pipeline (LDST pipeline when processing MUL instructions, MUL pipeline when processing LDST instructions) Processing that identifies the pipeline is also performed. In this process, when there are two pipelines that can be the process takeover source / process takeover pipeline, the process takeover source / process is selected from the pipelines by a preset algorithm. One pipeline is selected as the takeover destination pipeline.

  In short, in step S104, the scheduler 12 determines that the read instruction is a MUL instruction, at least one of the LDST pipelines p2 and p3 is free, and at least one of the MUL pipelines p0 and p1 is an ALU process. Is executed, it is determined that the process takeover condition is satisfied. In addition, the scheduler 12 takes over processing of one MUL pipeline that has been found to be executing ALU processing and one LDST pipeline that has been found free at the time of the determination. Specify the original pipeline and the processing takeover destination pipeline.

  In the scheduler 12, the read instruction is an LDST instruction, at least one of the MUL pipelines p0 and p1 is free, and at least one of the LDST pipelines p2 and p3 is executing an ALU process. Even in this case, it is determined that the conditions for enabling the process takeover are satisfied. In addition, the scheduler 12 takes over processing of one LDST pipeline that has been found to be executing ALU processing and one MUL pipeline that has been found to be free at the time of the determination. Specify the original pipeline and the processing takeover destination pipeline.

If the scheduler 12 determines that the process takeover condition is satisfied (step S104; YES), the updated control information related to the process takeover source pipeline is used as the control information register related to the process takeover destination pipeline. 21 _X is set (step S106).
).

More specifically, when the read instruction is a MUL instruction, the scheduler 12 processes the control information updated by the instruction update circuit 22 _K of the process takeover source pipeline pK (K = 0 or 1). The three-input multiplexer 24 _L is controlled so as to be set in the control information register 21 _L regarding the takeover destination pipeline pL (L = 2 or 3). When the read instruction is an LDST instruction, the scheduler 12 updates the control information updated by the instruction update circuit 22 _K of the process takeover source pipeline pK (K = 2 or 3) to the process takeover destination pipeline. The three-input multiplexer 24 _L is controlled so that it is set in the control information register 21 _L regarding pL (L = 0 or 1).

Then, the scheduler 12, the processing takeover original pipeline pK, processing of issuing an instruction read from the instruction buffer 11 (step S107), i.e., performs the process of writing the control information in the control information register 21 _K.

  Then, the scheduler 12 once ends the process of FIG. 3 and enters a state of waiting for the timing to execute the process of FIG. 3 again.

  On the other hand, if it is determined in step S104 that the process takeover condition is not satisfied (NO), the scheduler 12 completes the processing of one of the pipelines (one of the pipelines performs a new process). It waits until it can be started (step S105).

  Then, when the processing of any pipeline is completed, the scheduler 12 starts the processing after step S102 again. Although not explicitly shown in the flowchart, in this case, the processing executed by the scheduler 12 in steps S102 and S103 is an instruction (issued in the previous cycle) that has been read from the instruction buffer 11 by the pipeline that has completed processing. This is a process for determining whether or not an instruction that could not be issued can be issued.

Although it is considered to be clear from the above description, the operation (function) of the present arithmetic unit 10 will be described based on a specific example.

  Consider a case where the same instructions vadd, vmul, vload, vmul as already described are input to the instruction buffer 11 of the arithmetic unit 10 in this order.

  In this case, when each instruction up to vload is processed, branching to the YES side is performed in step S103 of FIG. Therefore, for example, vadd, vmul, and vload are issued to the pipelines p0, p1, and p2, respectively, according to the priority setting contents for each pipeline.

  If vadd, vmul, and vload are issued to the pipelines p0, p1, and p2, respectively, the LDST pipeline p3 that cannot perform MUL-related processing when the fourth instruction vmul is processed It will only be free. Therefore, in this case, the scheduler 12 determines that there is no pipeline that can issue an instruction (step S103; NO), and determines whether or not the process takeover condition is satisfied (step S104).

  Since vmul is a MUL instruction, the LDST pipeline p3 is free, and the MUL pipeline p0 is executing an ALU process (vadd), the scheduler 12 takes over the process in step S104. Judge that the possible conditions are met. In step S104, the scheduler 12 specifies the MUL pipeline p0 that is executing the ALU processing as the processing takeover source pipeline, and specifies the vacant LDST pipeline p3 as the processing takeover destination pipeline. .

Thereafter, the scheduler 12 performs the process of step S106. That is, the scheduler 12, the process takeover control information updated by the instruction update circuit 22 ₀ of the original pipeline p0 is, as set in the control information register 21 ₃ about the processing takeover destination pipeline p3, 3-input multiplexer 24 ₃ To control.

  As already described, each pipeline pX provided in the present arithmetic unit 10 repeats processing in which only operands are different for each cycle. Any pipeline pX can execute ALU processing, and the pipeline identified by the scheduler 12 as a processing takeover source pipeline is a pipeline that executes ALU processing. Therefore, if the control information for the next cycle of the pipeline p0 is the control information for the next cycle of the pipeline p3, the process takeover source pipeline p0 has performed so far as schematically shown in FIG. The remaining part of the process ("vadd" in FIG. 4) is thereafter performed by the process takeover destination pipeline p3 ([1]).

  More specifically, as schematically shown in FIGS. 5A and 5B, the pipeline p3 causes the remaining part of the processing that the pipeline p0 has performed so far (in this case, addition processing (ALU processing) ) Is required to be repeated five times.

  Further, as schematically shown in FIG. 4, the scheduler 12 that has finished the process of step S106 issues vmul to the process takeover source pipeline p0 to which the control information has been moved ([2]). Therefore, as shown in FIGS. 5A and 5B, the processing related to the fourth instruction vmul is started from the fourth cycle immediately after the instruction is read by the pipeline p0.

As is apparent from the above description, the arithmetic unit 10 according to the embodiment is somewhat inferior in performance to the arithmetic unit of FIG. 6 because the number of MUL processing and LDST processing that can be executed simultaneously is small. However, in general, MUL-based processing and LDST-based processing are not frequently performed in a program, and therefore, almost the same performance can be expected in many programs. 6 shows the configuration of the arithmetic unit (FIG. 8) including the four pipelines p0 to p3 having all the processing functions described above in more detail (configuration of the arithmetic unit 10 shown in FIG. 1). (At the same level).

  Further, the scheduler 12 and the control path 13 of the arithmetic unit 10 can be realized by performing simple improvements to the scheduler and the control path of the arithmetic unit in FIG. 6, respectively. The data path 14 of the arithmetic unit 10 requires fewer elements and wirings than the data path of the arithmetic unit shown in FIG. 6, and is less frequently used and has a smaller number of elements, such as MUL processing and LDST processing. Large circuits are also few units.

  Therefore, it can be said that the configuration adopted in the arithmetic unit 10 can realize an arithmetic unit having performance equivalent to the conventional one and lower power consumption than the conventional one at a lower cost. I can do it.

  The arithmetic unit 10 is somewhat inferior in performance as compared with the configuration shown in FIG. 9, but requires only a register file having a relatively small number of ports. On the other hand, the arithmetic unit shown in FIG. 9 requires a register file having more ports (16 read ports and 8 write ports), so that the area becomes very large.

  Therefore, the configuration employed in the arithmetic unit 10 is also superior in cost performance compared to the configuration of FIG.

  The configuration shown in FIG. 7 is the same as the configuration shown in FIG. 9 in that the function is “scheduler in which the number of instructions that can be issued to the data path at the same time is limited to four (only four pipelines or less It is modified / improved so as to have the same function as the “operation unit having a scheduler that cannot be operated”. In this way, if a 4-input multiplexer is provided between the register file and each pipeline, the number of read ports can be set to the register file 25 in an arithmetic unit having a plurality of pipelines having a single processing function. A register file equal to can be used. However, the number of bits (width) of information in the data path is larger than the number of bits of information in the control path, and the number of required multiplexers is larger in the configuration shown in FIG. In addition, in order to use a register file having exactly the same configuration as the register file 25 in the arithmetic unit having the configuration shown in FIG. 7, it is necessary to provide a multiplexer on the output side of each pipeline.

  Therefore, it can be said that the configuration adopted in the arithmetic unit 10 is superior to the configuration of FIG.

  As described above, the configuration adopted in the arithmetic unit 10 according to the embodiment can realize an arithmetic unit with lower manufacturing cost and lower power consumption than when any other configuration is adopted. . Therefore, if the arithmetic unit of a processor for a supercomputer or a processor for a general electronic device (DSP or the like) is configured as described above, a processor with a lower manufacturing cost and lower power consumption than an existing one can be realized. Become.

<Deformation>
The arithmetic unit 10 described above can be modified in various ways. For example, although the performance is slightly reduced, the arithmetic unit 10 moves the control information from the LDST pipeline to the MUL pipeline, or the control information from the MUL pipeline to the LDST pipeline. Can be transformed into one that can only be moved.

The scheduler 12 can be modified to perform control information transfer and instruction issuance to the processing takeover source pipeline in different cycles. Further, the arithmetic unit 10 is transformed into a unit such as a vector unit or SIMD (Single Instruction Multiple Data) (a unit in which control information may be simultaneously set in a plurality of control information registers 21 _X ). You can also. Further, the arithmetic unit 10 includes a unit having a different number of pipelines as described above, a unit in which each pipeline (execution stage) is a vector unit / SIMD, etc., and a function of each pipeline (processing each pipeline has) The combination of functions) may be modified to a unit different from the above.

In addition, the arithmetic unit 10 controls the scheduler 12 and the three-input multiplexers 24 _{0 to} 24 ₃ so that processing that a certain pipeline has already started (processing that repeats ALU processing) is taken over by another pipeline. However, a circuit having another configuration can also be adopted as the circuit.

DESCRIPTION OF SYMBOLS 10 Arithmetic unit 11 Instruction buffer 12 Scheduler 13 Control path 14 Data path 21 _{0 to} 21 ₃ Control information register 22 _{0 to} 22 ₃ Instruction update circuit 23 ₀ to 23 ₃ Two-input multiplexer 24 _{0 to} 24 ₃ Three-input multiplexer 25 Register file

Claims (5)

One or more first pipelines having an execution function of a first type process and an execution function of a second type process, and one or more having an execution function of a first type process and an execution function of a third type process A plurality of pipelines for multi-cycle operation, including a second pipeline of
A function of taking over the first type loop process completed by executing the first type process a plurality of times, which has already been started by a certain first pipeline, to the second pipeline ready to start a new process. A control circuit having
An arithmetic unit comprising: The control circuit further comprises:
The first pipeline in a state in which a new process can be started has a function of taking over the first type loop process already started by a certain second pipeline. Arithmetic unit. The control circuit includes:
The process to be started in any one of the pipelines is a second type loop process that is completed by executing the second type process a plurality of times, and there is no first pipeline that is ready to start a new process. When there is a second pipeline that is ready to start a new process and a first pipeline that is executing the first type loop process, the second pipe that is ready to start a new process Causing the line to take over the first type loop process being executed by a certain first pipeline, and then causing the first pipeline to start the second type loop process to be executed by any of the pipelines;
The process to be started in any one of the pipelines is a third type loop process that is completed by executing the third type process a plurality of times, and there is no second pipeline in a state where a new process can be started. When there is a first pipeline ready to start a new process and a second pipeline executing a first type loop process, the first pipe ready to start a new process Causing the second pipeline to take over the first type loop processing being executed by a certain second pipeline, and then causing the second pipeline to start the third type loop processing to be executed by any one of the pipelines. The arithmetic unit according to claim 2, wherein: The control circuit comprises:
A plurality of control information registers, each of which is associated with a specific pipeline and in which control information defining the operation content in the next cycle of the corresponding pipeline is set for each cycle;
The function of moving control information in the control information register for any first pipeline to the control information register for any second pipeline, and the control information in the control information register for any second pipeline A control information moving circuit having a function of moving to a control information register for an arbitrary first pipeline;
The arithmetic unit according to claim 2, comprising: The control circuit includes:
The process to be started in any one of the pipelines is a second type loop process that is completed by executing the second type process a plurality of times, and there is no first pipeline that is ready to start a new process. When there is a second pipeline that is ready to start a new process and a first pipeline that is executing the first type loop process, the control information moving circuit is controlled to control the first pipeline. After moving the control information set in the control information register for a certain first pipeline that is executing the seed loop process to the control information register for the second pipeline that is ready to start a new process, A scheduler that sets control information related to the second type loop processing to be started in any pipeline in the control information register for the first pipeline;
The process to be started in any one of the pipelines is a third type loop process that is completed by executing the third type process a plurality of times, and there is no second pipeline in a state where a new process can be started. When there is a first pipeline that is ready to start a new process and a second pipeline that is executing the first type loop process, the control information moving circuit is controlled to control the first pipeline. The control information set in the control information register for a certain second pipeline that is executing the seed process is moved to the control information register for the first pipeline that is ready to start a new process, and then A control information register for the second pipeline includes a scheduler that sets control information related to the third type loop processing to be started in any of the pipelines. The arithmetic unit according to claim 4.

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