JP2004070692A - System for multiprocessing - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a system for multiprocessing which can enhance the capability of processing and reduce a hardware cost. <P>SOLUTION: The system for multiprocessing comprises a control circuit 105, which generates a signal 115 for controlling internal activities and an end-of-computing on the basis of instructions from a first instruction memory 104 and a second instruction memory 112; a first register file 109 for storing a computing result of its own and outputting a first source data; a second register file 113 for storing the result of computing migrated from another processor for execution and outputting a second source data; an input selector 114 for selecting the first source data or the second source data; and an output selector 108 for assigning the outputs from an arithmetic unit 106 and an arithmetic unit 107, which execute the arithmetic in response to an output value from the input selector 114, to the first register file 109 and the second register file 113. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a multiprocessor system that performs parallel processing by a plurality of processors.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a multiprocessor system in which a plurality of processors perform parallel processing is as shown in FIG.
FIG. 2 is a block diagram of a multiprocessor system showing the prior art.
In FIG. 2, reference numeral 202 denotes a first processor, 203 denotes a second processor, and 212 denotes a data address bus connecting the first processor 202 and the second processor 203. Further, as an internal circuit of the second processor 203, 204 is an instruction storage memory, 205 is a control circuit, 206 is a first operator, 207 is a second operator, 208 is an output selector, 209 is a register file, 210 is an output register , 211 are source data.
The inside of the first processor 202 includes the same circuit as the second processor 203, and the first processor 202 and the second processor 203 execute instructions independently. However, the two processors operate as one master and the other as a slave, and the slave's internal area is mapped to the master's address.
[0003]
Next, for example, an operation in a case where the first processor 202 is a master and the second processor 203 is a slave will be described.
The first processor 202 obtains a new operation result by referring to the operation result held in the register file 209 of the second processor 203 and writing data to the register file 209. When the instruction storage memory 204 is a rewritable memory, the first processor 202 also writes instructions to the instruction storage memory 204. In the second processor 203, the instruction output from the instruction storage memory 204 is decoded by the control circuit 205, and the control circuit 205 instructs to output data corresponding to the instruction from the register file 209 as the source data 211. The source data 211 is input to the first arithmetic unit 206 and the second arithmetic unit 207, and the respective arithmetic results are input to the output selector 208. The first arithmetic unit 206 and the second arithmetic unit 207 are circuits that perform different operations, and may be, for example, arithmetic operations, logical operations, multiplications, and table ROMs.
[0004]
Although an example in which there are two arithmetic units is shown here, a larger number of arithmetic units may be included. The output selector 208 receives a command from the control circuit 205 to determine which of the first and second arithmetic units 206 and 207 performs the arithmetic at that time, and outputs a corresponding arithmetic result. The output of the output selector 208 is input to the register file 209 and the output register 210, and receives an instruction from the control circuit 205 according to the instruction at that time, and holds the operation result. The operation result held in the register file 209 is used as source data 211 in a subsequent instruction. The operation result held in the output register 210 becomes an output corresponding to the operation result to the outside of the second processor 203.
[0005]
[Problems to be solved by the invention]
However, in the above-described multiprocessor system, if the instructions executed by the respective processors are biased, the throughput of each processor varies due to the difference in the processing capability, which hinders the improvement of the processing capability of the system. Was.
Further, there is a case where the circuit scale of the arithmetic unit becomes very large as compared with the control circuit or the selector depending on the type of operation. In such a case, since each processor must have an operation unit for performing the operation, there is a problem that operation resources are duplicated and hardware cost is increased.
[0006]
The present invention has been made to solve the above problems, and has as its object to provide a multiprocessor system capable of improving the processing capability of a system and reducing hardware costs.
[0007]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, the present invention provides a multi-processor system in which a plurality of processors perform parallel processing, a first instruction storage memory for storing instructions to be executed by itself, and an instruction whose execution has been shifted from another processor. And a control circuit for controlling internal operations and generating an operation end signal based on instructions from the first and second instruction storage memories, and holding its own operation result And a first register file for outputting the first source data, a second register file for holding an operation result shifted to execution from another processor and outputting the second source data, and a first register file for outputting the first source data. An input selector for selecting the second source data, a plurality of arithmetic units for performing an operation in accordance with an output value from the input selector, and an output from the plurality of arithmetic units. It is obtained by having an output selector for distributing to the first register file and said second register file.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram of a multiprocessor system showing an embodiment of the present invention.
In FIG. 1, reference numeral 102 denotes a first processor, 103 denotes a second processor, and 117 denotes a data address bus connecting the first processor 102 and the second processor 103. Further, as internal circuits of the second processor 103, 104 is an instruction storage memory, 105 is a control circuit, 106 is a computing unit 1, 107 is a computing unit 2, 108 is an output selector, 109 is a register file, 110 is an output register, 111 Is the first source data, 112 is the second instruction storage memory, 113 is the second register file, 114 is the input selector, 115 is the operation end signal, and 116 is the second source data.
[0009]
The present invention differs from the prior art in that a second instruction storage memory 112 for storing an instruction whose execution has been shifted from another processor is provided separately from the first instruction storage memory 104 for storing an instruction to be executed by itself. In addition, separately from the first register file 109 for holding its own calculation result and outputting the first source data, it holds the calculation result whose execution has been shifted from another processor and outputs the second source data. A second register file 113 is provided, and an input selector 114 for selecting the first source data 111 and the second source data 116 is provided.
Note that the inside of the first processor 102 includes the same circuit as the second processor 103, and the first processor 102 and the second processor 103 execute instructions independently. However, the first arithmetic unit 106 or the second arithmetic unit 107 is not necessarily common, and there is an arithmetic unit which only one has. The two processors operate with one as a master and the other as a slave, and the internal area of the slave is mapped to the address of the master.
[0010]
Next, the operation will be described.
When the first processor 102 is the master and the second processor 103 is the slave, the first processor 102 refers to the operation result held in the first register file 109 of the second processor 103, and stores the data in the first register file 109. To obtain a new calculation result. When the first instruction storage memory 104 is a rewritable memory, the first processor 102 also writes instructions to the first instruction storage memory 104. The second instruction storage memory 112 is a rewritable memory. When the number of processes performed by the first processor 102 is larger than the number of processes performed by the second processor 103, some of the instructions are transferred to the second instruction storage memory 112. I do. Also, if there is an instruction that cannot be operated by the operation unit of the first processor 102 and can be operated by the operation unit of the second processor 103, the instruction is also transferred to the second instruction storage memory 112. In the second processor 103, the control circuit 105 decodes the instruction output from the first instruction storage memory 104, and simultaneously monitors the output of the second instruction storage memory 112. If the operation unit used in the instruction output from the first instruction storage memory 104 is different from the operation unit used in the instruction output from the second instruction storage memory 112, the control circuit 105 stores the data corresponding to the instruction in the first instruction storage memory. An instruction is issued from the register file 109 to output the first source data 111. At the same time, it instructs the second register file 113 to output data corresponding to the output instruction of the second instruction storage memory 112 as the second source data 116. The first source data 111 and the second source data 116 are input to the input selector 114. In response to an instruction from the control circuit 105, the input selector 114 determines whether the first source data 111 and the second source data 116 are to be used as inputs to the first arithmetic unit 106 or the second arithmetic unit 107. select. The operation results of the first operation unit 106 and the second operation unit 107 are input to the output selector 108. The first arithmetic unit 106 and the second arithmetic unit 107 are circuits that perform different operations, and may be, for example, arithmetic operations, logical operations, multiplications, table ROMs, and the like.
[0011]
Although an example in which there are two arithmetic units is shown here, a larger number of arithmetic units may be included. The output selector 108 receives an instruction from the control circuit 105 as to whether the operation results of the first and second operation units 106 and 107 are held in the register file 109, the output register 110, or the second register file 113, and responds accordingly. Distribute to output. The register file 109, the output register 110, and the second register file 113 hold the output from the output selector 108 in accordance with a command from the control circuit 105. The operation results held in the register file 109 and the second register file 113 are used as the first source data 111 or the second source data 116 in the subsequent instructions. The operation result held in the output register 110 becomes an output corresponding to the operation result to the outside of the second processor 103. When all the instructions in the second instruction storage memory 112 are completed, the control circuit 105 generates an operation end signal 115 and notifies the first processor 102 of the end of the processing. At this time, the operation end signal 115 may be used as an interrupt signal of the first processor 102 or may be used as a status bit assigned to the address of the first processor 102 for monitoring by polling. If the instruction output from the instruction storage memory 104 and the arithmetic unit used in the instruction output from the second instruction storage memory 112 are the same, the instruction output from the instruction storage memory 104 is preferentially performed. When no instruction is stored in the second instruction storage memory 112, only instructions in the instruction storage memory 104 are processed as in the conventional multiprocessor system.
[0012]
Therefore, the multiprocessor system according to the present embodiment includes a first instruction storage memory 104 for storing instructions to be executed by itself, a second instruction storage memory 112 for storing instructions whose execution has been shifted from another processor, and A control circuit 105 for controlling internal operations and generating an operation end signal 115 based on instructions from the first instruction storage memory 104 and the second instruction storage memory 112, holding its own operation result, and outputting first source data A first register file 109 for holding the operation result shifted from execution by another processor and a second register file 113 for outputting the second source data, and a first register file 109 for storing the first source data and the second source data. An input selector 114 for performing selection, a plurality of operators 106 and 107 for performing an operation in accordance with an output value from the input selector 114, Is provided with an output selector 108 for distributing the outputs from the arithmetic units 106 and 107 to the first register file 109 and the second register file 113, so that the arithmetic unit not used by one processor is used by the other processor. When used in processors, the bias of instructions executed by each processor can be averaged, so that the processing capacity of the system can be improved.
In addition, since duplication of arithmetic units can be reduced between one processor and the other processor, hardware costs can be reduced.
[0013]
【The invention's effect】
As described above, according to the present invention, in a multiprocessor system, a first instruction storage memory for storing an instruction to be executed by itself and a second instruction storage memory for storing an instruction whose execution has been shifted from another processor A control circuit for controlling internal operations and generating an operation end signal based on instructions from the first instruction storage memory and the second instruction storage memory, and holding its own operation result and outputting the first source data A first register file to be executed, a second register file to hold an operation result shifted to execution from another processor and output the second source data, and select the first source data and the second source data. An input selector, a plurality of operation units for performing an operation according to an output value from the input selector, and outputs from the plurality of operation units to the first register file and the second register Since the configuration is provided with an output selector for distributing the data to the files, by using an arithmetic unit that is not used by one processor in the other processor, the bias of instructions executed by each processor can be averaged. Processing capacity can be improved.
In addition, since duplication of arithmetic units can be reduced between one processor and the other processor, hardware costs can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram of a multiprocessor system showing an embodiment of the present invention.
FIG. 2 is a block diagram of a multiprocessor system showing a conventional technique.
[Explanation of symbols]
101 Multiprocessor system of the present invention 102 First processor 103 Second processor 104 First instruction storage memory 105 Control circuit 106 First operator 107 Second operator 108 Output selector 109 First register file 110 Output register 111 First source data 112 second instruction storage memory 113 second register file 114 input selector 115 operation end signal 116 second source data 117 data address bus

Claims (1)

In a multiprocessor system that performs parallel processing by a plurality of processors,
A first instruction storage memory for storing instructions to be executed by itself,
A second instruction storage memory for storing an instruction whose execution has been shifted from another processor;
A control circuit for controlling internal operations and generating an operation end signal based on instructions from the first instruction storage memory and the second instruction storage memory;
A first register file for holding its own operation result and outputting the first source data;
A second register file for holding an operation result whose execution has been shifted from another processor and outputting the second source data;
An input selector for selecting the first source data and the second source data;
A plurality of computing units that perform computations according to output values from the input selector;
A multiprocessor system comprising an output selector for distributing outputs from the plurality of arithmetic units to the first register file and the second register file.

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