JP5598036B2 - Control board, image reading apparatus, image forming apparatus, imaging apparatus, and control method - Google Patents

Description

  The present invention relates to a sensor control board that processes a signal output from a solid-state imaging device or the like, and more specifically, may occur due to an excessive output or an excessive output in the output signal of the solid-state imaging device or the like, or a signal rampage. The present invention relates to a control board, an image reading apparatus, an image forming apparatus, an imaging apparatus, and a control method that can prevent problems.

  In an image reading device such as a scanner, a solid-state imaging device such as a charge coupled device (CCD) reads an image of a document on a contact glass (not shown) and optically separates each color (R, G, B). The image signal is output to. The image signals for each separation color are respectively buffered by an emitter follower circuit and then input to an analog front end (AFE) via AC coupling. The AFE samples the input image signal, converts it into digital image data, and outputs it. The digital image signal thus obtained is transmitted to the subsequent image processing unit via the interface and subjected to various digital processes.

  In such a circuit configuration, an over-signal output, an under-signal output, or a signal ramp of a CCD occurs during a transient operation when power is turned on, turned off, clock-on, or clock-off. The problem that overcurrent is applied has been pointed out. Hereinafter, the problem of the overvoltage and overcurrent applied to the AFE will be described in detail with reference to FIGS.

  FIG. 12 is a diagram showing a schematic configuration of a sensor control board including a conventional CCD. A sensor control board 1000 shown in FIG. 12 includes a timing generator (TG) 1002, a CCD driver (DRV) 1004, a CCD 1006, and an AFE 1008. The timing generator 1002 generates and outputs various clock signals and gate signals. Of the signals generated by the timing generator 1002, the signal (xccd_clk) is input to the CCD 1006 as a CCD clock signal (CCD_CLK) via the CCD driver 1004. An emitter follower (EF) circuit 1010 and a capacitive element (capacitor) are provided between the CCD 1006 and the AFE 1008, and an analog image signal (ccdout) output from the CCD 1006 is buffered by the emitter follower circuit 1010, and AC The data is input to the AFE 1008 by combining.

  The AFE 1008 performs sample and hold, clamp operation, offset correction, signal amplification, and the like, and generates and outputs digital image data from the input analog image signal by A / D (Analogue to digital) conversion. In addition, a signal (xshd) output from the timing generator 1002 is supplied to the AFE 1008 as a sample hold signal (SHD) via the CCD driver 1004, and a master clock signal (MCLK) output from the timing generator 1002 Is supplied directly to the AFE 1008.

  FIG. 13 is a diagram showing a circuit configuration of a sensor control board including a conventional CCD. As an output buffer of the CCD 1006, an emitter follower circuit is generally used. Among the emitter follower circuits, a two-stage circuit configured by sequentially connecting an NPN transistor and a PNP transistor is used to reduce impedance. Preferably used. In this two-stage circuit, in the first-stage emitter follower (hereinafter referred to as the first emitter follower) 1012, the falling slew rate is limited due to the emitter resistance (Re1), and the falling response is Become slow. Similarly, the second stage emitter follower (hereinafter referred to as the second emitter follower) 1014 also has a slow rise response, but when the clamp circuit 1016 in the AFE 1008 operates, the emitter resistance (Re2) and the coupling capacitance This is only about the rising response (up to several ms) determined by the time constant of (Cac). For this reason, the response speed is not a problem during a normal operation in which an image signal within the expected range at the time of design is input.

  However, in the transient driving state of the CCD 1006, such as when the power is turned on, when the power is turned off, when the clock is turned on, when the clock is cut off, or when the drive timing is changed, the CCD 1006 outputs an excessive signal output, an excessive signal output, or a signal rampage. It is known to generate. At this time, the output signal of the CCD 1006 is greatly different from that during normal operation. When attention is paid to the direct current component, a steady level between the power supply voltage (for example, 10 V) and the ground voltage (GND) is output, and the alternating current component is output. When attention is paid, a large-amplitude and high-speed (pixel order) signal change from a power supply voltage (for example, 10 V) to a ground voltage (0 V) which cannot be considered normally can occur.

  The CCD 1006 and the AFE 1008 connected via the emitter follower circuit 1010 generally have different power supply voltages (for example, the power supply voltage of the CCD is 10V, whereas the power supply voltage of the AFE is 3.3V). Therefore, an output signal from the CCD 1006 is input to the AFE 1008 regardless of the AFE 1008.

  That is, an overvoltage (“A”, “B”) is applied to the AFE 1008 or an overcurrent (“C”, “D”) flows due to a transient output signal from the CCD 1006, and further the emitter follower 1012. , 1014 itself is subject to an overvoltage (base-emitter reverse bias ("ho", "he")).

  This overvoltage or overcurrent to the AFE 1008 is considered to occur due to the signal change being transmitted to the AFE 1008 side by inputting the CCD output signal by AC coupling. The overvoltage (reverse bias) generated in the emitter follower circuit 1010 changes the emitter voltage (Ve1 or Ve2) to the base voltage (Vb1) when there is a change exceeding the responsiveness of the first emitter follower 1012 or the second emitter follower 1014. Or, it is considered to be caused by being unable to follow Vb2).

  In the circuit configuration shown in FIG. 13, the responsiveness of the first emitter follower 1012 is generally sufficiently fast for both rising and falling, so overvoltage (reverse bias) is not a problem for the first emitter follower 1012. However, for the second emitter follower 1014, when the clamp circuit 1016 is always ON, such as when the power is turned on (generally, the constant ON is released by the initial setting), the capacity of AC coupling (up to several μF). ) Is charged, the rise response becomes slow (for example, about several ms). That is, for the second emitter follower 1014, the responsiveness of the fall is discharge through the transistor, and thus is sufficiently fast. Therefore, the reverse bias is not a problem. On the other hand, the reverse bias can be a problem at the rise.

  Hereinafter, the overvoltage applied to the AFE and the emitter follower due to the fluctuation of the CCD output signal will be described with reference to FIG. FIG. 14 shows an operation sequence of the sensor control board in the conventional image reading apparatus. In the operation sequence in the sensor control, power is first supplied to the CCD 1006, the CCD driver 1004, and the timing generator 1002, and this is detected (here, a power supply voltage of 10V is detected), and after tPOR (Power on Reset). The reset signal (XRESET) is released. Here, the reset signal (XRESET) is a signal indicating a reset state (Low) or a reset release state (High), and is input to the timing generator 1002 and the AFE 1008 (not shown).

  When the reset signal (XRESET) is released, the timing generator 1002 and the AFE 1008 start operating, and then a soft reset is performed by communication from the CPU. When the soft reset is released, the registers are initialized to shift the timing generator 1002 and the AFE 1008 to normal operation. Thereafter, automatic adjustment such as gain adjustment of the AFE 1008 is performed, and the system shifts to a reading standby state. When the power is turned off, there is basically no control. When the power is turned off (here, the power supply voltage of 10V is detected), the reset signal (XRESET) goes to the reset state (Low) and the power is turned off. Is done.

  On the other hand, the timing generator 1002 does not output the CCD drive clock signal during the reset period, but outputs the CCD drive clock signal according to the hardware default value of the register after the reset is released. The timing generator 1002 does not output the CCD drive clock signal even during the soft reset period, but when the phase and width of the predetermined drive clock are set by the initial setting thereafter, the CCD drive clock signal (xccd_clk) in the normal operation is output. And the system shifts to a reading standby state. When the power is turned off, the timing generator 1002 keeps outputting the CCD drive clock signal until the reset signal (XRESET) becomes the reset state (Low). When the reset signal (Low) is reached, the clock signal is stopped and the power is turned off. Is done.

  Looking at the CCD output signal (ccdout), the clock signal (CCD_CLK) is not input to the CCD 1006 during the period after the power is turned on (the period indicated by “Power ON” in FIG. 14). There is a possibility that the CCD output signal (ccdout) becomes an excessive signal output that rises to near the power supply voltage (for example, 10 V) due to leakage of the charge detection capacitor to the power supply side through the reset / clamp transistor. Depending on the characteristics of the CCD 1006, the CCD output signal (ccdout) may become an under-signal output near the ground voltage (GND: 0V) due to leakage to the ground side.

  The excessive signal output shown in FIG. 14 rises in response to the rise of the power supply voltage (up to several ms). However, since the rise response of the second emitter follower 1014 is slower than that, the emitter voltage Ve2 of the second emitter follower 1014 is increased. Cannot follow, and a reverse bias is generated between the base and emitter of the second emitter follower 1014 ("f" in FIG. 13).

  On the other hand, after the reset signal (XRESET) is released (period indicated by “POR” in FIG. 14), as shown in FIG. 14, the CCD output signal (ccdout) may be violated. This is because the CCD output signal (ccdout) becomes a normal offset level (here, about 5 V because the power supply voltage is 10 V), and the charge accumulated during the reset is discharged as a signal. Although this change is a large-amplitude and high-speed falling change, the response of the first emitter follower 1012 is fast, so the emitter voltage (Ve1) follows the base voltage (Vb1) well, and the first emitter follower 1012 No reverse bias is applied between the base and the emitter. On the other hand, as shown in FIG. 13, the second emitter follower 1014 has a fast falling response and thus does not generate a reverse bias due to this signal violence. However, the reverse bias does not occur in the subsequent rising change to the normal offset level. ("F" in FIG. 13).

  The signal fluctuation generated in the CCD output signal (ccdout) is also transmitted to the AFE 1008, and an overvoltage exceeding the power supply voltage (for example, 3.3V) or the ground voltage at the input of the AFE 1008 ("a" and "b" in FIG. 13). If an internal protection diode is turned on, an overcurrent ("C" and "D" in FIG. 13) is generated.

  Similarly, during the soft reset period (the period indicated by “soft reset” in FIG. 14), the output of the clock signal is temporarily stopped and then restarted, so that a transient operation occurs. During the initial setting period (period indicated by “initial setting” in FIG. 14), a transient operation occurs in which the setting of the CCD drive clock signal changes from the initial value to the normal setting value. For this reason, the CCD output signal (ccdout) may be disturbed in both the soft reset period and the initial setting period. Also in this case, an overvoltage is generated in the second emitter follower 1014 and the AFE 1008.

  On the other hand, during the reading standby state (period indicated by “normal state (reading standby)” in FIG. 14), a normal overvoltage does not occur. However, for example, when light is unexpectedly incident from the outside, it is larger than expected. Since an output signal with an amplitude and high-speed falling change can be output, an overvoltage to the AFE 1008 may occur.

  When the power is turned off (period indicated by “power OFF” in FIG. 14), if the power supply voltage of the CCD 1006 decreases before the reset signal (XRESET) shifts to the reset state (low), a signal fluctuation occurs. there's a possibility that. This is because charge injection from the power source side of the CCD 1006 to the charge detection unit occurs, and this signal change is also a large-amplitude and high-speed falling change, which can be an overvoltage to the AFE 1008. Since this phenomenon appears in the output only when a clock signal is input to the CCD 1006, it does not occur in a reset state in which the CCD drive clock signal is stopped. However, even in the reset state, an overvoltage to the AFE 1008 may occur in the same manner because an output signal may be disturbed when switching to stop the clock output or when the power is turned off.

  As described above, the overvoltage and overcurrent generated in the AFE and the emitter follower due to the CCD output signal occur in a series of transient states where the CCD is not in a normal state, such as when the power is turned on or when the power is turned off. Even if the CCD is in a normal state, it is generated by abnormal light.

  In order to cope with the above-described problems due to overvoltage, there has been conventionally known a technique for preventing overvoltage and overcurrent to the AFE by blocking the signal or limiting the amplitude of the signal in the emitter follower upstream of the AFE. For example, Japanese Patent Laid-Open No. 2007-214688 (Patent Document 1) delays the power of the emitter follower to suppress the overvoltage to the AFE, thereby turning off the transistor and not transmitting the CCD output signal to the AFE. Thus, a technique for preventing the AFE from being overvoltaged is disclosed.

  FIG. 15 is a diagram for explaining a conventional technique aimed at preventing an overvoltage applied to the AFE. In the circuit configuration shown in FIG. 15, the emitter follower circuit 1110 is provided with a delay circuit 1116 for overvoltage protection in addition to the first emitter follower 1112 and the second emitter follower 1114. In the circuit configuration shown in FIG. 15, the power supply voltage (Vcc_ef) of the second emitter follower 1114 rises gently by the delay circuit 1116 when the power is turned on. At this time, since the start of rising of the power supply voltage (Vcc_ef) of the second emitter follower 1114 is lower than the CCD output signal (ccdout), when the base voltage is higher than the emitter voltage in the second emitter follower 1114 (Vb2> Ve2), The NPN transistor of the second emitter follower 1114 is cut off, and the ramping of the CCD output signal (ccdout) can be cut off.

  Even when the base voltage is smaller than the emitter voltage (Vb2 <Ve2), only the signal change corresponding to the difference passes through the second emitter follower 1114, so that the signal change transmitted to the AFE 1108 can be reduced. In this way, overvoltage to the AFE 1108 can be prevented. However, the prior art disclosed in FIG. 15 was not sufficient from the viewpoint described below.

  Hereinafter, the problems in the prior art shown in FIG. 15 will be described with reference to FIG. FIG. 16 shows an operation sequence of the sensor control board in the prior art shown in FIG. In the operation sequence shown in FIG. 16, the power supply voltage (Vcc_ef) of the second emitter follower 1114 is changed from the period indicated by “Power ON” to the period indicated by “POR” in FIG. It can be said that overvoltage can be reduced. However, in this conventional technique, in order to put the second emitter follower 1114 in the cut-off state, a reverse bias is intentionally applied between the base and the emitter of the second emitter follower 1114. There is a problem that occurs.

  Further, in the conventional technology to be described, the signal to the AFE 1108 is blocked by setting the second emitter follower 1114 to the blocking state (Vb2> Ve2), but in the non-blocking state (Vb2 <Ve2), the difference signal Changes can be communicated. In order to completely cut off the signal, it is necessary to sufficiently increase the delay time applied to the power supply voltage (Vcc_ef) of the second emitter follower 1114. However, in this case, variation in delay time also increases, and although it is necessary for Vcc_ef to rise to a normal voltage at the time of automatic adjustment, there is a case where the individual does not rise, and the worst case occurs. In a case, the system will go down.

  Therefore, in the above prior art, it is generally difficult to sufficiently lengthen the delay time, and as a result, it is possible to suppress the overvoltage generated in the control performed in the second half after power-on such as the soft reset period and the initial setting period. However, the effect of preventing AFE overvoltage was limited and could not be said to be sufficient. Further, after the power supply voltage Vcc_ef of the second emitter follower 1114 rises, there is no effect of overvoltage protection. Therefore, the overvoltage at the normal state or when the power is turned off cannot be prevented at all and cannot be said to be sufficient. It was.

  In short, the conventional technique of blocking or limiting the signal by the emitter follower can partially avoid the overvoltage and overcurrent applied to the AFE, but the effect is limited, and the emitter follower itself is overvoltaged. There was a problem that was not enough.

  The present invention has been made in view of the above prior art, and the present invention relates to an AFE and an emitter caused by an abnormal output such as an excessive output or an excessive output in a signal output means of a signal output means such as a solid-state imaging device or a signal fluctuation. An object of the present invention is to provide a control board, an image reading apparatus, an image forming apparatus, an imaging apparatus, and a control method capable of suitably preventing an overvoltage and an overcurrent that can occur in both follower circuits.

  In order to solve the above-described problems, the present invention includes signal output means for outputting a sensor response such as a solid-state imaging device, and signal processing means for processing an input signal such as an analog front end, and further includes the following features: A control board is provided. The control board according to the present invention includes an overvoltage protection unit including a switch unit that interrupts transmission of the output signal to a subsequent stage during a setting period in which the output signal is input and the signal output unit may generate an abnormal output. Buffer means for buffering an output signal transmitted from the output means through the switch means and outputting it to the signal processing means.

  Further, according to the present invention, the switching and switching of the output signal can be controlled by switching the control signal of the switch means at a change speed equal to or lower than the response speed of the buffer means. Furthermore, in the present invention, the set period during which the signal output means can generate an abnormal output can include a period from when the power to the control board is turned on until the signal output means shifts to normal operation.

  In addition, according to the present invention, it is possible to provide an image reading apparatus including the control board having the above characteristics, an image forming apparatus including the image reading apparatus or the control board. Furthermore, according to the present invention, it is possible to provide an imaging device that operates as a signal output unit in the control board and generates an analog image signal as an output signal by photoelectric conversion.

  Furthermore, according to this invention, the control method which the said control board performs is provided. In the control method of the present invention, the switch means shuts off the output signal in response to the start of a set period during which the signal output means can generate an abnormal output, and the switch means at the end of the set period. Responsively conducting the output signal.

  According to the above configuration, since the output of the output signal to the subsequent buffer means and the signal processing means is interrupted by the switch means during the setting period in which the signal output means can generate an abnormal output, the abnormal output Therefore, it is possible to suitably prevent an overvoltage or an overcurrent that can occur in both the signal processing means and the buffer means.

The figure which shows the circuit structure of the image sensor control board by 1st Embodiment. The figure which shows the operation | movement sequence of the image sensor control board by 1st Embodiment. The figure which shows the circuit structure of the image sensor control board by 2nd Embodiment. The figure which shows the operation | movement sequence of the image sensor control board of 2nd Embodiment. The figure which shows the circuit structure of the image sensor control board by 3rd Embodiment. The figure which shows the operation | movement sequence of the image sensor control board of 3rd Embodiment. The figure which shows the circuit structure of the image sensor control board by 4th Embodiment. The figure which shows the operation | movement sequence of the image sensor control board of 4th Embodiment. The figure which shows the circuit structure of the part relevant to CCD and the overvoltage protection of the image sensor control board by 5th Embodiment. 1 is a diagram illustrating a hardware configuration of a copying machine. FIG. 3 is a diagram illustrating a mechanism configuration of a scanner unit of a copying machine. The figure which shows schematic structure of a sensor control board provided with CCD of a prior art. The figure which shows the circuit structure of a sensor control board provided with CCD of a prior art. The figure which shows the operation | movement sequence of the sensor control board in the image reading apparatus of a prior art. The figure explaining the prior art for the purpose of preventing the overvoltage concerning AFE. The figure which shows the operation | movement sequence of the sensor control board in a prior art.

  Hereinafter, although embodiment of this invention is described, embodiment of this invention is not limited to embodiment described below. FIG. 1 is a diagram illustrating a circuit configuration of an image sensor control board according to the first embodiment. The image sensor control board 100 shown in FIG. 1 includes a CCD 110 and an AFE 120. Further, an emitter follower circuit 130, an overvoltage protection circuit 140, and a capacitor element 128 are provided between the CCD 110 and the AFE 120. It has been.

  The CCD 110 is a photoelectric conversion sensor, for example, reads a document image on a contact glass (not shown), and outputs an analog image signal (ccdout) generated by photoelectric conversion. The CCD 110 constitutes the signal output means and the imaging device of this embodiment. The analog image signal (ccdout) output from the CCD 110 passes through the overvoltage protection circuit 140, is buffered by the emitter follower circuit 130, and is input to the AFE 120 by AC coupling. The AFE 120 performs sample and hold, clamp operation, offset correction, signal amplification, and the like, and the analog image signal input to the AFE 120 is A / D converted into digital image data and output. The AFE 120 constitutes the signal processing means and analog processing circuit of this embodiment.

  The emitter follower circuit 130 of this embodiment includes a first-stage emitter follower (hereinafter referred to as a first emitter follower) 132 and a second-stage emitter follower (hereinafter referred to as a second emitter follower) 134. A two-stage configuration in which an NPN transistor and a PNP transistor are connected in order. This two-stage emitter follower circuit 130 can be suitably used from the viewpoint of sufficiently reducing the impedance. The emitter follower circuit 130 constitutes the buffer means of this embodiment.

  The overvoltage protection circuit 140 of the present embodiment is configured to include a switch 142, and the switch 142 blocks the signal so that the abnormal output of the CCD output signal (ccdout) is not transmitted to the subsequent AFE 120. The switch 142 of the overvoltage protection circuit 140 can be realized by a semiconductor element that performs a switch operation such as a bipolar transistor or a MOS (Metal Oxide Semiconductor) transistor. In the present embodiment, a problem caused by a reverse bias applied to the switch 142 itself. From the viewpoint of avoiding the problem, a MOS transistor (more specifically, an NMOS transistor) can be preferably used.

  This MOS transistor has a built-in parasitic diode (body diode) 142a between its drain and source. Therefore, when the CCD output signal (ccdout) is output, the switch 142 is cut off by the control signal (output_on) unless the base voltage (Vb1) of the input of the first emitter follower 132 is lower than the output signal (ccdout). However, there is a concern that the output signal (ccdout) may be transmitted to the base (Vb1) of the first emitter follower 132 via the parasitic diode 142a. Therefore, in the overvoltage protection circuit 140 of the present embodiment, a pull-down is configured after the switch 142, and the ground voltage (GND) is regulated so that the voltage when the switch is cut off is always equal to or lower than the output signal (ccdout).

  When the switch 142 is switched from the cutoff state (OFF) to the energized state (ON) or from the energized state (ON) to the cutoff state (OFF), the base voltage (Vb1) of the first emitter follower 132 is changed to the ground voltage ( There is a concern that the voltage may suddenly change from 0V) to the CCD output signal level (about 5V for a 10V power supply voltage) or vice versa.

  Therefore, in this embodiment, the control signal (output_on) of the switch 142 is gently changed, and the signal change at the time of the change is performed by gradually switching between the cut-off state (OFF) and the energized state (ON). Reduce. The change speed (time constant) of the control signal (output_on) at this time is the response speed of the first emitter follower 132 or the second emitter follower 134 so that the first emitter follower 132 and the second emitter follower 134 can sufficiently respond. It is preferable to set it to a value less than or less.

  Hereinafter, a mechanism for preventing an overvoltage that may be generated in the AFE and the emitter follower due to the fluctuation of the CCD output signal in the image sensor control board shown in FIG. 1 will be described with reference to FIG. FIG. 2 is a diagram illustrating an operation sequence of the image sensor control board 100 according to the first embodiment. In the operation sequence in this embodiment, first, the power supply voltage is input to the CCD 110, the CCD driver (DRV: not shown), and the timing generator (TG: not shown), and in response thereto, the reset signal (XRESET) after tPOR. ) Is canceled. The reset signal (XRESET) is a signal indicating a reset state (Low) or a reset release state (High), and is input to a timing generator (not shown) and the AFE 120.

  When the reset signal (XRESET) is released, the timing generator and the AFE 120 start to operate, and then reset again by communication from the CPU. This reset is a software-controlled reset (hereinafter referred to as a soft reset) performed in order to avoid a situation in which the reset is not applied when the power supply is momentarily interrupted. When the soft reset is cancelled, the registers are initialized to shift the timing generator and the AFE 120 to the normal operation. Thereafter, automatic adjustment such as gain adjustment of the AFE 120 is performed, and the system shifts to a reading standby state. When the power is turned off, there is basically no control. When the power is turned off, the reset signal (XRESET) goes to the reset state (Low) and the power is turned off.

  Further, in the present embodiment, the control signal (output_on) of the switch 142 is in the cut-off state (Low) until the initial setting is completed, and after the initial setting is completed, the switch switching period according to the change speed (time constant) of the control signal. It is set to be in a conductive state (High) after passing through. The completion of the initial setting corresponds to the timing when the CCD 110 shifts to the normal operation although the automatic adjustment of the AFE 120 has not yet been performed. As described above, in this embodiment, the control signal (output_on) is delayed and gradually changes from the cutoff state (Low) to the conduction state (High), so that the signal change in the base voltage (Vb1) of the first emitter follower 132 also occurs. Be gentle.

  Further, since the output voltage level changes from the ground voltage (0 V), there is a concern about the reverse bias in the second emitter follower 134. However, as shown in the column of Vb2 / Ve2 in FIG. Since the control signal (output_on) is changed with a time constant that can respond to the second emitter follower 134, no reverse bias is applied.

  On the other hand, since the input voltage (afein) of the AFE 120 also changes gradually, the clamp circuit 122 of the AFE 120 gradually charges and discharges the AC coupling capacitance (Cac) of the capacitor 128. Accordingly, in the present embodiment, a sufficient waiting time (wait: tw) is provided until the automatic adjustment is started, and it is ensured that the input voltage to the AFE 120 is sufficiently stabilized before the automatic adjustment is started.

  As described above, according to the image sensor control board 100 of the first embodiment, it is possible to suitably block the signal fluctuation from the CCD 110 input to the AFE 120 and the emitter follower circuit 130. Therefore, not only the overvoltage and overcurrent that can be generated in the AFE 120 but also the occurrence of reverse bias between the base and the emitter that can be generated in the emitter follower circuit 130 can be suitably prevented.

  In particular, in the first embodiment, the control signal (output_on) of the switch 142 is in the cut-off state (Low) during the period from when the power is turned on until the CCD 110 shifts to the normal operation. The signal (ccdout) can be cut off before the emitter follower circuit 130 is input, and a problem of overvoltage due to a series of signal fluctuations can be preferably avoided. Similarly, when the power is turned off, the control signal (output_on) of the switch 142 is gradually changed to the cut-off state (Low) to cut off the transmission of the CCD output signal (ccdout) in the transient state. The problem of overvoltage due to signal fluctuation at the time of disconnection can also be suitably avoided.

  However, in this case, it is necessary to detect power-off with high accuracy, which may lead to an increase in cost. Further, when the control signal (output_on) is delayed, it takes time until the power is turned off and the switch 142 is turned off. Depending on the delay time, the CCD output signal (ccdout) may be ramped. There is a possibility that the switch 142 cannot be shut off and an overvoltage is generated as shown in FIG.

  Further, the input voltage (Vb1) of the emitter follower circuit 130 during the period in which the switch 142 is in the cutoff state (OFF) is 0 V, and there is a large difference from the original output signal level. For this reason, after the switch 142 is turned on and the CCD output signal (ccdout) is input to reach the original signal level, the charging time of the AC coupling capacitor (Cac) is further secured, and the clamp potential at the input of the AFE 120 is obtained. We need to wait for it to stabilize. Therefore, a sufficient waiting time (tw) must be provided before the start of automatic adjustment, which may lead to a long system startup. Hereinafter, a second embodiment will be described in which overvoltage is prevented while alleviating the lengthening of the startup.

  FIG. 3 is a diagram showing a circuit configuration of the image sensor control board according to the second embodiment. The image sensor control board 200 shown in FIG. 3 has the same configuration as that of the image sensor control board 100 according to the first embodiment, except that an overvoltage protection circuit 240 having a slightly different configuration from that of the first embodiment is provided. In the overvoltage protection circuit 240 of the second embodiment, the output signal level when the switch 242 is in the cut-off state is not the ground level (0 V) but the voltage dividing ratio of the resistance elements 244a and 244b is controlled. The bias voltage (Vbias) which is about the offset level (Vofs) of the CCD output signal is set, while the weight provided in the first embodiment is omitted or shortened. The resistance element 244 constitutes a bias voltage setting unit of the present embodiment.

  On the other hand, when the bias voltage (Vbias) is set high, even if the switch 242 is controlled to be in the cut-off state, the signal violence occurs through the parasitic diode 242a for a signal less than the base voltage (Vb1) of the first emitter follower 232 There is a concern of being transmitted to the emitter follower circuit 230 side and generating an overvoltage in the AFE 220 and the emitter follower circuit 230. Therefore, in the second embodiment, the bias voltage (Vbias) in the overvoltage protection circuit 240 is set to satisfy the following conditional expressions (1) to (4). Thereby, even when the bias voltage (Vbias) is set to about the offset voltage (Vofs), it is possible to prevent the occurrence of overvoltage in the AFE 220 and the emitter follower circuit 230.

  In the conditional expressions (1) to (4), Vo_min indicates the minimum signal level of the CCD output signal (ccdout), and Vo_max indicates the maximum signal level of the CCD output signal (ccdout). Vebo1 and Vebo2 indicate the reverse breakdown voltage between the base and emitter of the first emitter follower 232 and the second emitter follower 234, respectively. ΔVe1 represents a negative level at which the first emitter follower 232 can follow the base voltage, and ΔVe2 represents a positive level at which the second emitter follower 234 can follow the base voltage. ΔVafe (+) and ΔVafe (−) indicate a positive side level and a negative side level at which the AFE 220 can change without generating an overvoltage or overcurrent, respectively.

  Conditional expression (1) indicates that the reverse bias of the base-emitter voltage of the first emitter follower 232 generated by a signal change when the power is cut off when the switch is shut off does not exceed the reverse withstand voltage value. The voltage (Vbias) should be set, and the conditional expression (2) indicates that the voltage between the base and the emitter of the second emitter follower 234 generated by the signal change when the power is turned on when the switch is shut off. This indicates that the bias voltage (Vbias) should be set in a range where the reverse bias does not exceed the reverse withstand voltage value.

  Conditional expression (3) indicates that the reverse bias between the base and emitter of the first and second emitter followers 232 and 234 generated by a signal change at the time of switch switching (conduction / cutoff) does not exceed the reverse withstand voltage value. This indicates that the voltage (Vbias) should be set, and the above conditional expression (4) indicates that the change in the AFE input voltage due to the signal change at the time of switching the switch state (conduction / cutoff) does not exceed the level at which the overvoltage and overcurrent are exceeded. Represents that the bias voltage (Vbias) should be set.

  Hereinafter, a mechanism for preventing an overvoltage that may occur in the AFE and the emitter follower due to the abnormal output of the CCD output signal in the image sensor control board 200 shown in FIG. 3 will be described with reference to FIG. FIG. 4 shows an operation sequence of the image sensor control board 200 of the second embodiment. In the sequence shown in FIG. 4, the bias voltage (Vbias) is set so as to satisfy the above equations (1) to (4) and coincide with the offset level.

  In the second embodiment, as shown in FIG. 4, the signal offset level at the input of the emitter follower circuit 230 is changed before and after the control signal (output_on) is switched from the cutoff state (Low) to the conduction state (High). Almost does not occur. For this reason, even when the switch 242 is turned on, the time for waiting for the input voltage (afein) to the AFE 220 to stabilize can be minimized.

  In addition, when the power is turned on, the reverse bias in the second emitter follower 234 is concerned by changing from the ground voltage (0 V) to the bias voltage (Vbias). As described above, the bias voltage (Vbias) is Since it is set at a level that does not exceed the reverse withstand voltage value (Vebo2) between the base and emitter of the emitter follower 234, even if the emitter voltage (Ve2) cannot follow the base voltage (Vb2), no overvoltage is generated. .

  Even when the bias voltage (Vbias) does not completely match the offset level, the difference in signal offset level at the input of the emitter follower circuit 230 before and after switching from the cutoff state (Low) to the conduction state (High) is sufficiently small. The time for waiting for stabilization of the AFE input signal (afein) can be significantly reduced as compared with the first embodiment. For this reason, the waiting time (tw) can be made much shorter than in the case of the first embodiment.

  According to the second embodiment described above, the relations of the conditional expressions (1) to (4) are satisfied, and the bias voltage (Vbias) of about the CCD offset level (Vofs) is set, thereby AC coupling. It is possible to shorten or eliminate the stabilization waiting time of the clamp potential caused by the charge / discharge of the capacitor (Cac). For this reason, overvoltage that may occur in the AFE 220 and the emitter follower can be avoided while minimizing the lengthening of the system startup time.

  In the above description, a case where a general-purpose MOSFET (MOS field effect transistor) is used has been exemplified, and thus a parasitic diode is mentioned. However, depending on the device configuration, there is a device in which a diode having a direction opposite to that of a parasitic diode is inserted and blocked, and a device in which a semiconductor substrate and a source are not connected to each other as an independent terminal. In these device configurations, since the abnormal output of the CCD output signal is not transmitted to the emitter follower circuit side via the parasitic diode, the possibility of occurrence of overvoltage can be further reduced, but the bias voltage (Vbias) is expressed by the above equation. The point which must satisfy (1)-(4) is the same.

  According to the second embodiment described above, a series of overvoltages that can occur from when the power is turned on to when the CCD shifts to the normal operation can be suitably avoided while minimizing the delay of the system startup time. . However, when the power supply voltage changes rapidly, such as when switching power on and power off with a switch element in power saving control, etc., the signal change increases accordingly, and the AFE overvoltage and overcurrent at power on and power off are reduced. There is a possibility of generating. Hereinafter, a third embodiment for preventing AFE overvoltage in response to a case where the power supply voltage changes rapidly will be described.

  FIG. 5 is a diagram showing a circuit configuration of the image sensor control board according to the third embodiment. The image sensor control board 300 shown in FIG. 5 has the same configuration as the image sensor control board 200 of the second embodiment, except that the overvoltage protection circuit 340 is slightly different from that of the second embodiment. Prepare.

  In the overvoltage protection circuit 340 of the third embodiment, the bias voltage (Vbias) is set to about the offset level (Vofs) by the voltage dividing circuit including the capacitive element 346 and the resistive elements 344a, 344b, and 344c. A voltage dividing circuit including the capacitive element 346 and the resistive elements 344a, 344b, and 344c constitutes a bias voltage setting unit of the present embodiment.

  In the third embodiment, the bias voltage (Vbias) of the overvoltage protection circuit 340 changes slowly because the capacitance element 346 is added, and the generated bias voltage (Vbias) is changed via the resistance element 344c. Applied. In the overvoltage protection circuit 340 of the third embodiment, the reverse bias of the first emitter follower 332 and the second emitter follower 334 is a level at which the bias voltage (Vbias) does not become an overvoltage, as in the second embodiment. This is not a problem here.

  Hereinafter, a mechanism for preventing an overvoltage that may occur in the AFE and the emitter follower in the image sensor control board 300 shown in FIG. 5 will be described with reference to FIG. FIG. 6 shows an operation sequence of the image sensor control board 300 according to the third embodiment.

  As shown in FIG. 6, even when the power supply voltage changes rapidly when the power is turned on, in the third embodiment, the bias voltage (Vbias) changes slowly regardless of the change speed. Therefore, an overvoltage to the AFE 320 does not occur. In this manner, by using the capacitor element and gradually changing the bias voltage (Vbias) of the overvoltage protection circuit 340, even when the change in the power supply voltage at the time of turning on the power is high, the AFE is performed. It is possible to suitably prevent the overvoltage.

  According to the embodiments described above, it is possible to suitably prevent a series of overvoltages that may occur during the period from when the power is turned on to when the CCD shifts to the normal operation in the image sensor control board. On the other hand, in the embodiments described above, there is a possibility that an overvoltage is generated when abnormal light is incident in the normal state (reading standby state) or when the power is turned off. In the third embodiment, the occurrence of overvoltage due to the change rate of the power supply voltage when the power is turned off is not a problem, but there is still a possibility that an overvoltage is generated due to charge injection into the charge detection unit of the CCD 310. .

  The reason why this overvoltage occurs is that it cannot be controlled or controlled in the normal state or when the power is turned off, and it is necessary to detect the disconnection with high accuracy when the power is turned off. It becomes difficult to suppress. Therefore, in the fourth embodiment described below, the approach is not to shut off the abnormal output for the overvoltage at the time of power-off, but to prevent the emitter from generating an overvoltage and an overcurrent even if the abnormal output is input. Configure a follower circuit. A fourth embodiment for preventing overvoltage that may occur in the AFE and the emitter follower circuit, including generation of overvoltage due to charge injection into the charge detection unit of the CCD, will be described below.

  FIG. 7 is a diagram showing a circuit configuration of the image sensor control board according to the fourth embodiment. An image sensor control board 400 shown in FIG. 7 has the same configuration as that of the image sensor control board 300 of the third embodiment, except that the emitter follower circuit 430 is slightly different from that of the third embodiment. Yes. As shown in FIG. 7, in the emitter follower circuit 430 of this embodiment, a resistance element 434a having a resistance value Rc2 is added to the collector of the PNP transistor of the second emitter follower 434. In the fourth embodiment, with such a configuration, the input / output current from the AFE 420 is limited, the voltage is limited, and the occurrence of overvoltage and overcurrent is suppressed.

  FIG. 8 shows an operation sequence of the image sensor control board 400 according to the fourth embodiment. As shown in FIG. 8, the CCD output signal (ccdout), the base voltage (Vb1) of the first emitter follower 432, and the emitter voltage Ve1 have been described so far even if abnormal light is incident in the normal state (reading standby state). It is the same. However, in the AFE 420, when an excessive output whose signal greatly changes to the negative side is input, the protection diode of the AFE 420 in FIG. 8 is turned on, and an overcurrent flows from the AFE 420 to the second emitter follower 434. At this time, in this embodiment, most of the current from the AFE 420 flows to the resistance element 434a that functions as a current limiting resistor, and the PNP transistor of the second emitter follower 434 is gradually saturated.

  When the PNP transistor of the second emitter follower 434 is completely saturated, no further current flows through the collector of the transistor, and flows through the emitter resistance element (Re1) of the first emitter follower 432 through the base. The value of the emitter resistance element (Re1) is provided to define the idle current of the NPN transistor of the first emitter follower 432, and is generally about 1 kΩ. Therefore, the current bypassed to the base side of the second emitter follower 434 flows only about several mA at most, and as a result, the current from the AFE 420 is limited. Therefore, since the input voltage of the AFE 420 is also limited, overvoltage / overcurrent that can occur in the AFE 420 can be suitably suppressed.

  The current limitation by the resistance element 434a is effective for the negative side overvoltage and overcurrent of the AFE 420. On the other hand, since the overcurrent on the positive side of the AFE 420 is also limited by the emitter resistance element (Re2 to 1 kΩ) of the second emitter follower 434, the overcurrent on the positive side of the AFE420 does not cause a problem in configuration. Note that the resistance element 434a constitutes a current limiting unit of the present embodiment.

  According to the fourth embodiment, in addition to the overvoltage and overcurrent that can occur from power-on to the normal operation transition of the CCD, the overvoltage and overcurrent that can be generated in the incident of abnormal light or power off in the normal state are suitable. Can be prevented.

  In the above embodiment, the CCD and the overvoltage protection circuit are configured as separate circuits, but in other embodiments, the configuration is not limited to this. Hereinafter, a fifth embodiment will be described in which at least a part of the overvoltage protection circuit is integrated in the CCD to realize overvoltage prevention in a space-saving manner.

  FIG. 9 is a diagram showing a circuit configuration of a part related to CCD and overvoltage protection of the image sensor control board according to the fifth embodiment. The image sensor control board 500 shown in FIG. 9 has the same configuration as the image sensor control board 400 according to the fourth embodiment except that at least a part of the overvoltage protection circuit 540 is integrated in the CCD 510. Prepare.

  In the image sensor control board 500 of the fifth embodiment, a part of the overvoltage protection circuit 540 is integrated in the CCD 510, and a switch 542 is built in a stage preceding the CCD signal output (ccdout). Since the CCD 510 is generally manufactured by an NMOS (Negative channel MOS) process, if the switch 542 is constituted by an NMOS transistor, the design change of the CCD can be minimized. That is, according to the fifth embodiment, the development cost can be reduced, and the above-described overvoltage protection circuit can be mounted in a small space and at a low cost.

  Hereinafter, an image reading apparatus on which the image sensor control board according to the above-described embodiments is mounted will be described by taking a copying machine as an example. FIG. 10 is a diagram illustrating a hardware configuration of the copying machine 600. A copying machine 600 shown in FIG. 10 includes a scanner unit 610 and a main unit 630. The scanner unit 610 includes a timing generator (TG) 612, a CCD driver (DRV) 614, a CCD 616, and an AFE 622.

  The timing generator 612 outputs various clock signals and gate signals. Of the signals output from the timing generator 612, the signal (xccd_clk) is input to the CCD 616 via the CCD driver 614 as a CCD clock signal (CCD_CLK).

  Between the CCD 616 and the AFE 622, the above-described overvoltage protection circuit (OVP) 618, an emitter follower circuit (EF) 620, and a capacitor element (not shown) are provided, and an output signal (ccdout) output from the CCD 616 is overvoltage protection. After the circuit 618 is switch-controlled, it is buffered by the emitter follower circuit 620 and input to the AFE 622 by AC coupling. A signal (xshd) output from the timing generator 612 is supplied to the AFE 622 as a sample hold signal (SHD) via the CCD driver 614. Although not shown, a master clock signal (MCLK) is input from the timing generator 612 to the AFE 622.

  The CCD 616 reads an image of a document on a contact glass (not shown) and outputs an analog image signal. The output analog image signal is A / D converted by the AFE 622, and the AFE 622 outputs digital image data. Digital image data output from the AFE 622 is transmitted to the main unit 630 side by serial differential transfer via an LVDS (Low Voltage Differential Signaling) interface 624.

  The main unit 630 includes a CPU 632, an LVDS interface 634 connected to the LVDS interface 624 on the scanner unit 610, and an image processing circuit unit 636 that performs various types of image processing. The digital image data transmitted to the main unit 630 via the LVDS interface 634 is passed to the image processing circuit unit 636 and subjected to various image processing such as line interpolation correction, shading correction, and gamma correction. After image processing, the digital image data is passed to the printer engine 640 via the interface 638. The printer engine 640 forms an image on the transfer member by an image forming process such as electrophotography according to the received digital image data.

  In this copying machine 600, overvoltage and overcurrent that can be generated in the AFE 622 and the emitter follower circuit 620 are suitably suppressed by the circuit configuration of the sensor control board described above, so that stable operation and high reliability are realized. be able to. In FIG. 10, a copying machine 600 is illustrated as an image reading apparatus. However, an apparatus that can implement the overvoltage protection circuit according to the above-described embodiment is not limited to the copying machine. In another embodiment, the overvoltage protection circuit according to the above-described embodiment is a CCD, such as an image reading device such as a scanner, an image forming device such as a multifunction peripheral, an image communication device such as a facsimile, a photographing device such as a digital camera or a digital video camera. And any device with AFE.

  FIG. 11 is a diagram showing a mechanism configuration of the scanner unit of the copying machine 600 shown in FIG. A mechanism configuration 700 of the scanner unit shown in FIG. 11 includes a contact glass 712 on which an original is placed, a white reference plate 716 for correcting distortion caused by an optical system, a first carriage 722, and a second carriage. 728 and a lens unit 730. The scanner unit mechanism configuration 700 further includes an image sensor control board 734 including the CCD 732 of the present embodiment.

  The first carriage 722 includes a document exposure xenon lamp 718 and a first reflection mirror 720, and the second carriage 728 includes a second reflection mirror 724 and a third reflection mirror 726. The first carriage 722 and the second carriage 728 move in the sub-scanning direction A by driving a stepping motor (not shown) during scanning.

  The light emitted from the xenon lamp 718 is reflected by the original surface on the contact glass 712, and the reflected light passes through the optical system such as the mirrors 720, 724, 726 and the lens unit 730 and is coupled onto the light receiving surface of the CCD 732. Imaged. The analog image signal output from the CCD 732 is digitized on the image sensor control board 734 and input to the main unit via a communication cable (not shown), and various digital image processing is performed.

  As described above, according to the above-described embodiment, it can occur in both the AFE and the emitter follower circuit due to an abnormal output such as an excessive output or an excessive output in the output signal of a solid-state imaging device such as a CCD or a signal fluctuation. It is possible to provide a control board, an image reading apparatus, an image forming apparatus, an imaging apparatus, and a control method that can suitably prevent overvoltage and overcurrent.

  Although the embodiments of the present invention have been described so far, the embodiments of the present invention are not limited to the above-described embodiments, and those skilled in the art may conceive other embodiments, additions, modifications, deletions, and the like. It can be changed within the range that can be done, and any embodiment is included in the scope of the present invention as long as the effects of the present invention are exhibited.

100, 200, 300, 400, 500 ... Image sensor control board, 110, 210, 310, 410, 510 ... CCD, 120, 220, 320, 420 ... AFE, 122, 222, 322, 422 ... Clamp circuit, 128, 228, 328, 346, 428 ... capacitor elements, 130, 230, 330, 430 ... emitter follower circuits, 132, 232, 332, 432 ... first emitter followers, 134, 234, 334, 434 ... second emitter followers, 140 , 240, 340, 440, 540 ... overvoltage protection circuit, 142, 242, 342, 542 ... switch, 142a, 242a ... parasitic diode, 244, 344, 434a ... resistance element, 600 ... copier, 610 ... scanner unit, 612 ... Timing generator, 614 ... CCD driver 616: CCD, 618: Overvoltage protection circuit, 620: Emitter follower circuit, 622 ... AFE, 624, 634 ... LVDS interface, 630 ... Main unit, 632 ... CPU, 636 ... Image processing circuit unit, 638 ... Interface, 640 ... Printer engine, 700 ... Mechanical configuration, 712 ... Contact glass, 716 ... White reference plate, 718 ... Xenon lamp, 720 ... First reflection mirror, 722 ... First carriage, 724 ... Second reflection mirror, 726 ... Third reflection Mirror, 728 ... second carriage, 730 ... lens unit, 732 ... CCD, 734 ... image sensor control board, 1000 ... sensor control board, 1002 ... timing generator, 1004 ... CCD driver, 1006 ... CCD, 1008, 1108 ... AFE 1010,1110 An emitter follower circuit, 1012,1112 ... first emitter follower, 1014,1114 ... second emitter follower, 1016 ... clamp circuit, 1116 ... delay circuit

JP 2007-214688 A

Claims (16)

A control board comprising signal output means for outputting a sensor response and signal processing means for processing an input signal,
Overvoltage protection means comprising switch means for interrupting transmission to the subsequent stage of the output signal during a set period in which the output signal from the signal output means is input and the signal output means can generate an abnormal output;
An emitter follower circuit that buffers the output signal transmitted from the signal output means through the switch means and outputs the buffered output signal to the signal processing means, and the switch means is in series with the output of the signal output means. A control board connected and provided after the signal output means and before the emitter follower circuit . 2. The control board according to claim 1, wherein a control signal of the switch means for controlling conduction and interruption of the output signal is switched at a change speed equal to or lower than a response speed of the emitter follower circuit .   3. The control board according to claim 1, wherein the setting period during which the signal output unit can generate an abnormal output includes a period from when the power to the control board is turned on until the signal output unit shifts to a normal operation. The signal output means is a solid-state imaging device that outputs an analog image signal generated by photoelectric conversion as the output signal, and the emitter follower circuit includes a first emitter follower and a second emitter follower, and the signal 4. The control board according to claim 1, wherein the processing means is an analog processing circuit that amplifies an input signal and converts the analog image signal into digital image data.   The overvoltage protection means includes a bias voltage setting means at a subsequent stage of the switch means, which divides a power supply voltage of the signal output means to set a signal level in a cutoff state of the switch means to a bias voltage. Item 5. The control board according to any one of Items 1 to 4.   The control board according to claim 5, wherein the bias voltage setting unit includes a capacitive element that delays generation of the bias voltage. The control board according to claim 1, wherein the emitter follower circuit includes a current limiting unit that limits an input / output current of the signal processing unit.   The setting period during which the signal output means can generate an abnormal output includes a period from when the power supply to the control board is detected until the signal output means stops. The control board as described in. The bias voltage Vbias is defined by the following conditional expressions (1) to (4)
Satisfying the relationship defined by
In the above conditional expressions (1) to (4), Vo_min represents the minimum signal level of the output signal, Vo_max represents the maximum signal level of the output signal, and Vebo1 and Vebo2 are the respective values of the emitter follower circuit . the base of the first emitter follower and a second emitter follower - shows a reverse breakdown voltage between emitter, delta Ve1, the first emitter follower indicates the level of the negative side can follow the base voltage, is DerutaVe2, the first 2 indicates a positive level at which the emitter follower can follow the base voltage, and ΔVafe (+) and ΔVafe (−) are positive values that can be changed without causing the signal processing means to generate an overvoltage or overcurrent, respectively. The control board according to claim 5, wherein the control board indicates a side level and a negative level.   The control board according to claim 4, wherein the solid-state imaging device incorporates the switch unit of the overvoltage protection unit.   An image reading apparatus comprising the control board according to claim 1. An image forming apparatus comprising the image reading apparatus according to claim 11 . An imaging device that generates an analog image signal by photoelectric conversion, wherein the imaging device
Signal output means for outputting an analog image signal;
The analog image signal is input, and in a setting period in which the imaging apparatus can generate an abnormal output, the switch means for cutting off the output to the subsequent stage of the analog image signal,
An output signal output from the imaging device through the switch means is buffered by an emitter follower circuit and input to a signal processing means for processing the signal , and the switch means is connected in series with the output of the signal output means. And is provided after the signal output means and before the emitter follower circuit,
Imaging device. Overvoltage protection means comprising signal output means for outputting a sensor response, switch means for conducting or blocking the output signal output from the signal output means to the subsequent stage, and buffering the output signal transmitted from the signal output means A control board comprising an emitter follower circuit and signal processing means for processing the output signal input from the emitter follower circuit , wherein the switch means is connected in series to the output of the signal output means; and A method implemented on the control board after the signal output means and before the emitter follower circuit ,
The switching means shuts off the output signal in response to the start of a set period during which the signal output means may generate an abnormal output;
The switch means includes a step of conducting the output signal in response to the end of the set period. The step of shutting off includes a step of switching from a cutoff state to a conductive state at a rate of change below the response speed of the emitter follower circuit , wherein the control signal of the switch means for controlling conduction and cutoff of the output signal. Item 15. The control method according to Item 14.   16. The start of the set period is a timing at which power-on to the control board is detected, and an end of the set period is a timing at which the signal output unit shifts to a normal operation. Control method.