JP5584179B2 - Connected device detection circuit - Google Patents

Description

  The present invention relates to a detection circuit for a connected device connected to an electronic device, and more particularly to a detection circuit for a connected device connected to an electronic device having a USB terminal.

Currently, a microphone can be connected to a computer or mobile phone, and voice can be input to the computer or the like. When a computer or the like and a microphone are connected, the computer automatically detects that the microphone is connected and starts application software for voice processing.
As a conventional technique for automatically detecting that a computer or the like and a microphone are connected, there is, for example, Patent Document 1. Patent Document 1 describes a technique for detecting that a microphone is connected to a computer from the number of pins of a microphone jack. Further, such a technique cannot distinguish between stereo headphones and a microphone connected to a computer or the like using a jack having the same configuration. In order to solve this problem, an invention for detecting whether or not the signal input to the jack is an audio signal is described.

  In the invention described in Patent Document 1, when it is determined that an audio signal is input to the jack, it is determined that a microphone is connected to the computer.

JP 2002-101491 A

  Incidentally, in recent years, a USB (Universal Serial Bus) terminal is used not only as a signal terminal but also as a power supply terminal for supplying power to peripheral devices from a computer or a mobile phone. A peripheral device that receives power from a computer using a USB terminal includes a microphone. However, in the future, more peripheral devices may use a USB terminal to exchange signals and power with a computer.

USB terminals are more versatile than jack / plug connectors, and some of them are small and thin. Therefore, the USB terminals are in line with the trend toward thinner and smaller computers.
However, the above-described invention described in Patent Document 1 uses a time change of a signal to determine whether or not the signal input to the jack is an audio signal. For this reason, the invention described in Patent Document 1 requires a codec and a CPU for detecting a time change of a signal, so that the circuit configuration is complicated and the size is increased.

When such a conventional technique is applied, even if the microphone is connected to the computer using the USB terminal, there is a possibility that the detection circuit of the microphone may hinder the downsizing and thinning of the computer or the like.
The present invention has been made in view of the above points, and provides a detection circuit for a connected device capable of detecting that a peripheral device such as a microphone is connected to a computer while having a small and simple configuration. The purpose is to provide.

In order to solve the above-described problems, a detection circuit for a connection device according to the present invention includes an input terminal (for example, the input terminal 101 shown in FIG. 2) and a voltage detection that detects a signal based on an electrical signal input from the input terminal. between the circuit (N-channel MOS transistor 103 shown in FIG. 2, for example) the first switch that is provided between the (e.g. voltage detecting circuit 104 shown in FIG. 2), and the first switch and the voltage detection circuit A power supply terminal (for example, the terminal 111 shown in FIG. 2) that supplies power to the node, and a connection device that is provided between the power supply terminal and the node and connected to the input terminal. An impedance element (for example, the resistance element 109 shown in FIG. 2) through which a current flows, and the voltage detection circuit is configured such that an input voltage input to the input terminal is a resistance value of the connected device and the impedance And detecting the values of the divided divided voltage by the resistance value of the impedance element.

  Further, in the above-described invention, the detection circuit for the connected device according to the present invention is provided between the impedance element and a ground power source, and when a voltage equal to or higher than a preset voltage value is input from the input terminal. It is desirable to further include a second switch (for example, a P-channel MOS transistor 108 shown in FIG. 2) that turns on and discharges the voltage input to the input terminal to the ground power supply.

In the connection device detection circuit of the present invention, in the above-described invention, the first switch includes a first MOS transistor having a body diode whose forward direction is from the power supply terminal to the input terminal (for example, in FIG. 2). The N-channel MOS transistor 103) shown is desirable.
In the connection device detection circuit according to the present invention, in the above-described invention, the first switch includes a body diode whose forward direction is from the input terminal to the power supply terminal, and the first MOS transistor and the It is desirable to further include a second MOS transistor (for example, N-channel MOS transistor 703 shown in FIG. 8) provided between the impedance element.

The detection circuit of the connection device of the present invention, in the invention described above, the second switch, the third 3MOS transistor whose source is connected between the source and the source of the first 2MOS transistor of the first 1MOS transistor (e.g. It is desirable to include the P-channel MOS transistor shown in FIG.
In the detection circuit for a connection device of the present invention, in the above-described invention, the impedance element is preferably a resistance element (for example, the resistance element 109 shown in FIG. 2).
In the connection device detection circuit of the present invention, in the above-described invention, the impedance element is preferably a MOS transistor (for example, a P-channel MOS transistor 118 shown in FIG. 11).

  According to the present invention, it is possible to provide a detection circuit for a connected device that can detect that a peripheral device such as a microphone is connected to a computer while having a small and simple configuration.

It is a schematic diagram for demonstrating the USB device incorporating the detection circuit of the connection apparatus of Embodiment 1 of this invention. It is a figure for demonstrating the detection circuit of Embodiment 1 of this invention. FIG. 3 is a diagram illustrating a circuit configuration of a voltage detection circuit illustrated in FIG. 2. FIG. 3 is a diagram illustrating another circuit configuration of the voltage detection circuit illustrated in FIG. 2. FIG. 3 is a diagram for explaining a gate voltage generation circuit shown in FIG. 2. FIG. 3 is a diagram for explaining a reference voltage generation circuit shown in FIG. 2. It is a timing chart for demonstrating operation | movement of the detection circuit of Embodiment 1 of this invention. It is a circuit diagram for demonstrating the detection circuit of Embodiment 2 of this invention. It is a timing chart for demonstrating operation | movement of the detection circuit of Embodiment 2 of this invention. It is a circuit diagram for demonstrating the detection circuit of Embodiment 3 of this invention. It is a circuit diagram for demonstrating the detection circuit of Embodiment 4 of this invention. FIG. 12 is a circuit diagram for explaining a configuration of a reference voltage generation circuit shown in FIG. 11. FIG. 12 is a circuit diagram for explaining a configuration of another reference voltage generation circuit shown in FIG. 11. It is a timing chart for demonstrating operation | movement of the detection circuit of Embodiment 4 of this invention. It is a figure for demonstrating the detection circuit of Embodiment 5 of this invention. It is a figure for demonstrating the detection circuit of Embodiment 6 of this invention.

Embodiments 1 to 6 of the connection device detection circuit of the present invention will be described below with reference to the drawings. In Embodiments 1 to 6 described below, it is assumed that a microphone is connected to an electronic device such as a computer (hereinafter referred to as a USB device) using a USB terminal. The detection circuit is provided inside the USB device.
(Embodiment 1)
Circuit Configuration FIG. 1 is a schematic diagram for explaining a USB device in which a detection circuit (hereinafter simply referred to as a detection circuit) of a connected device according to Embodiment 1 of the present invention is built. The USB device includes an input terminal 101 connected to a USB terminal. The USB device also includes a plurality of circuits having different uses and functions, such as circuit A, circuit B, and circuit C. Each of the circuit A, the circuit B, and the circuit C receives a signal and power from the USB terminal, and outputs a signal corresponding to each application and function to the corresponding output terminal.

FIG. 2 is a diagram for explaining the detection circuit according to the first embodiment of the present invention, and corresponds to the circuit C shown in FIG. In this specification, the configuration illustrated in FIG. 2 will be described in the first embodiment. In the following embodiments, the same configurations as those illustrated in FIG. It shall be omitted.
The detection circuit according to the first embodiment includes a resistance element 109 for detecting the microphone resistance RMIC. A power supply voltage VCC is connected to one end of the resistance element 109. The other terminal of the resistance element 109 is connected to the node 107 of the detection circuit.

The detection circuit according to the first embodiment includes a voltage detection circuit 104 that detects the input voltage VIN divided by the microphone resistor RMIC and the resistance value R1 of the resistance element 109. A signal VOUT output from the voltage detection circuit 104 based on the input voltage Vin is output from the output terminal 102.
The detection circuit according to the first embodiment includes an N-channel MOS transistor 103 which is turned on / off on the signal transmission node 107 between the input terminal 101 and the voltage detection circuit 104 and which connects and disconnects the signal transmission nodes 107a and 107b. A body diode 103 a is formed in the N-channel MOS transistor 103. A USB terminal is connected to the input terminal 101.

The detection circuit according to the first embodiment includes a gate voltage generation circuit 105 that generates the gate voltage VG of the N-channel MOS transistor 103. The gate voltage generation circuit 105 outputs a gate voltage VG for making the N-channel MOS transistor 103 conductive with a low on-resistance. The gate voltage VG is a voltage generated by boosting the power supply voltage VCC. The output of the gate voltage VG is performed in accordance with the timing when the USB device instructs to detect the microphone resistance RMIC. The detection of the microphone resistance RMIC is periodically performed at predetermined time intervals.
In the above configuration, the power supply voltage VCC is divided by the microphone resistance RMIC and the resistance value R1 of the resistance element 109. The voltage detection circuit 104 detects whether or not the divided voltage VSNS exceeds a preset threshold value. When the divided voltage is less than the threshold value, it is detected that a microphone is connected to the USB device.

  By the way, since the pins of the USB terminal are exposed and air exists in the space between the pins, a surge voltage may be generated. Furthermore, since the external shape of the USB terminal is standardized by the USB standard, there is a possibility that the user erroneously inserts the USB terminal for power supply into the USB terminal for microphone. In these cases, a high voltage may be input from the microphone USB terminal.

  When a surge voltage is applied to the USB device shown in FIG. 2, if no measures are taken, the current flows backward to the terminal 111 that supplies the power supply voltage VCC, and other internal circuits connected to the power supply There is a risk of destruction or malfunction. In order to prevent this, the detection circuit according to the first embodiment has a function of discharging the surge voltage and protecting the internal circuit of the USB device when a surge voltage is input to the USB terminal when detecting the microphone resistance RMIC. (Hereinafter also referred to as a protection circuit).

Protection circuit The protection circuit of the first embodiment is for controlling the on / off of the P-channel MOS transistor 108 that functions as a switch for discharging a surge voltage input to the input terminal 101 and the P-channel MOS transistor 108. And a reference voltage generation circuit 106 for generating a reference voltage VR.

Voltage Detection Circuit FIGS. 3 and 4 are diagrams illustrating the circuit configuration of the voltage detection circuit 104. The voltage detection circuit 104 illustrated in FIG. 3 includes a comparator 201. The divided voltage VSNS is input to the inverting input terminal of the comparator 201, and the reference voltage VREF is supplied from the power source 202 to the non-inverting input terminal. The comparator 201 determines whether or not the divided voltage VSNS is equal to or higher than the reference voltage VREF. When the divided voltage VSNS has a value equal to or higher than the reference voltage VREF, the voltage detection circuit 104 assumes that the microphone resistance RMIC cannot be detected (open state), and is referred to as a Low level signal (hereinafter referred to as an L level signal). ) To the output terminal 102. On the other hand, when the divided voltage VSNS is less than the reference voltage VREF, the voltage detection circuit 104 outputs a high level signal (hereinafter referred to as an H level signal) to the output terminal 102 as detecting the microphone resistance RMIC.

  The voltage detection circuit 104 shown in FIG. 4 includes an inverter composed of a current source 301, a P channel MOS transistor 302, and an N channel MOS transistor 303. When the divided voltage VSNS is less than the reference voltage VREF, the N channel MOS transistor 303 is turned off and the P channel MOS transistor 302 is turned on to output an H level signal to the output terminal 102. In the voltage detection circuit 104 shown in FIG. 4, the value of the reference voltage VREF is determined by the current I 0 flowing through the current source 301.

Gate Voltage Generation Circuit FIGS. 5A and 5B are diagrams for explaining a configuration example of the gate voltage generation circuit 105 shown in FIG. The circuit shown in FIG. 5A includes an AND circuit 411 and two inverters 412 and 413. The AND circuit 411 and the inverters 412 and 413 are connected to each other in series. The AND circuit 411 receives a clock signal CLK and an enable signal SWON for turning on the N-channel MOS transistor 103. The inverter 412 outputs the clock signal CLK_B from the output of the AND circuit 411, and the inverter 413 inverts the clock signal CLK_B and outputs the clock signal CLK_BB.

  The gate voltage generation circuit 105 shown in FIG. 5B is configured as a charge pump circuit (boost circuit). The gate voltage generation circuit 105 includes a switch 401 and a switch 402 connected in series, and switches 403 and 404 connected in series. The switches 401 and 402 and the switches 403 and 404 are connected in parallel to each other. A capacitor 405 is connected between the switch 401 and the switch 402, and between the switch 403 and the switch 404, and between the switch 402 and the output terminal of the gate voltage generation circuit 105 and the ground power supply. 406 is connected. A resistance element 409 and an N-channel MOS transistor 408 are connected in series between the output terminal of the gate voltage generation circuit 105 and the ground power supply. The output of the inverter 407 is connected to the gate of the N-channel MOS transistor 408, and the enable signal SWON is input to the inverter 407.

The switches 401 to 404 are turned on and off by the clock signal CLK_B or the clock signal CLK_BB output from the circuit shown in FIG. Further, it is assumed that the capacitance value C1 of the capacitor 405 and the capacitance value C2 of the capacitor 406 are equal.
After turning on the power supply voltage VCC, a clock signal CLK (denoted as CLK_BB in the figure) is supplied to a switch 401, 404 from a microcomputer (not shown), and an inverted clock signal CLK (denoted as CLK_B in the figure) is obtained by inverting the clock signal CLK. It is given to the switches 402 and 403. Charges are stored in the capacitor 405 when the switches 401 and 404 are turned on, and charges stored in the capacitor 405 are transferred to the capacitor 406 when the switches 402 and 403 are turned on. By repeating the above operation, the gate voltage generation circuit 105 boosts the power supply voltage VCC. On the other hand, when the N-channel MOS transistor 103 is turned off, the enable signal SWON becomes the Low level, is inverted by the inverter 407, and is input to the gate of the N-channel MOS transistor 408. Then, the N channel MOS transistor 408 is turned on, and the electric charge stored in the capacitive elements 405 and 406 is discharged to the ground power supply via the resistance element 409 and the N channel MOS transistor 408, and becomes 0V.

Reference Voltage Generation Circuit FIG. 6 is a diagram for explaining the reference voltage generation circuit 106 shown in FIG. The reference voltage generation circuit 106 includes a current source 501 and a resistance element 502 connected in series with the current source 501, and outputs a reference voltage VR from a connection point between the current source 501 and the resistance element 502. The reference voltage VR is generated by flowing a current IREF flowing through the current source 501 through the resistance element 502.

  In the reference voltage generation circuit 106, when the allowable maximum voltage of the input voltage of the voltage detection circuit 104 is the allowable maximum voltage VLIM and the threshold voltage of the P-channel MOS transistor 108 is Vth, the current IREF is set so that VR = VLIM−Vth. A resistance value R2 of the resistance element 502 is set. That is, when the source voltage of the P-channel MOS transistor 108 exceeds VR + Vth, the gate-source voltage VGS exceeds Vth.

At this time, the P-channel MOS transistor 108 is turned on. The input voltage VIN exceeding the allowable maximum voltage VLIM is discharged through the P channel MOS transistor 108. The reference voltage generation circuit 106 and the P channel MOS transistor 108 constitute a clamp circuit.
In the first embodiment, Vcc = 1.8V, VR = 0.3V, Pth MOS transistor 108's Vth = 0.7V, allowable maximum voltage VLIM = 1.0V, and the voltage detection circuit 104 is connected to a microphone. Is set to 0.5V. Further, it is assumed that the ON resistance of N channel MOS transistor 103 and the ON resistance of P channel MOS transistor 108 are sufficiently smaller than the resistance value of resistance value R 1 of resistance element 109.

Operation Hereinafter, the operation of the detection circuit according to the first embodiment described above will be described.
FIG. 7 is a timing chart for explaining the operation of the detection circuit according to the first embodiment. The vertical axis in FIG. 7 is the voltage level, and the horizontal axis is time. This timing chart shows a power supply voltage VCC, a reference voltage VR, a MICCHK signal that instructs to detect whether or not a microphone is connected to the USB device, a clock signal CLK input to the gate voltage generation circuit 105, and an N-channel MOS. An enable signal SWON for turning on the transistor 103, a gate voltage VG inputted to the gate of the N-channel MOS transistor 103, an input voltage VIN, a divided voltage VSNS, an output voltage VOUT, and a current I_MP1 flowing through the P-channel MOS transistor 108 are shown. ing.

  The power is turned on to the terminal 111 shown in FIG. 2, and the power supply voltage VCC rises from 0V to 1.8V. The reference voltage VR output from the reference voltage generation circuit 106 increases from 0V to 0.3V. Then, a MICCHK signal for checking whether a microphone is connected from a microcomputer (not shown) becomes a high level. In synchronization with the rise of the MICCHK signal, the clock signal CLK is supplied to the gate voltage generation circuit 105 to start the boosting operation. Further, in synchronization with the rise of the MICCHK signal, the enable signal SWON for turning on the N-channel MOS transistor 103 becomes High level.

  Since the capacitance values C1 and C2 of the capacitive elements 405 and 406 of the gate voltage generation circuit 105 shown in FIG. 5B are equal, the gate voltage VG rises from 0V to 3.6V. As the gate voltage VG rises, the N channel MOS transistor 103 is turned on. The input voltage VIN rises by a voltage dividing circuit constituted by the resistance element 109 and the microphone resistance RMIC. On the other hand, the divided voltage VSNS input to the voltage detection circuit 104 is equal to the threshold voltage VF of the body diode of the N-channel MOS transistor 103 when R1 >> RMIC when the input voltage VIN is 0V. Therefore, the voltage is stepped down to the input voltage VIN.

  The gate voltage generation circuit 105 starts the boosting operation by the enable signal SWON. The gate voltage VG increases due to the boosting operation. The divided voltage VSNS is input to the voltage detection circuit 104 at the moment when the N-channel MOS transistor 103 is turned on. For example, the voltage detection circuit 104 shown in FIG. 3 compares the divided voltage VSNS with the reference voltage VREF. When the divided voltage VSNS is less than the reference voltage VREF (= 0.5 V), an H level signal is output as the output signal VOUT. The USB device detects that a microphone is connected by outputting an H level signal.

  Here, when a 30-V surge voltage is input to the input terminal 101, the source voltage of the P-channel MOS transistor 108 exceeds VR + Vth. Therefore, P channel MOS transistor 108 is turned on and the surge voltage is discharged to the ground. Further, the divided voltage VSNS exceeds the allowable maximum voltage VLIM (1 V) of the voltage detection circuit 104. For this reason, since the divided voltage exceeds the threshold value in the voltage detection circuit 104, an L level signal is output from the output terminal 102.

The surge voltage is discharged by the P channel MOS transistor 108. For this reason, the divided voltage VSNS maintains a low voltage of 1.0V. That is, since the divided voltage VSNS does not exceed the power supply voltage VCC, other circuits inside the USB device can be protected without a current flowing backward to the power supply that supplies the power supply voltage VCC via the terminal 111.
Furthermore, in the first embodiment, even when the N-channel MOS transistor 103 is off, the divided voltage VSNS exceeds the allowable maximum voltage VLIM, and a current flows through the P-channel MOS transistor 108.

In order to solve this problem, in the first embodiment, the detection circuit is designed or controlled so that VR = VCC when the enable signal SWON is at the low level. According to such control, when the N-channel MOS transistor 103 is off, no current flows through the P-channel MOS transistor 108, and the power consumption of the detection circuit can be reduced.
In the first embodiment described above, when a peripheral device is connected to the input terminal 101, a change in resistance (voltage) caused by the connection of the peripheral device is passively detected to determine whether or not the peripheral device is connected. be able to. Therefore, it is possible to apply a detection circuit that is effective for reducing the size and cost of the USB device.

  In the first embodiment, in the above configuration, when a surge voltage is input to the input terminal, the surge voltage can be discharged passively. Therefore, even if the input terminal is a USB terminal that is relatively easy to generate a surge voltage, it is possible to protect the circuit inside the device in which the detection circuit is built. In particular, the first embodiment can realize the detection circuit of the present invention with the minimum necessary configuration. For this reason, it is possible to reduce the size of the detection circuit, and hence the USB device incorporating the detection circuit.

Further, the first embodiment is not limited to the configuration described above. For example, the connection device detection apparatus according to the first embodiment is not limited to a configuration that detects a device connected to a USB device terminal, and protects an internal circuit of a device having another terminal for inputting a power source or a signal. It can also be applied.
Furthermore, Embodiment 1 is not limited to the structure which connects a microphone to an input terminal. Any peripheral device connected to the input terminal can be applied to the connection of any device.

(Embodiment 2)
Circuit Configuration FIG. 8 is a circuit diagram for explaining a detection circuit according to the second embodiment of the present invention. The detection circuit of the second embodiment shown in FIG. 8 differs from the detection circuit of the first embodiment in that an N-channel MOS transistor 703 is further provided between the N-channel MOS transistor 103 and the voltage detection circuit 104 shown in FIG. Is different. The N-channel MOS transistor 703 is formed with a body diode (drain bulk diode) 703a, and the forward direction of the body diode 703a is opposite to the forward direction of the body diode 103a. That is, since the anodes of the body diodes 103a and 703a are continuous with each other, no current flows through the N-channel MOS transistors 103 and 703.

  According to such a configuration, the threshold voltages of the body diodes 103a and 703a when the N-channel MOS transistors 103 and 703 are off can be canceled (cancelled) with each other. Therefore, in the second embodiment, the body diodes of the N-channel MOS transistors 103 and 703 can suppress current from flowing to the input terminal 101 when the N-channel MOS transistors 103 and 703 are off.

Operation FIG. 9 is a timing chart for explaining the operation of the detection circuit according to the second embodiment. The vertical axis in FIG. 9 is the voltage level, and the horizontal axis is time. This timing chart shows a power supply voltage VCC, a reference voltage VR, a MICCHK signal that instructs to detect whether or not a microphone is connected to the USB device, a clock signal CLK input to the gate voltage generation circuit 105, and an N-channel MOS. An enable signal SWON for turning on the transistor 103, a gate voltage VG inputted to the gate of the N-channel MOS transistor 103, an input voltage VIN, a divided voltage VSNS, an output voltage VOUT, and a current I_MP1 flowing through the P-channel MOS transistor 108 are shown. ing.

  The gate voltage generation circuit 105 starts the boosting operation by the enable signal SWON. The gate voltage VG increases due to the boosting operation. The divided voltage VSNS is input to the voltage detection circuit 104 at the moment when the N-channel MOS transistors 103 and 703 are turned on. When the divided voltage VSNS is equal to or lower than the reference voltage VREF (= 0.5 V), an H level signal is output as the output signal VOUT. The USB device detects that a microphone is connected by outputting an H level signal.

Also in the second embodiment, when a surge voltage of 30 V is input to the input terminal 101, the P-channel MOS transistor 108 is turned on and the surge voltage is discharged to the ground. Further, since the divided voltage exceeds the microphone detection threshold in the voltage detection circuit 104, an L level signal is output from the output terminal 102.
The surge voltage is discharged by the P channel MOS transistor 108. For this reason, the divided voltage VSNS maintains a low voltage of 1.0V. That is, since the divided voltage VSNS does not exceed the power supply voltage VCC, the other circuit of the USB device connected to the power supply can be protected without causing a current to flow back to the terminal 111.

  Furthermore, the second embodiment has a problem that even when the N-channel MOS transistors 103 and 703 are turned off, the divided voltage VSNS exceeds the allowable maximum voltage VLIM and a current flows through the P-channel MOS transistor 108. In the second embodiment, similarly to the first embodiment, when the SWON is L, the power consumption of the detection circuit can be reduced by designing or controlling the detection circuit so that VR = VCC.

(Embodiment 3)
Circuit Configuration FIG. 10 is a circuit diagram for explaining a detection circuit according to the third embodiment of the present invention. The difference between the detection circuit of the third embodiment shown in FIG. 10 and the detection circuit of the second embodiment shown in FIG. 8 is that the source of the P-channel MOS transistor 108 is the source of the N-channel MOS transistor 103 and the N-channel MOS transistor 703. It is a point connected between the source.

  According to the third embodiment, the forward direction of the body diode 103a of the N-channel MOS transistor 103 and the body diode 703a of the N-channel MOS transistor 703 are opposite to each other when viewed from the terminal 111. The source terminal of the P-channel MOS transistor 108 is connected between the anode of the body diode 103a and the anode of the body diode 703a. Therefore, no current flows from signal transmission node 107 to P channel MOS transistor 108. In the third embodiment, when the enable signal SWON is at the L level in the first and second embodiments, the current consumption of the detection circuit is further reduced as compared with the case where the detection circuit is not designed or controlled so that VR = VCC. can do.

  Note that the detection circuit of the third embodiment operates in the same manner as the detection circuit of the second embodiment. The difference between the operation of the third embodiment and the operation of the second embodiment is only that the divided voltage VSNS is 1.8V when the power supply voltage VCC is 1.8V and the gate voltage VG is 0V. For this reason, Embodiment 3 omits illustration and description of the operation of the detection circuit.

(Embodiment 4)
Circuit Configuration FIG. 11 is a circuit diagram for explaining a detection circuit according to the fourth embodiment of the present invention. The difference between the detection circuit of the fourth embodiment shown in FIG. 11 and the detection circuit of the first embodiment shown in FIG. 2 is that, instead of the resistance element 109 shown in FIG. And a node 107a to which the divided voltage VSNS is applied.

A reference voltage generation circuit 162 is connected to the gate of the P-channel MOS transistor 118, and a reference voltage is input to the gate of the P-channel MOS transistor. Therefore, P channel MOS transistor 118 functions as a current source.
In the fourth embodiment, a reference voltage generation circuit connected to the gate of the P channel MOS transistor 108 is used to distinguish between the reference voltage supplied to the P channel MOS transistor 118 and the reference voltage supplied to the P channel MOS transistor 108. The reference voltage generation circuit 161 is used. A reference voltage generation circuit connected to the gate of the P channel MOS transistor 118 is referred to as a reference voltage generation circuit 162. The reference voltage output from the reference voltage generation circuit 161 is VR1, and the reference voltage output from the reference voltage generation circuit 162 is VR2.

Reference Voltage Generation Circuit FIG. 12 is a circuit diagram for explaining a configuration example of the reference voltage generation circuit 161. FIG. 13 is a circuit diagram for explaining a configuration example of the reference voltage generation circuit 162. As shown in FIG. 12, the reference voltage generation circuit 161 is configured in the same manner as the reference voltage generation circuit 106 shown in FIG. 2, and a current source 1101 and a resistor are connected between the power supply for supplying the power supply voltage VCC and the ground. The element 1102 is connected in series. The reference voltage VR1 is generated by flowing a current IREF1 flowing through the current source 1101 through the resistance element 1102.

As shown in FIG. 13, the reference voltage generation circuit 162 has a configuration in which a P-channel MOS transistor 1201 and a current source 1202 are connected in series between a power supply that supplies a power supply voltage VCC and a ground. The reference voltage generation circuit 162 generates a voltage VR2 corresponding to the current IREF2 flowing through the current source 1202, and applies VR2 to the gate of the P-channel MOS transistor 118. Such a reference voltage generation circuit 162 forms a current mirror circuit with the P-channel MOS transistor 118.
In the fourth embodiment, the microphone resistor RMIC and the P-channel MOS transistor 118 constitute a voltage generation circuit, and a current flows from the P-channel MOS transistor 118 to the microphone resistor RMIC, so that the divided voltage to the voltage detection circuit 104 is obtained. VSNS is generated.

Operation FIG. 14 is a timing chart for explaining the operation of the detection circuit according to the fourth embodiment. The vertical axis in FIG. 14 is the voltage level, and the horizontal axis is time. This timing chart shows the power supply voltage VCC, the reference voltages VR1, VR2, the MICCHK signal that instructs to detect whether a microphone is connected to the USB device, and the clock signals CLK, N input to the gate voltage generation circuit 105. Enable signal SWON for turning on channel MOS transistor 103, gate voltage VG inputted to the gate of N channel MOS transistor 103, input voltage VIN, divided voltage VSNS, output voltage VOUT, current I_MP1 flowing through P channel MOS transistor 108 Is shown.

  The power is turned on, and the power supply voltage VCC shown in FIG. 2 rises from 0V to 1.8V. The reference voltage VR1 of the reference voltage generation circuit 161 increases from 0V to 0.3V. Then, a MICCHK signal for checking whether a microphone is connected from a microcomputer (not shown) becomes a high level. In synchronization with the rise of MICCHK, the clock signal CLK is supplied to the gate voltage generation circuit 105 to start the boosting operation. Further, in synchronization with the rise of the MICCHK signal, the enable signal SWON for turning on the N-channel MOS transistor 103 becomes High level.

  Since the capacitance values of the capacitive elements 405 and 406 of the gate voltage generation circuit 105 shown in FIG. 5B are the same, the gate voltage VG rises from 0V to 3.6V. As the gate voltage VG rises, the N channel MOS transistor 103 is turned on, and the input voltage VIN rises by a voltage generation circuit using a current flowing through the P channel MOS transistor 118 and the microphone resistance RMIC. On the other hand, the divided voltage VSNS input to the voltage detection circuit 104 is stepped down from the power supply voltage VCC to the input voltage VIN. The divided voltage VSNS when the input voltage VIN in FIG. 14 is 0V becomes the threshold voltage VF of the body diode of the N-channel MOS transistor 103 when R1 >> RMIC.

The input voltage VIN is a threshold voltage of 0.5V or less. Therefore, the voltage detection circuit 104 outputs H as the output signal VOUT at the moment when the gate voltage VG rises and the N-channel MOS transistor 103 is turned on, and detects that the microphone is connected.
Here, when a surge voltage of 30 V is input to the input terminal 101, the divided voltage VSNS exceeds the allowable maximum voltage VLIM (1 V). For this reason, the P-channel MOS transistor 108 is turned on, and the surge voltage is discharged to the ground. Further, since the divided voltage VSNS exceeds the threshold value, VOUT becomes L. Since the surge voltage is discharged to the ground by the P-channel MOS transistor 108, the divided voltage VSNS maintains a low voltage of 1.0V. That is, since the divided voltage VSNS does not exceed VCC, the circuit inside the USB device can be protected without the current flowing back to the terminal 111.
According to the fourth embodiment, since a MOS transistor is used as a resistance element, a resistance element having an arbitrary resistance value can be realized with a smaller area than when the resistance element 109 shown in FIG. 2 is used. .

(Embodiment 5)
Circuit Configuration FIG. 15 is a diagram for explaining a detection circuit according to the fifth embodiment of the present invention. In the detection circuit of the fifth embodiment, an N-channel MOS transistor 143 is provided between the N-channel MOS transistor 103 and the voltage detection circuit 104 of the detection circuit described in the fourth embodiment. A body diode generated in the N-channel MOS transistor 143 is shown as a body diode 143a in the drawing.

  In the fifth embodiment, the forward direction of the body diode 103a of the N-channel MOS transistor 103 is opposite to the forward direction of the body diode 143a of the N-channel MOS transistor 143. Therefore, the threshold voltage VF of the body diode can be canceled when the N-channel MOS transistors 103 and 143 are off. Therefore, in the fifth embodiment, the body diode of the N-channel MOS transistors 103 and 143 can also suppress the current from flowing to the input terminal 101 when the N-channel MOS transistors 103 and 143 are off.

Furthermore, in the fifth embodiment, when the N-channel MOS transistors 103 and 143 are off, the divided voltage VSNS exceeds the allowable maximum voltage VLIM, and a current flows through the P-channel MOS transistor 108. However, in the fifth embodiment, when the control is performed so that VR1 = VCC when the enable signal SWON is at the low level, the P-channel MOS transistor 108 is turned off and no current flows, so that power consumption can be reduced. .
Note that the operation of the detection circuit of the fifth embodiment operates in the same manner as the detection circuit of the second embodiment described above. At this time, N channel MOS transistor 143 operates in the same manner as N channel MOS transistor 103. For this reason, illustration and description of the operation of the detection circuit of Embodiment 5 are omitted.

(Embodiment 6)
Circuit Configuration FIG. 16 is a diagram for explaining a detection circuit according to the sixth embodiment of the present invention. In the detection circuit of the sixth embodiment, the source of the P-channel MOS transistor 108 of the detection circuit of the fifth embodiment is connected between the source of the N-channel MOS transistor 103 and the source of the N-channel MOS transistor 143. It is a difference. According to the configuration of the sixth embodiment, when the N-channel MOS transistors 103 and 143 are off, the direction of the body diode of the N-channel MOS transistor 143 is reversed as viewed from the terminal 111. Therefore, no current flows from signal transmission node 107 to P channel MOS transistor 108. In the sixth embodiment, when the SWON is L in the fourth and fifth embodiments, the consumption current of the detection circuit can be reduced as compared with the case where the detection circuit is not designed or controlled so that VR = VCC. .

  Note that the operation of the detection circuit of the sixth embodiment is the same as that of the detection circuit of the third embodiment described above. At this time, N channel MOS transistor 143 operates in the same manner as N channel MOS transistor 103. For this reason, illustration and description of the operation of the detection circuit of Embodiment 6 are omitted.

  The detection circuit for a connected device according to the present invention can be particularly preferably used in the field of a USB device having a USB terminal.

DESCRIPTION OF SYMBOLS 101 Input terminal 102 Output terminal 103,703 N channel MOS transistor 103a, 703a Body diode 104 Voltage detection circuit 105 Gate voltage generation circuit 106,161,162 Reference voltage generation circuit 107 Signal transmission node 108,118 P channel MOS transistor 109 Resistance element 111 terminals

Claims (7)

An input terminal, a first switch that is provided between the voltage detection circuit for detecting a signal based on the electric signal input from the input terminal,
A power supply terminal connected to a node between the first switch and the voltage detection circuit and supplying power to the node;
An impedance element that is provided between the power supply terminal and the node and flows current to a connection device connected to the input terminal;
The voltage detection circuit detects a value of a divided voltage obtained by dividing an input voltage input to the input terminal by a resistance value of the connection device and a resistance value of the impedance element. Detection circuit.   Provided between the impedance element and a ground power supply, and turns on when a voltage equal to or higher than a preset voltage value is input from the input terminal, and discharges the voltage input to the input terminal to the ground power supply. The connected device detection circuit according to claim 1, further comprising: a second switch that performs the operation.   3. The connection device detection circuit according to claim 1, wherein the first switch is a first MOS transistor having a body diode whose forward direction is from the power supply terminal to the input terminal. 4.   The first switch includes a body diode having a forward direction from the input terminal toward the power supply terminal, and further includes a second MOS transistor provided between the first MOS transistor and the impedance element. The detection circuit for a connected device according to claim 3, wherein It said second switch, the detection circuit of the connection device according to claim 4, characterized in that it comprises a first 3MOS transistor whose source is connected between the sources of said first 2MOS transistor of the first 1MOS transistor.   The detection circuit for a connected device according to any one of claims 1 to 5, wherein the impedance element is a resistance element.   6. The detection circuit for a connected device according to claim 1, wherein the impedance element is a MOS transistor.

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