JP5581966B2 - Electronic device and electric power steering device using the same - Google Patents

Description

  The present invention relates to an electronic device including a CPU (Central Processing Unit) and a memory connected to the CPU via an address bus and a data bus, and an electric power steering device using the electronic device.

  2. Description of the Related Art Conventionally, an electronic device that includes a CPU, a memory, an address bus, and a data bus and can detect a fault such as a ground fault, a power fault, and a short circuit of the address bus and the data bus is known. For example, the electronic device disclosed in Patent Document 1 uses “a value in which only one of all bits is 1 or 0” as the inspection value. For address bus failure detection, a checksum is calculated by reading a value from the ROM area specified by “an address where only one of all bits is 1 or 0”, and compared with the true checksum. Determine whether or not there is a failure. For data bus failure detection, whether or not there is a failure by writing and reading “a value in which any one of all bits is 1 or 0” to the RAM, comparing the read data with the written data. Determine.

JP 2008-210245 A

The number of bits of the inspection value corresponds to the number of address lines or data bus lines to be inspected. For example, if the number of bus lines is 4, an inspection value of 4 bits or more is used.
Here, the “ground fault” of the bus line refers to a failure in which the value of the bit that should originally be 1 is fixed to 0, and the “sky fault” of the bus line means that the value of the bit that should be 0 originally is 1. A failure that sticks to the surface. A bus line “short-circuit failure” is a failure in which the value of the bit corresponding to the bus line to be inspected is the same as the value of the bit corresponding to the bus line other than the inspection target, in other words, maintaining different values. A failure that cannot be performed.

In the electronic device described in Patent Literature 1, if the address bus or data bus to be detected is 4 bits, for example, two inspection values “0001” and “1110” are used for the power fault and the ground fault. Thus, it can be determined that the value of each bit does not stick to 1 and does not stick to 0. However, a short-circuit fault cannot be determined unless four inspection values “0001”, “0010”, “0100”, and “1000” are used.
As described above, in order to detect a short-circuit failure, it is necessary to execute a failure detection process using inspection values equal to or more than the number of bus lines. For example, at least 32 values need to be read to check the 32-bit address bus, and at least 32 writes and reads must be done to check the 32-bit data bus. Similarly, a 128-bit bus requires 128 inspections. That is, since the number of inspections increases in proportion to the number of bits, the processing load on the electronic device becomes excessive.

  In the electronic device described in Patent Document 1, a checksum is used for detecting an address bus failure. This is because when the number of inspections increases as described above, it is possible to reduce the processing load by inspecting some total value instead of the individual values. However, the method using a checksum has a problem in that a failure cannot be determined when the same bit value of a value acquired from a certain inspection address and a value acquired from another address are interchanged. For example, it is assumed that the value obtainable from the address “0001” is “00101010” and the value obtainable from the address “0010” is “11010101”. At this time, when the value is acquired from the address “0001” and becomes “00101000” when the value is acquired from the address “0010” due to the failure of the address bus, “11010111” is obtained (the first digit of the second digit). When the bits “0” and “1” are interchanged), the checksum value is the same regardless of whether there is a failure or failure, and failure detection is not possible.

  The present invention was created in view of the above points, and an object of the present invention is to reduce the number of inspection values necessary for failure detection in an electronic device that detects failure of an address bus and a data bus. Another object of the present invention is to provide an electronic device that reduces processing load related to failure detection and improves processing speed.

The electronic apparatus according to claim 1 includes a CPU, a ROM, and an address bus including four or more bus lines that connect the CPU and the ROM and transmit addresses.
The CPU compares the judgment value calculated from the value read from the ROM area specified by the plurality of address bus test addresses with the pre-calculated correct value for the address bus test, and if the address bus fails to match, It is determined that
The plurality of address bus test addresses include a value of 4 bits or more corresponding to 4 or more bus lines, including a value having a value of 0 of 2 bits or more and a value of 1 of 2 bits or more. By determining whether the bit corresponding to the target bus line and the bit corresponding to the bus line other than the inspection target maintain different values from each other, a plurality of bus lines including the inspection target bus line are Short circuit faults can be detected simultaneously.
In addition, the electronic device uses “a value where the value of the bit corresponding to the bus line to be tested is 1” as a plurality of address bus test addresses, and “the value of the bit corresponding to the bus line of the address bus”. Can be detected by using “the value at which the value of the bit corresponding to the bus line to be inspected is 0”. It is possible to detect “1 fixed failure”, which is “a failure fixed to 1 where the value of the bit corresponding to the bus line of the bus is supposed to be 0”.
Further, the plurality of address bus test addresses used for detecting the short-circuit failure are N-bit values corresponding to N bus lines, and are (N / 2) -bit 0 value and (N / 2) -bit address. (Log ₂ N), and the number of the plurality of address bus test addresses used for short circuit fault detection is minimized.

An electronic device according to a second aspect includes a CPU, a ROM, and a data bus including four or more bus lines that connect the CPU and the ROM and transmit data.
The CPU compares the judgment value calculated from the plurality of data bus test values read from the ROM area of the ROM with the pre-calculated correct value for the data bus test and determines that the data bus is faulty. To do.
The plurality of data bus check values are values of 4 bits or more corresponding to 4 or more bus lines, including values having a value of 0 of 2 bits or more and a value of 1 of 2 bits or more. A short circuit between a plurality of bus lines including the bus line to be inspected by determining whether or not the bits corresponding to the other bus line and the bits corresponding to the non-inspected bus line maintain different values. Faults can be detected simultaneously.
In addition, the electronic device uses “a value where the value of the bit corresponding to the bus line to be tested is 1” as a plurality of data bus test values, and the “value of the bit corresponding to the bus line of the data bus indicates It is possible to detect a “0-fixed failure”, which is “a failure fixed to 0 where it should originally be 1”, and use the “value where the value of the bit corresponding to the bus line to be inspected is 0” to “data bus It is possible to detect “1 fixed failure”, which is “a failure fixed to 1 where the value of the bit corresponding to the bus line is supposed to be 0”.
Further, the plurality of data bus check values used for detecting a short-circuit fault are N-bit values corresponding to N bus lines, which are (N / 2) -bit 0 values and (N / 2) -bit values. The number having a value of 1 is (log ₂ N), and the number of data bus test values used for detecting a short-circuit fault is minimized.

The invention according to claim 1 detects the failure of the address bus, and the invention according to claim 2 detects the failure of the data bus, and has corresponding technical features.
The failure of the address bus can be detected by comparing the judgment value calculated from the value read from the ROM area and the correct value for address bus inspection calculated in advance.
Failure of the data bus can be output RIKEN by the comparing the pre-calculated data bus inspection correct value and the determination value calculated from the values read from the ROM area.

In the inventions according to claims 1 and 2 , “a plurality of address bus test addresses or a plurality of data bus test values (hereinafter referred to as“ a plurality of test values ”)” is a value of 4 bits or more, It includes values having a value of 0 over 2 bits and a value of 1 over 2 bits. For example, in the case of 4 bits, the plurality of inspection values include values such as 0011, 0101, 0110, and the like. This is a feature different from the conventional technique in which “a value in which only one of all bits is 1 or 0” is used as an inspection value.

  As a result, it is possible to simultaneously detect a short-circuit failure between a plurality of bus lines. Here, the short circuit failure means a failure in which a bit corresponding to a bus line to be inspected and a bit corresponding to a bus line other than the inspection target cannot maintain different values. The inspection value for detecting a short-circuit failure is required to make the value of the bit corresponding to the bus line to be inspected different from the value of the bit corresponding to another bus line. That is, it is necessary to construct a combination of all the bits in which the value of the bit to be inspected is 0 and the value of the other bit is 1 or the value of the inspected bit is 1 and the value of the other bit is 0.

  According to the prior art, for example, when an inspection value of “0001” is used and the inspection object is the least significant bit (0th bit), the 0th bit having a value of 1 and the 2nd digit of the second value having a value of 0 are used. Short circuit faults between the 1st bit, the 2nd bit of the 3rd digit, or the 3rd bit of the 4th digit can be detected simultaneously. However, when the inspection target is one of the first, second, and third bits, only one short-circuit fault between that bit and the 0th bit can be detected at the same time.

On the other hand, since the inspection value of the present invention has a value of 0 of 2 bits or more and a value of 1 of 2 bits or more, even if any of the bits is to be inspected, it has a value different from the value of the bit. Short-circuit faults between two or more other bits can be detected simultaneously.
Thereby, the number of inspection values can be reduced with respect to the prior art. As a result, it is possible to reduce the processing load on the electronic device related to failure detection and improve the processing speed of the electronic device.

  Further, in the prior art, in order to reduce the processing load on the electronic device due to an increase in the inspection value, a method for calculating the checksum based on the read value has to be taken. For this reason, a failure cannot be detected when the same bit value obtained from a different address is replaced. On the other hand, in the present invention, the number of inspection values can be reduced and the processing load of the electronic device can be reduced. Accordingly, it is possible to compare the read value with the correct value as it is or calculate the CRC by a generator polynomial within a practical memory capacity range without using a low-reliability method such as checksum. Therefore, more reliable processing can be executed.

According to the first and second aspects of the present invention, the plurality of inspection values used for detecting the short-circuit fault are N-bit values corresponding to N bus lines. The plurality of inspection values used for detection of the short-circuit fault are (log ₂ N ) values having 0 values of (N / 2) bits and 1 values of (N / 2) bits, and the inspection values Minimize the number of ( Log ₂ N ) is a logarithm of N with 2 as the base.

Taking the case where the inspection value is 8 bits as an example, “value having (N / 2) bit 0 value and (N / 2) bit 1 value” is as follows: 00001111, 0101101 A value having four 0 values and four 1 values. By using these values, (N / 2) short circuit faults between the bus lines can be detected simultaneously.
That is, the inspection value specified by 請 Motomeko 1 and 2, is limited to a value having four values in this case 1. As a result, when the number of bits to be inspected increases, it is possible to efficiently detect a short-circuit fault between a plurality of bus lines simultaneously.

The present invention as described in claim 1 is intended to minimize the number of the plurality of test values used in the detection of short-circuit failure. Here, the number of short-circuit determination combinations is the number of combinations in which two bits are selected from all bits. If the total number of bits is N bits, it is necessary to construct a combination of a plurality of inspection values of _N C _2. There is. When the number of bits to be inspected is 4 bits, the short-circuit determination is made for 6 patterns corresponding to the number of combinations ( ₄ C ₂ ) in which ₄ to 2 are selected.

For example, when “0011” is used for the inspection value, the four bits between the 0th bit and the 2nd bit, the 0th bit and the 3rd bit, the 1st bit and the 2nd bit, and the 1st bit and the 3rd bit, A short circuit can be determined. Furthermore, when “0101” is used as the inspection value, it is possible to make a short circuit determination for the two bits between the 0th bit and the 1st bit and the 2nd bit and the 3rd bit that cannot be determined by “0011”. That is, when the inspection value is 4 bits, six short-circuit determinations can be made by using (log ₂ 4) = 2 inspection values having two 0 values and two 1 values. .

Similarly, when the inspection value is 8 bits, (log ₂ 8) = 3 inspection values having four 0 values and four 1 values are used, and when the inspection value is 16 bits, A short circuit determination can be made by using (log ₂ 16) = 4 test values having 8 0 values and 8 1 values.

According to the prior art, inspection values equal to or more than the number of bits are necessary to detect a short circuit fault. On the other hand, in the present invention, by including a test value “having a value of (N / 2) bit 0 and a value of (N / 2) bit 1”, the test value necessary for detecting a short-circuit fault The number can be reduced. Moreover, by the test value meets the above requirements and (log 2 _N) pieces, it is possible to minimize the number of test values required to detect the short-circuit failure.

On the other hand, regarding the detection of the 0-fixation failure and the 1-fixation failure, when the inspection value is 4 bits, for example, “1111” can be used to detect all 0-fixation failures, and “0000” can be used to detect all It is possible to detect a 1 bit failure. By detecting the 0-fixed failure, it is possible to detect a ground fault in the bus line or a disconnection failure when the value of the corresponding bit becomes 0 when the disconnection occurs. Further, by detecting a 1-fixation failure, it is possible to detect a bus-line power-failure failure or a disconnection failure when the value of the corresponding bit is 1 when a disconnection occurs.

In addition, it is possible to detect 0-fixed faults and 1-fixed faults of all bits by using two inspection values “1100” and “0011”. In this case, since the requirements of the test value according to claims 1 and 2 are satisfied and a short-circuit fault and a zero-fixed fault or a short-circuit fault and a single-fixed fault can be detected simultaneously for each bit, the test value is comprehensively Can be reduced.

The electronic device according to claim 3 , wherein the plurality of address bus test addresses or the plurality of data bus test values used for detecting the zero stuck fault and the one stuck fault are “a plurality of address bus tests used for detecting a short circuit fault”. Address or any one of a plurality of data bus test values "and" one test value obtained by inverting the 0 value of each bit of the test value to 1 and the 1 value to 0 " Value ".

A fourth aspect of the invention includes the electronic device according to any one of the first to third aspects, a motor driven by the electronic device, and power transmission means for transmitting rotation of the motor to the steering shaft, and assists steering torque. The present invention relates to an electric power steering apparatus.
The electric power steering device is required to detect a failure at an early stage and execute a quick and accurate process from the viewpoint of safety, so that the effect of improving the processing speed by the electronic device of the present invention is effectively exhibited. Is done.

1 is a schematic configuration diagram of an electric power steering device to which an electronic device according to an embodiment of the present invention is applied. 1 is a system diagram of an electronic device according to an embodiment of the present invention. 4 is an address bus abnormality detection flowchart according to an embodiment of the present invention. The data bus abnormality detection flowchart by one Embodiment of this invention. (A) A diagram showing a reference example of a test value when the test target bit is 2 bits, (b) a diagram showing an example of a test value when the test target bit is 4 bits, (c) 8 bits of the test target bit The figure which shows the example of the test value at the time of. The schematic diagram which shows the ROM area | region by one Embodiment of this invention. The figure which shows the example of a test value when a test object bit is 16 bits. The figure which shows the example of a test value when a test object bit is 32 bits. (A) The figure which shows another example of the test value when a test object bit is 4 bits, (b) The figure which shows another example of the test value when a test object bit is 8 bits.

An embodiment in which an electronic device (hereinafter referred to as “ECU”) of the present invention is applied to an electric power steering device for assisting steering operation of an automobile or the like will be described with reference to the drawings.
(One embodiment)
FIG. 1 shows the overall configuration of a steering system provided with an electric power steering device. In the electric power steering apparatus 1 provided in the steering system 90, a torque sensor 94 for detecting a steering torque is installed on a steering shaft 92 connected to a handle 91.
A pinion gear 96 is provided at the tip of the steering shaft 92, and the pinion gear 96 meshes with the rack shaft 97. A pair of wheels 98 are rotatably connected to both ends of the rack shaft 97 via tie rods or the like.

  As a result, when the driver rotates the handle 91, the steering shaft 92 connected to the handle 91 rotates, and the rotational motion of the steering shaft 92 is converted into the linear motion of the rack shaft 97 by the pinion gear 96. The pair of wheels 98 are steered at an angle corresponding to 97 linear motion displacement.

The electric power steering apparatus 1 includes a motor 80 that generates steering assist torque, a reduction gear 89 as a “power transmission unit” that decelerates rotation of the motor 80 and transmits the rotation to the steering shaft 92, and the motor driving apparatus 2. The motor 80 is a three-phase brushless motor, and rotates the reduction gear 89 forward and backward. The motor drive device 2 includes an ECU 10. The motor drive device 2 also includes a rotation angle sensor 85 that detects the rotation angle of the motor 80, the above-described torque sensor 94, and a vehicle speed sensor 95 that detects the vehicle speed.
With this configuration, the electric power steering apparatus 1 generates a steering assist torque for assisting the steering of the handle 91 and transmits the steering assist torque to the steering shaft 92.

FIG. 2 shows a schematic system diagram of the ECU. The ECU 10 includes a microcomputer (hereinafter referred to as “microcomputer”) 11, an input circuit 16, and an output circuit 17.
The microcomputer 11 includes a CPU (Central Processing Unit) 12, a ROM 13, a RAM 14, and an I / O 15. The CPU 12 executes operations such as comparison between the value read from the ROM 13 and the correct value. The ROM area 13a in the ROM 13 stores an address bus check correct value Vt. The data bus inspection area 14d in the RAM 14 is a RAM area arranged at an arbitrary address. When the data bus 22 has N bits, the data bus inspection area 14d is an area of at least (N / 8) bytes.

The I / O 15 exchanges signals with the input circuit 16 and the output circuit 17.
The input circuit 16 inputs signals from various sensors for making the microcomputer 11 control conditions. The output circuit 17 drives the actuator according to the control of the microcomputer 11.
In the present embodiment, the input circuit 16 inputs signals from the rotation angle sensor 85, the torque sensor 94 and the vehicle speed sensor 95 described above, and the output circuit 17 drives the motor 80 in accordance with the control of the microcomputer 11.

The address bus 21 connects the CPU 12 and the ROM 13 and the CPU 12 and the RAM 14 and designates write and read addresses.
The data bus 22 connects the CPU 12 and the ROM 13, and the CPU 12 and the RAM 14, and designates or acquires write and read data.
Each of the address bus 21 and the data bus 22 includes a plurality of bus lines. The number of bus lines is generally 2 ⁿ (4, 8, 16, 32...) And corresponds to the number of addresses or data bits to be transmitted.

  Next, processing executed by the CPU 12 in the ECU 10 according to the embodiment will be described with reference to the flowcharts of FIGS. 3 and 4. In the following description of the flowchart, the symbol S indicates “step”.

FIG. 3 is a flowchart for detecting a failure in the address bus 21.
In S11, a value is read from the ROM area 13a specified by the address bus check address Ad. In S12, a determination value Vj is calculated from the read value. For example, a checksum is calculated, or a CRC is calculated using a generator polynomial. Alternatively, the read value itself by multiplying the read value by 1 may be used as the determination value Vj.
The checksum is preferably used when a failure mode in which the same bit value obtained from different addresses is replaced does not cause a problem for the system.

In S13, the determination value Vj and the address bus check correct value Vt calculated in advance are compared to determine whether or not they match. If YES, it is determined in S14 that the address bus 21 is normal, and if NO, it is determined in S15 that the address bus 21 has failed.
The correct value Vt for the address bus check is a correct value obtained from the ROM value necessary and sufficient for detecting the failure of the address bus 21. The correct answer value Vt is sufficient for detecting the failure of the address bus 21, and need not be prepared for all ROM areas.

  If a failure occurs in the address bus 21, an incorrect address value is read in S 11, and therefore the determination value Vj and the correct value Vt do not match. Therefore, the failure of the address bus 21 can be detected by the flow of FIG.

FIG. 4 is a flowchart for detecting a failure in the data bus 22.
In S21, the data bus inspection value Md is written in the data bus inspection area 14d of the RAM 14. In S22, a value is read from the data bus inspection area 14d. In S23, the read value Mr read in S22 and the inspection value Md written in S21 are compared to determine whether or not they match. If YES, it is determined in S24 that the data bus 22 is normal, and if NO, it is determined in S25 that the data bus 22 has failed.

  When a failure occurs in the data bus 22, data cannot be written or read, so the written value does not match the read value. Therefore, the failure of the data bus 22 can be detected by the flow of FIG.

The present invention is characterized by the selection requirement of the address bus inspection address Ad or the data bus inspection value Md. A plurality of address bus test addresses Ad or data bus test values Md are selected according to the number of bus lines to be tested. The selection of the address bus inspection address Ad in the failure detection of the address bus 21 and the selection of the data bus inspection value Md in the failure detection of the data bus 22 are the same. “Ad or a plurality of data bus inspection values Md” are collectively referred to as “a plurality of inspection values D”.
An object of the present invention is to minimize the number of inspection values D for detecting a failure, reduce the processing load on the ECU 10, and improve the processing speed by selecting a plurality of inspection values D according to characteristic requirements. To do.

Here, three types of bus line failures will be described.
1) 0 stuck fault This is a fault stuck to 0 where the value of the bit corresponding to the bus line should originally be 1. This is equivalent to a ground fault or a disconnection fault when the bit value is 0 when a disconnection occurs.
2) 1 stuck fault This is a fault stuck to 1 where the value of the bit corresponding to the bus line should be 0. This is a power failure or a disconnection failure when the bit value is 1 when the disconnection occurs.
3) Short circuit failure A failure in which the value of a bit corresponding to a bus line is the same as the value of a bit corresponding to another bus line, that is, a failure in which different values cannot be maintained between two bus lines. . A failure due to a short circuit between the bus lines corresponds to this.

The requirements of the inspection value D for detecting these failures are as follows.
1) The value of the bit corresponding to the bus line to be inspected is set to 1 for a 0 fixing failure.
2) The value of the bit corresponding to the bus line to be inspected is set to 0 for one fixing failure.
3) For a short circuit failure, the bit value corresponding to the bus line to be inspected is set to a value different from the bit values corresponding to other bus lines. That is, a combination in which the value of the bit to be inspected is 0 and the value of the other bit is 1 or the value of the bit to be inspected is 1 and the value of the other bit is 0 is constructed for all bits. The number of short-circuit determination combinations is the number of combinations in which two bits are selected from all bits. If the total number of bits is N bits, it is necessary to construct a combination of a plurality of inspection values D as _N C ₂ .

  Hereinafter, a specific example of the inspection value D will be described for each number of bits to be inspected. In the inspection value D of N bits, the least significant bit is represented as the 0th bit, the second digit is represented as the first bit, and the most significant bit is represented as the (N-1) th bit. When a hexadecimal number is expressed, “h” is added to the end. In addition, the example shown below is an example to the last.

(2-bit reference example)
First, FIG. 5A shows an example in which the inspection target bit is 2 bits as a reference example. In this example, the inspection value D itself is 8 bits, but the inspection object bits are only 2 bits of the 0th and 1st bits. By using two of 01h (00000001) and FEh (11111110) as the inspection value D, it is possible to detect the 0 fixing failure and the 1 fixing failure. Further, there are one combination of short circuit determinations between the 0th bit and the 1st bit, and a short circuit failure can be detected by any of 01h and FEh. The number of inspection values is two, and there is no difference from the prior art.

(Example of 4 bits)
FIG. 5B shows an example in which the inspection target bits are 4 bits. In this example, the inspection value D itself is 8 bits, but the inspection object bits are only 4 bits of the 0th to 3rd bits. Three inspection values D, 03h (00000011), 05h (00000101), and FCh (11111100) are used. It is possible to detect a 0-fixation failure and a 1-fixation failure with 03h and FCh. Also, there are ₄ C ₂ = 6 combinations of short circuit determinations, of which 4 are (between the 0th bit and the 2nd bit, between the 0th bit and the 3rd bit, between the 1st bit and the 2nd bit, the 1st bit And the third bit) can be detected at 03h, and the remaining two (between the 0th bit and the first bit and between the second bit and the third bit) can be detected at 05h.

In this case, the number of inspection values D necessary for the short-circuit determination is (log ₂ 4) = 2, and one inspection value also serves to detect one of the 0-fixed failure and the 1-fixed failure. Therefore, by adding another detection value D for detecting the other of the 0-fixed fault and the 1-fixed fault, it becomes possible to detect all three types of faults. Therefore, the number of inspection values D for failure detection is (log ₂ 4) + 1 = 3.

  According to the prior art using a test value “only one of all bits is 1 or 0”, a 4-bit test has a minimum of four test values (for example, 01h (00000001), 02h (00000010), 04h (00000100), 08h (00001000)). This is because short circuit faults of a plurality of bus lines cannot be simultaneously detected for one inspection value. In the present invention, a single inspection value can simultaneously detect a short-circuit failure of a plurality of bus lines, so the number of inspection values can be reduced.

(Example of 8 bits)
An example in which the inspection target bits are 8 bits is shown in FIG. In this example, four values of 0Fh (00001111), 33h (00110011), 55h (01010101), and F0h (11110000) are used as the inspection value D. It is possible to detect 0 fixing failure and 1 fixing failure at 0Fh and F0h. In addition, there are ₈ C ₂ = 28 combinations for short circuit determination, 16 of which can be detected at 0Fh, 8 other than overlapping combinations can be detected at 33h, and the remaining 4 can be detected at 55h. It is.

In this case, the number of inspection values D required for short circuit determination is (log ₂ 8) = 3, and the number of inspection values D for failure detection is (log ₂ 8) + 1 = 4. is there.
According to the prior art, an 8-bit inspection requires a minimum of 8 inspection values, so that the number of inspection values can be reduced by half according to the present invention.

FIG. 6 is a diagram schematically showing the inspection value D, that is, the address bus inspection address Ad in the ROM area 13a in the case where the failure of the address bus 21 is detected. In this example, an address of 8 bits, that is, 1 byte can be stored in the ROM area up to 2 ⁸ = 256 bytes. The ROM area rows correspond to the values of the 0th to 3rd bits, and the ROM area columns correspond to the values of the 4th to 7th bits. In addition, although the four addresses FCh to FFh are shown as the correct value Vt for the address bus check, the arrangement of the correct value Vt for the address bus check is arbitrary.

  By the way, since the address in the vicinity of FFh, which is the maximum value area of the ROM area, may be a prohibited area specific to the device, it is desirable to avoid use as the address Ad for address bus inspection. However, according to the prior art, the value of FEh (11111110) in which only the 0th bit takes a value of 0 has to be used. In the present invention, since the degree of freedom in selecting the address bus inspection address Ad is high, it is easy to avoid an address that is likely to be included in the prohibited area, such as FEh.

(Example of 16 bits)
FIG. 7 shows an example in which the inspection target bits are 16 bits. In this example, five inspection values D of 00FFh, 0F0Fh, 3333h, 5555h, and FF00h (binary notation is omitted) are used. 00FFh and FF00h can detect 0-fixation failure and 1-fixation failure. Moreover, there are ₁₆ C ₂ = 120 combinations for short circuit determination, 64 of which can be detected with 00FFh, 32 with the exception of overlapping combinations can be detected with 0F0Fh, and 16 with the exception of overlapping combinations Can be detected at 3333h, and the remaining 8 patterns can be detected at 5555h.

In this case, the number of inspection values D necessary for short circuit determination is (log ₂ 16) = 4, and the number of inspection values D for failure detection is (log ₂ 16) + 1 = 5. is there.
According to the prior art, 16-bit inspection requires at least 16 inspection values, so that the number of inspection values can be reduced to about 30% according to the present invention.

(32-bit example)
An example in which the inspection target bits are 32 bits is shown in FIG. In this example, six inspection values D of 0000FFFFh, 00FF00FFh, 0F0F0F0Fh, 3333333h, 5555555h, and FFFF0000h (binary notation is omitted) are used. 00FFh and FF00h can detect 0-fixation failure and 1-fixation failure. Also, there are ₃₂ C ₂ = 496 combinations of short circuit determinations, 256 of which can be detected with 0000FFFFh, 128 of which can be detected with 00FF00FFh, and 64 with the exception of overlapping combinations which can be detected with 0F0F0F0Fh. In addition, 32 patterns excluding overlapping combinations can be detected by 33333333h, and the remaining 16 patterns can be detected by 555555555h.

In this case, the number of inspection values D required for short circuit determination is (log ₂ 32) = 5, and the number of inspection values D for failure detection is (log ₂ 32) + 1 = 6. is there.
According to the prior art, a minimum of 32 inspection values are required for the 32-bit inspection, and therefore the number of inspection values can be reduced to 20% or less according to the present invention.

  Thus, in the prior art, the number of inspection values increases in proportion to the number of inspection target bits, whereas in the present invention, the number of inspection values D is obtained by adding a constant 1 to the logarithm of the number of inspection target bits. Therefore, the number of inspection values can be greatly reduced as the number of bits increases. Therefore, it is possible to reduce the processing load on the ECU 10 related to failure detection and improve the processing speed.

  Further, in the prior art, in order to reduce the processing load on the ECU due to an increase in the inspection value, a method for calculating the checksum based on the read value has to be taken. For this reason, a failure cannot be detected when the same bit value obtained from a different address is replaced. On the other hand, in the present invention, the number of inspection values D can be reduced and the processing load on the ECU 10 can be reduced. Accordingly, it is possible to compare the read value with the correct value as it is or calculate the CRC by a generator polynomial within a practical memory capacity range without using a low-reliability method such as checksum. Therefore, more reliable processing can be executed.

  For example, when the ECU 10 is applied to the electric power steering apparatus 1, it is possible to detect a failure at an early stage, execute a quick and accurate process, and realize an electric power steering apparatus with high reliability.

(Example of configuring test values with bit-inverted value pairs)
While the above example is an example of minimizing the number of inspection values D, here another value is created by adding other inspection values to the minimum number of inspection values based on the above example. An example will be described.
In the example shown in FIG. 9A, when the number of bits to be inspected is 4, the FAh (11111010) is added third to the inspection value D in the first embodiment (see FIG. 5B). ing. This FAh is a value obtained by inverting the 0 value of each bit of the second 05h (00000101) to 1 and the 1 value to 0. That is, FAh and 05h are in a pair relationship in which the value of each bit is inverted. Note that the first 03h and the fourth FCh are in a pair relationship in which the value of each bit is inverted.

By doing so, two values of 0 and 1 are equally assigned to each bit by the four test values. For this reason, the number of determinations for a zero-fixed fault and the number of determinations for a single-fixed fault in one process are the same. Therefore, the reliability with respect to the determination error is improved.
Further, when a physical operation is performed in which a current flows through the bus line when the bit value is 1 and no current flows through the bus line when the bit value is 0, the load on each bus line is equalized. Thus, it is possible to suppress bias such as heat generation.

  In the example shown in FIG. 9B, when the number of bits to be inspected is 8 bits, AAh (10101010) is added fourth to the inspection value D in the second embodiment (see FIG. 5C). Fifth, CCh (11001100) is added. AAh is in the relationship of the third 55h (01010101) and the pair in which the value of each bit is inverted, and CCh is in the relationship of the second 33h (00110011) and the pair in which the value of each bit is inverted. In this case, the same effect as described above can be obtained.

  In this example, when the number of bits to be inspected is 4, the number of inspection values is 4, which is the same as the number of inspection values according to the prior art. However, when the number of bits to be inspected is 8 bits, the number of inspection values is 6, which is still reduced compared to 8 in the prior art. Further, as the number of bits to be inspected increases, the number of inspection values can be sufficiently reduced as compared with the prior art even if an inspection value obtained by inverting the value of each bit is added.

(Other embodiments)
(A) In the above embodiment, for the data bus 22, the data bus test value Md is written to the data bus test area 14d of the RAM 14, and the read value Mr and the data bus test value Md read from the data bus test area 14d are written. The failure is detected by comparing
Not only this, but the data bus 22 is also detected in the same way as the address bus 21 by comparing the judgment value calculated from the value read from the ROM area 13a with the data bus check correct value calculated in advance. It may be.

  (B) In addition to the electric power steering device, the electronic device of the present invention can be applied to various applications such as VGRS (gear ratio variable steering) and ARS (active rear steering).

  As mentioned above, this invention is not limited to such embodiment, In the range which does not deviate from the meaning of invention, it can implement with a various form.

1 ... Electric power steering device,
2 ... Motor drive device,
10: ECU (electronic device),
11: Microcomputer,
12 ... CPU,
13 ... ROM,
13a ... ROM area,
14 ... RAM,
14d ... Data bus inspection area,
15 ... I / O,
16 ・ ・ ・ Input circuit,
17... Output circuit,
21 ... Address bus,
22 ・ ・ ・ Data bus,
D: Inspection value,
Ad: Address bus inspection address,
Vj ... judgment value,
Vt ... (for address bus check) correct value,
Md: Data bus inspection value,
Mr: Read value.

Claims (4)

A CPU, a ROM, and an address bus composed of four or more bus lines for connecting the CPU and the ROM and transmitting addresses;
The CPU compares the judgment value calculated from the value read from the ROM area specified by the plurality of address bus test addresses with a pre-calculated correct value for the address bus test, and if the address bus does not match, Judge that it is broken,
The plurality of address bus test addresses include a value of 4 bits or more corresponding to 4 or more bus lines, a value having a value of 0 of 2 bits or more and a value of 1 of 2 bits or more, By determining whether or not the bit corresponding to the bus line to be inspected and the bit corresponding to the bus line other than the inspection target maintain different values, a plurality of bus lines including the bus line to be inspected are determined. Can be detected at the same time,
And, as the plurality of address bus inspection addresses,
Using a value that makes the value of the bit corresponding to the bus line to be inspected as 1, the 0 fixed failure that is a failure fixed to 0 where the value of the bit corresponding to the bus line of the address bus should be originally 1 Is detectable,
Using a value with which the value of the bit corresponding to the bus line to be inspected is 0, a 1 fixed failure, which is a failure that is fixed to 1 where the value of the bit corresponding to the bus line of the address bus is supposed to be 0 Ri detectable der,
The plurality of address bus test addresses used for detecting the short-circuit failure are N-bit values corresponding to N bus lines, and are (N / 2) -bit 0 values and (N / 2) -bits. And (log ₂ N) values having a value of 1, and the number of the plurality of address bus test addresses used for detecting the short-circuit fault is minimized . A CPU, a ROM, and a data bus composed of four or more bus lines for connecting the CPU and the ROM and transmitting data;
The CPU compares the judgment value calculated from the plurality of data bus test values read from the ROM area of the ROM with a pre-calculated correct value for data bus test, and if the data bus fails, the data bus fails. It is determined that
The plurality of data bus test values include a value of 4 bits or more corresponding to four or more bus lines, a value having a value of 0 of 2 bits or more and a value of 1 of 2 bits or more. By determining whether the bit corresponding to the target bus line and the bit corresponding to the bus line other than the inspection target maintain different values from each other, a plurality of bus lines including the inspection target bus line are Short circuit faults can be detected at the same time,
And, as the plurality of data bus inspection values,
Using a value that makes the value of the bit corresponding to the bus line to be inspected as 1, a 0 fixed failure that is a failure fixed to 0 where the value of the bit corresponding to the bus line of the data bus is supposed to be 1 Is detectable,
By using a value in which the value of the bit corresponding to the bus line to be inspected is 0, a 1 fixed failure which is a failure fixed to 1 where the value of the bit corresponding to the bus line of the data bus should be 0 Ri detectable der,
The plurality of data bus check values used for detecting the short-circuit fault are N-bit values corresponding to N bus lines, and are (N / 2) -bit 0 values and (N / 2) -bit values. An electronic apparatus comprising: (log ₂ N) values having a value of 1 and minimizing a number of the plurality of data bus test values used for detecting the short-circuit fault . The electronic device according to claim 1 or 2 ,
The plurality of address bus test addresses or the plurality of data bus test values used for detecting the 0-fixed fault and the 1-fixed fault are:
One of the plurality of address bus test addresses or the plurality of data bus test values used for detecting the short-circuit fault, and the value of 0 of each bit of the test value is set to 1. An electronic apparatus characterized by being one inspection value obtained by inverting a value to zero. The electronic device according to any one of claims 1 to 3 ,
A motor driven by the electronic device;
Power transmission means for transmitting the rotation of the motor to a steering shaft,
An electric power steering device that assists steering torque.

Images