JP5578344B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a configuration for operating a content reference memory (CAM) stably and at high speed without increasing current consumption regardless of variations in temperature and manufacturing process.

  The content reference memory (CAM) has a function of determining whether stored data (reference data) matches given search data in addition to a data read / write function. One entry for storing one reference data word is composed of a plurality of CAM cells, and reference data word bits of search candidates are stored in these CAM cells.

  Each entry is provided with a match line to which corresponding CAM cells are coupled in parallel. If the search data word matches the stored data word of the entry, the corresponding match line is maintained in the precharge state of H data (logical value “1”), and if there is a mismatch, the corresponding match line is L data ( It is driven to the state of logical value “0”. By identifying the voltage level of the match line, it is possible to determine whether data corresponding to the search data is stored.

  Usually, in the content reference memory, one entry is composed of about 40 to 80 bits of CAM cells, and the number of entries is, for example, 64K. A database is constituted by data stored in the plurality of entries. When the data matches in a plurality of entries, for example, the address of the smallest entry is output.

  In a general configuration, the match line is precharged to the power supply voltage VDD (or the ground voltage GND level) during the precharge period. The search data and the reference data word are compared for each entry during a search period in which a match between the stored data and the search data (address key) is detected. When the comparison result indicates a mismatch, the corresponding match line is driven (discharged or charged) to a voltage level different from the precharge voltage by the transistor in the CAM cell. Therefore, when there are n non-matching CAM cells in one entry, for example, one match line is discharged or charged by a current of I_miss × n. Here, the current I_miss is a 1-bit miss current that flows when one CAM cell is in a mismatched state.

  In a recent content reference memory, entries are provided from 256K to 512K or more, and the operating frequency is from 250 MHz to 350 MHz or more. Therefore, there arises a problem that current consumption / power due to the charge / discharge current of the match line is increased. In addition, when such an operating current is large, switching noise is generated, which may adversely affect the circuit operation.

  For example, Patent Document 1 (Japanese Patent Application Laid-Open No. 2007-317342) discloses a configuration that achieves such low current consumption, high speed, and stable operation of the conventional content reference memory (CAM).

  In the configuration disclosed in Patent Document 1, the match line is precharged to a precharge voltage level equal to or lower than an intermediate value between the power supply voltage and the ground voltage. Further, during the search, the voltage of the match line is compared with a reference voltage having a level equal to or lower than the precharge voltage, and a signal indicating the search result is generated based on the comparison result.

JP 2007-317342 A

  In the configuration disclosed in Patent Document 1 described above, the precharge voltage level of the match line is lowered to reduce the match line charge / discharge current, thereby reducing power consumption, and switching noise is generated by reducing the current. Suppress.

  Normally, the match line precharge voltage and the comparison reference voltage for the match line voltage are generated using a power supply circuit provided in the CAM. In the configuration of Patent Document 1 described above, the match line precharge voltage level is a voltage level between 1/2 times and 1/5 times the power supply voltage VDD. However, when a high-speed operation is required so that the operating frequency is 250 MHz to 350 MHz, it is necessary to pass an operating current of 1 mA or more by design value to each power supply circuit. Otherwise, high speed operation cannot be performed, and there is a problem that the match line cannot be sufficiently charged.

  That is, transistor characteristics vary due to process variations in the manufacturing process, and transistor operating characteristics also vary depending on operating temperature conditions. Even on the same wafer, the manufacturing parameters vary depending on the position of the semiconductor chip on the wafer. In particular, when a MOS transistor (insulated gate field effect transistor) is used as a constituent element, the drain current Id varies depending on process variations and operation temperature, and the operation speed varies. In other words, the drain current Id of the MOS transistor decreases and the operation speed decreases under worst finish conditions and high temperature operation conditions of the MOS transistor. Therefore, in order to ensure a normal required operating speed, it is necessary to flow an operating current of at least twice (about 2 mA or more) the design value with a typical finish to each power supply circuit. However, in this case, in the MOS transistor having the best finish condition, the operating current is approximately doubled, and an operating current of about 4 mA flows.

  Due to the miniaturization of wirings or vias and the thinning of wirings in recent processes, the electromigration resistance of wirings has become weak. Therefore, when a MOS transistor with such a best finish condition flows a large operating current, the wiring or via may be destroyed, and the operating current cannot be increased sufficiently. For this reason, the problem that it becomes impossible to speed up a power supply circuit stably arises.

  In addition, when the match line precharge voltage is an internal voltage that is 1/2 to 1/5 times the power supply voltage VDD, a cross-coupled match amplifier is generally used to determine the low potential level. . In such a cross-curl type match amplifier, under the worst finish conditions, the drain current Id of the N-channel MOS transistor of the match amplifier that receives the match line potential at the gate decreases as the match line potential decreases. Cost. In addition, erroneous determination may occur.

  When the match line precharge potential is simply increased, high speed can be realized for the MOS transistor having the worst finish condition with less off-leakage current and less influence on power consumption. However, the MOS transistor under the best finish condition has a problem that the off-leakage current increases and the current consumption increases, which further increases the power consumption.

  In a cross-coupled match amplifier that detects the match line potential, the level of the match line potential is determined using a reference potential. When only one CAM cell is in a disagreement state in one entry, the match line is set to the ground voltage level (using only the search transistor composed of the N channel MOS transistor (insulated gate field effect transistor) of this one CAM cell. VSS) is discharged or charged to the power supply voltage level (VDD). Therefore, when the N-channel MOS transistor for driving the match line is a worst-finished transistor and under high-temperature operation conditions, the match line potential drops below the reference potential, and the match amplifier determines that there is a mismatch. Will be required. In order to speed up the judgment time when there is a mismatch, the reference potential level with respect to the match line potential must be increased, the potential difference between the match line potential and the reference potential level must be reduced, and the match line potential must quickly reach the reference potential. I must.

  On the other hand, when the N channel MOS transistor is in the best finish condition, the match line potential can be discharged quickly. However, when the match line is in the coincidence state, the match line needs to be maintained at the same H level as the precharge potential level (the level at which the match amplifier determines “1”). In this case, under the best finish conditions, the off-leakage current is large, and the corresponding match line potential is lowered in a short period by the N-channel MOS transistors of the plurality of CAM cells connected to the match line of the matching entry. Accordingly, the time (data retention time) during which the match line is maintained at the H level where the match amplifier determines that the match line potential is “1” after the match line precharge is completed before the match amplifier operation is reduced. In this case, it is necessary to reduce the reference potential level with respect to the match line potential, expand the potential difference between the precharge potential of the match line and the match line reference potential, and ensure a sufficient data holding time.

  Therefore, the conditions required for the match line potential and the match line reference potential are contradictory in accordance with the finish conditions of the MOS transistor. The conflicting relationship between the match line precharge potential and the match line reference potential is the same in the case of a circuit configuration in which the match line is precharged to the power supply voltage VDD, and the same problem occurs.

  In the aforementioned Patent Document 1, a configuration is shown in which the amplitude of the match line voltage is reduced and the reference potential is lowered. This configuration includes an intermediate potential generation circuit corresponding to a power supply circuit having a configuration of the present invention described later. As a result, the match line is precharged to an intermediate potential, the match line potential MLMA separated in the match state is driven to the power supply voltage, and the search result is identified as a match. Conversely, in the case of a mismatch, the separated match line potential MLMA is driven to the ground voltage (GND) level, and the search result is identified as a mismatch.

  However, in this Patent Document 1, in the configuration in which the match line potential itself is compared with the match line reference potential, there is nothing about adjustment of the operation speed of each circuit according to variations in transistor manufacturing parameters and operation temperature conditions. Not considered.

  In general, in a semiconductor device, in a test process, which is the final process of the manufacturing process, the operating conditions are tested and the operating conditions (operating current, internal voltage level) are determined by the fuse element program so as to satisfy the optimal operating conditions. The operation timing is adjusted. However, it is difficult to inspect the finish of the process for each semiconductor chip and adjust with the fuse element according to the inspection result. For example, even in the same semiconductor wafer, the transistor finish may be different between the central part and the peripheral part of the semiconductor wafer. If the inspection is performed for each semiconductor chip and the fuse element is programmed for each semiconductor chip, the test time increases. Cost increases. In addition, the operating temperature varies depending on the operating environment and use conditions, and even if the specific temperature conditions are adjusted by the fuse program, the different temperature conditions cannot be handled.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device that operates stably at high speed with low current consumption.

  Another object of the present invention is to provide a semiconductor device capable of performing a search operation stably at high speed with low current consumption regardless of the operation characteristics and operation temperature of a transistor.

  In summary, the semiconductor device according to the present invention is provided with a current monitoring transistor, and according to the drain current flowing through the monitoring transistor, the level of the voltage generated in the device or the operation current of the circuit is adjusted. To do.

  In other words, the semiconductor device according to the first embodiment of the present invention has a memory array having a plurality of entries each storing reference data, arranged corresponding to each entry, and each is provided with reference data of a corresponding entry. A plurality of match amplifiers that transmit a potential corresponding to the match / mismatch with the search data and a match potential of the corresponding entry to a reference potential and output a signal corresponding to the comparison result Including. In each of the plurality of entries, content reference memory cells (CAM cells) arranged in the row direction are provided. Each of the plurality of match lines is arranged corresponding to each entry, and each of the match lines is coupled to the content addressable memory cell of the corresponding entry and is precharged to a predetermined precharge potential.

The semiconductor device according to one embodiment of the present invention further includes a monitor transistor, and generates a signal corresponding to the current flowing through the monitor transistor, and at least one of the precharge voltage and the reference voltage. A power supply circuit for generating a voltage is provided. The monitor transistor is formed on the same semiconductor substrate as the memory cell array. The power supply circuit adjusts the level of the generated voltage in accordance with the output signal of the current monitor circuit.
There is further provided a search line driving circuit that is provided in common to the plurality of entries, generates search data in accordance with external search data from the outside of the apparatus, and transmits the search data to the plurality of entries. The power supply circuit includes a search line power supply voltage generation circuit for generating an operation power supply voltage for the search line drive circuit. The search line power supply voltage generation circuit adjusts the operating current according to the output signal of the current monitor circuit, selectively detects the search line power supply voltage according to the output signal of the level detection circuit, and determines whether the search line power supply voltage is at a predetermined level. And a circuit for generating the search line power supply voltage. The power supply circuit generates a precharge voltage and raises the precharge voltage in accordance with a decrease in the current flowing through the monitor transistor .

  A semiconductor device according to another embodiment of the present invention includes a memory array having a plurality of entries, a plurality of match lines provided corresponding to each entry, and a plurality of match amplifiers provided corresponding to each match line. Including. In each entry, content reference memory cells arranged in the row direction are arranged. Each match line is arranged corresponding to each entry, coupled to the content reference memory cell of the corresponding entry, and precharged to a predetermined precharge potential. Each match amplifier is arranged corresponding to each entry, and compares the match line potential of the corresponding entry with the reference potential, and outputs a signal corresponding to the comparison result.

  The semiconductor device according to another embodiment further includes a current monitoring transistor, and generates a signal corresponding to the current flowing through the monitoring transistor, and at least one of the precharge voltage and the reference voltage. A power supply circuit for generating two voltages; The monitor transistor is formed on the same semiconductor substrate as the memory cell array. The power supply circuit adjusts the operating current amount of the internal circuit in accordance with the output signal of the current monitor circuit.

  In the present invention, the internal operating conditions are adjusted in accordance with the amount of current using the monitoring transistor. Therefore, it is possible to set the optimum operating condition by monitoring the variation of the process parameter and the fluctuation of the operating temperature condition. As a result, the operating conditions can be adjusted for each semiconductor chip, and a semiconductor device that operates at high speed with low current consumption can be realized.

1 schematically shows an entire configuration of a semiconductor device according to the present invention. FIG. FIG. 2 is a diagram showing a configuration of memory cells arranged in the memory array shown in FIG. 1. FIG. 2 is a diagram showing a configuration of a modification example of a memory cell included in the memory array shown in FIG. 1. 1 schematically shows a structure of a main portion of the semiconductor device according to the first embodiment of the invention. FIG. FIG. 5 is a diagram illustrating a configuration of a match amplifier illustrated in FIG. 4. FIG. 6 is a diagram illustrating an example of a configuration of a latch circuit illustrated in FIG. 5. FIG. 6 is a timing chart showing the operation of the configuration shown in FIGS. 4 and 5. It is a figure which shows the level adjustment operation | movement of the match line reference electric potential in Embodiment 1 of this invention. FIG. 5 is a diagram illustrating an example of a configuration of a current monitor circuit illustrated in FIG. 4. FIG. 10 is a diagram showing an operation and a level adjustment operation of the current monitor circuit shown in FIG. 9. FIG. 5 is a diagram showing a configuration of a first modification of the current monitor circuit shown in FIG. 4. FIG. 12 is a timing diagram illustrating an operation of the current monitor circuit illustrated in FIG. 11. FIG. 5 is a diagram illustrating a configuration of a second modification of the current monitor circuit illustrated in FIG. 4. FIG. 5 is a diagram showing a configuration of a third modification of the current monitor circuit shown in FIG. 4. FIG. 5 is a diagram illustrating a configuration of a fourth modification of the current monitor circuit illustrated in FIG. 4. FIG. 6 is a diagram illustrating a configuration of a fifth modification of the current monitor circuit illustrated in FIG. 4. FIG. 10 is a diagram showing a configuration of a sixth modification of the current monitor circuit shown in FIG. 4. It is a figure which shows the operation | movement before tuning of the current monitor circuit shown in FIG. It is a figure which shows the operation | movement after tuning of the current monitor circuit shown in FIG. It is a figure which shows the example of a change of the current monitor circuit shown in FIG. FIG. 21 is a diagram showing an operation before tuning of the current monitor circuit shown in FIG. 20. FIG. 21 is a diagram showing an operation after tuning of the current monitor circuit shown in FIG. 20. FIG. 5 is a diagram schematically showing a configuration of a power supply circuit shown in FIG. 4. FIG. 24 is a diagram showing an output voltage level adjustment operation of the power supply circuit shown in FIG. 23. FIG. 24 is a diagram showing an example of a configuration of a tunable reference potential generation circuit shown in FIG. 23. FIG. 24 is a diagram showing an example of a configuration of a match line reference potential generation circuit shown in FIG. 23. FIG. 24 is a diagram showing a configuration of a first modification of the match line reference potential generation circuit shown in FIG. 23. FIG. 24 is a diagram showing a configuration of a modified example of the power supply circuit shown in FIG. 23. FIG. 29 is a diagram schematically showing a configuration of a reference potential generating circuit with a tuning function shown in FIG. 28. FIG. 30 is a diagram showing a list of tuning conditions of the reference potential generating circuit with a tuning function shown in FIG. 29. FIG. 29 is a diagram schematically showing a configuration of a modification example of the reference potential generating circuit with a tuning function shown in FIG. 28. FIG. 32 is a diagram showing an example of a configuration of a level adjustment buffer shown in FIG. 31. FIG. 5 is a diagram schematically showing a configuration of a power supply circuit for a search line driving circuit of the power supply circuit shown in FIG. 4. FIG. 34 is a diagram schematically showing a configuration of a detector shown in FIG. 33. It is a figure which shows schematically the structure of the principal part of the semiconductor device according to Embodiment 2 of this invention. FIG. 36 is a waveform diagram showing an operation of the circuit shown in FIG. 35. FIG. 36 is a diagram showing an example of a configuration of a delay circuit shown in FIG. 35. FIG. 38 is a waveform diagram showing an operation of the delay circuit shown in FIG. 37. FIG. 36 is a diagram showing an example of a modification of the delay circuit shown in FIG. 35. FIG. 40 is a waveform diagram showing an operation of the delay circuit shown in FIG. 39. It is a figure which shows roughly the structure of the principal part of the semiconductor device according to Embodiment 3 of this invention. It is a figure which shows roughly the example of a change of the principal part of the semiconductor device according to Embodiment 3 of this invention. It is a figure which shows roughly the structure of the modification 2 of the semiconductor device according to Embodiment 3 of this invention. It is a figure which shows schematically the structure of the modification 3 of the principal part of the semiconductor device according to Embodiment 3 of this invention.

[Embodiment 1]
FIG. 1 schematically shows a whole structure of a semiconductor device according to the present invention. In FIG. 1, a semiconductor device (CAM chip) 1 includes a memory array 2 including a plurality of entries ERY. As an example, 256K to 512K entries ERY are provided. In each entry ERY, CAM cells are arranged in the row direction. For example, a 40 to 80-bit CAM cell is arranged in one entry ERY.

  For memory array 2, search line drive circuit 3, address decoder 4 and write / read amplifier circuit 5 are provided. Search line drive circuit 3 receives data DQ supplied from address / data input / output circuit 7 as search data during a search operation, and transmits a search data bit to a search line provided in memory array 2.

  Address decoder 4 generates a signal for selecting an entry in memory array 2 in accordance with address signal ADD from address / data input / output circuit 7. The address decoder 4 selects an entry in the memory array, and writes and reads data to and from the selected entry in the memory array 2. Write / read amplifier circuit 5 writes data to or reads data from an entry designated by address decoder 4. At the time of writing, write data from address / data input / output circuit 7 is transferred to the write amplifier of write / read amplifier circuit 5, and at the time of reading, internal reading from write / read amplifier circuit 5 is performed. Is transferred to the address / data input / output circuit 7 and read out of the apparatus.

  Although the configuration of the match amplifier circuit 6 will be described in detail later, it includes a match amplifier provided corresponding to each entry ERY, and detects the potential of the match line provided for each entry during the search operation. A signal indicating a match / mismatch between the search data and the stored data (reference data) of the entry is generated according to the detection result.

  The operation mode of the search operation and external data writing / reading is specified by the instruction input circuit 8 generating an internal command CMD in accordance with a command (instruction) CMDE for instructing an external operation mode. . An internal command CMD is given to the control circuit 9, and each operation mode is set.

  The control circuit 9 is supplied with the internal clock signal CLK from the clock generation circuit 10, and each operation cycle is defined by the internal clock CLK. The clock generation circuit 10 performs buffer processing and / or frequency division on an external clock signal CLKE to generate an internal clock signal CLK.

  The semiconductor device 1 is further provided with a priority encoder 11 and a search result output circuit 12 unique to the CAM. The priority encoder 11 selects an entry according to a predetermined priority (for example, the minimum address) and designates an entry indicating a match when there are a plurality of entries indicating a match according to the output signal of each match amplifier from the match amplifier circuit 6 An entry address to be generated is generated and a signal indicating a match / mismatch determination result is output. The search result output circuit 12 outputs the match / mismatch result and the entry address from the priority encoder 11 to the outside as a search result SR.

  A power supply circuit 14 is provided for generating a match line precharge potential or the like in the match amplifier circuit 6, and a fuse program circuit 16 for fixedly trimming a voltage level generated by the power supply circuit 14 is provided. In the match amplifier circuit 6, a match line reference potential is generated by a local power supply circuit disposed therein.

  Further, according to the present invention, a current monitor circuit 18 for monitoring the drain current of the monitoring transistor provided therein is provided. The current monitor circuit 18 includes a monitor transistor formed in the same manufacturing process as each transistor (MOS transistor (insulated gate field effect transistor)) in the CAM chip (semiconductor device), and the drain current of the monitor transistor A signal corresponding to (Id) is generated. In the power supply circuit 14 and the match amplifier circuit 6, the level of the generated voltage or the operating current is adjusted according to the monitor signal generated by the current monitor circuit 18.

  Using this current monitor circuit 18, the generated internal voltage level and / or operating current amount are adjusted according to the operating characteristics and temperature conditions of the MOS transistors of the internal components. The operating state can be adjusted according to the finishing conditions such as the worst finishing condition and the best finishing condition of the MOS transistor, and the operating temperature conditions such as high temperature and low temperature operation. Thereby, it is possible to realize a CAM (semiconductor device) that performs a search operation stably at high speed and with low current consumption.

  FIG. 2 is a diagram showing an example of the configuration of the CAM cell included in the memory array 2 shown in FIG. The CAM cell shown in FIG. 2 selectively masks the search operation of the CAM cell in accordance with the mask instruction signal MASK, the storage unit SMC that stores the reference data bits, the search unit SRU that compares the stored data and the search data. Channel MOS transistor NQ7. Mask MOS transistor NQ7 is connected between match line ML and internal node ND3, and receives a mask instruction signal MASK at its gate.

  Storage unit SMC is substantially an SRAM (Static Random Access Memory) cell, and inverters IV1 and IV2 connected in antiparallel and internal nodes ND1 and ND2 are respectively bitd according to the signal potential on word line WL. N channel MOS transistors NQ1 and NQ2 coupled to lines BL and / BL are included. Inverter-connected or cross-coupled inverters IV1 and IV2 form an inverter latch and hold complementary data at nodes ND1 and ND2.

  Search unit SRU includes N channel MOS transistors NQ3 and NQ4 connected in series between node ND3 and the ground node, and N channel MOS transistors NQ5 and NQ6 connected in series between node ND3 and the ground node. . MOS transistor NQ3 has its gate connected to node ND1, and MOS transistor NQ4 has its gate coupled to complementary search line / SL. MOS transistor NQ5 has its gate connected to node ND2, and its gate connected to search line SL. Search data bits complementary to each other are transmitted to search lines SL and / SL.

  N channel MOS transistor NQ7 is rendered non-conductive when mask designation signal MASK is at L level, and separates match line ML and node ND3. Thereby, the search result of the search unit SRU does not affect the match line ML potential, and sets the search data bit to the “don't care” state.

  In the CAM cell shown in FIG. 2, complementary data bits are stored in nodes ND1 and ND2 in storage unit SMC. The logical values of the search data and the storage data are considered based on data bits transmitted via the bit line BL and the search line SL. A data bit transmitted through bit line BL is stored in node ND1 of storage unit SMC, and a data bit transmitted through bit line / BL is stored in node ND2.

  At the time of search when mask instruction signal MASK is set to H level, if the stored data bit of node ND1 and the stored data bit transmitted through search line SL are equal, at least one of MOS transistors NQ3 and NQ4 is in an off state, MOS At least one of transistors NQ5 and NQ6 is turned off. Therefore, match line ML is maintained at the precharge potential level. On the other hand, when the logical values of the data bits transmitted through bit line BL (data bits stored in node ND1) and the search data bits transmitted through search line SL are different, MOS transistors NQ3 and NQ4 are both Either the on state or MOS transistors NQ5 and NQ6 are both on. Therefore, when the search data bit and the stored data bit do not match, the potential of match line ML changes from the precharge potential level. Normally, the precharge potential is higher than the ground potential, as will be described later, and mismatched CAM cells discharge the corresponding match line ML in the direction of the ground potential VSS. Therefore, the CAM cell shown in FIG. 2 is a BCAM cell (binary CAM cell) that performs binary determination of matching and mismatching.

  FIG. 3 is a diagram illustrating a modification example of the CAM cell of the memory array 2. The CAM cell shown in FIG. 3 is not provided with a mask function. In FIG. 3, the CAM cell includes two storage units SMC1 and SMC2, and a search unit SRUT that compares search data with data stored in these storage units SMC1 and SMC2.

  Storage unit SMC1 includes inverters IV3 and IV4 connected in parallel to store complementary data bits, and N channels coupling the input and output nodes of inverter IV3 to bit lines BLn and / BLn, respectively, according to a signal on word line WL0. MOS transistors NQ8 and NQ9 are included. Storage unit SMC2 includes inverters IV5 and IV6 forming an inverter latch, and N channel MOS transistors NQ10 and NQ11 for coupling the input node and the output node of inverter IV5 to bit lines BLn + 1 and / BLn + 1, respectively, according to a signal on word line WL1. Including.

  Each of these storage units SMC1 and SMC2 is composed of SRAM cells, and the storage data can be individually set.

  Search unit SRUT includes N channel MOS transistors NQ12 and 13 connected in series between match line ML and the ground node, and N channel MOS transistors NQ14 and NQ15 connected in series between match line ML and the ground line. Including. MOS transistor NQ12 has its gate coupled to the output node of inverter IV3 (input node of inverter IV4), and MOS transistor NQ13 has its gate coupled to search line SL. The gate of MOS transistor NQ14 is coupled to the output node of inverter IV5 (input node of inverter IV6) of storage unit SMC2, and the gate of MOS transistor 15 is coupled to complementary search line / SL.

  In the CAM cell shown in FIG. 3, the logical values of the data bits stored in storage units SMC1 and SMC2 correspond to the logical values of the data bits transmitted through bit lines BLn and BLn + 1, respectively. When data bits “1” are stored in storage nodes NDT1 and NDT2 of storage units SMC1 and SMC2, respectively, in search unit SRU, MOS transistors NQ12 and NQ14 are always in an off state. Therefore, match line ML is maintained at the precharge potential level regardless of the logical value of the search data bit transmitted through search lines SL and / SL. That is, in this case, the CAM cell always expresses a matching state (don't care state).

  On the other hand, when data bit “0” is stored in storage nodes NDT1 and NDT2 of storage units SMC1 and SMC2, in search unit SRUT, MOS transistors NQ12 and NQ14 are always on. In this case, regardless of the logical value of the search data bit transmitted to search lines SL and / SL, one of the paths of MOS transistors NQ12 and NQ13 and the paths of MOS transistors NQ14 and NQ15 are conducted, and match line ML is discharged. Is done. Accordingly, in this case, the CAM cell always expresses a mismatch state (usually, the always mismatch state is not used).

  On the other hand, when data bits “1” and “0” are stored in storage nodes NDT1 and NDT2 of storage units SMC1 and SMC2, MOS transistor NQ12 is always off, and MOS transistor NQ14 is always on. . In this case, match line ML is discharged when data of H level potential (“1”) is transmitted to search line / SL. That is, when data bits “1” and “0” are stored in storage units SMC1 and SMC2, search unit SRUT discharges match line ML when the search data bit is “0”. Therefore, when data bits “1” and “0” are stored in storage units SMC1 and SMC2, a match state is indicated when search data is “1”, match line ML is held at the precharge potential, and the search data When “0” is “0”, a mismatch state occurs, and the match line ML is discharged.

  Conversely, when “0” and “1” are stored in storage nodes NDT1 and NDT2 of storage units SMC1 and SMC2, respectively, MOS transistor NQ12 is always on and MOS transistor NQ14 is always off. Therefore, match line ML is discharged when a data bit (“1”) of an H level potential is transmitted to search line SL. Therefore, when data bits “0” and “1” are stored in storage units SMC1 and SMC2, a match state is indicated when search data is “0”, match line ML is held at the precharge potential, and the search data When “1” is “1”, a mismatch state occurs, and the match line ML is discharged.

  Therefore, the CAM cell shown in FIG. 3 is a TCAM (Ternary CAM) cell that can realize a “don't care” state in addition to a match state and a mismatch state, and can store a ternary state.

  As the CAM cell, an SRAM cell is used in the configuration shown in FIGS. However, instead of the SRAM cell, a CAM cell may be configured using a DRAM cell or a logic circuit.

  FIG. 4 schematically shows a structure of a main portion of the semiconductor device (CAM) according to the first embodiment of the present invention. In FIG. 4, in the memory array (CM array) 2, a plurality of entries ERY0 to ERYn are provided. In each of the entries ERY0 to ERYn, CAM cells MCC0 to MCCm are arranged in the row direction. As the CAM cells MCC0 to MCCm, either the binary CAM cell shown in FIG. 2 or the ternary CAM cell shown in FIG. 3 may be used.

  Match lines ML0-MLn are provided corresponding to entries ERY0-ERYn, respectively. Each of match lines ML0-MLn is commonly coupled to CAM cells MCC0-MCCm included in corresponding entries ERY0-ERYn.

  Search line pairs SL0, / SL0, SL1, / SL1,... SLm, / SLm are provided for CAM cells aligned in the column direction of entries ERY0 to ERYn. These search line pairs SL0, / SL0-SLm, / SLm are commonly coupled to search units (SRU or SRUT) of CAM cells MCC0-MCCm in the corresponding columns. Therefore, during the search operation, search data from search line drive circuit 3 is transmitted in parallel to entries ERY0-ERYn, and the search operations are performed in parallel in entries ERY0-ERYn.

  In match amplifier circuit 6 shown in FIG. 1, match line potential amplification / latch circuits MAP0 to MAPn are provided corresponding to match lines ML0 to MLn, respectively. These match line potential amplification / latch circuits MAP0 to MAPn have the same configuration, and include a precharge circuit 20 and a match line potential determination circuit 22. The precharge circuit 20 supplies the match line precharge voltage VMPG to the corresponding match lines ML0 to MLn. Although the configuration of match line potential determination circuit 22 will be described in detail later, the potential of corresponding match lines ML0-MLn is compared with a reference potential (not shown), and match line potential determination result signal MLOUT0- MLOUTn is generated. Match line potential determination circuit 22 also includes a latch circuit therein and has a function of latching match line potential determination result signals MLOUT0 to MLOUTn.

  The power supply circuit 14 includes an ML precharge voltage generation circuit 24 that generates a match line precharge voltage VMPG, and an SL power supply voltage generation circuit 26 that generates a high-level voltage when the search line is driven. The match line precharge voltage VMPG generated by the ML precharge voltage generation circuit 24 may be lower than the power supply voltage (VDD) or may be at the power supply voltage VDD level. The voltage generated by the SL power supply voltage generation circuit 26 is at a voltage level higher than the power supply voltage VDD, and a high voltage is transmitted to the search lines SL0, / SL0-SLm, / SLm so that the search portion of the CAM cell can be performed at high speed. Drive with.

  The current monitor circuit 18 includes a MOS transistor formed in the CAM chip as a current monitor transistor, an Id detection circuit 30 that detects a current Id that flows through the monitor MOS transistor, and a monitor current that is detected by the Id detection circuit 30. Id determination circuit 32 for generating a level adjustment signal corresponding to According to the output signal of Id determination circuit 32, the level of match line precharge voltage VMPG generated by ML precharge voltage generation circuit 24 or the operating current and voltage generated by SL power supply voltage generation circuit 26 is adjusted, and SL The operating current of the power supply voltage generation circuit 26 is adjusted. The output signal of the Id determination circuit 32 is also supplied to the match line potential determination circuit 22 and the reference potential level is adjusted.

  The current Id flowing through the monitor transistor reflects the manufacturing condition (finishing condition) and operating temperature condition of the MOS transistor formed in the CAM chip. Therefore, by adjusting the precharge voltage level of the match line to be generated and / or the match line reference potential or adjusting the operating current according to the operating characteristics of the transistors of this CAM chip, the operating speed fluctuation is compensated, The search operation can be performed accurately, quickly and stably with low current consumption.

  FIG. 5 is a diagram showing an example of the configuration of match line potential amplification / latch circuits MAP0 to MAPn shown in FIG. Since match line potential amplification / latch circuits MAP0 to MAPn have the same configuration, FIG. 5 representatively shows the configuration of match line potential amplification / latch circuit MAPi provided for match line MLi.

  In FIG. 5, precharge circuit 20 includes an N-channel MOS transistor NT1 for precharging match line MLi to match line precharge voltage VMPG. This precharge MOS transistor NT1 becomes conductive when the match line precharge enable signal MLPRE is activated (at the H level), and transmits the match line precharge voltage VMPG onto the match line MLi.

  The match line potential determination circuit 22 includes a match line reference potential generation circuit (local power supply circuit) 35, a separation circuit 34, a cross couple type match amplifier 36, and a latch circuit 38 that latches an output signal of the cross couple type match amplifier 36. Including.

  The local power supply circuit (match line reference potential generating circuit) 35 is an N-channel MOS that precharges the capacitive element C1 and the main electrode of the capacitive element C1 to the precharge voltage VMPG (= VML) level according to the match line precharge enable signal MLPRE. Matching transistor NT2, N channel MOS transistor NT3 that selectively couples the main electrode of capacitive element C1 to node ND10 in accordance with reference potential lowering instruction signal REFDOWN, and capacitive element C2 coupled between node ND10 and the ground node N channel MOS transistor NT4 for precharging internal node ND10 to the ground potential level according to line precharge enable signal MLPRE, and capacitive elements C3-Ck are included.

  Capacitance element C2 is coupled between internal node ND10 and the ground node, and capacitance elements C3-Ck are coupled to internal node ND10 via switching MOS transistors NN3-NNk, respectively. These MOS transistors NN3-NNk receive the output signal of the current monitor circuit 18 at their gates and are selectively turned on.

  Match with the main electrode or node ND12 of the capacitive element C1 that has been precharged to the match line precharge voltage VMPG in advance under the condition that the match line precharge enable signal MLPRE is “1” and the separation instruction signal MLI is “1”. The node C2plus grounded by the line precharge enable signal MLPRE is capacitively coupled according to the condition that the match line precharge enable signal MLPRE is “0” and the reference potential lowering instruction signal REFDOWN is “1” immediately before the match line potential determination. The node ND12 is lowered from the match line precharge voltage VMPG by the potential difference and the capacitance difference, and the level of the node ND12 is used as a match line reference potential MLREF for match / mismatch determination.

  Note that the capacitance of the node C2plus is adjusted by the current monitor circuit 18 when the switching MOS transistors NN3-NNk are turned on or off. That is, the current monitor circuit 18 can control the match line reference potential MLREF immediately before the match line potential determination to an optimal value.

  Separation circuit 34 includes an N channel MOS transistor NT5 that couples match line MLi to internal node ND11 in accordance with isolation instruction signal MLI, and an N channel MOS that couples the main electrode of capacitive element C1 to internal node ND12 in accordance with match line isolation instruction signal MLI. Includes transistor NT6. The match line potential MLMA corresponding to the potential on the match line MLi is confined to the internal node ND11, and the reference potential MLREF corresponding to the main electrode potential of the capacitive element C1 is confined in the internal node ND12. At this time, reference potential MLREF is at a level lower than match line precharge voltage VMPG by reference potential lowering instruction signal REFDOWN immediately before confinement according to isolation instruction signal MLI. Next, the cross line type match amplifier 36 differentially amplifies the match line potential MLMA and the match line reference potential MLREF. The match line precharge potential VMPG has a voltage level that is 1/2 to 1/5 times the power supply voltage VDD, and is hereinafter referred to as a match line precharge voltage VML.

  Cross-coupled match amplifier 36 is activated when cross-coupled P-channel MOS transistors PT1 and PT2, cross-coupled N-channel MOS transistors NT8 and NT9, and match line amplification enable signal MAE (when H level). P channel MOS transistor PT3 that couples the source nodes of MOS transistors PT1 and PT2 to the power supply voltage and MOS transistor NT8 and NT9 source nodes are coupled to the ground node in response to activation of match amplifier enable signal MAE. N channel MOS transistor NT10 to be included.

  Cross-couple type match amplifier 36 includes an inverter formed of MOS transistors PT1 and NT8 and an inverter formed of MOS transistors PT2 and NT9, and constitutes a latch type sense amplifier. When MOS transistors PT3 and NT10 are on, cross-coupled match amplifier 36 is activated, and potentials MLMA and MLREF on internal nodes ND11 and ND12 are differentially amplified and latched.

  In the configuration shown in FIG. 5, the match line precharge voltage VMPG (= VML) is capacitively divided by the capacitive elements C1 and C2-Ck of the local power supply circuit (latch line reference potential generation circuit) 35, and the match line precharge voltage is obtained. A reference potential MLREF lower than VMPG (= VML) is generated. As an example, the reference potential MLREF is set to a voltage level 100 mV lower than the match line precharge potential VML as a design value (typical value).

  FIG. 6 is a diagram showing an example of the configuration of latch circuit 38 shown in FIG. 6, latch circuit 38 includes an inverter 43 that inverts match line latch instruction signal MLAT, a tristate inverter buffer 40 that receives voltage MLMA of internal node ND11, and a tristate inverter buffer 42 that receives voltage MLREF of internal node ND12. And an inverter latch 44 that latches the output signal of the tri-state inverter buffer 40. Inverter 43 outputs complementary match line latch instruction signal / MLAT.

  Tristate inverter buffers 40 and 42 are activated when latch instruction signals MLAT and / MLAT are activated, and invert and amplify potentials MLMA and MLREF on internal nodes ND11 and ND12, respectively. Inverter latch 44 inverts and latches the output signal of tristate inverter buffer 40 to generate match line potential determination result signal (search result determination signal) MLOUTi. The reason why the tristate inverter buffer 42 is provided for the reference potential MLREF is to make the loads on the internal nodes ND11 and ND12 equal to each other.

  FIG. 7 is a timing chart showing the search operation of the semiconductor device (CAM) shown in FIGS. The search operation of the semiconductor device shown in FIGS. 4 to 6 will be described below with reference to FIG. The cycle of this search operation is defined according to the external clock signal CLKE (500 MHz to 700 MHz as an example).

  The search operation requires two clock cycles of the external clock signal CLKE. Match line precharge enable signal MLPRE is activated for a half clock cycle period in synchronization with the rising of every other clock cycle of external clock signal CLKE. At time T1, match line precharge enable signal MLPRE is driven to H level. In response, MOS transistors NT1 and NT2 shown in FIG. 5 are turned on. At this time, match line isolation instruction signal MLI is at the H level, and potentials MLMA and MLREF on internal nodes ND11 and ND12 are precharged to the level of precharge voltage VMPG (= VML level). Here, the precharge voltage VMPG is a voltage (= VML) lower than the power supply voltage VDD, and the precharge voltage VML is a voltage whose typical value is in the range of VDD / 2 to VDD / 5.

  When the precharge of the precharge voltage VML level of the main electrode of capacitive element C1 in match line ML and local power supply circuit 35 is completed, then match line pre-sync is synchronized with the fall of external clock signal CLKE at time T2. Charge enable signal MLPRE falls to L level, while search lines SL and / SL are driven to H level and L level in accordance with search data, and a search operation is executed. According to this search result, the potential level of the match line MLi decreases when there is a mismatch (miss). In response to a decrease in potential MLMA of match line MLi, reference potential drop instruction signal REFDOWN is driven to the H level. Accordingly, MOS transistor NT3 shown in FIG. 5 is turned on, and reference potential MLREF on internal node ND12 decreases due to capacitive division of capacitive elements C1 and C2-Ck. Normally, the reference potential MREF is set to a potential level that is about 100 mV, lower than the precharge voltage VML. If the search result is miss, the match line potential MLMA drops from the precharge potential. When the potential difference between potentials MLMA and MLREF is sufficiently secured, at time T3, match line isolation instruction signal MLI is at L level, MOS transistors NT5 and NT6 are turned off, and match line potential MLMA and match line reference potential MLREF are It is held in internal nodes ND11 and ND12. When match line MLi and internal node ND11 are separated by match line isolation instruction signal MLI, reference potential effect instruction signal REFDOWN is driven to the L level, and MOS transistor NT3 is turned off. Thereby, the capacitive element C1 and the capacitive element C2-Ck are separated.

  Next, when the potential levels of internal nodes ND11 and ND12 are stabilized, match amplifier enable signal MAE is activated, cross-coupled match amplifier 36 is activated, and the potentials of internal nodes ND11 and ND12 are differentially amplified. . In this mismatch state (miss), the match line potential MLMA is lower than the match line reference potential MLREF, so that the match line reference potential MLREF on the internal node ND12 is driven to the power supply voltage VDD level. Line potential MLMA is driven to the ground potential level.

  When the amplitude of the output signal of cross-coupled match amplifier 36 is sufficiently increased, match line latch instruction signal MLAT is activated, and latch circuit 38 transmits the output signal of cross-coupled match amplifier 36 to the output node. Latch with. When the search results do not match, search result determination signal MLOUT is driven to L level.

  At time T4, the match amplifier enable signal MAE is deactivated after the latch instruction signal MLAT is deactivated, and the search result determination signal MLOUTi is maintained at the L level by the latch circuit 38.

  Thereafter, match line isolation instruction signal MLI attains an H level, isolation MOS transistors NT5 and NT6 are turned on, and the potential amplified by match amplifier 36 is transmitted to match line MLi and the main electrode node of capacitive element C1.

  When one search cycle is completed and the next search cycle is entered, at time T5, match line precharge enable signal MLPRE is driven to H level again, and match line MLi is set to a predetermined precharge voltage VMPG (= VML) level. The potential MLREF of the main electrode node of the capacitive element C1 also becomes the level of the precharge voltage VMPG (= VML).

  At time T6, match line precharge instruction signal MLPRE is driven to the L level, and search lines SL and / SL are driven according to the search data. When the search result is a match state, the match line MLi is maintained at the precharge potential level. Thereafter, voltage drop instruction signal REFDOWN is driven to H level, MOS transistor NT3 is turned on, and the potential MLREF of main electrode node of capacitive element C1 and internal node ND12 is lowered by capacitive division.

  Thereafter, at time T7, match line isolation instruction signal MLI is driven to the L level, and internal nodes ND11 and ND12 are isolated from match line MLi and the main electrode node of capacitive element C1, respectively. Subsequently, the match amplifier enable signal MAE is activated to cause the cross-couple type match amplifier 36 to perform an amplification operation. Subsequently, the latch instruction signal MLAT is driven to the H level, and the output signal of the match amplifier 36 is latched by the latch circuit 38. In the match state (match), the match line potential MLMA is higher than the match line reference potential MLREF, and the output signal MLOUT from the latch circuit 38 is at the H level of the power supply voltage VDD level.

The above-described series of search operations are repeatedly executed every time search data is given.
When match line precharge potential VMPG is at power supply voltage VDD level, P channel MOS transistors are used in place of precharge transistors NT1 and NT2, and P channel MOS transistors are used in place of isolation transistors NT5 and NT6. It is done. This is for reliably transmitting power supply voltage VDD in accordance with control signals MLPRE and MLI of amplitude power supply voltage level (when precharge instruction signal MLPRE and isolation instruction signal MLI are applied to a P-channel MOS transistor, the logic level is The logical value is the opposite of the logical value shown in FIG.

  FIG. 8 is a diagram showing an adjustment operation of match line reference potential MLREF generated by local power supply circuit 35 based on the output signal of current monitor circuit 18 shown in FIG. At the time of mismatch, the match line ML is discharged from the precharge potential VML toward the ground potential. In this case, the transistor (search transistor) in the search part of the CAM cell has a different drain current to be driven depending on the finishing condition. When the finishing condition of the search transistor is the best condition, the discharge current (drain current) is large, the 1-bit miss current Imiss (b) is large, and the match line ML is discharged at high speed. Here, the 1-bit miss current Imiss (b) or Imiss (w) is a match line ML precharged to the precharge potential VML when the search data is different from the stored data only in the 1-bit CAM cell in one entry. Is discharged to the ground node. Further, Imiss (b) is a 1-bit miss current at the best finish, and Imiss is a 1-bit miss current at the worst finish.

  When a mismatch occurs in a plurality of bits at the time of search, the match line ML precharged to the precharge potential VML in the plurality of CAM cells is discharged to the ground node, so that the potential drop rate of the match line ML is fast. However, when only one bit is mismatched (miss), the match line ML charged to the precharge potential VML only by the 1-bit CAM cell is discharged to the ground node, so the discharge current is small and the potential of the match line ML is low. The descent is slow. In particular, when the search transistor finish condition is the worst condition, the drain current is small, the 1-bit miss current Imiss (w) is the smallest, the discharge current of the match line ML is the smallest, and the potential drop is the slowest. For this reason, it is delayed for the match amplifier to determine that there is a mismatch, which hinders high-speed operation.

  In the match amplifier, the match line potential MLMA and the match line reference potential MLREF are differentially amplified. In this case, there is a minimum value as the difference value ΔVS that can be detected by the match amplifier. Usually, in the final process after the test process, the operation start timing of the match amplifier 36 is fixedly adjusted according to the test result by fuse programming or the like. However, since the timing adjustment is not performed by performing the test individually for all the chips, when the transistor finish condition is the worst condition, the voltage difference value ΔVS is small at the set amplifier operation timing. As indicated by the match line potential MLMA (error), there is a possibility that the match amplifier 36 makes an erroneous determination and determines that the mismatch state is a match state.

  Therefore, in order to accurately determine the search result, a period in which the match amplifier is activated until the time when the difference ΔVS between the match line potential MLMA and the match line reference potential MLREF reaches a predetermined value is assumed in the worst case. Need to slow down. That is, when the search transistor is in the worst finish condition, the 1-bit miss current Imiss (w) is small, the difference value between the match line reference potential MLREF and the match line potential MLMA is small, It is necessary to delay the activation timing. In this case, the operation start timing of the match amplifier 36 is delayed and the search cannot be performed at high speed.

  On the other hand, when the finish condition of the search transistor is the best finish condition, the match line potential MLMA changes quickly due to the miss current Imiss (b). In this case, the voltage difference value ΔVS has a sufficient size, and the match amplifier 36 can accurately perform the sensing operation.

  Therefore, in the first embodiment, when dealing with a state where the search results do not match, the match line reference potential MLREF is increased and the difference value ΔVSC is sufficiently increased in consideration of the worst finish condition. As a result, the activation timing of the match amplifier can be advanced (the match line isolation instruction signal MLI can be activated at an early timing to separate the match amplifier and the match line), and the determination time can be shortened.

  On the other hand, in the match (HIT) state, all the search transistors of the CAM cell of the corresponding entry are off in the match line ML, and the match line ML is discharged by the off-leakage current of the search transistor of the CAM cell of the corresponding entry. Is done. When the search transistor finish condition is the worst finish condition, the off-leakage current Ioff (w) is small and the potential drop of the match line ML is small. On the other hand, when the finish condition of the search transistor is the best finish condition, the off-leakage current Ioff (b) is large and the potential of the match line ML is relatively lowered.

  In the match amplifier 36, the difference between the match line potential MLMA and the match line reference potential MLREF differs according to the finish condition of the search transistor. When the finish condition of the search transistor is the best condition, the difference between the match line reference potential MLREF and the match line potential MLMA becomes small due to the off-leakage current, and the match amplifier makes an erroneous determination as shown by the solid line MLMA (error) in FIG. there is a possibility. In this case, the match amplifier is activated when the time (holding time) for maintaining the match line potential MLMA at the H level indicating the coincidence state is shortened and the match line potential in the disagreement state is not sufficiently expanded. Become.

  Therefore, in the first embodiment, for the mismatch condition (MISS), when the search transistor is in the worst finish condition, the match line reference potential MLREF is increased, and the match line potential MLMA is quickly changed to the match line reference potential. Lower to below MLREF. Thereby, regardless of the finish condition of the search transistor, the difference between the match line potential MLMA and the match line reference potential MLREF can be generated quickly, and the match amplifier can be activated at an early timing.

  Note that when the matching condition is the worst-finished condition of the search transistor, the off-leakage current of the search transistor is small, so that the match line reference potential MLREF falls slowly, and the difference ΔVR between the match line potential MLMA and the match line reference potential MLREF Even if the value is reduced, a sufficient data holding time can be secured.

  For the matching condition (HIT), when the search transistor is in the best finish condition, the match line reference potential is lowered to increase the difference ΔVR between the match line potential MLMA and the match line reference potential MLREF. As a result, even if MLMA falls on the match line due to off-leakage current, the match line potential MLMA is higher than the match line reference potential MLREF, and the data holding time that the match amplifier can determine as a match can be made longer. it can.

  If the search transistor has the best finish condition under the mismatch condition, the search transistor has a large discharge current. Therefore, even if the match line reference potential MLREF is lowered, the match line MLMA is lowered in a short time, and the match line is referenced. Since the potential is lower than MLREF, there is no influence on the operation speed.

  That is, with respect to the matching condition and the mismatching condition, the match line reference potential MLREF is raised in the case of the worst finish condition of the transistor according to the finish condition of the search transistor, and the match line is referenced in the case of the best finish condition. The potential MLREF is decreased. This treatment may be executed only for either one or both conditions.

  As described above, the semiconductor device can be accurately operated at high speed by adjusting the level of each semiconductor device according to the ability of the created transistor.

[Configuration 1 of current monitor circuit]
FIG. 9 is a diagram showing an example of the configuration of current monitor circuit 18 shown in FIGS. 4 and 5. In current monitor circuit 18 shown in FIG. 9, Id detection circuit 30 includes a P-channel MOS transistor PT30 and a resistance element R0 connected in series between a power supply node and an internal output node, and an internal output node and a ground node. And a monitoring N-channel MOS transistor NT30 connected thereto.

  MOS transistor PT30 receives activation signal ENA via inverter IV30 at its gate. MOS transistor NT30 has its gate coupled to the power supply node. The MOS transistor NT30 is used as a monitoring transistor, and a drain current corresponding to variations in manufacturing parameters is passed. In this case, the detection voltage Vidn is generated according to the ratio of the on-resistance of the resistance element R0 and the monitoring MOS transistor NT30.

  This monitoring transistor NT30 is formed in the same manufacturing process as other MOS transistors in the internal circuit in the semiconductor device, and reflects the manufacturing finish conditions of the MOS transistors in the semiconductor chip. Therefore, by detecting the drain current Id flowing through the monitoring transistor NT30, it is possible to detect the finish condition of the transistors in the chip.

  Id determination circuit 32 compares resistance elements RA and RB connected in series between the power supply node and the ground node, reference voltage Vrf from the connection node of resistance elements RA and RB, and output voltage Vidn of Id detection circuit 30. And a comparison circuit 50a.

  Due to the resistance division of the power supply voltage VDD by the resistance elements RA and RB, a voltage of VDD · RB / (RA + RB) is generated as the reference voltage Vrf. The comparison circuit 50a sets the output switching signal SW to L level when the reference voltage Vrf is higher than the detection voltage Vidn, and sets the switching signal SW to H level when the reference voltage Vrf is lower than the detection voltage Vidn. Set.

  FIG. 10 schematically shows a determination operation of the current monitor circuit shown in FIG. The operation of the current monitor circuit shown in FIG. 9 will be described below with reference to FIG.

  Now, it is assumed that the on-resistance of the MOS transistor PT30 is negligible compared to the resistance value of the resistance element R0. In this case, if the drain current flowing through the monitoring transistor NT30 is Id, the detection voltage Vidn is expressed by VDD−Id · R0. The monitoring MOS transistor NT30 reflects the variation state of the manufacturing parameters of the MOS transistor in the CAM chip (semiconductor device). Due to this manufacturing variation, when the MOS transistor is worse than a typical value (design value) and has a worst finish condition, the drain current Id becomes small and the level of the detection voltage Vidn becomes higher than the reference voltage Vrf. In this case, the switching signal SW from the comparison circuit 50a becomes H level.

  Here, the detection voltage Vidn and the reference voltage Vrf are measured using the ground voltage as a reference value. In the following description, voltage and potential are used in the same meaning for voltage level.

  On the other hand, when the finishing condition of the MOS transistor is the best finishing condition, the drain current Id of the monitoring MOS transistor NT30 increases. In this case, the detection voltage Vidn becomes lower than the reference voltage Vrf, and the switching signal SW from the comparison circuit 50a becomes L level. The finished state of the transistor can be identified by the logical value of the switching signal SW.

  As shown in FIG. 5, the match line reference potential MLREF is generated by capacitive division of the capacitive element in the local power supply circuit 35. When the combined capacitance C2plus connected to the internal node ND10 increases, the match line reference potential MLREF decreases. On the other hand, when the combined capacitance C2plus connected to the internal node ND10 decreases, the match line reference potential MLREF increases. Therefore, by selectively turning on or off the MOS transistors NN3 to NN9 shown in FIG. 5 by the switching signal SW from the current monitor circuit 18, the potential level according to the finish condition of the MOS transistor (search transistor) The match line reference potential MLREF can be set to.

  In this case, the temperature dependency of the drain current of the monitoring MOS transistor NT30 is also reflected in the detection voltage Vidn, and the match line reference potential MLREF is set to a potential level according to the finishing condition and / or the operating temperature condition. Can do.

  Note that the level adjustment of the match line reference potential MLREF may be performed by any method of adjusting only the level increase, adjusting only the level decrease, and adjusting both the level increase / decrease.

  The activation signal ENA may be activated in response to power-on, may be maintained in an inactive state during standby, and may be activated during a CAM operation such as a search operation. In this case, activation / deactivation of activation signal ENA is controlled in accordance with a command designating an external operation mode.

[Modification example 1 of current monitor circuit]
FIG. 11 schematically shows a configuration of a modification of the current monitor circuit shown in FIGS. In the current monitor circuit 18 shown in FIG. 11, a P-channel MOS transistor PT31 is used as a monitor transistor in the Id detection circuit 30. Monitor MOS transistor PT31 is connected between the power supply node and the internal output node, and its gate is connected to the power supply node. Resistive element R0 and N channel MOS transistor NT31 are connected in series between the internal output node and the ground node. Activation signal ENA is applied to the gate of MOS transistor NT31.

  The configuration of the Id determination circuit 32 is substantially the same as the configuration of the Id determination circuit 32 shown in FIG. However, comparison circuit 50b receives detection voltage Vidp from Id detection circuit 30 at its negative input, and receives reference voltage Vrf at its positive input.

  FIG. 12 schematically shows a determination operation of current monitor circuit 18 shown in FIG. Hereinafter, the determination operation of the current monitor circuit 18 shown in FIG. 11 will be described with reference to FIG.

  Also in the Id detection circuit 30 shown in FIG. 11, the detection voltage Vidp is determined according to the ON resistance of the MOS transistor PT31 and the resistance value of the resistance element R0. It is assumed that the on-resistance of the MOS transistor NT31 is a value that can be ignored compared to the resistance value of the resistance element R0.

  In the configuration shown in FIG. 11, the detection voltage Vidp is expressed by Id · R0 from the drain current Id flowing through the MOS transistor PT31 and the resistance value R0 of the resistance element R0. On the other hand, the reference voltage Vrf is represented by VDD · RB / (RA + RB). The state where the detection voltage Vidp is higher than the reference voltage Vrf is a state where the drain current Id flowing through the monitoring MOS transistor PT31 is large. In this state, switching signal SW from comparison circuit 50b is set to the L level.

  On the other hand, when the detection voltage Vidp is lower than the reference voltage Vrf, the drain current Id of the monitoring MOS transistor PT31 is small, and the finishing condition is, for example, the worst condition which is worse than the typical condition. In this case, switching signal SW from comparison circuit 50b is set to H level.

  Therefore, the finish condition of the MOS transistor can be identified by the drain current Id flowing through the monitor MOS transistor PT31. Like the current monitor circuit shown in FIG. 9, the best finish condition (good finish condition) and the worst finish condition are obtained. The logic level of the switching signal SW can be switched according to (defective finish condition). As a result, the voltage level of the match line reference voltage MLREF can be adjusted in the capacity division ratio of the match line reference voltage, and the match line reference voltage MLREF corresponding to the finish condition of the MOS transistor (search transistor) is accurately generated. be able to.

  In the configuration of the current monitor circuit 18 shown in FIG. 11 as well, the voltage level can be adjusted only in the direction in which the voltage is increased, only in the direction in which the voltage is decreased, or in both the upward / downward directions. Good. If the switching signal SW shown in FIG. 11 is inverted by an inverter, a switching signal having a logic opposite to the waveform shown in FIG. 12 can be generated. This also applies to the configuration of the current monitor circuit shown in FIG.

[Modification example 2 of current monitor circuit]
FIG. 13 is a diagram illustrating a configuration of a second modification of the current monitor circuit. In the current monitor circuit 18 shown in FIG. 13, the output voltage of the constant current circuit 55 is applied to the MOS transistor PT30 in the Id detection circuit 30. The constant current flowing through the constant current circuit 55 keeps the current flowing through the MOS transistor PT30 constant.

  Constant current circuit 55 is connected in series between resistance element RR coupled to the power supply node, MOS transistors PT41 and NT41 connected in series between resistance element RR and the ground node, and between the power supply node and the ground node. MOS transistors PT40 and NT40. MOS transistors PT40 and PT41 have their gates coupled to internal node ND20, and MOS transistors NT40 and NT41 have their gates connected to each other. N channel MOS transistors NT40 and NT41 form a current mirror circuit having MOS transistor NT41 as a master.

  Constant current circuit 55 further includes N channel MOS transistors NT42 and NT43 connected in series between node ND20 and a ground node, and MOS transistors PT42 and NT44 connected in series between a power supply node and a ground node. . N channel MOS transistors NT42 and NT43 have their gates connected to internal node ND22. P channel MOS transistor PT42 is connected between a power supply node and internal node ND22, and has its gate coupled to a ground node, and operates as a current source transistor. N channel MOS transistor NT44 is connected between internal node ND22 and the ground node, and has its gate connected to the gates of MOS transistors NT40 and NT41. Therefore, the MOS transistor NT44 forms a current mirror circuit with the MOS transistor NT41.

  In Id detection circuit 30, MOS transistors PT30 and NT30 are connected in series between a power supply node and a ground node. P channel MOS transistor PT30 receives the potential of internal node ND20 of constant current circuit 55 at its gate. N channel MOS transistor NT30 has its gate coupled to the power supply node, and operates as a current monitoring transistor.

  Id determination circuit 32 includes resistance elements Ra-Rc connected in series between a power supply node and a ground node, and comparison circuits 50A and 50B that generate switching signals SWA and SWB, respectively. The comparison circuit 50A compares the detection voltage Vidn output from the Id detection circuit 30 with the voltage Vr1 from the connection node between the resistance elements Ra and Rb, and sets the switching signal SWA to H when the detection voltage Vidn is higher than the voltage Vr1. Set to level. Comparison circuit 50B compares detection voltage Vidn with voltage Vr2 from the connection node of resistance elements Rb and Rc, and sets switching signal SWB to H level when voltage Vr2 is higher than detection voltage Vidn.

  In constant current circuit 55, when power is turned on, MOS transistor PT42 is turned on to raise the potential level of internal node ND22. Thereby, MOS transistors NT42 and NT43 are turned on to lower the potential level of internal node ND20. The pull-down operation of MOS transistors NT42 and NT43 prevents the gates of MOS transistors PT40 and PT41 from being pulled up to the power supply voltage level when the power is turned on to prevent the constant current operation from being performed. MOS transistors NT42 and NT43 have a sufficiently small current driving capability.

  After the power is turned on, the voltage level of internal node ND20 increases in accordance with the level increase of power supply voltage VDD. Accordingly, when the drain voltage of MOS transistor NT41 exceeds the threshold voltage of MOS transistors NT40 and NT41, MOS transistors NT40 and NT41 perform a current mirror operation. At this time, the MOS transistor NT44 performs a current mirror operation to discharge the internal node ND22. In this state, MOS transistors NT42 and NT43 only operate in the off state or in a very weak inversion region, and the discharge current can be almost ignored.

  In the constant current operation, MOS transistors NT40 and NT41 form a current mirror circuit, and a mirror current of the current flowing through MOS transistor NT41 flows through MOS transistor NT40. When the current flowing through MOS transistor PT40 becomes larger than the current flowing through MOS transistor NT41, the voltage level of internal node ND20 rises, the gate voltage of MOS transistor PT40 rises, and the source-gate voltage becomes As a result, the amount of current flowing through the MOS transistor PT40 is reduced.

  Further, when the current flowing through MOS transistor PT40 becomes smaller than the current flowing through MOS transistor NT41, the voltage level of node ND20 decreases and the current flowing through MOS transistor PT40 increases. Therefore, due to the feedback operation of MOS transistor PT40, currents of the same magnitude flow through the paths of MOS transistors PT41 and NT41 and MOS transistors PT40 and NT40. In this case, the current value can be set by the resistance value of resistance element RR and the size ratio of MOS transistors PT40 and PT41. This relationship can be derived from the drain current equation when the MOS transistors PT40 and PT41 operate in the saturation region.

  In the Id detection circuit 30, the MOS transistor PT30 constitutes a current mirror circuit with the MOS transistor PT40, and therefore flows the same current as the current flowing through the constant current circuit 55 (when the MOS transistors PT30 and PT40 have the same size). . Therefore, in the Id detection circuit 30, when the on-resistance of the monitoring MOS transistor NT30 varies due to variations in the manufacturing process and varies due to temperature variations, the voltage Vidn indicating the degree of variation can be accurately generated. it can. In the case where the resistance element is used in the Id detection circuit 30 by passing a constant current through the MOS transistor PT30 using the constant current circuit 55 instead of the current / voltage conversion resistance element (R0) shown in FIG. As compared with the above, the layout area of the circuit can be reduced.

  The resistance ratio of the resistance elements Ra and Rb is set so that the Id determination circuit 32 generates the reference potentials Vr1 and Vr2 according to the level of the detection voltage Vidn according to the finishing condition of the monitor MOS transistor.

  The comparison circuit 50a sets the switching signal SWA to the H level when the detection voltage Vidn is higher than the reference voltage Vr1. The comparison circuit 50B sets the switching signal SWB to the H level when the detection voltage Vidn is lower than the reference voltage Vr2. Therefore, when the detection voltage Vidn is higher than the reference voltage Vr1, the logical values of the switching signals SWA and SWB can be set according to the state between the reference voltages Vr1 and Vr2 and the state lower than the reference voltage Vr2. And finer adjustments can be made.

  When the power supply monitor circuit 18 shown in FIG. 13 is used, a constant current is passed through the monitor transistor, so that variations in manufacturing parameters and the influence of temperature can be accurately detected.

  In this current monitor circuit 18, a configuration using a P-channel MOS transistor as the monitoring MOS transistor may be used. In this case, the resistor R0 shown in FIG. 11 is removed, the drain of the enable MOS transistor NT31 is connected to the node that outputs the detection voltage Vidp, and the enable MOS transistor NT31 is replaced with a current limiting N-channel MOS transistor. Thus, the gate is coupled to the gates of MOS transistors NT40 and NT41 of constant current circuit 55 shown in FIG.

[Modification example 3 of current monitor circuit]
FIG. 14 schematically shows a configuration of a third modification of current monitor circuit 18 shown in FIG. In current monitoring circuit 18 shown in FIG. 14, variable resistance circuit 58 whose resistance value can be tuned is provided between monitoring N-channel MOS transistor NT30 and activation P-channel MOS transistor PT30. The variable resistance circuit 58 includes a resistance element ZRn-ZR1 connected in series between the resistance element ZRm and the N-channel MOS transistor NT30, and a CMOS transmission gate TXn-TX1 connected in parallel to each of these resistance elements ZRn-ZR1. including.

  In order to control the conduction of each of the CMOS transmission gates TX1 to TXn of the variable resistance circuit 58, a tuning signal TUn-TU1 is generated by blowing / non-blowing of the fuses FZn-FZ1 included in the fuse program circuit 16. In the fuse program circuit 16, resistance elements FRn-FR1 are provided in series with the fuse elements FZn-FZ1, respectively. When the fuse element FZi is blown, the corresponding tuning signal TUi is H level, and when the fuse element FZi is not blown, the corresponding tuning signal TUi is L level.

  The other configuration of the Id detection circuit 30 is the same as the configuration of the Id detection circuit 30 shown in FIG. 9, and the configuration of the Id determination circuit 32 is the same as the configuration of the Id determination circuit shown in FIG. Parts are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the tuning function variable resistance circuit 58, when the tuning signal TUi is at the H level, the corresponding CMOS transmission gate TXi is turned on, and the corresponding resistance element ZRi is short-circuited. On the other hand, when tuning signal TUi is at L level, corresponding CMOS transmission gate TXi is in an off state, and the resistance value of corresponding resistance element ZRi is valid. Therefore, the resistance value of the variable resistor circuit 58 with a tuning function can be adjusted by selectively setting the tuning signal TUn-TU1 to the H level. Resistive elements also have finished variations, and this variation in resistance values hinders accurate detection of the finished conditions of MOS transistors in a current monitor circuit that uses the resistive elements. However, with this variable resistance configuration, the resistance value of the resistance element (R0) that gives the ratio to the on-resistance of the monitoring transistor NT30 can be set accurately, and the change in the on-resistance of the monitoring MOS transistor NT30 is monitored. Therefore, it is possible to accurately generate the detection voltage Vidn at a level corresponding to parameter variation or temperature variation.

  Also in the configuration of current monitor circuit 18 shown in FIG. 14, a configuration using a P-channel MOS transistor as a current monitor transistor may be used. In this case, the fuse program circuit 16 is added in place of the resistance element R0 shown in FIG. 11 in place of the resistance element ZRm shown in FIG. 14 and the variable resistance circuit 58 with a tuning function.

[Modification example 4 of current monitor circuit]
FIG. 15 is a diagram schematically showing a configuration of a fourth modification of the current monitor circuit 18. In FIG. 15, the Id detection circuit 30 of the current monitor circuit 18 has the same configuration as that of the Id detection circuit shown in FIG. 9, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  In Id determination circuit 32, a plurality of resistance elements RAm-RA0 and RBn-RB0 and RC are connected in series between the power supply node and the ground. Comparison circuits 50Am-50A0 are provided for the respective resistance elements RAm-RA0, and comparison circuits 50Bn-50B0 are provided corresponding to the respective resistance elements RBn-RB0.

  Each of comparison circuits 50Am-50A0 receives output voltage Vidn of Id conversion circuit 30 at the positive input, and receives the voltage of the lower node of the corresponding resistance element at the negative input. On the other hand, in comparison circuits 50Bn-50B0, contrary to comparison circuits 50Am-50A0, negative input receives detection voltage Vidn and positive input receives the voltage of the lower node of the corresponding resistive element. The comparison circuit 50Ai (i = 0−m) sets the corresponding switching signal SWAi to the H level when the positive input potential is higher than the negative input potential. Similarly, the comparison circuit 50Bj (j = 0-n) sets the corresponding switching signal SWBj to the H level when the positive input potential is higher than the negative input potential.

  Comparison circuits 50Am-50A0 output switching signals SWAm-SWA0, respectively, and comparison circuits 50Bn-50B0 output switching signals SWA0-SWB0, respectively. By using these switching signals SWAm-SWA0 and SWBn-SWB0 for controlling on / off of MOS transistors NN3-NNk provided for the capacitive elements C3-Ck of the local power supply circuit 35 shown in FIG. The value of the composite capacitor C2plus can be adjusted accurately, and the match line reference potential MLREF can be adjusted.

  By generating a plurality of switching signals, the internal environment (match line reference potential MLREF or the like) can be adjusted more accurately according to the amount of current flowing through the monitoring MOS transistor NT30. In particular, it becomes possible to adjust the operating current and voltage level as described later more precisely.

  Further, these switching signals SWAm-SWA0 can be used as control signals for increasing current or voltage, and switching signals SWBn-SWB0 can be used as switching signals for decreasing current or voltage level.

  Therefore, by generating a plurality of switching signals, the internal operating environment can be precisely adjusted according to the magnitude of the drain current of the monitoring MOS transistor NT30.

[Modification example 5 of current monitor circuit]
FIG. 16 is a diagram schematically showing a configuration of a fifth modification of the current monitor circuit 18. In the current monitor circuit 18 shown in FIG. 16, the Id detection circuit 30 uses a monitoring P-channel MOS transistor PT31. In Id determination circuit 32, similarly to the configuration of Id determination circuit 32 shown in FIG. 15, resistance elements RAm-RA0, RBn-RB0 and RC are connected in series between the power supply node and the ground node. Comparison circuits 50Cm-50C0 and 50Dn-50D0 are provided corresponding to resistance elements RAm-RA0 and RBn-RB0. Comparison circuits 50Cm-50C0 receive the converted voltage Vidp from Id detection circuit 30 at the negative input, and receive the voltage of the lower node of the resistance element corresponding to the positive input. Comparison circuits 50Dn-50D0 receive conversion voltage Vidp at the positive input and receive the voltage of the lower node of the resistance element corresponding to the negative input. Comparison circuits 50Cm-50C0 output switching signals SWAm-SWA0, respectively, and comparison circuits 50Dn-50D0 output switching signals SWBn-SWB0, respectively. These comparison circuits set the switching signal output when the positive input potential is higher than the negative input potential to the H level.

  In the configuration of the current monitor circuit 18 shown in FIG. 16, a monitoring P-channel MOS transistor PT31 is used in the Id detection circuit 30. Therefore, the logic of switching signals SWAm-SWA0 and SWBn-SWB0 output from comparison circuits 50Cm-50C0 and 50Dn-50D0 is the same as the logic of the switching signal of current monitor circuit 18 shown in FIG. Even if the configuration shown in FIG. 16 is used, the voltage / current can be finely adjusted in the same manner as the current monitor circuit shown in FIG.

[Modification Example 6 of Current Monitor Circuit]
FIG. 17 is a diagram schematically showing a configuration of a sixth modification of the current monitor circuit 18. In the current monitor circuit 18 shown in FIG. 17, in the Id detection circuit 30, a variable resistance element 60 is provided between the activation P-channel MOS transistor PT30 and the internal output node. N channel MOS transistor NT30 having its gate receiving power supply voltage VDD is provided between the internal output node and the ground node. Variable resistance element 60 has a configuration similar to that of the variable resistance circuit shown in FIG. 14, and its resistance value is tuned according to a program tuning signal from a fuse program circuit (not shown).

  In the Id determination circuit 32, a temperature reference potential generation circuit 62 that generates a temperature reference potential and a comparison circuit 50E0-50E3 that compares the output potential of the temperature reference potential generation circuit with the level of the output voltage Vidnt of the Id detection circuit 30 are provided. Provided. Temperature reference potential generating circuit 62 includes resistance elements RR4-RR0 connected in series between a power supply node and a ground node. Reference potentials T120, T100, T80, and T60 are generated from the connection node of resistance elements RR4-RR0. These reference potentials T120, T100, T80, and T60 are reference potentials corresponding to temperatures of 120 ° C., 100 ° C., 80 ° C., and 60 ° C., respectively. The temperature to be detected can be arbitrarily set according to the resistance ratio of the resistance elements RR0 to RR4 and the like.

  Comparison circuits 50E0-50E3 each receive detection voltage Vidnt at the positive input, and receive corresponding temperature reference potentials T120-T60 at the negative input. These comparison circuits 50E0-50E3 output switching signals SW120, SW100, SW80 and SW60, respectively.

  18 is a diagram showing the relationship between the detection voltage Vidnt and the temperature before tuning the resistance value of the variable resistance element 60 of the current monitor circuit shown in FIG. In FIG. 18, the vertical axis represents the detection voltage Vidnt, and the horizontal axis represents the temperature Tj.

  When the finish condition of the transistor in the CAM chip is the worst finish condition, the drain current Id of the detection MOS transistor NT30 is smaller than that of the typical (typical finish) condition, the on-resistance is increased, and the detection voltage Vidnt is increased. On the other hand, when the finish condition is the best finish condition, the drain current Id is larger and the detection voltage Vidnt is lower than the typical condition.

  In the MOS transistor, as indicated by straight lines I, II and III in FIG. 18, as the temperature Tj rises, the on-resistance increases and the level of the detection voltage Vidnt increases (the on-resistance of the MOS transistor is positive). (Because it has temperature dependence) Over the entire temperature range, the level of the detection voltage Vidn varies depending on the finishing conditions.

  The upper limit value of the specification operating temperature is normally defined as 130 ° C. Note the temperature of 80 ° C., which is intermediate between the operating temperatures specified in the specification. In accordance with a fuse program of a fuse program circuit (not shown), the resistance value is set according to the finishing condition so that the resistance value of the variable resistance element 60 becomes the same value at 80 ° C. regardless of the finishing condition. In this case, as shown in FIG. 19, the temperature dependency of the detection voltage Vidnt is equal for each of the worst finish condition, the best finish condition, and the typical finish condition close to the design value.

  In current monitor circuit 18 shown in FIG. 17, switching signals SW120, SW100, SW80, and SW60 from comparison circuits 50E0-50E3 are at the H level when detected voltage Vidnt is higher than the corresponding temperature reference potential T120-T60. . Thereby, the temperature inside the CAM chip can be detected. As shown in FIG. 17, by adjusting the voltage level (or current value described later) according to the internal operating temperature in accordance with switching signals SW120, SW100, SW80, and SW60 output from comparison circuits 50F0-50F3. The search operation can be performed accurately and at high speed over the entire temperature range.

  Note that the level adjustment according to the detected temperature and the level adjustment according to the finished condition of the transistor may be used individually or in combination.

[Example 7 of changing current monitor circuit]
FIG. 20 is a diagram schematically showing a configuration of a seventh modification of the current monitor circuit 18. The current monitor circuit 18 shown in FIG. 20 uses the current monitor circuit shown in FIG. 17 and a P-channel MOS transistor PT31 as a current monitor transistor in the following points. More specifically, monitoring P channel MOS transistor PT31 is connected between the power supply node and the internal output node, and variable resistance element 64 and N channel MOS transistor NT31 are connected in series between the internal output node and the ground node. The variable resistance element 64 can be tuned by a fuse program circuit (not shown).

  In the Id determination circuit 32, the comparison circuits 50F0 to 50F3 respectively receive the detection voltage Vidpt from the Id detection circuit at the negative input, and temperature reference potentials T60 and T80 from the temperature reference potential generation circuit 62 at the positive input, respectively. , T100 and T120. Comparison signals 50F0-50F3 output switching signals SW60, SW80, SW100, and SW120, respectively.

  That is, in current monitor circuit 18 shown in FIG. 20, switching signals SW60, SW80, SW100 and SW120 are generated based on the temperature dependence of the drain current of P-channel MOS transistor PT31.

  The P-channel MOS transistor PT31 also has a positive dependency on resistance, and the drain current decreases as the temperature increases. Therefore, as shown in FIG. 21, before the tuning of the resistance value of the variable resistance element 64, when the finish condition of the transistor of the CAM chip is the best finish condition, the typical (typical) finish condition, and the worst finish condition, As the temperature Tj increases, the voltage level of the detection voltage Vidpt decreases. The detection voltage Vidpt has the lowest drain current in the worst finish conditions, the detection voltage Vidpt is low, and in the best finish conditions, the drain current of the MOS transistor PT31 is large, and the voltage level of the detection voltage Vidpt is the highest.

  In this state, the resistance value of the variable resistance element 64 is adjusted so as to match in all finishing conditions at a temperature of 80 ° C., for example. The reason for paying attention to the temperature of 80 ° C. is the same reason as the adjustment of the current monitor circuit shown in FIG.

  After tuning of the resistance value of the variable resistance element 64, as shown in FIG. 22, the temperature dependence of the detection voltage Vidpt becomes equal regardless of the finishing condition. Therefore, for example, by matching the level of the detection voltage Vidp at a temperature of 80 ° C., the operating temperature in the CAM chip can be detected. Thus, as shown in FIG. 20, the voltage level (or current amount described later) is adjusted according to the internal operating temperature in accordance with switching signals SW60, SW80, SW100 and SW120 output from comparison circuits 50F0-50F3. Thus, the search operation and the like can be performed accurately and at high speed over the entire temperature range.

  Any of the configurations of the current monitor circuit described so far may be used. Further, any of level adjustment by temperature detection, level adjustment by finishing conditions, and level adjustment by both may be performed. By monitoring the drain current of the monitoring MOS transistor and adjusting the internal operating environment according to the detection potential corresponding to the amount of drain current, the operating conditions can be accurately set for each chip, and the low current consumption Operation and high-speed operation can be realized.

[Configuration of Match Line Precharge Voltage Generation Circuit]
FIG. 23 schematically shows an example of a circuit configuration for generating match line precharge voltage (reference potential) VML. This match line precharge voltage generation circuit is included in power supply circuit 14 shown in FIG. In FIG. 23, a circuit for generating match line precharge voltage (reference potential) VML generates a tunable reference potential generation circuit 66 for generating reference potential Vtur, and generates match line precharge potential VML in accordance with tunable reference potential Vtur. Match line reference potential generating circuit 68 is included.

  The tunable reference potential generation circuit 66 fixedly adjusts the potential level of the reference potential Vtur according to the program signal from the local fuse program circuit 16M included in the fuse program circuit 16.

  Match line reference potential generating circuit 68 adjusts the level of match line precharge potential VML in accordance with switching signals SWI and SWD from monitor circuit 18M included in current monitor circuit 18. The level of the match line precharge voltage VML is in the range of 1/2 to 1/5 times the power supply voltage VDD.

  As the current monitor circuit 18M, any of the configurations of the current monitor circuit described above may be used as long as it generates the level increase switching signal SWI and the level decrease switching signal SWD.

  FIG. 24 schematically shows a level adjustment operation of match line precharge voltage VML in the circuit shown in FIG. Hereinafter, with reference to FIG. 23, the adjustment operation of match line precharge potential VML shown in FIG. 23 will be described.

  At the time of mismatch (MISS), the match line is discharged, and the match line potential MLMA gradually decreases. In this case, the 1-bit miss current Imiss, which is the discharge current of only the 1-bit CAM cell (the minimum discharge current when the search data and the stored data differ by only 1 bit), differs depending on the transistor finishing conditions or the operating temperature. The match line potential MLMA is lower than the hatch line reference potential MLREF due to a miss current, and a potential difference ΔV is generated. This potential difference ΔV is amplified by a cross-couple type match amplifier.

  When the finish condition of the transistor of the CAM chip is the worst condition and the 1-bit miss current Imiss (w) is small, the finish condition of the cross-coupled match amplifier transistor is also poor and the drain current (Id) is small. If the potential difference ΔV is small in the cross-coupled match amplifier, the sensing operation cannot be performed at high speed.

  At this time, match line precharge potential VML is raised, and match line reference potential MLREF is raised accordingly (match line reference potential MLREF is given by capacitive division of match line precharge voltage VML). Even when the match line precharge potential VML is raised and the potential difference ΔV between the match line potential MLMA and the match line reference potential MLREF is small, the drain current of the N-channel MOS transistor that receives these potentials at the gate in the cross-coupled match amplifier ( Id) increases, and a search result determination signal can be generated by performing a sensing operation at high speed and with high sensitivity.

  At the time of coincidence (HIT), match line ML is maintained at precharge potential VML level. At this time, the match line ML is discharged by the off-leakage current Ioff of the search transistor of the CAM cell, and the match line potential MLMA is lowered. Therefore, when the finishing condition is the best, the off-leakage current Ioff (b) increases and the current consumption increases.

  At this time, the match line precharge potential VML is lowered to reduce power consumption due to off-leakage current. In the case of this adjustment, although the match line precharge potential MLREF is lowered according to the cross-coupled match amplifier, the transistor is in the best finish condition and can drive a large drain current. A sense amplification operation can be performed.

  The match line reference potential MLREF is generated from the match line precharge voltage VML by capacitive division of the capacitive element. By adjusting the capacitance division ratio according to the output signal of the current monitor circuit, it is possible to prevent malfunction (false determination) of the match amplifier.

  Even if this finish condition is a typical condition, the drain current (Id) decreases when the temperature rises, so that a state similar to the worst condition occurs, and the drain current increases when the temperature drops. A state similar to the finishing condition occurs. Therefore, the same adjustment operation is performed according to the temperature to adjust the potential at the time of precharging the match line potential MLMA. The configuration of each part of the circuit shown in FIG. 23 will be described below.

  FIG. 25 shows an example of the configuration of local fuse program circuit 16M and tunable reference potential generation circuit 66 shown in FIG. In FIG. 25, local fuse program circuit 16M is provided exclusively for programming match line precharge potential VML in fuse program circuit 16, and one end is connected to each of power supply nodes, and resistance elements RM0-RM3 and their resistances are connected. Fuse elements FM0-FM3 connected between elements RM0-RM3 and the ground node are included. Tuning signals TUNE <0> -TUNE <3> are generated in accordance with the fusing / non-blown state of fuse elements FM0-FM3. Tuning signals TUNE <0> -TUNE <3> are set to the H level when the corresponding fuse elements FM0 to FM3 are in the blown state, and are set to the L level when the corresponding fuse elements FM0-FM3 are in the blown state.

  Tunable reference potential generating circuit 66 includes an activated P-channel MOS transistor PT40 whose source is connected to the power supply node, and resistance elements R10-R1 connected in series between MOS transistor PT40 and the ground node. Resistance elements R10-R6 are connected in series between MOS transistor PT40 and output node ND40, and resistance elements R5-R1 are connected in series between output node ND40 and the ground node. Resistance elements R3, R4, and R5 have resistance values that are 1/2 times, 1/4 times, and 1/8 times the resistance value of resistance element R2. Resistance elements R6-R9 have resistance values that are 1/8 times, 1/4 times, 1/2 times, and 1/1 times the resistance value of resistance element R2, respectively. That is, resistance elements having the same resistance value with respect to internal output node ND40 are arranged symmetrically.

  In parallel with resistance elements R2-R9, CMOS transmission gates TM2-TM9 are provided, and buffers BF2-BF5 and inverters VF6-VF9 are provided corresponding to CMOS transmission gates TM2-TM9, respectively. Buffer BF5 and inverter VF6 receive tuning signal TUNE <0>, and buffer BF4 and inverter VF7 receive tuning signal TUNE <1>. Buffer BF3 and inverter VF8 receive tuning signal TUNE <2>, and buffer BF2 and inverter VF9 receive tuning signal TUNE <3>.

  CMOS transmission gates TM5-TM2 and TM6-TM9 are complementarily turned on by buffers BF2-BF5 and inverters VF6-VF9. For example, when tuning signal TUNE <0> is at the H level, CMOS transmission gate TM5 is turned on and CMOS transmission gate TM6 is turned off.

The resistance elements R2-R9 are short-circuited when the corresponding transmission gates TM2-TM9 are in the ON state, and the resistance value becomes invalid. The tuning reference potential Vtur can be washed without the following equation:
Vtur = VDD · (sum of effective resistance values of resistance elements R1-R5) / (sum of effective resistance values of resistance elements R1-R10)
Here, the effective resistance value is the resistance value of the resistance element in which the corresponding transmission gate is non-conductive.

  In the fuse program circuit 16M, after the test process of the final manufacturing process is completed, the fuse element FM-FM3 is programmed to be blown / not blown so that the voltage level corresponds to the optimum value (design value).

  FIG. 26 is a diagram showing an example of the configuration of the match line reference potential generating circuit 68 shown in FIG. 23, and shows the configuration of a so-called PMOS driver type VDC. In FIG. 26, a match line reference potential generation circuit 68 includes a level shifter 72 for level shifting the tuning reference potential Vtur from the tunable reference potential generation circuit 66, a level shifter 73 for level shifting the match line precharge potential VML, and the level shifter. Error amplifier 70 that compares the output voltages of 72 and 73, and a drive P-channel MOS transistor 74 that outputs the level of match line precharge voltage VML in accordance with the output signal of error amplifier 70 are included.

  Level shifter 72 includes P channel MOS transistors PQ40 and PQ41 connected in series between a power supply node and a ground node. P-channel MOS transistor PQ40 receives a ground voltage at its gate and operates as a resistance element. The MOS transistor PQ41 receives the tuning reference potential Vtur at its gate, operates in the source follower mode, shifts the gate potential by the absolute value (Vthp) of the threshold voltage, and generates a reference potential after level adjustment.

  Level shifter 73 similarly includes P channel MOS transistors PQ42 and Q43 connected in series between a power supply node and a ground node. MOS transistor PQ42 operates in a resistance mode with its gate connected to the ground node. MOS transistor PQ43 receives match line base precharge voltage VML at its gate, and outputs a level shifted by the absolute value (Vthp) of the threshold voltage. The level shifters 72 and 73 raise the tuning reference potential Vtur and the match line precharge voltage VML to a level that can be detected by the error amplifier 70, thereby operating the error amplifier 70. Thereby, for example, even when the match line precharge voltage VML is a low potential of 0.5 V to 0.25 V, for example, the amplification operation can be performed stably.

  Error amplifier 70 includes a P-channel MOS transistor PQ40 connected between a power supply node and internal node ND42, P-channel MOS transistors PQA10-PQA1m whose gates and drains are connected to internal node ND42, and these MOS transistors PQA10, respectively. -P channel MOS transistors PQA00 to PQA0m connected in series with PQA1m. MOS transistors PQA00 to PQA0m receive decrement switching signals SWD0 to SWDm through inverters IVA0 to IVAm, respectively.

  Decrement switching signals SWD0 to SWDm correspond to switching signals SWA0 to SWAm generated from the current monitor circuit shown in FIG. When the drain current of the monitoring MOS transistor is large in the current monitor circuit 18, the decrement switching signals SWD0 to SWDm can be selectively set to “1” to lower the level of the match line precharge voltage VML.

  Error amplifier 70 further includes a P-channel MOS transistor PQ41 connected between the power supply node and internal node ND44, P-channel MOS transistors PQB10-PQB1m whose gates and drains are interconnected, and these MOS transistors PQB10-PQB1m. P channel MOS transistors PQB00-PQB0m connected in series with power supply nodes are included.

  MOS transistors PQB00-PQB0m receive incremental switching signals SWI0-SWIm applied through inverters IVB0-IVBm at their gates. Incremental switching signals SWI0-SWIm correspond to switching signals SWB0-SWBn output from the current monitor circuit shown in FIG. When the drain current (Id) of the monitoring MOS transistor in the current monitor circuit 18 is small, the incremental switching signals SWI0-SWIn are selectively set to “1” in accordance with the drain current amount, so that the match line pre- The level of charge voltage VML can be raised.

  Error amplifier 70 further includes N channel MOS transistor NQ40 connected between the common source and internal node ND42, MOS transistor N channel MOS transistors NQA00-NQA0m and NQA10-NQA1m connected in series with each other, N-channel MOS transistors NQ41 and NQB0-NQBm and NQB10-NQB1m provided between the internal node ND44 and N-channel MOS transistors NTA0-NTA2 for adjusting operating current. N channel MOS transistors NQ41 and NQB0-NQBm and NQB10-NQB1m are connected in series with each other.

  MOS transistors NQ40 and NQA10-NQA1m each receive an output voltage of level shifter 72 at its gate, and its drain is connected to internal node ND42. MOS transistors NQA00 to NQA0m are connected in series with MOS transistors NQA10 to NQA1m and receive incremental switching signals SWI0 to WSIm at their gates.

  MOS transistors NQB10-NQB1m have their drains connected to internal node ND44 and receive the output voltage of level shifter 73 at their gates. MOS transistors NQB00-NQB0m receive decrement switching signals SWD0-SWDm at their gates.

  N channel MOS transistor NTA0 receives activation signal ENVD at its gate, and MOS transistors NTA1 and NTA2 receive output signals of AND gates GTa and GTb at their gates, respectively. AND gate GTa receives activation signal ENVD and incremental switching signal SWA. The activation signal ENVD is a signal that activates the match line reference potential generation circuit when asserted. AND gate GTb receives decrement switching signal SWB and activation signal ENVD applied through inverter IVC.

  Switching signals SWA and SWB may be generated from the same current monitoring circuit as switching signals SWI0-SWIm and SWD-SWDm described above, or may be generated from another current monitoring circuit. The switching signal SWA is asserted when the drain current of the monitoring transistor of the current monitoring circuit is smaller than a set reference value, and increases the operating current of the error amplifier 70 and increases its operating speed. The switching signal SWB is asserted when the drain current of the monitoring transistor is larger than a set reference value, and reduces the operating current of the error amplifier 70 to ensure reduction of current consumption and electromigration resistance. The activation signal ENVD is generated from the control circuit 9 shown in FIG. 1 and, for example, is asserted in response to power-on of the semiconductor device (CAM chip).

  In FIG. 26, as an example, only MOS transistors corresponding to a total of two types of switching signals SWA and SWB are shown. However, a configuration in which only one of these switching signals SWA and SWB and only a corresponding MOS transistor is provided may be used.

  When a plurality of switching signals are generated as in the current monitor circuit shown in FIG. 15, by providing a plurality of MOS transistors NTA1 and NTA2 and corresponding to the plurality of switching signals, the operation speed and The operating current can be controlled.

  The internal output node is further provided with a capacitor element 76 for stabilizing the match line precharge potential. Error amplifier 70 compares the output voltages of level shifters 72 and 73, and adjusts the gate potential of drive P-channel MOS transistor 74 in accordance with the comparison result.

  Switching signals SWI0-SWIm shown in FIG. 26 give an instruction to raise the potential level of match line precharge voltage VML when it is at the H level. That is, the increment switching signals SWI0 to SWIm are asserted (H level) when the drain current Id in the Id detection circuit of the current monitor circuit is small.

  When incremental switching signals SWI0-SWIm are selectively asserted (H level), MOS transistors PQB0m-PQB00 are selectively turned on, and MOS transistors NQA00-NQA0m are selectively turned on. In this case, the amount of current flowing through MOS transistors PQ41 and PQB10-PQB1m increases, the D voltage level of internal node ND41 increases, and accordingly, the amount of current flowing through MOS transistor PQ40 is reduced. At the same time, the amount of current flowing through MOS transistors NQ40 and NQA10-NQA1m increases, and the potential level when error amplifier 70 of internal node ND42 is in the standby state is lowered.

  Accordingly, the level of match line precharge voltage VML output from drive P-channel MOS transistor 74 receiving the potential of internal node ND42 at the gate is raised.

  Even if only one of the combination of P channel MOS transistors PQB10-PQB1m and PQB00-PQB0m and inverters IVB0-IVBm and the combination of N channel MOS transistors NQB10-NQB1m and NQB00-NQB0m is mounted, the match line An effect of increasing the level of the precharge voltage VML can be obtained.

  In the VDC circuit (reference potential generation circuit) shown in FIG. 26, when the level of the match line precharge voltage VML decreases due to current consumption, the error amplifier 70 detects the level decrease and decreases the level at the output of the node ND42. The drive P-channel MOS transistor 74 is turned on to supply current. When match line precharge voltage VML rises to a predetermined level due to this current supply, error amplifier 70 raises the potential level of internal node ND42 to turn off drive P-channel MOS transistor 74 and stop supplying current. The VDC circuit returns to the standby state. Normally, the current supply operation and standby recovery of the MOS transistor driver 74 are repeatedly executed intermittently. In general, the output potential appears to be stable because it is averaged when the capacitance of the stabilizing capacitive element 76 or the load capacitance of the voltage supply target is sufficiently large.

  Further, when the potential level at the time of standby of the error amplifier 70 of the internal node ND42 is increased, the level of the match line precharge voltage VML at which the error amplifier 70 starts operating or enters the standby state is lower than the reference voltage Vtur. Become. Conversely, when the potential level of the internal node ND42 is lowered, the error amplifier 70 starts or stops operating (the driver transistor 74 supplies or stops supplying current). The level of the match line precharge voltage VML is: It becomes higher than the reference voltage Vtur. Thereby, the level of match line precharge voltage VML can be adjusted by controlling the potential level of internal node ND42 when error amplifier 70 is in the standby state.

  When the drain current (Id) of the monitoring MOS transistor of the current monitor circuit is small, that is, when the transistor finish condition is poor or under high temperature operation conditions, the current increment signals SWI0-SWIm can be selectively activated. Then, the potential level of the match line precharge voltage VML is increased, and the cross-coupled match amplifier provided for the match line is operated at high speed.

  On the other hand, when decrement switching signals SWD0-SWDm are selectively activated, MOS transistors PQA00-PQA0m are selectively turned on, the supply current to internal node ND42 increases, and internal node ND42 is in a standby state. Increase the potential level. In parallel, MOS transistors NQB00-NQB0m are also selectively turned on, increasing the amount of discharge current to the ground node and lowering the potential level at the time of standby of internal node ND44. Due to the current mirror operation, the amount of current supplied to internal node ND42 of MOS transistor PQ40 and selected MOS transistors PQA10-PQA1m increases, and the potential level of error amplifier 70 at internal node ND42 during standby is raised. As the potential level of standby state of internal node ND42 increases, the level of match line precharge voltage VML decreases.

  The decrement switching signals SWD0 to SWDm are selectively asserted when the drain (Id) of the monitoring MOS transistor in the current monitor circuit is large.

  Under these conditions. By reducing the match line precharge potential, the off-leak current in a CAM cell with poor finish conditions can be reduced, the potential amplitude of the match line can be reduced, and the current consumption can be reduced. Further, during low temperature operation, the drain current of the monitoring MOS transistor in the current monitor circuit increases, so that the match line potential MLMA and the match line reference potential MLREF of the match amplifier both decrease, and the drain current of the match amplifier transistor Therefore, the detection operation characteristic can be compensated for temperature and the detection operation can be performed stably.

  Further, by selectively activating switching signals SWA and SWB, MOS transistors NTA1 and NTA2 are selectively turned on and off. When both MOS transistors NTA1 and NTA2 are on, the operating current of error amplifier 70 is the largest. When the decrease switching signal SWB is asserted, the output signal of the inverter IVC becomes L level, and accordingly, the output signal of the AND gate GTb becomes L level, and the MOS transistor NTA2 is turned off. Thereby, the operating current of the error amplifier 70 can be reduced. On the other hand, when switching signal SWA is asserted to H level, MOS transistor NTA1 is turned on. At that time, if switching control signal SWB is at L level, MOS transistors NTA1 and NTA2 are both turned on, and the operating current is reduced. Will be increased.

  Therefore, by adjusting the operating current according to the output signal of the current monitor circuit in accordance with the finishing conditions of the MOS transistors constituting error amplifier 70, a high-speed amplification operation can be performed. In this case, switching signals SWA and SWB may be temperature detection signals instead of MOS transistor finishing conditions, and switching signals SWI0-SWIm and SWD0-SWDm may also be temperature detection signals. When the temperature is high, the detection drain current decreases, so the level of the precharge voltage VML is increased and the operating current of the error amplifier 70 is increased. On the contrary, at the time of low temperature, the same adjustment as that corresponding to the state where the drain current Id is increased is performed to reduce the operating current of the error amplifier 70 and lower the level of the match line base precharge voltage VML. Thereby, level adjustment according to finishing conditions and / or temperature can be performed.

[Modification Example 1 of Reference Potential Generation Circuit]
FIG. 27 schematically shows a structure of a modification of match line reference potential generation circuit 68 shown in FIG. 27 includes an NMOS driver type VDC (internal voltage generation circuit) 80 and a PMOS driver type VDC 82. The match line reference potential generation circuit 68 shown in FIG. The PMOS driver type VDC 82 has the same configuration as that shown in FIG. 26. In FIG. 27, the configuration is simply shown as a block.

  The NMOS driver type VDC 80 includes an error amplifier 70 that compares the reference potential Vtur from the tunable reference potential generation circuit 66 with the match line precharge voltage VML. Error amplifier 70 is connected in series between P-channel MOS transistor PQ45 and P-channel MOS transistors PQC10-PQC1m whose drains are coupled to internal node ND45, and between these MOS transistors PQC10-PQC1m and internal node ND45. P-channel MOS transistors PQC00-PQC0m, P-channel MOS transistor PQ46 and P-channel MOS transistors PQD10-PQD1m whose drains are coupled to internal node ND47, and serial connection between these MOS transistors PQD10-PQD1m and internal node ND47 P-channel MOS transistors PQD00 to PQD0m connected to each other.

  MOS transistors PQC00-PQC0m receive incremental switching signals SWI0-SWIm applied to the gates through inverters IVD0-IVDm, respectively. MOS transistors PQD00-PQD0m receive at their gates decrement switching signals SWD0-SWDm applied through inverters IVE0-IVEM, respectively.

  Error amplifier 70 further includes N channel MOS transistors NQ47 and NQC10-NQC1m whose drains and gates are connected to internal node ND45, respectively, and an N channel MOS transistor connected in series between MOS transistors NQC10-NQC1m and the ground node. NQC00-NQC0m, N-channel MOS transistors NQD10-NQD1m whose drains and gates are connected to internal node ND45, and N-channel MOS transistors NQD00 connected in series between these MOS transistors NQD10-NQD1m and the ground node, respectively -NQD0m, an N channel MOS transistor NQ48 whose gate is connected to internal node ND45, drain is connected to internal node ND47, and source is grounded. No.

  MOS transistors NQC00 to NQC0m receive decrement switching signals SWD0 to SWDm at their gates. MOS transistors NQD00-NQD0m receive incremental switching signals SWI0-SWIm at their gates, respectively.

  Error amplifier 70 further includes P channel MOS transistors PTB0-PTB2 connected between the power supply node and internal node ND46. MOS transistor PTB0 receives activation signal ENVD at its gate via inverter IVF0. The activation signal ENVD is a signal that activates the error amplifier 70.

  MOS transistors PTB1 and PTB2 receive the output signals of NAND gates NGT1 and NGT2 at their gates. NAND gate NGT1 receives activation signal ENVD and incremental switching signal SWA applied through buffer BUF0, and outputs a signal obtained by NANDing these signals. NAND gate NGT2 receives decrement switching signal SWB and activation signal ENVD applied through inverter IVF1, and outputs a signal obtained by processing the received signal at a difficult point.

  Further, an N channel MOS transistor 84 and a stabilization capacitor element 76 are provided for internal output node ND48. N channel MOS transistor 84 is connected between internal output node ND48 and the ground node, and has its gate connected to internal node ND45. Stabilizing capacitive element 76 stably holds match line precharge potential VML on internal node ND48.

  The NMOS driver type VDC 80 is obtained by inverting the P channel type and the N channel type of the MOS transistor of the PMOS driver type VDC shown in FIG. 26 and inverting the ground node and the power supply node.

  That is, when incremental switching signals SWI0-SWIm are selectively asserted, P channel MOS transistors PQC00-PQC0m are selectively turned on at the same time, and N channel MOS transistors NQD00-NQD0m are selectively turned on. MOS transistors NQ47 and NQC10-NQC1m and N-channel MOS transistors NQ48, NQD10-NQD1m constitute a current mirror circuit. Therefore, in this case, the potential level at the time of standby of error amplifier 70 of internal node ND45 decreases, and accordingly, the level of match line precharge voltage VML increases.

  In the NMOS driver type VDC circuit 80 shown in FIG. 27, when the level of the match line precharge voltage VML rises due to a current supply to any match line precharge voltage VML, the error amplifier 70 starts operating, and the internal node ND45 Is raised to turn on N-channel MOS driver transistor 84 to discharge to the ground node. When the level of the match line precharge voltage VML is lowered to a predetermined level due to discharge or current consumption, the error amplifier 70 lowers the level of the internal node ND45 and turns off the N channel MOS driver transistor 84 to perform a discharge operation. To return to the standby state.

  Usually, these operations are executed intermittently repeatedly. In general, the output potential appears to be stabilized because the output potential is averaged when the capacitance value of the stabilization capacitor element 76 or the load capacitance to be supplied is large.

  Further, when the potential level at the time of standby of the error amplifier 70 of the internal node ND45 is increased, the potential level at which the error amplifier 70 starts operating (starts discharging current by the driver transistor) or returns from standby (stops current discharge). , It becomes lower than the reference voltage BVtur. Conversely, when the internal node ND45 is lowered during standby, the level of the match line precharge voltage VML at which the error amplifier 70 starts operating or returns to standby increases with respect to the reference voltage Vtur. In this way, the level of match line precharge voltage VML can be adjusted by controlling the potential level of standby of error amplifier 70 of internal node ND45.

  In the NMOS driver type VDC 80 shown in FIG. 27, the level shifter as shown in FIG. 26 is not provided. This is because the reference voltage Vtur and the match line precharge voltage VML are received by the gates of the P-channel MOS transistors PQ45, PQC10-PQC1m, PQ46, and PQD10-PQC1m, and even when these potential levels are low, This is because the current change can be generated accurately by operating in the saturation region.

  In the case of the match line reference potential generating circuit shown in FIG. 27, both the PMOS driver type VDC 82 and the NMOS driver type VDC 80 are used. Therefore, when the match line precharge voltage VML is lower than the set potential level, it is pulled up by the PMOS driver type VDC 82, and when it is higher than the set potential level, it is pulled down by the NMOS driver type VDC 80. Therefore, match line precharge potential VML can be reliably maintained at a desired potential level.

  Also in the configuration of the match line reference potential generating circuit shown in FIG. 27, the required match line precharge potential level is accurately adjusted in accordance with the transistor characteristics and the operating temperature in accordance with the output signal of the current monitor circuit. be able to.

[Modification example of match line reference potential generator]
FIG. 28 schematically shows a configuration of a modification of the match line reference potential generation unit shown in FIG. The tunable reference potential generation circuit 66 shown in FIG. 23 is supplied with only the tuning signal from the local fuse program circuit 16M, whereas the reference potential generation circuit 90 with a tuning function shown in FIG. Switching signals SWI and SWD from current monitor circuit 18M are applied together with a tuning signal from circuit 16M.

  28 is not supplied with the tuning signal from local fuse program circuit 16M and switching signals SWI and BSWD from current monitor circuit 18M. The match line reference potential generation circuit 68 generates a match line precharge voltage (match line reference voltage) VML according to only the reference tuning voltage Vtur output from the reference potential generation circuit 90 with a tuning function.

  That is, in the configuration shown in FIG. 28, the potential level of the reference voltage Vtur is adjusted according to the magnitude of the drain current (Id) of the monitoring MOS transistor included in the current monitor circuit 18M.

  FIG. 29 schematically shows an example of the configuration of reference potential generating circuit 90 with a tuning function shown in FIG. In FIG. 29, a reference potential generating circuit 90 with a tuning function includes a fixed value generating circuit 92 that generates a fixed value, and a tuning signal TUNE according to output signals SWI <2: 1> and SWD <2: 1> of the current monitor circuit 18M. And the output value of the fixed value generation circuit 92, and the tunable reference potential generation for generating the reference potential Vtur whose level is adjusted by adjusting the resistance division ratio according to the output value Y of the calculator 94 Circuit 66.

  Tuning signal TUNE includes tuning signals TUNE <0> -TUNE <n> generated in response to blowing / non-blowing of fuse elements FM0-FM <n> included in local fuse program circuit 16M. The fuse elements FM <0> -FM <n> of the local fuse program circuit 16M are connected at one end between the resistance elements RM0-RMn connected to the power supply node and the ground node, and therefore the fuse elements FMi (i = 0-n), the corresponding tuning signal TUNE <i> is set to the H level.

  For example, the fixed value generation circuit 92 generates four types of fixed values +2, +1, −1, and −2. As an example of the configuration of the fixed value generation circuit 92, a configuration in which a fixed value output node is coupled to a power supply node or a ground node by wiring to generate a fixed value of 2 bits may be used. The fixed value generation circuit 92 may be configured to generate a fixed value according to the on / off state of the switching element, or may be configured to store the fixed value in the register circuit. Good.

  The arithmetic unit (ALU) 94 selectively performs an addition operation between the fixed value and the tuning signal in accordance with the operation activation signal ZACT from the local fuse program circuit 16MM (included in the fuse program circuit 16).

  FIG. 30 is a diagram showing a list of arithmetic processing contents of the arithmetic unit 94 shown in FIG. As shown in FIG. 30, when the operation activation signal ZACT is set to H level (“1”) by the resistance element RMN when the fuse element FMM of the local fuse program circuit 16MM is blown, the arithmetic unit (ALU) 94 Outputs the tuning signal TUNE from the local fuse program circuit 16M as the output value Y without executing the calculation.

  When operation activation signal ZACT is at L level (when fuse element FMM is not blown), operation unit 94 has a fixed value in accordance with output signals SWI <2: 1> and SWD <2: 1> of current monitor circuit 18M. An arithmetic process is performed on the output value of the generation circuit 92 and the tuning signal TUNE to generate a post-conversion tuning signal Y. In this case, when the switching signals SWI <2> and SWI <1> are at the H level (“1”), the arithmetic unit 94 performs an addition process of +2 and +1 on the tuning signal TUNE. The post-conversion tuning signal Y is generated. When the decrement switching signals SWD <2> and SWD <1> are “1”, the arithmetic unit 94 performs a subtraction operation of −2 and −1 on the tuning signal TUNE to obtain the converted tuning signal Y. Is generated.

  In this addition / subtraction operation, an addition / subtraction operation is performed using the tuning signal TUNE <n: 0> as an (n + 1) -bit digital value to generate an output signal Y. According to the tuning signal Y after the calculation, the level of the reference potential output from the tunable reference potential generation circuit 66 is increased / decreased in predetermined step units (see FIG. 25).

  When all the switching signals out of the output signals SWI <2: 1> and SWD <2: 1> of the current monitor circuit 18M are “0”, the arithmetic unit 94 outputs from the local fuse program circuit 16M. 0 is added to the tuning signal TUNE to generate a converted tuning signal Y (the tuning signal TUNE is output as a converted tuning signal without performing addition / subtraction operation).

  The tunable reference potential generating circuit 66 adjusts the voltage dividing ratio according to the post-conversion tuning signal Y to generate the match line reference voltage Vtur. Even in this configuration, the level of the reference voltage Vtur is adjusted according to the drain current of the monitoring MOS transistor included in the current monitor circuit 18M, and the level of the reference voltage Vtur decreases when the drain current (Id) is large. When the drain current is small, the potential level of the reference voltage Vtur is increased. As a result, the level of the match line precharge potential VML can be adjusted according to the finishing conditions or operating temperature of the MOS transistor in the CAM chip.

[Modification example of reference potential generator with tuning function]
FIG. 31 schematically shows a configuration of a modification of reference potential generating circuit 90 with a tuning function shown in FIG. In FIG. 31, the reference potential generation circuit 90 with a tuning function adjusts the level of the tunable reference potential generation circuit 66 and the reference voltage Vturf from the tunable reference potential generation circuit 66 to generate the tuning reference voltage Vtur. A buffer 95 for use.

  The tunable reference potential generating circuit 66 has a configuration similar to that shown in FIG. 25, and the potential level of the generated reference voltage Vturf is a tuning signal from a local fuse program circuit (16M) not shown in FIG. It is preset according to (TUNE).

  The level adjusting buffer 95 adjusts the level of the reference voltage Vturf in accordance with the switching signals SWI <n: 0> and SWD <n: 0> from the current monitor circuit 18M to generate the tuning reference voltage Vtur.

  FIG. 32 shows an example of the configuration of level adjustment buffer 95 shown in FIG. In FIG. 32, level adjusting buffer 95 selectively supplies a current between power supply node and internal node ND50 in accordance with P channel MOS transistor PQE50 connecting power supply node and internal node ND50, and decrement switching signals SWD0 to SWDn. P channel MOS transistors PQE00-PQE0n for supplying current, P channel MOS transistor PQF50 for connecting the power supply node to internal node ND52, and P for selectively supplying current between the power supply node and internal node ND52 according to incremental switching signals SWI00-SWI0n Channel MOS transistors PPQF00-PQF0n and PQF10-PQF1n, N channel MOS transistor NQE50 receiving reference voltage Vturf at its gate and connecting internal node ND50 and common source, and incremental switching N-channel MOS transistors NQE00-NQE0n and NQE10-NQE1n that selectively pass current between internal node ND50 and common source according to signals SWI00-SWI0n, tuning reference potential Vtur at the gate, and internal node ND52 and common source node N channel MOS transistor NQF50 to be connected and N channel MOS transistors NQF00 to NQF0n and NQF10 to NQF1n for selectively passing a current between internal node ND52 and the common source in accordance with decrement switching signals SWD0 to SWDn.

  P channel MOS transistors PQE00 to PQE0n receive decrement switching signals SWD0 to SWDn through inverters IVE0 to IVEn, respectively, at their gates. P channel MOS transistors PQE10-PQE1n are connected in series with MOS transistors PQE00-PQE0n, respectively, and have their gates and drains connected to each other. P channel MOS transistor PQE50 has its gate and drain commonly connected to the gates and drains of MOS transistors PQE10-PQE1n.

  P channel MOS transistors PQF00-PQF0n receive incremental switching signals SWI0-SWIn at their gates through inverters IVF0-IVFn, respectively. P channel MOS transistors PQF10-PQF1n are connected in series with MOS transistors PQF00-PQF0n, respectively, and their gates are connected to the gates of P channel MOS transistor PQF50 and P channel MOS transistor PQE50.

  N channel MOS transistors NQE00-NQE0n receive incremental switching signals SWI0-SWIn at their gates, respectively. N-channel MOS transistors NQE10-NQE1n receive reference voltage Vturf from tunable reference potential generation circuit 66 at their gates, respectively, and selectively allow current to flow from internal node ND50 to the common source. N channel MOS transistors NQF00-NQF0n receive decrement switching signals SWD0-SWDn at their gates. N-channel MOS transistors NQF10-NQF1n each receive tuning reference voltage Vtur at their gates, and selectively allow current to flow from internal output node ND52 to the common source. N channel MOS transistors NQE50 and NQF50 receive reference potentials Vturf and Vtur at their gates, respectively, and flow current from internal nodes ND50 and ND52 to the common source.

  Level adjusting buffer 95 is further provided with an N-channel MOS transistor NQEF for supplying the buffer operating current in accordance with buffer activation signal ENBF. The buffer activation signal ENBF is generated from the control circuit 9 shown in FIG. 1, and is activated, for example, when the power is turned on.

  In the level adjustment buffer 95 shown in FIG. 32, when the buffer switching signal SWI0-SWIn is selectively asserted when the buffer activation signal ENBF is asserted and the buffer 95 is activated ("1" level). P channel MOS transistors PQF00-PQF0n are selectively turned on to selectively increase the amount of current flowing from the power supply node to internal node ND52. Accordingly, the potential level of internal node ND52 rises. N channel MOS transistors NQE00 to NQE0n are also selectively turned on, increasing the amount of current flowing to the ground node, and lowering the potential level of internal node ND50. Thus, the amount of current flowing from the power supply node of P channel MOS transistors PQF00 to PQF0n selectively turned on to P channel MOS transistor PQF50 receiving the voltage of internal node ND50 at the gate to internal node ND52 increases, The level of the tuning reference j voltage Vtur which is the voltage level of the node ND52 increases.

  On the other hand, when decrement switching signal SWD0-SWDn is selectively asserted, P channel MOS transistors PQE00-PQE0n are selectively turned on, and the amount of current flowing from the power supply node to internal node ND50 increases. Accordingly, the potential level of internal node ND50 rises, the amount of current flowing through P channel MOS transistor PQF50 receiving this is reduced, and the potential level of internal node ND52 falls.

  N channel MOS transistors NQF00-NQF0n connected between internal node ND52 and the ground node are also selectively turned on in accordance with decrement switching signal SWD00-SWD0n, and can flow between internal node ND52 and the ground node. The level of the tuning reference potential Vtur, which is the potential level of the internal node ND52, is further reduced.

  As described above, the potential level of the tuning reference voltage Vtur can be adjusted according to the output signal of the current monitoring circuit 18M, and the match line precharge potential can be adjusted accordingly.

  In FIG. 32, the tuning reference voltage vturf is gate-inputted as an N-channel MOS transistor as the level adjustment buffer 95, and the P-channel MOS transistor constitutes a current mirror stage. However, in this level adjustment buffer 95, by replacing the P-channel type or N-channel type of the MOS transistor and replacing the power supply node and the ground node, the P-channel MOS transistor receives the reference voltage Vturf at the gate, and the N-channel MOS A buffer circuit in which a transistor constitutes a current mirror stage can be realized. Even in the case of this configuration, the potential level of the tuning reference voltage Vtur can be adjusted by a similar action.

  In the current monitor circuit 18M, switching signals SWI0-SWIn and SWD0-SWDn are generated in accordance with the drain current Id of the monitoring MOS transistor. However, in this case, temperature may be monitored by current monitor circuit 18M, and switching signals SWI0-SWIn and SWD0-SWDn may be generated according to the temperature condition.

  Also, by adjusting the potential level of the reference voltage Vtur that defines the match line precharge potential, the match line precharge potential is adjusted according to the internal environment including transistor characteristics and operating temperature. Can do.

  Also, the level of the reference potential can be adjusted according to the internal environment, and even if the number of fuse elements of the local fuse program circuit that trims the output voltage of the tunable reference potential generation circuit is reduced, it can be adjusted accurately And the fuse program is simplified.

[Configuration of power supply circuit for search line drive circuit]
FIG. 33 schematically shows a structure of a circuit for generating an operating power supply voltage for search line drive circuit 3 shown in FIG. In FIG. 33, the operating power supply voltage of the search line driving circuit is generated by the booster circuit 100 arranged in the power supply circuit 26. The booster circuit 100 includes a detector 102 that detects the level of the search line drive circuit power supply voltage Vbs, an oscillator 104 that selectively oscillates in accordance with the output signal OSACT of the detector 102, and a charge pump operation in accordance with the oscillation signal PCLK from the oscillator 104. Is included to generate the power supply voltage Vbs.

  Detector 102 is activated when detector enable signal DETEN is activated, and compares the level of tuning reference potential VTU from tunable reference potential generation circuit 66 with the level of boosted voltage (search line drive circuit power supply voltage) Vbs, and the comparison result. In response to this, the oscillator activation signal OSACT is asserted.

  Oscillator 104 is formed of, for example, a ring oscillator, and performs oscillation operation at a predetermined cycle when oscillator activation signal OSACT from detector 102 is activated to generate pump clock signal PCLK.

  When pump enable signal PUPEN is activated, charger pump 106 pumps the capacitive element in accordance with pump clock signal PCLK from oscillator 104 to generate boosted voltage Vbs that is higher than power supply voltage VDD. The detector enable signal DETEN and the pump enable signal PUPEN are generated from the control circuit 9 shown in FIG. 1, and are activated when the CAM chip is in a selected state and performs an internal operation.

  The detector 102 has its operating current adjusted in accordance with the increment and decrement switching signals SWI and SWD output from the current monitor circuit 18S. That is, the current monitor circuit 18S generates the switching signals SWI and SWD according to the drain current flowing through the current monitoring MOS transistor described so far. When the drain current Id of the monitoring MOS transistor is small and the finishing condition is poor or the operating temperature is high, the detector 102 increases the operating current in accordance with the switching signal SWI and brings its operating speed close to the specification value ( Or make it faster).

  On the other hand, when the drain current of the monitoring transistor is large, the operating current of the detector 102 is reduced according to the decrement switching signal SWD, and the current consumption is reduced.

  The tunable reference potential generation circuit 66A may have any of the configurations shown in FIGS. 25, 29, and 31 as long as the level of the reference potential VTU generated can be adjusted. In this case, the reference potential VTU generated by the tunable reference potential generation circuit 66A may be adjusted according to the output signal of the current monitor circuit (18S). When the finishing conditions are poor or the operation temperature is high, the potential level of the reference voltage VTU is increased, the level of the boost voltage Vbs is increased, and the operation speed of the search line driving circuit is increased (or closer to the design value). .

  FIG. 34 is a diagram showing an example of the configuration of the detector 102 shown in FIG. In FIG. 34, the detector 102 compares the tuning reference voltage VTU with the boosted voltage Vbs, the tristate inverter buffer 112 that buffers the output signal of the comparison circuit 110, and the output signal of the tristate inverter buffer 112. An inverter IVG1 that inverts and generates an oscillator activation signal OSACT is included.

  P channel MOS transistor PQG4 is provided at the input node of inverter IVG1, and detector 102 is inactive when detector enable signal DETEN is "0" and tristate inverter buffer 112 is in the output high impedance state. In this state, the input node of inverter IVG1 is fixed at the power supply potential level.

  Comparison circuit 110 includes P channel MOS transistors PQG0 and PQG1 forming a current mirror stage, N channel MOS transistors NQG0 and NQG1 connected in series with P channel MOS transistors PQG0 and PQG1, respectively, and MOS transistors NQG0 and NQG1. N channel MOS transistors NQH0 and NQH1-NQHn connected in parallel between the source node and the ground node. P channel MOS transistor PQG0 has its gate and drain interconnected and functions as a master of the current mirror stage.

  N channel MOS transistors NQG0 and NQG1 receive tuning reference voltage VTU and boosted voltage Vbs at their gates, respectively. N channel MOS transistor NQH0 receives detector enable signal DETEN at its gate. N channel MOS transistor NQH1 receives an output signal of AND gate GG1 at its gate, and MOS transistor NQHn receives an output signal of AND gate GG2 at its gate. The AND gate GG1 receives the detector enable signal DETEN and the incremental switching signal SWI via the buffer BUFG0. AND gate GG2 receives decrement switching signal SWD and detector enable signal DETEN that have passed through inverter IVG2. AND gates GG1-GG2 are appropriately provided according to the number of N-channel MOS transistors NQH1-NQHn, and the number thereof is appropriately determined according to the number of bits of incremental switching signal SWI and the number of bits of decrementing switching signal SWD. .

  Tristate inverter buffer 112 has P channel MOS transistor PQG3 and N channel MOS transistor NQG2 receiving the output signal of comparison circuit 110 at its gate, and P channel MOS transistor PQG2 connected between P channel MOS transistor PQG3 and the power supply node. N channel MOS transistor NQG3 connected between N channel MOS transistor NQG2 and the ground node. Detector enable signal DETEN is applied to the gate of P channel MOS transistor PQG2 via inverter IVG0, and detector enable signal DETEN is applied to the gate of MOS transistor NQG3.

  When detector enable signal DETEN is at the inactive L level, P channel MOS transistor PQG2 and N channel MOS transistor NQG3 are turned off, and tristate inverter buffer 112 is in an output high impedance state. At this time, P channel MOS transistor PQG4 is turned on, and the input node of inverter IVG1 is maintained at the power supply voltage level. In this state, the oscillator activation signal OSACT is maintained at the L level, and the oscillation operation of the next-stage oscillator 104 is stopped.

  On the other hand, when detector enable signal DETEN is at the H level, P channel MOS transistor PQG4 is in an off state and has no effect on the output signal of tristate inverter buffer 112. P channel MOS transistor PQG2 and N channel MOS transistor NQG3 are turned on, and tristate inverter buffer 112 operates as an inverter and inverts the output signal of comparison circuit 110.

  In comparison circuit 110 shown in FIG. 34, currents of the same magnitude flow in P channel MOS transistors PQG0 and PQG1 (when the transistor sizes are equal). When tuning reference voltage VTU is higher than boosted voltage Vbs, the amount of current flowing through N channel MOS transistor NQG0 is larger than the current flowing through N channel MOS transistor NQG1. A current having the same magnitude as that flowing through N channel MOS transistor NQG0 is applied to N channel MOS transistor NQG1 through P channel MOS transistor PQG1, and the level of output signal DOUT of comparison circuit 110 rises. Accordingly, the output signal of tristate inverter buffer 112 becomes L level, the output signal of inverter IVG1 becomes oscillator activation signal OSACT becomes H level, oscillator 104 is enabled, and the oscillation operation is continued.

  On the other hand, when boosted voltage Vbs is higher than tuning reference voltage VTU, the amount of current flowing through N channel MOS transistor NQG1 increases as the amount of current flowing through N channel MOS transistor NQG0. In this case, since the current of P channel MOS transistor PQG1 does not increase, the potential level of output signal DOUT decreases. Accordingly, oscillator activation signal OSACT output from tristate inverter buffer 112 and inverter IVG1 attains L level, and the oscillation operation of oscillator 104 is stopped.

  In operation, when incremental switching signal SWI is set to H level, N-channel MOS transistor NQH1 is turned on, the operating current of comparison circuit 110 is increased, and the comparison operation is speeded up. On the other hand, when decrement switching signal SWD is set to H level, the output signal of gate GG2 becomes L level, N-channel MOS transistor NQHn is turned off, the operating current of comparison circuit 110 is reduced, and the consumption current is reduced. Reduced.

  Only one of the switching signals SWD and SWI may be used, or both may be used. The operating current of the comparison circuit 110 is adjusted according to the drain current of the monitoring transistor that varies depending on the finishing conditions or operating temperature. When the finishing conditions are poor or the operating temperature is high and the drive current amount of N-channel MOS transistor NQH0 is small, N-channel MOS transistors NQH1 and NQH2 are set to the ON state, and the operating current of comparison circuit 110 is increased. Make it work. On the other hand, if the finishing conditions are good or the operating temperature is low and the drive current of N-channel MOS transistor NQH0 is larger than the specification value (typical value), N-channel MOS transistor NQHn is set to the off state and the operating current is Reduce current consumption.

  In the configuration of detector 102 shown in FIG. 34, the same effect can be obtained by switching the P channel type and N channel type of the MOS transistor of comparison circuit 110 and switching the power supply node and the ground node again.

  As described above, according to the first embodiment of the present invention, the level of the voltage generated inside or the operating current is adjusted in accordance with the drain current flowing through the monitoring MOS transistor provided inside. As a result, a semiconductor device that operates accurately and at high speed can be realized even when the element characteristics are different due to manufacturing parameter variations and the operating temperature is different depending on the use environment.

[Embodiment 2]
FIG. 35 schematically shows a structure of a main portion of the semiconductor device according to the second embodiment of the present invention. In the configuration shown in FIG. 35, delay circuits 120A and 120B receiving output signals SWI and SWD of current monitor circuit 18 are provided. Output delay switching signals SWID and SWDD of delay circuits 120A and 120B are applied to adjustment target circuit 125. The adjustment target circuit 125 includes a reference potential generation circuit with a tuning function that generates reference potentials Vtur and VTU, a local power supply circuit that generates a match line reference potential MLREF, and a match line precharge voltage generation circuit that generates a match line precharge voltage VML One of the power supply circuit for generating the power supply voltage Vbs of the search line driving circuit and the cross-coupled match amplifier.

  The potential level or operating current generated by target circuit 125 is adjusted according to delay switching signals SWID and SWDD output from delay circuits 120A and 120B. Current monitor circuit 18 has any of the configurations of the circuits described in the first embodiment.

  In the configuration shown in FIG. 35, delay circuits 120A and 120B operate equivalently as a low-pass filter. Any of the current monitor circuit configurations described in the first embodiment may be used as the current monitor circuit 18.

  FIG. 36 is a signal waveform diagram representing operations of delay circuits 120A and 120B shown in FIG. The operation of the configuration shown in FIG. 35 will be described below with reference to FIG.

  The switching signals SWI and SWD output from the current monitor circuit 18 compare the detection voltages (Vidb, Vidn) with the comparison reference potential by an internal comparison circuit. Therefore, it is conceivable that the switching signal SWI / SWD oscillates when the levels of these detection voltages and the comparison reference potential are close. Delay circuits 120A and 120B delay switch signals SWI and SWD output from current monitor circuit 18 to generate delay switch signals SWID and SWDD. During the delay operation, the delay circuits 120A and 120B are delayed in charging / discharging of the internal node, operate as a low-pass filter, remove the vibration components (high frequency components) of the output signals SWI and SWD of the current monitor circuit 18, and shape the waveform. Alternatively, a signal in which noise components are suppressed is generated. Thereby, the operation in the target circuit 125 can be stabilized.

  FIG. 37 shows an example of the configuration of delay circuits 120A and 120B shown in FIG. In FIG. 37, the delay circuit 120 refers to one of these delay circuits 120A and 120B. In FIG. 37, the delay circuit 120 inverts the output signal of the delay stage 127 that delays the input signal IN by a predetermined time τ, the NAND circuit 130 that receives the output signal of the delay stage 127 and the input signal IN, and the output signal of the NAND circuit 130. An inverter circuit 132 that generates the output signal OUT is included. The input signal IN is the switching signal SWI or SWD, and the output signal OUT is one of the delay switching signals SWID and SWDD.

  Delay stage 127 includes a plurality of single podiums composed of inverter IVH and capacitive elements Ca and Cb. Capacitance elements Ca and Cb delay charging / discharging of the output signal of corresponding inverter IVH, and remove the high-frequency component of the output signal of inverter IVH.

  FIG. 38 is a timing chart showing an operation of delay circuit 120 shown in FIG. Hereinafter, the operation of the delay circuit 120 shown in FIG. 37 will be described with reference to FIG.

  The delay stage 127 has its delay time set by the gate delay caused by the inverter IVH, the high-side capacitive element Ca, and the low-side capacitive element Cb and the charge / discharge delay of the capacitive element, and delays the input signal IN by a predetermined time τ. During this delay operation, the rise and fall of the signal are delayed by the capacitive elements Ca and Cb. The arrival of the output signal of the delay stage to the voltage level determined as the logic high level and the logic low level is delayed by time τ with respect to the input signal IN. Therefore, high frequency components are removed from the output signal of the delay stage 127, and noise components are sufficiently suppressed.

  The NAND circuit 130 and the inverter circuit 132 form an AND circuit. Therefore, the output signal OUT becomes H level only while both the input signal IN and the output signal of the delay stage 127 are H level (logic high level). Thereby, even if the input signal IN vibrates, the noise component can be removed from the output signal OUT, and the target circuit 125 can be operated stably. In this case, when a noise component exists at the falling edge of the input signal IN, there is a possibility that a similar noise component also exists at the falling edge of the output signal. In that case, there is no effect if the noise component does not exceed the high / low decision level. The noise component at the rising edge of the input signal IN can be removed by the delay stage 127 regardless of the amplitude.

"Modification of delay circuit"
FIG. 39 schematically shows a configuration of a modification of delay circuit 120A or 120B shown in FIG. In FIG. 39, the delay circuit 120A or 120B is indicated by the delay circuit 120. 39 includes a delay stage 127 that receives the input signal IN, a NOR circuit 134 that receives the output signal of the delay stage 127 and the input signal IN, and an inverter circuit 136 that inverts the output signal of the NOR circuit 134. .

  Similarly to the configuration shown in FIG. 37, delay stage 127 includes an inverter IVH, a high-side capacitive element Ca, and a low-side capacitive element Cb. An output signal OUT is generated from the inverter circuit 136. Input signal IN corresponds to switching signal SWI or SWD output from monitor circuit 18, and output signal OUT corresponds to delay switching signal SWID or SWDD shown in FIG.

  FIG. 40 is a timing chart showing an operation of delay circuit 120 shown in FIG. Hereinafter, the operation of the delay circuit shown in FIG. 39 will be described with reference to FIG.

  The delay stage 127 outputs the input signal IN after delaying the input signal IN by a predetermined time τ. During this delay operation, similarly to the configuration shown in FIG. 37, the transition speed of the input signal IN is delayed by the capacitive elements Ca and Cb and the gate capacitance of the inverter IVH, thereby realizing the low-pass filter processing. The NOR circuit 134 outputs an L level signal when one of the input signal IN and the output signal of the delay stage 127 is at an H level, and the inverter circuit 136 inverts the output signal of the NOR circuit 136. Therefore, the output signal OUT becomes H level when one of the input signal IN and the output signal of the delay stage 127 is H level.

  The delay circuit 120 shown in FIG. 39 is a falling delay circuit that delays the falling of the input signal IN. Noise components are removed when the input signal IN falls. Even when the noise amplitude of the input signal IN is large at the time of falling, the noise component can be sufficiently removed if the vibration is within the delay time τ.

  Therefore, any transition timing can be changed by selectively using the rising delay circuit and the falling delay circuit shown in FIGS. That is, in the target circuit 125, by using the circuit configuration of the delay circuits 120A and 120B depending on which of the adjustment start and stop is prioritized, the direction of priority characteristic change can be set and stable. The target circuit 125 can be operated.

  Further, as the delay circuits 120A and 120B, low-pass filters that filter high-frequency noise components may be used.

  As described above, according to the second embodiment of the present invention, the switching signal is transmitted to the target circuit through the delay circuit that receives the output signal of the current monitor circuit. Therefore, even when the detection potential corresponding to the monitor current of the current monitor circuit and the comparison target potential are close to each other, the target circuit can be operated stably.

[Embodiment 3]
FIG. 41 schematically shows a structure of a main portion of the semiconductor device according to the third embodiment of the present invention. 41, the validity / invalidity of switching signals SWI and SWD applied to target circuit 140 is set according to a program signal from local fuse program circuit 16L included in fuse program circuit 16. In the configuration shown in FIG. That is, the gate circuits 142 i and 142 d are provided between the current monitor circuit 18 and the target circuit 140. The gate circuit 142i receives the incremental switching signal SWIF from the current monitor circuit 18 and the incremental activation program signal ACTI from the local fuse program circuit 16L, generates the incremental switching signal SWI, and supplies it to the target circuit 140. The gate circuit 142d receives the decrement switching signal SWDF from the current monitor circuit 18 and the decrement activation program signal ACTD from the local fuse program circuit 16L, generates a decrement switching signal SWD, and supplies it to the target circuit 140.

  Current monitor circuit 18 has the configuration described in the first embodiment, and generates switching signals SWIF and SWDF in accordance with the drain current flowing through the monitoring transistor included therein.

  Local fuse program circuit 16L programs the states of activation program signals ACTI and ACTD by fusing / not fusing fuse elements FZI and FZD connected between resistance elements RLI and RLD and the installation node, respectively. When incremental activation program signal ACTI is in an inactive state (L level), that is, when fuse element FZI is not blown, gate circuit 120i maintains switching signal SWI at an inactive L level, and the target circuit The current / potential increment control operation at 140 is stopped. When the fuse element FZI is blown, the incremental activation program signal ACTI becomes H level by the resistance element RLI, and the gate circuit 142i generates the switching signal SWI according to the incremental switching signal SWIF from the current monitor circuit 18 and supplies it to the target circuit 140. .

  Gate circuit 142d maintains decrement switching signal SWD applied to target circuit 140 at an L level when fuse element FZL is in an unblown state and decrement activation program signal ACTD is at an L level. In this case, in the target circuit 140, the potential / current decrement adjustment operation is stopped. When the fuse element FZI is blown, the incremental activation program signal ACTD becomes H level by the resistance element RLD, and the gate circuit 142d generates the switching signal SWD according to the incremental switching signal SWDF from the current monitor circuit 18 and supplies it to the target circuit 140. .

  The target circuit 140 is a circuit that generates the match line reference potential MLREF described above, a circuit that generates the match line precharge voltage VML, or a reference potential generation with a tuning function that generates the match line precharge potential reference voltage Vtur. Any of a circuit, a cross-coupled match amplifier, and a circuit that generates the search line power supply voltage Vbs may be used. Any circuit may be used as long as the level of the voltage generated by the switching signals SWI and SWD or the operating current is adjusted.

  In the local fuse program circuit 16L in the fuse program circuit 16, the resistance elements RLI and RLD and the fuse elements FZI and FZD are programmed (blown / unblown) in the test process after the manufacturing process is completed. That is, when the fuse element program included in the normal fuse program circuit 16 cannot sufficiently guarantee the operating characteristics, the fuse elements FZI and FZL are blown, and the switching signals SWI and SWD are output from the current monitor circuit 18. Adjust according to the signals SWIF and SWDF. As a result, even when the finish condition of the MOS transistor is greatly deviated from the standard condition (design value) and the operating temperature fluctuates from the specified value, the operating characteristics can be accurately guaranteed and the product yield can be guaranteed. Can be improved.

  The adjustment of the switching signal may be performed for each of the incremental switching signal SWI and the decrementing switching signal SWD. When there are a plurality of switching signals SWI <n: 0> and SWD <n: 0>, the activation program signal ACTI <i is individually applied to each bit SWI <i> and SWD <i> of the switching signal. > And ACT <i> may be generated to individually enable / disable the switching signal.

[Example of change]
FIG. 42 schematically shows a structure of a modification of the main portion of the semiconductor device according to the third embodiment of the present invention. In the configuration shown in FIG. 421, switching signals SWI and SWD from gate circuits 142i and 142d are applied to level adjustment buffer 145 corresponding to level adjustment buffer 95 shown in FIG.

  The level adjustment buffer 145 adjusts the level of the tuning reference potential Vref from the tunable reference potential generation circuit 66 shown in FIG. 31, generates the level-adjusted reference potential VREF, and supplies it to the target circuit 148. The target circuit 148 corresponds to a circuit that generates the match line reference potential VML and a circuit that generates the power supply voltage Vbs of the search line driving circuit, and the potential level of the output voltage VOUT to be generated is set according to the reference potential Vref. The

  Similarly to the configuration shown in FIG. 41, activation program signals ACTI and ACTD from local fuse program circuit 16L included in fuse program circuit 16 are applied to gate circuits 142i and 142d, respectively. In the configuration shown in FIG. 41, switching signals SWI <i> and SWD <i> are generated for switching signals SWIF and SWDF <i> from current monitor circuit 18, respectively, and the activation / non-activation of each switching control unit. The activity is set according to whether the fuse elements FZI and FZD are blown or not blown. In this case, similarly to the configuration shown in FIG. 41, activation program signal ACTI <i> is generated in common to switching signal SWI <n: 0>, and common to switching signal SWD <n: 0>. An activation program signal ACTD may be generated.

  Also in the configuration shown in FIG. 42, the level adjustment operation can be selectively set to the valid state by the program of local fuse program circuit 16L in accordance with the finish condition of the MOS transistor, and the product yield is improved.

[Modification 2]
FIG. 43 schematically shows a structure of a second modification of the main portion of the semiconductor device according to the third embodiment of the present invention. In the configuration shown in FIG. 42, activation program signals ACTI and ACTD fix the potentials of pads PDI and PDD to power supply voltage VDD or ground potential by wiring program circuits 150i and 150d. The wiring program circuits 150i and 150d are usually composed of bonding wires. After the test process, the validity / invalidity of the level adjustment function is determined by wire connection in accordance with the finish of the MOS transistor.

  In this configuration, a plurality of pads PDI and PDD may be arranged according to the number of signals and / or functions, and the number of pads is not particularly limited.

  The configuration shown in FIG. 42 is used in place of local fuse program circuit 16L having the configuration shown in FIG. 41 or FIG.

[Modification 3]
44 schematically shows a structure of a third modification of the main portion of the semiconductor device according to the third embodiment of the present invention. In the configuration shown in FIG. 44, activation program signals ACTI and ACTD are stored and generated in register circuits 157i and 157d included in register file 155. For register circuits 157i and 157d, data DINa and DINb from the outside are stored under the control of control circuit 9 shown in FIG. 1, and states (logical values) of activation program signals ACTI and ACTD are stored. Is set.

  In the register file 155 shown in FIG. 44, the states of activation program signals ACTI and ACTD are set according to the data stored in register circuits 157i and 157d accessible from the outside. In circuit operation analysis or the like, the level adjustment operation can be selectively set to an effective state from the outside.

  In the configuration shown in FIG. 44, register circuits 157i and 157d may be provided corresponding to switching signals SWIF <i> and SWDF <i> output from the current monitor circuit (see FIG. 41), Further, it may be provided for the decremental switching control and the incremental switching control so as to execute the incremental switching control and / or the decrementing switching control in common.

  As described above, according to the third embodiment of the present invention, the adjustment operation according to the finish of the MOS transistor or the operation temperature is selectively set to the valid state. As a result, the level adjustment operation can be made effective only for the required semiconductor device (chip), and the semiconductor chip under worst conditions can be relieved. In addition, the operating conditions can be set according to the variation in the operating characteristics of the transistors in each semiconductor chip, and the reliability can be improved.

  The semiconductor device according to the present invention can be realized as a semiconductor device including a circuit that operates at high speed and generates an internal voltage therein, thereby realizing high-speed and low power consumption operation. The present invention relates to a match line low potential precharge type CAM, DRAM, flash memory, 1T-SRAM (1-transistor / 1-capacitor SRAM), twin cell RAM (DRAM which stores 1-bit data in two DRAM cells), read / write The present invention can be applied to semiconductor memory devices such as SRAM (Static Random Access Memory) with a write assist function.

  The temperature detection function in the current monitor circuit may be used as a temperature sensor as a single circuit. In this case, a temperature sensor having a simple circuit configuration and a small occupation area can be realized as the temperature sensor.

  1 CAM chip, 2 memory array, ERY entry, 3 search line drive circuit, 6 match amplifier circuit, 12 power supply circuit, 16 fuse programmable circuit, 18 current monitor circuit, MAP0-MAPn match amplifier, 22 match line potential determination circuit, 24 ML precharge voltage generation circuit, 26 SL power supply voltage generation circuit, 30 Id detection circuit, 32 Id determination circuit, 35 local power supply circuit, NT30, PT31 monitor MOS transistor, 55 constant current circuit, 58 tunable variable resistance element, 50a 50b, 50A0-50Am, 50B0-50Bm, 50C0-50Cm, 50D0-50Dm, 50E0-50E3 Comparison circuit, 16M Local fuse program circuit, 66 Tunable reference potential generation circuit, 68 Match line reference voltage Generating circuit, 70 Error amplifier, 82 PMOS driver type VDC, 90 Reference potential generating circuit with tuning function, 18M current monitor circuit, 92 fixed value generating circuit, 94 arithmetic unit (ALU), 16MM local fuse program circuit, 95 level adjustment Buffer, 100 Pump power supply circuit, 102 Detector, 104 Oscillator, 106 Charge pump, 66A Tunable reference potential generation circuit, 18S Current monitor circuit, 110 Comparison circuit, 112 Tri-state inverter buffer, 120, 120A, 120B Delay circuit, 125 Target Circuit, 140 target circuit, 16L local fuse program circuit, 145 level adjustment buffer, 148 target circuit, 150i, 150d wiring program circuit, PDI, PDD pad, 1 55 Register file, 157i, 157d Register circuit.

Claims (5)

A memory array including a plurality of associative memory cells each arranged in a row direction and having a plurality of entries for storing reference data;
Arranged corresponding to each entry, each coupled to the associative memory cell of the corresponding entry and precharged to a predetermined precharge voltage, each matching the reference data of the corresponding entry and the provided search data / Multiple match lines that transmit voltage according to mismatch
A plurality of match amplifiers arranged corresponding to each entry, each of which compares a match line voltage of a corresponding entry with a reference voltage and outputs a signal corresponding to the comparison result;
A current monitor circuit that includes a monitor transistor formed on the same semiconductor substrate as the memory array, and generates a signal corresponding to a current flowing through the monitor transistor;
A power supply circuit that generates a voltage of at least one of the precharge voltage and the reference voltage by adjusting a level of a generated voltage according to an output signal of the current monitor circuit; and a device provided in common for the plurality of entries, A search line driving circuit for generating the search data according to external search data from the outside and transmitting the search data to the plurality of entries;
The power supply circuit includes a search line power supply voltage generation circuit that generates a search line power supply voltage that is an operation power supply voltage for the search line drive circuit,
The search line power supply voltage generation circuit includes:
A level detection circuit that adjusts an operating current according to an output signal of the current monitor circuit and determines whether the search line power supply voltage is at a predetermined level;
A circuit that selectively generates the search line power supply voltage according to an output signal of the level detection circuit,
The power supply circuit generates the precharge voltage;
The semiconductor device, wherein the power supply circuit increases the precharge voltage in accordance with a decrease in current flowing through the monitoring transistor. The power supply circuit generates the reference voltage;
The semiconductor device according to claim 1, wherein the power supply circuit increases the reference voltage in accordance with a decrease in a current flowing through the monitoring transistor. The power supply circuit is
A reference voltage generation circuit with a tuning function for generating a reference voltage whose level is adjustable;
A voltage generation circuit for generating the precharge voltage according to the reference voltage from the reference voltage generation circuit with the tuning function;
The voltage generating circuit, operating current to generate the precharge voltage is adjusted in accordance with an output signal of said current monitoring circuit, the semiconductor device according to claim 1, wherein. The semiconductor device includes:
A local fuse program circuit for generating tuning information fixedly;
The power supply circuit is
A reference voltage generation circuit with a tuning function for generating a reference voltage whose level is adjustable;
A voltage generation circuit for generating the precharge voltage according to the reference voltage from the reference voltage generation circuit with the tuning function;
The reference voltage generation circuit with a tuning function is:
An arithmetic unit that selectively updates the tuning information according to an output signal of the current monitor circuit to generate an adjustment tuning signal;
The semiconductor device according to claim 1, further comprising: a tunable reference voltage generation circuit that generates the reference voltage in accordance with an adjustment tuning signal output from the arithmetic unit. The semiconductor device includes:
A local fuse program circuit for generating tuning information fixedly;
The power supply circuit is
A reference voltage generation circuit with a tuning function for generating a reference voltage whose level is adjustable;
A voltage generation circuit for generating the precharge voltage according to the reference voltage from the reference voltage generation circuit with the tuning function;
The reference voltage generation circuit with a tuning function is:
A tunable reference voltage generating circuit for generating a reference voltage whose level is adjustable;
The semiconductor device according to claim 1, further comprising: a level adjustment buffer that adjusts a level of the comparison reference voltage according to an output signal of the current monitor circuit to generate the reference voltage.

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