JP2007317342A - Content addressable memory - Google Patents

Content addressable memory Download PDF

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JP2007317342A
JP2007317342A JP2006308145A JP2006308145A JP2007317342A JP 2007317342 A JP2007317342 A JP 2007317342A JP 2006308145 A JP2006308145 A JP 2006308145A JP 2006308145 A JP2006308145 A JP 2006308145A JP 2007317342 A JP2007317342 A JP 2007317342A
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voltage
circuit
match
current
level
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Inventor
Mihoko Akiyama
Teruhiko Amano
Katsumi Dosaka
Isamu Hayashi
Gen Morishita
Naoya Watanabe
Kenji Yoshinaga
賢司 吉永
勝己 堂阪
照彦 天野
勇 林
玄 森下
直也 渡邊
実邦子 秋山
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Renesas Technology Corp
株式会社ルネサステクノロジ
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Priority to JP2006120890 priority Critical
Application filed by Renesas Technology Corp, 株式会社ルネサステクノロジ filed Critical Renesas Technology Corp
Priority to JP2006308145A priority patent/JP2007317342A/en
Priority claimed from US11/730,969 external-priority patent/US20070247885A1/en
Publication of JP2007317342A publication Critical patent/JP2007317342A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption during a search cycle of a content addressable memory and to increase the speed of a search operation. <P>SOLUTION: An entry (ERY) including multiple bits of unit cells (UC) each storing data bit is coupled to a match line (ML). The match line is supplied with a charging current (Ip) having a restricted current value smaller than a match line current flowing in a one-bit miss state, but larger than a match line current flowing in an all-bit match state. A precharge voltage level of the match line is restricted to a voltage level (VML) of half a power supply voltage (VDD) or smaller. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a content reference memory, and more particularly to a configuration for reducing current consumption and peak current during a search operation and speeding up the search operation.

  A content addressable memory (CAM) has a function of determining whether or not the stored data matches given search data, in addition to a data read / write function. One entry for storing a search data word is composed of a plurality of CAM cells, and word bits of search candidates are stored in these CAM cells. Each entry is provided with a match line to which corresponding CAM cells are coupled in parallel. When the search data word matches the stored data word of the entry, the corresponding match line is maintained in the “1” state, and when there is no match, the corresponding match line is driven to the “0” state.

  By identifying the voltage level of the match line, it can be determined whether the data corresponding to the search data is stored in a table, for example. Such a content reference memory is used in, for example, determination of a cache miss / hit in a router for use in communication and a cache memory. IP packet routing performed by a network router or the like is performed by comparing an IP address stored in a content reference memory provided in the router with an IP address input from the outside. For example, a value indicating the next destination address is written in the IP packet based on the match line information in the match state in the content reference memory in the router, and transmitted from the corresponding port.

  Normally, in a CAM used in a communication router or the like, the bit width of search data is 72 to 288 bits, and the number of entries is about 64K.

  In the conventional CAM, the match line is precharged to the power supply voltage VDD (or the ground voltage GND level) during the precharge period. The search data and the data bit of the entry CAM cell are compared in the search period for detecting the match between the stored data and the search data. In the case of mismatch, the corresponding match line is discharged (or charged) to a ground voltage (or power supply voltage level) different from the precharge voltage by the transistor in the CAM cell. Therefore, when there are n non-matching CAM cells in one entry, for example, one match line is discharged (or charged) by a current of I_miss × n. Here, I_miss is a current that is driven when one CAM cell is in a mismatch state. If all data bits match in all CAM cells in the entry, the CAM cell has no discharge (or charge) path. Therefore, the match line in the coincidence state is maintained at the precharge voltage (power supply voltage VDD or ground voltage GND) level.

  In CAM, search data is given to a plurality of entries in parallel, and the search operation is executed in parallel in each entry. A search line for transmitting search data and a match line for generating a signal indicating a match result are precharged to a predetermined voltage level for each search cycle in which each search operation is performed. As an example, the search line is precharged to the ground voltage level, and the match line is precharged to the power supply voltage level. CAM cells of all entries are coupled to this search line. Therefore, the capacity load of the search line is large. Further, the majority of match lines other than the match at the time of search change between the power supply voltage level and the ground voltage level for each search cycle. Therefore, the charge / discharge current of the search line and the match line is large, and there is a problem that current consumption / power is increased.

  The content that reduces the current consumption in the reference memory and performs the search operation at high speed is described in Non-Patent Document 1 (H. Noda, et. Al., “A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift. redundancy architecture ”, JSSCC, Vol.40, 2005, pp.245-253. In the configuration shown in Non-Patent Document 1, the match lines are hierarchically structured. A plurality of local match lines are provided for one entry. These multiple local match lines are coupled to a common global match line. The search operation is executed in a pipeline manner in each local match line. For example, 144-bit search data is divided into 72-bit data. In the local match line of the block that does not match in the first 72 bits, it is not necessary to continue the subsequent search. Therefore, in the entry corresponding to the non-matching block, the search line is not activated in the next stage, and the local match line is not discharged. The number of local match lines to be charged / discharged can be reduced, and power consumption can be reduced.

  In Non-Patent Document 1, a DRAM cell structure is used for storing search data, and data bits are stored in individual DRAM cells to store ternary data. The CAM cell that stores the ternary data is generally called a TCAM (Ternary CAM) cell and can store a don't care state.

  A configuration for speeding up the search operation is shown in Patent Document 1 (Japanese Patent Laid-Open No. 10-27481). In the configuration disclosed in Patent Document 1, the match line is precharged to the ground voltage level during standby. During the search operation, a current having the same magnitude as the current that flows when the search data does not match 1 bit is supplied to each match line. An attempt is made to reduce the current consumption by suppressing the voltage rise of the match line of the mismatched entry to the reference voltage or lower.

  Patent Document 2 (Japanese Patent Application Laid-Open No. 2004-192695) similarly shows a configuration for reducing current consumption during a search. In Patent Document 2, the search line is precharged to an intermediate voltage level by short-circuiting the complementary search line during standby. The match line is precharged to the ground voltage during standby, and is charged up by the charge charged from the capacitive element at the start of the search operation. The upper limit value of the voltage level of the match line is set to an intermediate voltage level lower than the power supply voltage by capacitive division between the capacitive element and the match line. The voltage level of the match line is detected by a buffer circuit.

  Japanese Patent Laid-Open No. 2003-100086 discloses a configuration for performing a search operation at high speed even when the match line load increases. In Patent Document 3, a reference voltage generation circuit and a differential amplifier circuit are provided corresponding to each match line. By comparing the reference voltage with the match line voltage by the differential amplifier circuit, the search determination operation is speeded up.

  Patent Document 4 (Japanese Patent Laid-Open No. 2002-358791) shows a configuration for reducing a precharge current during a search operation. In this patent document 4, a CAM entry is divided. The precharge voltage level of the divided CAM entry and the drive voltage level of the match line at the time of mismatch are set in reverse. That is, on the one hand, the match line is set to H level precharge and L level discharge when there is a mismatch, and the other is set to L level discharge when the match line is L level precharge and does not match. By short-circuiting the match line of the divided CAM entry, the match line is driven to an intermediate voltage level by redistribution of charges at the time of precharging in the mismatched entry, thereby reducing current consumption.

  Patent Document 5 (Japanese Patent Laid-Open No. 2002-245783) also shows a configuration for reducing current consumption during a search operation. In the configuration disclosed in Patent Document 5, a dummy match line having the same capacity as the entry in the matching state is provided. The match line and the dummy match line are precharged to the ground voltage, and a current is supplied during the search operation. When the voltage level of the dummy match line is determined to be H level, a determination timing signal is generated, and charging to the match line is stopped. Current consumption is reduced by shortening the match line charging period. A differential amplifier circuit is used to determine the voltage level of the match line, and the reference voltage is compared with the match line voltage.

Patent Document 6 (Japanese Patent Laid-Open No. 2001-319481) shows a configuration for reducing current consumption during search operation and for speeding up the search operation. In the configuration disclosed in Patent Document 6, a bit line for data writing / reading and a search line for transferring search data are provided separately. The bit line is precharged to H level, and the search line is precharged to L level. At the time of the search, according to the search data, the search line and the bit line are short-circuited to set the high-level search line to the intermediate voltage level, and the search line voltage amplitude is set to the ground voltage and the intermediate voltage level. The match line is precharged to an intermediate voltage level, and the match line is charged up via a decouple transistor during a search operation. The match line and the sense amplifier are coupled via the decoupled transistor. Even if the sense node at the input node of the sense amplifier is charged, the decoupling transistor suppresses the rise in the voltage on the match line. When there is a mismatch, the sense node is discharged through the match line. By limiting the voltage amplitude of the match line and / or search line, the current consumption is reduced and the search operation speed is increased.
JP-A-10-27481 JP 2004-192695 A JP 2003-100086 A JP 2002-357891 A Japanese Patent Laid-Open No. 2002-245783 JP 2001-319481 A H. Noda, et. Al., "A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture", JSSCC, Vol.40, 2005, pp.245-253.

  As described above, in the content reference memory (CAM, TCAM), the search line and the match line are charged / discharged for each search cycle, and current consumption is large. In Non-Patent Document 1 described above, the match lines have a hierarchical structure, and a search operation is performed in a pipeline manner for each of a plurality of local match line blocks. For a mismatched entry in a certain pipeline stage (local match line block), subsequent discharge of the search line and local match line is stopped to reduce current consumption.

  However, in this Non-Patent Document 1, although a hierarchical structure is used for match lines, search lines are provided in common for all entries. Therefore, a search line with a large load capacity is charged / discharged according to the search data between the power supply voltage level and the ground voltage level, and there is room for improvement in reducing current consumption.

  Further, a search operation is simultaneously performed on each of a large number of search lines and local match lines. For this reason, the simultaneous operation current (peak current) is large, causing a problem that causes switching noise.

  Further, the global match line and the local match line are charged / discharged between the power supply voltage level and the ground voltage level in Non-Patent Document 1 described above. Therefore, there is a problem that the signal amplitude of the local / global match line indicating the coincidence detection result is large, and there is a limit in reducing current consumption and reducing the time until the coincidence result is determined. It is possible to decrease the power supply voltage level and reduce the signal amplitude. However, in this case, there is a lower limit of the power supply voltage level due to the operation speed of the transistor element, and this method has a limitation in speeding up.

  In the configuration disclosed in Patent Document 1, a current at the time of 1 bit miss is generated and supplied to the match line using the same transistor as the CAM cell. The match line is charged through a transistor receiving a reference voltage at the gate, and the voltage rise of the mismatched match line is suppressed to a reference voltage or lower. However, the match line in the coincidence state is charged to the power supply voltage level, causing a problem that the voltage amplitude becomes large. This Patent Document 1 does not show a configuration for setting the voltage amplitude of the match line to be equal to or lower than the intermediate voltage level regardless of the coincidence state and the disagreement state. Further, the influence of the off-leakage current flowing in the entry matching CAM cell on the match line precharge current is not considered.

  In the configuration disclosed in Patent Document 2, the precharge voltage level is set by charge redistribution by capacitive division of the match line with the capacitive element. Therefore, accuracy is required for adjustment of the capacitance value between the match line and the capacitive element, and it is difficult to charge up the match line that is in a matched state to a desired intermediate voltage level accurately. In Patent Document 2, search lines are precharged by short-circuiting complementary search lines to reduce the charge / discharge current of the search lines. However, even in this case, the capacity of the search line is not reduced. Accordingly, since the search line is charged from the intermediate voltage level to the power supply voltage level according to the search data, there is a problem in that the current consumption cannot be reduced when the number of entries increases and the load capacity of the search line increases. Arise.

  In the configuration shown in Patent Document 3, a reference voltage generation circuit and a differential amplifier circuit are provided corresponding to each match line. However, in Patent Document 3, the match line is precharged to the power supply voltage level. Therefore, there is a problem that the voltage amplitude of the match line is large and high-speed search operation and current consumption reduction cannot be realized.

  In the configuration shown in Patent Document 4, the CAM entry is divided, the precharge voltage level is different in the divided entry, and there is a problem that it is difficult to match the operation speeds between the divided entries. Further, in each entry, it is necessary to control the connection of the match lines of the divided entries in accordance with the match / mismatch of the divided entries, which causes a problem that the area occupied by the circuit for performing this connection increases. Furthermore, the voltage amplitude of the match line of each divided entry is the power supply voltage level, which causes a problem that the search operation cannot be performed at high speed. Further, when the number of bits of the search data increases and the number of bits of the CAM cell of the entry increases, the load on the match line increases accordingly, and the precharge current consumption from the intermediate voltage level to the power supply voltage level increases. The problem arises.

  In the configuration disclosed in Patent Document 5, the voltage level of the dummy match line is detected, the determination timing is set, and the match line precharge period is adjusted. However, there is no consideration for limiting the precharge current value. In addition, charging of the match line in the matching state is not stopped, and there is a limit in reducing current consumption during the search operation.

  In the configuration disclosed in Patent Document 6, the voltage amplitude of the search line is set to an intermediate voltage smaller than the power supply voltage due to a short circuit between the search line and the bit line. Therefore, it is necessary to precharge the bit line to the power supply voltage level, resulting in a problem that current consumption cannot be reduced. In addition, the match line and the buffer (sense amplifier) are coupled via a decoupled transistor to charge up the matched match line to the intermediate voltage level and pull up the sense node to the power supply voltage level. Therefore, the discharge speed of the sense node is slow when the search data 1 bit does not match, and there is a problem that the search operation cannot be performed at high speed. In another example, in Patent Document 6, the voltage level of the matched match line is set by redistribution of the charge charges of the capacitive element. Therefore, similarly to the configuration of the above-mentioned Patent Document 2, there arises a problem that it is difficult to adjust the load capacitance of the capacitive element and the match line.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a content reference memory capable of reducing current consumption and performing a search operation at high speed even when the number of bits of search data is large.

  In summary, the content reference memory according to the present invention performs a sensing operation by separating a match line and an amplifier circuit of a match amplifier using an isolation gate. The match line is precharged to a voltage equal to or lower than an intermediate voltage level between the power supply voltage and the ground voltage.

  A content reference memory according to an embodiment of the first aspect of the present invention includes a plurality of entries each having a plurality of content reference memory cells, arranged corresponding to each entry, and referring to the content of the entry corresponding to each entry A plurality of match lines to which memory cells are coupled, a search data bus coupled in parallel to each entry and transferring search data to each entry in parallel, and a plurality of match amplifiers coupled to each match line . Each match amplifier includes a precharge circuit that precharges the corresponding match line to a precharge voltage level that is less than or equal to the intermediate value between the power supply voltage and the ground voltage, and a voltage level that is less than or equal to the precharge voltage. A plurality of match amplifiers including an amplifier circuit that compares a voltage and generates a signal indicating the comparison result, and a separation gate that separates the amplifier circuit and a corresponding match line before activation of the amplifier circuit .

  A content reference memory according to an embodiment of the second aspect of the present invention includes a plurality of entries each having a plurality of content reference memory cells, arranged corresponding to each entry, and referring to the contents of the entry corresponding to each entry A plurality of match lines to which memory cells are coupled, a search data bus coupled in parallel to each entry and transferring search data to each entry in common, and arranged corresponding to each match line and corresponding to the match line Including a matched amplifier. Each match amplifier compares the voltage of the corresponding match line with a reference voltage, generates a signal indicating the comparison result, and precharges the corresponding match line to the ground voltage level after the amplification operation of the amplifier circuit is completed. And a pull-up current supply circuit for supplying a current having a limited current value to the match line corresponding to the inactivation of the precharge circuit.

  A content reference memory according to an embodiment of the third aspect of the present invention includes a plurality of entries each having a plurality of content reference memory cells, arranged corresponding to each entry, and referring to the contents of the entry corresponding to each entry A plurality of match lines to which memory cells are coupled, a search data bus coupled in parallel to each entry and transferring search data in parallel to each entry, and a corresponding match line arranged corresponding to each match line A plurality of match amplifiers coupled to each other. Each match amplifier precharges the corresponding match line to the ground voltage level, and supplies a current having a limited current value to the corresponding match line when the precharge circuit is inactivated. A pull-up current supply / determination circuit that generates a signal having a voltage level corresponding to the voltage level of the match line is included. The current whose current value is limited is smaller than the current flowing through the corresponding match line when a 1-bit content reference memory cell is turned on in one entry, and all the bit content reference memory cells are turned off. Sometimes it is larger than the current flowing through the corresponding match line.

  A content reference memory according to an embodiment of the fourth aspect of the present invention includes a plurality of entries each having a plurality of content reference memory cells, arranged corresponding to each entry, and referring to the contents of the entry corresponding to each entry A plurality of match lines to which memory cells are coupled, a search data bus coupled in parallel to each entry and transferring search data to each entry in parallel, and a corresponding match line arranged corresponding to each match line A plurality of match amplifiers coupled to each other. Each match amplifier has a detection circuit that generates a signal of a voltage level corresponding to the voltage level of the corresponding match line, and a latch that latches a signal corresponding to the voltage level of the match line of the previous match detection cycle from this detection circuit And a charge circuit that selectively supplies a current to a corresponding match line during a search operation according to a latch signal of the latch circuit.

  A content reference memory according to an embodiment of the fifth aspect of the present invention has a plurality of search blocks including a plurality of entries. Each entry is coupled to a plurality of content reference memory cells for storing reference data and the plurality of content reference memory cells, and is driven in a predetermined voltage level direction by the corresponding content reference memory cell according to a match search result with the search data. Including match lines. Each search block further includes a search data bus coupled in common to the plurality of entries and transferring search data. The content reference memory according to the embodiment of the fifth aspect is further provided corresponding to each search block, each of which includes a plurality of search data input circuits for supplying search data to the search data bus of the corresponding search block And an activation control circuit for sequentially activating a plurality of search blocks and a search data input circuit in accordance with a clock signal.

  A content reference memory according to an embodiment of the sixth aspect of the present invention is provided with a plurality of entries each having a plurality of content reference memory cells, corresponding to each entry, and the contents of the entry corresponding to each entry A plurality of match lines to which reference memory cells are coupled, a search data bus coupled in parallel to each entry and transferring search data in parallel to each entry, and a plurality of lines arranged corresponding to each of the plurality of match lines Equipped with a match amplifier. Each match amplifier includes a precharge circuit that precharges the reference voltage node and the corresponding match line, and an amplifier circuit that compares the voltages of the first and second nodes and generates a signal indicating the comparison result. The precharge voltage is a voltage level equal to or lower than an intermediate voltage between the power supply voltage and the ground voltage. The first node of the amplifier circuit receives the voltage of the corresponding match line, and the second node is coupled to the reference voltage node. The match amplifier further includes a separation gate that separates the corresponding match line and reference voltage node from the first and second nodes of the amplifier circuit before activation of the amplifier circuit, and an amplifier circuit after the separation gate is separated. And a capacitive element that boosts the first node according to the boosting instruction signal before activation of the first node.

  A content reference memory according to an embodiment of the seventh aspect of the present invention is provided with a plurality of entries each having a plurality of content reference memory cells, corresponding to each entry, and the contents of the entry corresponding to each entry A plurality of match lines to which reference memory cells are coupled, a search data bus coupled in parallel to each entry and transferring search data in parallel to each entry, and a plurality of lines arranged corresponding to each of the plurality of match lines With a match amplifier. Each of the match amplifiers includes a precharge circuit that precharges a corresponding match line, and an amplifier circuit that compares the voltages at the first and second nodes and generates a signal indicating the comparison result. The precharge voltage is a voltage level equal to or lower than an intermediate voltage between the power supply voltage and the ground voltage. The first node receives the voltage of the corresponding match line. The second node receives a sense reference voltage. The match amplifier further includes an isolation gate that confines charge in the first and second nodes prior to activation of the amplifier circuit. The sense reference voltage is generated by changing the voltage at the precharge voltage level using the capacitive element.

  According to the present invention, a content reference memory that performs a search / determination operation at a high speed with low current consumption is realized.

  Typical effects obtained in the embodiment according to the present invention are as follows. By setting the precharge voltage level of the match line below the intermediate voltage level, the charge / discharge current of the match line can be reduced. In addition, the signal amplitude of the match line is reduced, and a high-speed search operation is possible. By separating the match line and the amplifier circuit of the match amplifier during the search operation and activating the amplifier circuit, it is not necessary to fully swing the match line during the operation of the amplifier circuit. In other words, the match line can be precharged or pulled up from the intermediate voltage level, the signal amplitude of the match line can be reduced, and the current consumption can be reduced. Further, when a cross-coupled latch amplifier is used as the amplifier circuit, the drive capacity of the amplifier circuit is reduced, and a high-speed amplification operation is realized.

  In addition, by supplying a current having a limited current value to the match line, the match line precharged to the ground voltage level can be charged to a predetermined voltage level according to comparison with the search data. In addition, the increased voltage level can be suppressed, and a high-speed search operation and a reduction in current consumption can be realized. Further, the voltage amplitude of the match line in the search mismatch state for charging / discharging the match line can be made smaller than the power supply voltage, and the current consumption can be reduced.

  This limited current value is made smaller than the current flowing from the match line through the entry in the 1-bit miss state and larger than the match line current flowing through the entry in the all-bit non-conduction state. As a result, even when there is a 1-bit miss, it is possible to suppress an increase in the voltage of the match line, and it is possible to compensate for a voltage drop due to a leak current of the match line in the match state. Accordingly, it is possible to reduce the voltage amplitude of the match line and realize a search operation with high speed and low current consumption.

  In addition, by dividing the entry into multiple search blocks and sequentially performing the search operation in each search block, a structure equivalent to the action of dividing the search line is realized, and the charge / discharge current of the search line can be reduced. Fast search operation is possible. Further, by sequentially performing the search operation in this search block, the peak current during the search operation can be reduced, and the influence of switching noise and the like can be suppressed.

  In the case where the charge line is confined and the sense line voltage level is sensed, the match line voltage is changed using the capacitive element. The wiring capacitance connected to the capacitive element is small, and the size of the capacitive element can be reduced and the layout area can be reduced compared to a configuration in which the voltage level of the entire match line is changed using the capacitive element. In addition, the voltage can be changed greatly with a small amount of charge, and the load capacity of the node that performs full swing during the amplification operation is small, so that power consumption can be reduced.

  Further, when the sense reference voltage is generated by changing the precharge voltage using the capacitive element, the precharge voltage level is changed using the charge pump operation (capacitive coupling action) of the capacitive element. In the case of generating by changing the sense reference voltage after charge confinement, the layout area of the capacitive element can be reduced. Further, by generating the sense reference voltage by changing the sense reference voltage using the capacitive element before the charge confinement, the match amplifier does not require a capacitive element for capacitive balancing of the sense nodes, and the layout area can be reduced. Further, even if the amplitude of the sense node (first and second nodes) of this amplifier circuit is fully swinged, the sense node has no capacitive element, and the current consumption required for charging / discharging the sense node can be reduced.

[Embodiment 1]
FIG. 1 schematically shows a whole structure of a content reference memory according to the first embodiment of the present invention. In FIG. 1, the content reference memory includes a memory cell array 1 in which unit cells UC are arranged in a matrix. Memory cell array 1 is divided into a plurality of entries ERY, and each entry ERY is provided with a match line ML to which unit cells UC in the corresponding entry are coupled in parallel. A search line pair SLP for transmitting search data is provided in common for each entry ERY of the memory cell array 1. A unit cell UC is provided corresponding to the intersection of search line pair SLP and match line ML. The unit cell UC has a data storage and retrieval function, the configuration of which will be described later. Various configurations of the unit cell are conceivable. Therefore, here, the name of the unit cell is used instead of the content reference memory cell (CAM cell).

  The content reference memory further includes a coincidence determination circuit 2 provided corresponding to each entry ERY and determining whether the search data matches the stored data of each entry. Match determination circuit 2 includes a match amplifier 10 coupled to a match line. The content reference memory further receives the intermediate voltage generation circuit 6 for supplying the intermediate voltage VML and the comparison reference voltage VREF to the match amplifier 10 of the coincidence determination circuit 2 and the search data SD from the outside, and searches the memory cell array 1. Control for controlling operations of the match determination circuit 2 and the search data input circuit 4 in accordance with the search data input circuit 4 transmitted to the line pair SLP and a command CMD for designating an operation mode from the outside according to the clock signal CLK. Circuit 8 is included.

  The intermediate voltage generation circuit 6 generates an intermediate voltage having a voltage level equal to or lower than the voltage VDD / 2 from the power supply voltage VDD. The intermediate voltage VML and the comparison reference voltage VREF may be at the same voltage level, or the intermediate voltage VML may be at a voltage level higher than the comparison reference voltage VREF. The intermediate voltage VML is used as a precharge voltage for precharging each match line ML via the match amplifier 10. By setting the amplitude of the match line ML to ½ times or less of the power supply voltage VDD, the current consumption is reduced and the search operation is speeded up.

  FIG. 2 is a diagram showing an example of the configuration of the unit cell UC shown in FIG. In FIG. 2, unit cell UC includes an SRAM cell SMC storing 1-bit data, an N channel MOS transistor (insulated gate field effect transistor) TR1 connected in series between match line ML and the ground node, and TR2 and N channel MOS transistors TR3 and TR4 connected in series between match line ML and the ground node are included. MOS transistors TR1 and TR3 have their gates coupled to search lines SL and / SL. MOS transistors TR2 and TR4 have their respective gates coupled to / D and D for the internal storage node of SRAM cell SMC. These internal storage nodes D and / D store complementary data bits. When SRAM cell SMC stores “1”, internal storage node D is at H level and internal storage node / D is at L level. Therefore, in this state, the MOS transistor TR2 is conductive and the MOS transistor TR4 is nonconductive. When the SRAM cell SMC stores data “0”, the reverse state occurs.

  Search lines SL and / SL constitute search line pair SLP shown in FIG. 1, and complementary data is transmitted during the search operation. In unit cell UC shown in FIG. 2, word line and bit line pairs for writing and reading data to and from SRAM cell SMC are provided, but these word lines and bit line pairs are not shown.

  Assume that search data “1” is given when the SRAM cell SMC stores “1” (internal storage node D is at H level) during the search operation. In this case, search line SL is at H level and complementary search line / SL is at L level. Therefore, MOS transistors TR2 and TR3 are nonconductive, and match line ML maintains the precharge voltage level. On the other hand, when the internal storage node D of the SRAM cell SMC is at the H level potential and the search data “0” is transferred to the search line SL, the search line SL is at the L level and the complementary search line / SL is at the H level. Become a level. In this case, MOS transistors TR3 and TR4 are rendered conductive, and match line ML is discharged from the precharge voltage level to the ground voltage level.

  Therefore, when the unit cell UC shown in FIG. 2 is used, it is possible to perform binary determination of coincidence / mismatch of search data and entry storage data. When the unit cells UC of the corresponding entries are coupled in parallel to the match line ML and all the unit cells UC of the entry ERY are in a match state, the match line ML maintains the precharge voltage level. On the other hand, when at least one bit unit cell in the entry is in a mismatched state, the match line ML is discharged through the unit cell in the mismatched state, and the potential of the match line ML drops from the precharge voltage level. Therefore, by amplifying the potential level of the match line ML with the match amplifier 10 of the match determination circuit 2, binary determination for determining match / mismatch between the search data and the stored data of each entry can be performed.

  FIG. 3 is a diagram showing another configuration of the unit cell UC shown in FIG. In FIG. 3, the unit cell UC is different in configuration from the unit cell UC shown in FIG. 2 in the following points. That is, instead of the SRAM cell SMC, the first cell MC1 and the second cell MC2 that can individually set the logical value of the stored data are used as data storage elements. Storage nodes ND1 and ND2 of first cell MC1 and second cell MC2 are coupled to the gates of MOS transistors TR2 and TR4, respectively. Each of the first cell MC1 and the second cell MC2 is realized by a DRAM-type memory cell in Non-Patent Document 1, for example. Data is stored by the charge stored in the capacitor. The other configuration of the unit cell UC shown in FIG. 3 is the same as that of the unit cell UC shown in FIG. 2, and the corresponding parts are denoted by the same reference numerals, and detailed description thereof is omitted.

  Also in FIG. 3, a word line and a bit line for writing / reading data are provided for first cell MC1 and second cell MC2, respectively. However, also in FIG. 3, word lines and bit lines for writing / reading these data are not shown in order to simplify the drawing.

  In the unit cell UC shown in FIG. 3, when complementary data is stored in first cell MC1 and second cell MC2, a search operation with the same logic as unit cell UC shown in FIG. 2 is performed. That is, the match line ML is discharged when there is a mismatch (at the time of a miss), and the match line ML is maintained at the precharge voltage level when there is a match (at the time of a hit).

  When data “0” (L level) is stored in both first cell MC1 and second cell MC2, MOS transistors TR2 and TR4 are both turned off. Therefore, in this state, the match line ML is not discharged regardless of the logical value of the search data, and the match line ML maintains the precharge state. Thereby, a “don't care” state can be realized.

  When data “1” (H level) is stored in both first cell MC1 and second cell MC2, both MOS transistors TR2 and TR4 are turned on. In this case, the match line ML is discharged regardless of the value of the search data. In this state, the stored data of the entry is invalidated regardless of the search data (always inconsistent). In the configuration of the unit cell UC shown in FIG. 3, ternary determination of match (match), mismatch (miss), and arbitrary (don't care) can be performed.

  Regardless of which unit cell UC shown in FIGS. 2 and 3 is used as a CAM (content reference memory) cell, in the event of a miss, the match line passes through the path of MOS transistors TR1 and TR2 or the path of MOS transistors TR3 and TR4. ML is discharged.

  FIG. 4 shows a specific structure of match amplifier 10 of the content reference memory according to the first embodiment of the present invention. In FIG. 4, in the memory cell array 1, (n + 1) entries ERY0 to ERYn are provided. Match lines ML [0] -ML [m] are provided corresponding to the entries ERY0-ERYn, respectively. A plurality of unit cells UC are provided in each of the entries ERY0 to ERYn. The memory cell (CAM cell) CC for data storage provided in each unit cell UC may be the SRAM cell SMC shown in FIG. 2, or may be the memory cells MC1 and MC2 shown in FIG. . In the following description, the CAM cell CC is used as a reference for both the unit cell that performs binary determination and the unit cell that performs ternary determination.

  Match amplifiers 10 are provided corresponding to the entries ERY0 to ERYn, respectively. FIG. 4 representatively shows a configuration of match amplifier 10 provided for entry ERY0. The match amplifier 10 compares the voltage on the corresponding match line ML (ML [0]) with the reference voltage VREF, and latches the output signal of the differential amplifier circuit 12 according to the latch instruction signal LAT. The precharge voltage VML is transmitted to the corresponding match line ML (ML [0]) in response to activation of the latch 16 that generates the search result instruction signal ML_OUT (ML_OUT [0]) and the precharge instruction signal PRE_n. A precharge transistor 14 is included.

  The differential amplifier circuit 12 is different from the differential amplifier 12a in which the positive input (+) is coupled to the corresponding match line ML and the negative input (−) receives the reference voltage VREF in response to the match amplifier activation signal MAE. And an amplifier activation transistor 12b for activating the dynamic amplifier 12a.

  The precharge voltage VML is a voltage level equal to or lower than ½ times the power supply voltage VDD, and the reference voltage VREF is a voltage level lower than the precharge voltage VML (0 <VREF <VML ≦ VDD / 2).

  Search lines SL and / SL are precharged to the ground voltage level during standby, and are selectively driven to the power supply voltage level according to the search data during the search operation.

  FIG. 5 is a timing chart showing the operation of the content reference memory shown in FIG. FIG. 5 shows an operation waveform for one entry. The search operation of the content reference memory shown in FIG. 4 will be described below with reference to FIG.

  In a standby state before time T1, search lines SL and / SL are at ground voltage GND level, and match line ML is also at ground voltage GND level.

  The search operation starts at time T1. As the search operation starts at time T1, precharge instruction signal PRE_n is set to L level, precharge transistor 14 is turned on, and each match line ML (ML [0] -ML [n]) is precharged at an intermediate voltage level. Precharged to voltage VML level. In the precharge period from time T1 to time T2, both search lines SL and / SL are maintained at the ground voltage level.

  At time T2, the precharge operation is completed, the source lines SL and / SL are activated, and the stored data and the search data are compared. In this activation / comparison cycle, precharge instruction signal PRE_n is at the H level, and precharge transistor 14 is turned off. On the other hand, search data is transmitted to search lines SL and / SL, and each is driven to a voltage level corresponding to the bit value of the search data. Thereby, the search operation is performed in parallel in each of the entries ERY0 to ERYn. In accordance with the match / miss (match / mismatch) between the stored data of the CAM cell CC and the search data, the corresponding match line is selectively discharged in each unit cell UC. As shown in FIG. 5, in an entry in which at least one bit unit cell is in a missed state, the match line ML is discharged through the path of MOS transistors TR1 and TR2 or TR3 and TR4 of the unit cell UC in the missed state. The precharge voltage level of match line ML decreases.

  When the voltage level of match line ML is sufficiently expanded at time T3, match amplifier activation signal MAE is activated. Accordingly, a determination cycle starts so as to overlap the data comparison cycle, and the differential amplifier circuit 12 performs a differential amplification operation. That is, a signal corresponding to the potential difference between the reference voltage VREF and the corresponding match line ML is generated from the differential amplifier circuit 12. At time T3, the latch instruction signal LAT also becomes H level, and the match amplifier (MA) output cycle starts in parallel. In this cycle, the latch 16 enters the through state, latches the output signal of the differential amplifier circuit 12, and transmits it to the output node. In FIG. 5, the corresponding entry is in a miss state, and the state of the search result instruction signal ML_OUT (any of ML_OUT [0] -ML_OUT [n]) changes to the ground voltage level.

  When the output signal of latch 16 is confirmed, at time T4, the determination cycle is completed and the search result is output, match amplifier activation signal MAE is deactivated, and latch instruction signal LAT is set to L level. Driven. Search lines SL and / SL are precharged to the ground voltage level again. When the latch instruction signal LAT becomes L level, the latch 16 becomes latched, and the output signal ML_OUT is maintained at L level indicating a miss state.

  Time T1 to T5 is one search cycle. A series of search operations including match line precharge, search line activation, data comparison, determination, and determination result output are sequentially executed in synchronization with the clock signal CLK.

  At time T5, the next search cycle starts again, the precharge instruction signal PRE_n becomes L level, and the match line ML is again precharged to the intermediate voltage level precharge voltage VML level. Although the voltage level of the match line in the coincidence state is slightly lowered due to the off-leakage current of the unit cell of the corresponding entry, the voltage drop amount in the continuous cycle is small and the precharge voltage level is maintained substantially. Here, the “off-leakage current” indicates a current flowing through a non-conducting transistor path (TR1, TR2 and TR3, TR4 path).

  At time T6, the voltage levels of search lines SL and / SL are set again according to the search data, and the stored data and the search data are compared in each entry.

  At time T7, match amplifier activation signal MAE is activated again, and latch instruction signal LAT is driven to the H level. When the search data and the stored data of the entry match (match state), all unit cells UC of the entry are non-conductive, there is no discharge path of the corresponding match line ML, and the match line ML is maintained substantially at the precharge voltage VML level. In response, an H level signal ML_OUT indicating this match state is generated from the latch 16 and latched.

  At time T8, the match amplifier activation signal MAE is deactivated, and the latch 16 enters the latch state. Thereafter, this search cycle is repeatedly executed according to the number of search data.

  As described above, in the configuration shown in FIG. 4, the match line ML changes between the ground voltage GND and the precharge voltage VML, and the potential of the match line ML is compared with the reference voltage VREF. The small-amplitude signal appearing on the match line ML is converted to a full-amplitude (amplitude is the power supply voltage level) signal by the match amplifier 10, and the search result instruction signal ML_OUT is generated. Therefore, in the search cycle, the voltage amplitude of the match line can be reduced, and the charge / discharge current of the match line ML can be reduced. The number of match lines ML in the miss state is sufficiently larger than the number of match lines ML in the match state, and the match line charge / discharge current can be greatly reduced by limiting the amplitude of the match line.

  Further, the differential voltage circuit 12 is used to compare the reference voltage VREF and the voltage of the match line ML, so that a high-speed sensing operation is possible. In entry ERY, in a 1-bit miss state in which a 1-bit unit cell is in a miss state, the current draw of the corresponding match line is delayed. However, the precharge voltage VML of the match line ML is equal to or lower than the intermediate voltage VDD / 2, and even in a 1-bit miss state, the time when the voltage level of the corresponding match line is lower than the reference voltage VREF is quick and matches at a fast timing. The potential level of the line can be determined. As a result, it is possible to realize a content reference memory that can perform a high-speed search with low current consumption.

  FIG. 6 is a diagram showing an example of a specific configuration of differential amplifier circuit 12 and latch 16 shown in FIG. In FIG. 6, differential amplifier 12a of differential amplifier circuit 12 includes an N-channel MOS transistor NQ1 whose gate is coupled to match line ML, an N-channel MOS transistor receiving reference voltage VREF at its gate, and these MOS transistors NQ1. And P channel MOS transistors PQ1 and PQ2 supplying current to NQ2. The sources of MOS transistors NQ1 and NQ2 are commonly coupled to the drain of activation transistor 12b. MOS transistors PQ1 and PQ2 form a current mirror stage. MOS transistor PQ1 has its gate and drain interconnected and acts as a master of the current mirror stage.

  The latch 16 inverts the latch instruction signal LAT, the tri-state inverter buffer BV selectively activated according to the latch instruction signal LAT and the output signal of the inverter IV1, and the output of the tri-state inverter buffer BV. Inverters IV2 and IV3 coupled are included. Inverter IV2 inverts the output signal of tristate inverter buffer BV to generate search result instruction signal ML_OUT. Inverter IV3 inverts the output signal of inverter IV2 and transmits it to the input of inverter IV2. Inverters IV1 and IV2 constitute a so-called inverter latch.

  In differential amplifier circuit 12, currents of the same magnitude flow through MOS transistors PQ1 and NQ1. When the voltage level of match line ML is higher than reference voltage VREF, the amount of current flowing through MOS transistor NQ1 is larger than the amount of current flowing through MOS transistor NQ2. MOS transistor PQ2 supplies a mirror current of the current flowing through MOS transistor PQ1 to MOS transistor NQ2. Therefore, in this case, MOS transistor NQ2 cannot discharge all the current supplied from MOS transistor PQ2, and the output signal of differential amplifier 12a becomes H level.

  When the voltage level of match line ML is lower than reference voltage VREF, the conductance of MOS transistor NQ2 is larger than the conductance of MOS transistor NQ1. In this state, the current supplied from MOS transistor PQ2 is all discharged through MOS transistor NQ2 and activation transistor 12b, and the output signal of differential amplifier 12a is at L level.

  In latch 16, when latch instruction signal LAT is at L level, tristate inverter buffer BV is in an output high impedance state, and its output signal ML_OUT does not change. On the other hand, when latch instruction signal LAT becomes H level, tristate inverter buffer BV operates as an inverter, and further amplifies the output signal of differential amplifier circuit 12. Inverters IV2 and IV3 latch and output the amplified signal.

  Accordingly, the match line ML is precharged to the intermediate voltage VML level by the precharge transistor 14, and even if the signal amplitude of the match line ML is small, the difference between the potential of the match line ML and the reference voltage VREF is different from that of the differential amplifier 12a. If the value is detectable, the sensing operation can be performed at high speed.

  FIG. 7 is a diagram showing an example of the configuration of the control circuit 8 shown in FIG. In FIG. 7, the control circuit 8 decodes the command CMD given in synchronization with the clock signal CLK, and sets the precharge instruction signal PRE_n to the L level for a predetermined period in accordance with the search operation instruction EN from the command decoder 20. And a precharge activation circuit 22 for driving the

  The control circuit 8 further includes a search line drive activation circuit 24 that changes the output logic level triggered by the transition of the clock signal CLK to the L level when the search operation instruction EN is activated, and the search operation instruction EN. Delay circuit 26 delaying one clock cycle period of clock signal CLK, and match amplifier activation circuit 28 generating match amplifier activation signal MAE and latch instruction signal LAT according to the output signal of delay circuit 26 and clock signal CLK.

  The command decoder 20 decodes the given command CMD in synchronization with the rise of the clock signal CLK, and drives the search operation instruction EN to an active state when the command CMD instructs a search operation. Precharge activation circuit 22 is formed of, for example, a gate circuit that receives clock signal CLK and search operation instruction EN, and precharges when clock signal CLK is at H level and search operation instruction EN is at H level. The instruction signal PRE_n is set to L level.

  Search line drive activation circuit 24 is formed of, for example, a T-type flip-flop, and activates its output signal (search line drive enable signal SLEN) triggered by the fall of clock signal CLK when search operation instruction EN is activated. Turn into. Search line activation instruction signal SLEN from search line drive activation circuit 24 is applied to search data input circuit 4. The search data input circuit 4 takes in the search data SD given when the search operation instruction EN is activated, and drives the search line according to the fetched search data SD when the search line drive activation instruction signal SLEN is activated. Search data input circuit 4 maintains both source lines SL and / SL at L level when source line activation instruction signal SLEN is inactivated.

  Match amplifier activation circuit 28 is formed of, for example, a gate circuit that receives the output signal of delay circuit 26 and clock signal CLK, and activates match amplifier when both of clock signal CLK and the output signal of delay circuit 26 are at the H level. Signal MAE and latch instruction signal LAT are maintained at the H level.

  By using the control circuit 8 shown as an example shown in FIG. 7, a match line precharge operation is performed at the start of the search operation, and after completion of the precharge, the search line can be driven according to the search data. Further, at the time of search line driving, match amplifier activation signal MAE and latch instruction signal LAT can be driven to H level for a half clock cycle period in the next cycle of clock signal CLK. Thereby, a control circuit that realizes the timing of the timing control signal shown in FIG. 5 can be realized.

  Note that the circuit that generates the intermediate voltage VML transmitted to the match line generates a voltage whose voltage level is a voltage level that is ½ times or less the power supply voltage VDD and that is higher than the reference voltage VREF. Any circuit can be used. An intermediate voltage generation circuit having an arbitrary configuration can be used as the precharge voltage generation circuit.

  As described above, according to the first embodiment of the present invention, the precharge voltage level of the match line is set to a voltage level equal to or lower than a voltage level equal to or lower than ½ times the power supply voltage, and the match line voltage is precharged. Compared with a reference voltage lower than the voltage, a signal indicating the search result is generated. Therefore, the charge / discharge current of the match line can be reduced, and the signal amplitude of the match line is reduced. As a result, it is possible to detect the match line voltage at high speed, and to realize a content reference memory that operates at high speed and with low current consumption.

[Embodiment 2]
FIG. 8 shows a structure of a main part of the content reference memory according to the second embodiment of the present invention. The configuration of the content reference memory shown in FIG. 8 is different from the content reference memory shown in FIG. 4 in the internal configuration of the latch amplifier 10. That is, the separation gate circuit 30 is provided in the previous stage of the differential amplifier circuit 12. Isolation gate circuit 30 includes isolation gates (charge confinement gates) 30a and 30b that are selectively turned off in accordance with isolation instruction signal MLI. The isolation gate 30a selectively isolates the match line ML and the positive input (plus) of the differential amplifier 12a. The isolation gate 30b blocks transmission of the reference voltage VREF to the negative input (minus) of the differential amplifier 12a. The other configuration of the content reference memory shown in FIG. 8 is the same as the configuration of the content reference memory shown in FIG. 4, and corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted.

  FIG. 9 is a timing chart showing the search operation of the content reference memory shown in FIG. The search operation of the content reference memory shown in FIG. 8 will be described below with reference to FIG.

  The search cycle starts from time T1. At time T1, in synchronization with the rise of the clock signal CLK, the precharge instruction signal PRE_n becomes L level, and each match line ML is precharged to the precharge voltage VML level of the intermediate voltage level.

  Next, at time T2, according to the fall of clock signal CLK, search lines SL and / SL are driven from the previous ground voltage level to the voltage level corresponding to the search data. In the corresponding entry of the match line ML, when the search data and the stored data do not match (miss), the voltage level of the match line ML is lower than the reference voltage VREF.

  At time T3, isolation instruction signal MLI is driven to the L level, and isolation gates 30a and 30b are turned off. In parallel with this, match amplifier activation signal MAE and latch instruction signal LAT are each driven to the H level. Accordingly, the differential amplifier circuit 12 is activated to perform a differential amplification operation, and the latch 16 enters a through state, and a signal corresponding to the output signal of the differential amplifier circuit 12 is generated.

  At time T3, the change in the voltage level of the match line ML and the reference voltage VREF have been transmitted to the positive and negative inputs of the differential amplifier circuit 12 so far. The differential amplifier circuit 12 performs a comparison operation (determination operation) between the transmitted match line voltage and the reference voltage. The match line ML is separated from the differential amplifier circuit 12 by the separation gate circuit 30. Therefore, in this state, it is not necessary to drive search lines SL and / SL according to the search data, and search lines SL and / SL are driven again to the ground voltage level.

  The differential amplifier circuit 12 performs differential amplification of the positive and negative input voltages according to the voltage level corresponding to the electric charge confined by the separation gate circuit 30.

  During the amplification operation of differential amplifier circuit 12, match line ML is separated from differential amplifier circuit 12, and search lines SL and / SL are set to the ground voltage level. Therefore, the charging / discharging operation of the match line ML is stopped and the match line ML is not discharged to the ground voltage GND level.

  At time T4, the data determination operation is completed, and the latch instruction signal LAT becomes L level. Accordingly, the latch 16 enters the latch state, and the signal ML_OUT indicating the comparison result enters the final state. In FIG. 9, a mismatch (miss) state is generated, and an L-level signal ML_OUT is generated.

  At time T5, the search cycle starts again, and the match line ML is precharged. In this case, the voltage level of match line ML is higher than ground voltage GND, and is driven to precharge voltage VML level at high speed. Next, similarly to the previous search cycle, driving according to the search data of the source line, charge confinement by the separation gates 30a and 30b, and amplification operation by the differential amplifier circuit 12 are executed.

  In FIG. 9, in the search cycle starting from time T5, the search data matches the stored data, and an H level signal ML_OUT indicating a match state is generated.

  Separation gates 30a and 30b of these separation gate circuits 30 are used to separate match line ML and differential amplifier circuit 12 during a sense operation (when a match amplifier is operating). As a result, the voltage amplitude of the match line ML can be further reduced, and the current consumption can be further reduced. Also, the precharge operation can be completed at an early timing.

  When the isolation gate circuit 30 is used for sensing (detection operation) in accordance with the charge confinement method, a current mirror type differential amplifier circuit shown in FIG. However, when performing the detection operation according to this charge confinement method, the detection operation can be performed more efficiently and at high speed by using a so-called cross-coupled latch sense amplifier as a differential amplifier circuit.

  FIG. 10 is a diagram showing another configuration of the differential amplifier circuit 12 shown in FIG. FIG. 10 shows a configuration of a match amplifier for match lines ML [i] and ML [i + 1]. The components of the differential amplifier circuit 12 and the latch 16 are the same for each match line. In FIG. 10, reference numerals are typically assigned to match amplifiers provided for the match line ML [i].

  10, differential amplifier 12a includes P-channel MOS transistors PQ3 and PQ4 whose gates and drains are cross-coupled, N-channel MOS transistors NQ3 and NQ4 whose gates and drains are cross-coupled, and an activation P-channel. MOS transistor PQ5 is included. P channel MOS transistor PQ5 couples the power supply node to the source nodes of MOS transistors PQ3 and PQ4 when complementary match amplifier activation signal MAEZ is activated.

  The respective drains of MOS transistors PQ3 and NQ3 and the respective gates of MOS transistors PQ4 and NQ4 are coupled to latch line ML [i] through isolation gate 30a. The gates of MOS transistors PQ3 and NQ4 and the drains of MOS transistors PQ4 and NQ4 commonly receive reference voltage VREF via isolation gate 30b.

  A match amplifier activation transistor 12b is further provided for the differential amplifier 12a. In response to match amplifier activation signal MAE, match amplifier activation transistor 12b couples the sources of MOS transistors NQ3 and NQ4 to ground.

  Latch 16 includes an inverter IV1 receiving latch instruction signal LAT, a tristate inverter buffer BV1 coupled to the drain of MOS transistor PQ3 of differential amplifier 12a and the gate of MOS transistor PQ4, the gate of MOS transistor NQ3, and MOS transistor NQ4. Includes a tri-state inverter buffer BV2 coupled to the drain node. Tristate inverter buffer BV1 is selectively activated in response to the output signal of inverter IV1 and latch instruction signal LAT. Tristate inverter buffer BV2 is selectively activated according to latch instruction signal LAT and the output signal of inverter IV1, but its output is in an open state.

  Latch 16 further includes inverters IV2 and IV3 constituting an inverter latch. These inverters IV2 and IV3 latch the output signal of tristate inverter buffer BV1, and generate search result instruction signal ML_OUT [i].

  In the latch 16 shown in FIG. 10, the tri-state inverter buffer BV2 is provided for the node receiving the reference voltage VREF for the following reason. That is, the load at the time of sensing of the sense nodes ND1 and ND2 of the differential amplifier 12a is the same. The sense nodes ND1 and ND2 have the same load, and the sense operation is accurately performed in the cross-coupled sense amplifier constituting the differential amplifier 12a.

  In differential amplifier circuit 12 shown in FIG. 10, match amplifier activation signals MAE and MAEZ are inactive in the precharge period and search line drive period, and MOS transistor PQ4 and match amplifier activation transistor 12b are inactive. It is in a conductive state. In isolation gate circuit 30a, isolation gates 30a and 30b are conductive. Even in the state where sense nodes ND1 and ND2 are precharged to intermediate voltage VML and reference voltage VREF levels, charge transfer between the reference voltage line and the corresponding match line via the internal node of differential amplifier 12a Is prevented. That is, sense node ND1 is at a voltage level higher than reference voltage VREF, and MOS transistor PQ4 is in an off state. Further, the MOS transistor 12b is in an off state. Therefore, even when MOS transistor NQ4 is turned on, the source node potential becomes reference voltage VREF level, and MOS transistor NQ4 is rendered non-conductive.

  MOS transistor PQ3 receives reference voltage VREF at its gate. Therefore, even if MOS transistor PQ3 is rendered conductive, when its source node rises to precharge voltage VML level, the source and drain voltages become equal and become non-conductive. Similarly, even when MOS transistor NQ3 becomes conductive according to reference voltage VREF, the common source node of MOS transistors NQ3 and NQ4 is charged to reference voltage VREF level by MOS transistor NQ4. Therefore, MOS transistor NQ3 has the same potential at its gate and source, and maintains a non-conductive state. Therefore, sense nodes ND1 and ND2 are maintained at the level of precharge voltage VML and reference voltage VREF, respectively, during the precharge operation.

  Next, a search (data comparison) operation is performed. Even if the potential of match line ML changes according to the search data and the potential of sense node ND1 changes, the voltage level of the common source node of MOS transistors PQ3 and PQ4 remains the precharge voltage VML level, and the common source of MOS transistors NQ3 and NQ4. The node voltage is maintained at the reference voltage VREF level. Accordingly, MOS transistors PQ3, PQ4, NQ3 and NQ4 maintain the non-conductive state. Therefore, sense node ND1 is set to a voltage level corresponding to the potential of match line ML (ML [i]).

  Next, isolation instruction signal MLI is set to L level, isolation gate circuit 30 is set to a non-conductive state, and charges are confined. Further, the match amplifier activation signal MAE is activated. Accordingly, MOS transistor PQ5 and activation transistor 12b are rendered conductive, and a sensing operation (determination operation) is performed. Of the sense nodes ND1 and ND2, the sense node having the higher potential is pulled up to the power supply voltage VDD level by the MOS transistor PQ3 or PQ4. On the other hand, the sense node having the lower potential is discharged to the ground voltage level by MOS transistor NQ3 or NQ4. The differential amplifier 12a is a latch type amplifier circuit. While match amplifier activation signals MAE and MAEZ are in an active state, amplified power supply voltage VDD level and ground voltage level signals are latched at sense nodes ND1 and ND2.

  As shown in FIG. 10, a cross-coupled sense amplifier is used as an amplifier circuit in a match amplifier, and voltage detection is performed by a charge confinement method. As a result, the load on the sense nodes ND1 and ND2 of the differential amplifier 12a is small, and the amplification operation can be performed at high speed. Further, during the amplification operation of the differential amplifier 12a, the separation gate circuit 30 is in a non-conductive state, and each of the match lines ML (M [i]) and ML ([i + 1]) can stop the discharge operation.

  In the second embodiment of the present invention, the same configuration as in the first embodiment can be used as the configuration of the control circuit. That is, in the configuration of control circuit 8 shown in FIG. 7, the search line drive activation circuit activates search line activation signal SLEN during the L level period of clock signal CLK. Isolation instruction signal MLI drives isolation instruction signal MLI to L level for one clock cycle period of clock signal CLK in accordance with the output signal of delay circuit 26 shown in FIG.

  As described above, according to the second embodiment of the present invention, the match amplifier detects the voltage level of the match line according to the charge confinement method. Therefore, the voltage amplitude of the match line can be further reduced, and the match line voltage can be detected at high speed.

[Embodiment 3]
FIG. 11 schematically shows an overall configuration of the content reference memory according to the third embodiment of the present invention. In the content reference memory shown in FIG. 11, the memory cell array 1 is divided into a plurality of entries ERY as in the first and second embodiments. A match line ML is provided for each entry ERY, and a search line pair SLP (search lines SL, / SL) is provided in common for each entry ERY. A search data bus is constituted by a plurality of search line pairs.

  In the coincidence determination circuit 2, a match amplifier 40 is provided corresponding to each entry ERY. The match amplifier 40 has a pull-up function for supplying a pull-up current to a corresponding match line during a data comparison operation. In order to control the pull-up current supply in the match amplifier 40, a bias voltage generation circuit 45 is provided. In accordance with the bias voltage BIAS_P from the bias voltage generation circuit 45, the match amplifier 40 supplies a pull-up current whose current value is limited to the corresponding match line ML.

  The intermediate voltage generation circuit 42 generates a precharge voltage VML and supplies it as a comparison determination reference voltage to the match amplifier 40 in the match determination circuit 2. Therefore, in this case, the reference voltage VREF is not used. The precharge voltage VML is used as a precharge voltage for the match line and is also used when determining the voltage level of the match line, thereby reducing the layout area and current consumption of the intermediate voltage generation circuit.

  In this content reference memory, similarly to the first and second embodiments, search data input circuit 4 and control circuit 8 are provided, and each internal operation cycle of the search cycle is set under the control of control circuit 8. (Based on the clock signal CLK).

  FIG. 12 is a diagram showing a specific configuration of match amplifier 40 shown in FIG. FIG. 12 also representatively shows a configuration of a match amplifier provided for match line ML [0]. Match amplifiers of the same configuration are provided for the other match lines.

  The match amplifier 40 shown in FIG. 12 is different in configuration from the match amplifier shown in FIG. 8 in the following points. That is, P channel MOS transistors PQ10 and PQ11 are provided in series between the power supply node and the corresponding match line ML (ML [0]). Bias voltage BIAS_P is applied to the gate of MOS transistor PQ10, and pull-up instruction signal MLPU_n is applied to the gate of MOS transistor PQ11. The other configuration of the match amplifier 40 shown in FIG. 12 and the configuration of each entry ERY (ERY0-ERYn) are the same as those shown in FIG. 8, and corresponding portions are denoted by the same reference numerals, and will be described in detail. Is omitted.

  The MOS transistor PQ10 supplies a constant current according to the bias voltage BIAS_P. This current is smaller than the 1-bit extraction current In flowing through the unit cell when the 1-bit unit cell is turned on in one entry, and all the unit cells of the corresponding entry are turned off. Is larger than the leakage current IOFF.

  Here, the 1-bit drawing current In indicates a current that flows through a series body of conducting transistors of a unit cell in a missed state, and does not include a leakage current in the path of the non-conducting transistor. The off-leakage current Ioff indicates a leakage current that flows through the unit cell in the match state. In a unit cell in a miss state, a 1-bit extraction current In and an off-leakage current flow. However, this 1-bit drawing current In is sufficiently larger than the current flowing through the series body of MOS transistors (TR1, TR2 or TR3, TR4) which are both non-conductive. Also, the combined resistance value of the non-conducting MOS transistors in the unit cell (TR1, TR2) in the missed unit cell is larger than the resistance value of the serial unit of the MOS transistors in the matched unit cell, and its leakage The current is sufficiently smaller than the off-leakage current Ioff. In the following description, unless otherwise specified, the 1-bit miss current Imiss including an off-leak component is treated as having the same magnitude as the 1-bit extraction current In. The 1-bit miss current Imiss is a current that flows through the unit cell in the miss state.

  A precharge voltage VML is used as a comparison reference voltage for detecting the voltage level on the match line. As the differential amplifier circuit 12, either the current mirror type differential amplifier circuit shown in FIG. 6 or the cross-coupled differential amplifier circuit (cross-coupled latch sense amplifier) shown in FIG. 10 may be used.

  FIG. 13 is a timing chart showing the search operation of the content reference memory shown in FIG. The search operation of the content reference memory shown in FIG. 12 will be described below with reference to FIG.

  The search cycle starts at time T1. When this search cycle starts, the precharge instruction signal PRE_n is driven to the L level, and the precharge transistor 14 becomes conductive. Responsively, match line ML is charged and its voltage level is driven to precharge voltage VML level which is an intermediate voltage level.

  When the precharge operation is completed, the precharge instruction signal PRE_n becomes inactive at time T2. Next or in parallel, search lines SL and / SL are driven to the power supply voltage level and the ground voltage level according to the search data. At this time, the pull-up instruction signal MLPU_n becomes L level. Responsively, MOS transistor PQ11 conducts, and pull-up current Ip is supplied from power supply node to corresponding match line ML via MOS transistors PQ10 and PQ11. This pull-up current Ip is smaller than the 1-bit extraction current In and larger than the all-bit off-leakage current IOFF. Therefore, in the entry, when the search data and the stored data do not match (miss), the corresponding match line ML is discharged, and the voltage level thereof becomes lower than the precharge voltage VML. In the match line in the coincidence state, the voltage drop due to the off-leakage current is compensated by the pull-up current, and the voltage level rises (this will be described later).

  Next, at time T3, the activation period of search lines SL and / SL is completed. In addition, the pull-up current supply period is completed, the pull-up instruction signal MLPU_n becomes H level, and the pull-up current supply to the match line is stopped. At time T3, the determination cycle starts, separation instruction signal MLI is at L level, match amplifier activation signal MAE is activated, and latch instruction signal LAT is at H level. Therefore, at the sense node (+, −) of differential amplifier circuit 12, the corresponding match line voltage and precharge voltage VML are confined, and differential amplifier circuit 12 performs a differential amplification operation on the voltage of the sense node. It is. At the time of a miss, the output signal of the differential amplifier circuit 12 becomes the ground voltage level L level, and the search result instruction signal ML_OUT becomes L level via the latch 16.

  When the period of data comparison and latch amplifier output is completed at time T4, match amplifier activation signal MAE and latch instruction signal LAT are driven to L level. Accordingly, the latch 16 is in a latched state and the differential amplifier circuit 12 is in an inactive state. At this time, isolation instruction signal MLI is at L level, and isolation gate circuit 30 is non-conductive. In this state, the search operation is completed, and search lines SL and / SL are both at the ground voltage level. Accordingly, there is no discharge path of the match line ML, and there is only an off-leakage current of the entry unit cell UC. Thereby, the match line substantially maintains the voltage level at time T3 in the period from time T3 to T5.

  When the next search cycle starts at time T5, the precharge instruction signal PRE_n again becomes L level, and the match line ML is driven to the precharge voltage VML level.

  Next, at time T6, a voltage level is set according to the search data of search lines SL and / SL. In addition, pull-up current Ip is supplied to match line ML by activation of pull-up instruction signal MLPU_n. When the search data and the stored data of the corresponding entry match, the match line ML has an off-leakage current IOFF (m · Ioff; m in the entry) of all bits of the unit cell UC in the corresponding entry. Only the number of unit cells). This all bit off-leakage current IOFF is compensated by the pull-up current Ip (IOFF <In), and the voltage level of the match line ML in the coincidence state (match state) is increased by the pull-up current Ip.

  At time T7, match amplifier activation signal MAE is activated, and separation instruction signal MLI becomes L level. Accordingly, isolation gate circuit 30 is turned off, and the amplification operation by differential amplifier circuit 12 is executed in the charge confined state. In the match state, the search result instruction signal ML_OUT from the latch 16 becomes the H level of the power supply voltage level.

  The voltage level of the match line ML in the match state is higher than the precharge voltage VML. In the next search cycle, the match line ML whose voltage level has been increased is driven to the precharge voltage VML level by the precharge operation by the precharge transistor 14 (the intermediate voltage generating circuit 42 for generating the intermediate voltage VML (FIG. 11)), it is only necessary to provide a structure for discharging the increased potential when the potential increases. Thereby, even when the voltage level of the match line ML is higher than the precharge voltage VML, the precharge voltage VML can be reliably set by executing the precharge.

  Further, the pull-up operation of the match line ML by the MOS transistor PQ10 can be stopped after the separation gate circuit 30 is shut off and the electric charge is confined. Therefore, even if this match line ML is in a match state, it does not fully swing to the power supply voltage VDD level, and current consumption can be reduced.

  FIG. 14 is a diagram showing an example of the configuration of bias voltage generation circuit 45 shown in FIG. In FIG. 14, the bias voltage generation circuit 45 includes a replica entry 50 having the same configuration as a path for discharging a match line of one entry ERY. The replica entry 50 includes the same number of replica unit cells as the unit cells UC included in the entry ERY in the memory cell array, one replica unit cell UCs is set in a miss state, and the remaining replica unit cells UCh are in a match state. Set to Replica unit cells UCs and UCh are coupled to a common replica match line RML. Current is supplied to replica match line RML via diode-connected P channel MOS transistor P60. This P-channel MOS transistor P60 functions as a current / voltage conversion element that generates a bias voltage BIAS_P at its gate.

  Replica unit cells UCs and UCh are transistors N61, N62, N63 of the same size (ratio of channel width to channel length) as transistors TR1, TR2, TR3 and TR4 of the match line discharge path in unit cell UC of entry ERY, respectively. N64 has the same current magnitude. In replica unit cell UCs in the miss state, MOS transistors N61 and N62 are set in a non-conductive state, and MOS transistors N63 and N64 are set in a conductive state.

  Therefore, in the missed replica unit cell UCs, a current having a magnitude equal to the 1-bit drawing current In of the unit cell UC is discharged from the replica match line RML to the ground node. In replica unit cell UCh, one of MOS transistors N61 and N62 is set to an off state and the other is set to a conductive state, and one of MOS transistors N63 and N64 is set to a conductive state and the other is set to a nonconductive state. In this discharge path, one MOS transistor is set in a non-conductive state and one is set in a conductive state, thereby realizing the same state as the match state in the unit cell UC of the entry ERY. In this match state, in unit cell UC, one of MOS transistors TR1 and TR2 is non-conductive, and one of MOS transistors TR3 and TR4 is non-conductive. As a result, a current having the same magnitude as the off-leakage current Ioff in the unit cells UC is discharged in these replica unit cells UCh.

  Therefore, a current In + (m−1) · Ioff is supplied from the MOS transistor P60. Here, m represents the total number of replica unit cells UCh and UCs in the replica entry, that is, the number of unit cells in one entry ERY.

  The size of MOS transistor P60 is set larger than the size of MOS transistor PQ10 (ratio of channel width to channel length). Therefore, current Ip flowing through MOS transistor PQ10 is smaller than the current flowing through the match line corresponding to the entry in the 1-bit miss state. By using the replica entry 50, the 1-bit replica unit cell UCs is set to the miss state, and the remaining replica unit cells UCh are set to the match state, so that the match line flows through the replica match line RML when 1 bit misses. A current having the same magnitude as the current can be passed.

  By forming a current mirror circuit with the MOS transistors P60 and PQ10 and adjusting their transistor sizes (current supply capability), it is ensured that the match line ML is smaller than the 1-bit extraction current In and all bits are off. A current larger than the leakage current IOFF can be supplied. Thereby, the comparison search operation can be performed using the precharge voltage VML as the comparison reference voltage.

  In the above description, a current smaller than the 1-bit drawing current In is passed as the match line pull-up current Ip. However, the current value of this pull-up current may be limited so as to be smaller than the current Imiss flowing through the match line when one bit misses (the bias voltage generating circuit shown in FIG. The bias voltage BIAS_P is generated so as to supply

[Example of change]
FIG. 15 shows a configuration of a modification of the third embodiment of the present invention. The content reference memory shown in FIG. 15 differs from the content reference memory shown in FIG. 14 in the following points. That is, in each of the match amplifiers 40, capacitive elements CQ (CQ0, CQ1,...) Are provided on the opposite side of the differential amplifier circuit 12 adjacent to the separation gate 30b of the separation gate circuit 30. A common precharge voltage VML is supplied to these capacitive elements CQ through a P channel MOS transistor 55 which is selectively turned on in accordance with a precharge instruction signal PRE_n. The other configuration of the content reference memory shown in FIG. 15 is the same as that of the content reference memory shown in FIGS. 12 and 14, and the corresponding parts are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the configuration of the content reference memory shown in FIG. 15, MOS transistors 14 and 55 are turned on when precharge instruction signal PRE_n is activated. Therefore, in parallel with the precharge operation to the precharge voltage VML level for the match line ML (ML [0] -ML [n]), the precharge voltage VML is applied to the capacitive element CQ (CQ0, CQ1,...). Supplied. When the precharge instruction signal PRE_n is inactivated, the charging voltage VML_i of the capacitive element CQ (CQ0, CQ1,...) Is the same voltage level as the precharge voltage level of the match line when the precharging is completed. During the search operation, the precharge voltage VML_i of the capacitive element CQ (CQ0, CQ1,...) Is confined by the isolation gate circuit 30 and is used as the comparison reference voltage VML_ref to compare the potential with the corresponding match line. During the operation of the differential amplifier circuit 12, the comparison reference voltage VML_ref can be maintained at a voltage level substantially equal to the precharge voltage level of the match line. Even if the voltage level of the precharge voltage VML generated from the intermediate voltage generation circuit in the memory fluctuates, the precharge voltage level at the time of precharge can be reliably used as the comparison reference voltage in each search cycle. . Thereby, a sufficient margin can be ensured during the amplification operation (sense operation) of the differential amplifier circuit 12.

  Even if the voltage level of the precharge voltage VML generated from the intermediate voltage generation circuit is reduced by the precharge operation, the voltage level is restored to the original voltage level (the voltage level restoration method depends on the configuration of the intermediate voltage generation circuit). Can be considered). Therefore, there is a possibility that the precharge voltage VML when the precharge is completed is different from the voltage level of the precharge voltage VML when the sense operation (differential amplification operation) is started. However, by holding the precharge voltage VML when the precharge is completed in the capacitive element CQ (CQ0, CQ1,...), The comparison reference voltage VML_ref is surely set to the same voltage level as the precharge voltage level of the match line. Can be set.

  Further, since the signal lines 57 are provided in common for these capacitive elements CQ0, CQ1,... And the precharge voltage VML transistor 55 is shared by the match amplifiers 40, the comparison reference voltage levels in the match amplifiers 40 may be the same. it can. Thus, during the determination cycle, the differential amplifier operation can be performed accurately using the comparison reference voltage at the same level in the match amplifier 40, and the shift of the determination result determination timing can be reduced.

  As described above, according to the third embodiment of the present invention, the same voltage level as the precharge voltage is used as the comparison reference voltage. Therefore, the layout area and power consumption of the internal voltage generation circuit can be reduced. Also, by supplying a pull-up current when the match line is activated, the voltage level of the match line can be reliably set to a voltage level higher or lower than the precharge voltage level according to the search result. The search determination operation can be performed accurately. Further, by using the isolation gate circuit 30, the match line pull-up period can be shortened, the potential amplitude of the match line can be reduced, and current consumption can be reduced.

  Further, the precharge voltage when the match line precharge is completed is held in the capacitor element. Therefore, the determination operation can be performed using the precharge voltage level of the match line as the comparison reference voltage, and the determination operation with a large noise margin can be performed.

In addition, the same effects as in the first to third embodiments can be obtained.
[Embodiment 4]
FIG. 16 shows a structure of a main portion of the content reference memory according to the fourth embodiment of the present invention. The content reference memory shown in FIG. 16 differs from the content reference memory shown in FIG. 15 in the following points. In other words, for each match line ML (ML [0] -ML [n]), a discharge N-channel MOS transistor 60 is provided for discharging the corresponding match line to the ground voltage level in response to discharge instruction signal DIS. . The other configuration of the content reference memory shown in FIG. 16 is the same as that of the content reference memory shown in FIG. 15, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 17 is a timing chart showing the search operation of the content reference memory shown in FIG. The operation of the content reference memory shown in FIG. 16 will be described below with reference to FIG.

  The search cycle starts at time T1. At the start of the search cycle from time T1, precharge instruction signal PRE_n is first activated. Accordingly, match line ML (ML [0] -ML [n]) is precharged to a precharge voltage VML at an intermediate voltage level via corresponding precharge transistor 14.

  At time T2, search line activation and pull-up operation are performed, pull-up instruction signal MLPU_n is activated, and search data is transmitted to search lines SL and / SL. When the corresponding entry is in a miss state, the same operation as in the third and fourth embodiments is performed. That is, the match line ML is discharged through the unit cell in the miss state, and the voltage level thereof drops from the precharge voltage VML.

  At time T3, the search line activation and the pull-up operation are completed, and data detection and detection result output are performed. That is, at time T3, pull-up instruction signal MLPU_n is driven to the H level, and search lines SL and / SL are both driven to the ground voltage level. In addition, match amplifier activation signal MAE is activated, and latch instruction signal LAT is set to H level. Discharging of match line ML is completed, and separation gate circuit 30 is turned off in response to separation instruction signal MLI. The differential amplifier circuit 12 performs a differential amplification operation according to the charge confinement method, and the latch 16 generates the output ML_OUT. At the time of a miss, this search result instruction signal ML_OUT is at the ground voltage level.

  When search result instruction signal ML_OUT is in a definite state, at time T4, discharge instruction signal DIS is activated, match amplifier activation signal MAE is deactivated, and latch instruction signal LAT is at L level. Thus, the latch 16 is in a latched state. At this time, the separation gate circuit 30 is in a cut-off state. Match line ML is discharged through MOS transistor 60 to the ground voltage level.

  At time T5, the next search cycle is started, and match line ML is driven from the ground voltage level to the precharge voltage VML level in accordance with activation of precharge instruction signal PRE_n. Thereafter, at time T6, the search line is activated and a pull-up current is supplied. The voltage level of the match line ML in the match state is raised above the precharge voltage VML level by this pull-up current.

  At time T7, a data search result determination and a result output cycle are performed. In this cycle, isolation gate circuit 30 enters a cutoff state in response to the L level of isolation instruction signal MLI. Match amplifier activation signal MAE is activated, and latch instruction signal LAT attains an H level. Search result instruction signal ML_OUT is driven to an H level indicating a match state.

  When the comparison result determination and the search result output are completed at time T8, match amplifier activation signal MAE is deactivated, latch instruction signal LAT becomes L level, and search result instruction signal ML_OUT is in the latch state of H level. Maintained. At time T8, discharge instruction signal DIS again attains H level, discharge transistor 60 is turned on, and each match line ML is discharged. The voltage level of match line ML in the match state is higher than precharge voltage VML, and is driven to a voltage level lower than precharge voltage VML by discharging (ground voltage level in FIG. 17).

  By the precharge at the time of the search cycle from the next time T9, the match line ML in the match state is driven to the precharge voltage VML level.

  Note that, as indicated by the one-dot chain line in FIG. 17, when discharge instruction signal DIS is generated in the form of a one-shot pulse, the match line ML in the match state stops discharging at a voltage level higher than ground voltage GND. It may be configured as follows. In the next search cycle, the match line in the match state is precharged from the voltage level between precharge voltage VML and ground voltage GND to the precharge voltage level.

  By using the discharge transistor 60, the precharge operation of the match line ML is always in a charging direction, that is, a pull-up operation. Therefore, in the intermediate voltage generating circuit for generating the precharge voltage VML, it is not necessary to provide a configuration for discharging the voltage level of the precharge voltage VML and maintaining it at a predetermined voltage level, and the circuit configuration is simplified. For example, a circuit for generating the precharge voltage VML can be realized by using a circuit configuration similar to that of the comparison circuit and the feedback type internal voltage down converter (VDC) of the current drive transistor. Alternatively, a circuit configuration in which the gate potential of the source follower transistor is maintained at a predetermined voltage level using the source follower mode operation of the N channel MOS transistor is used as a circuit for generating the precharge voltage VML. be able to.

  In this case, in the feedback control type circuit, it is not necessary to provide a circuit for reducing the voltage level when the voltage level of the intermediate voltage VML is increased. When a source follower transistor is used, it is not necessary to provide a source follower transistor (P channel MOS transistor) that discharges the precharge voltage VML as a source follower MOS transistor. Therefore, the circuit configuration is simplified, and the current consumption of the circuit that generates the precharge voltage VML can be reduced.

  FIG. 18 schematically shows a configuration of a control circuit used in the fourth embodiment. In FIG. 18, the control circuit 8 decodes the command CMD from the outside in synchronization with the clock signal CLK, and the precharge activation signal PRE_n according to the search operation instruction EN and the clock signal CLK from the command decoder 20. And a precharge activation circuit 22 for generating.

  Control circuit 8 further includes a search line drive activation circuit 64 for generating search line activation signal SLEN, a delay circuit 26 for delaying search operation instruction signal EN, and a match amplifier activation in accordance with an output signal of delay circuit 26. A match amplifier activation circuit 65 for generating signal MAE and latch instruction signal LAT, and a discharge control circuit 68 for generating a discharge instruction signal in accordance with the output signal of delay circuit 26 are included.

  Search line drive activation circuit 64 maintains search line activation signal SLEN for activating the search line in the active state during the L level of clock signal CLK when search operation instruction EN is activated.

  The delay circuit 26 delays the search operation instruction EN by one clock cycle period. Match amplifier activation circuit 66 drives match amplifier activation signal MAE and latch instruction signal LAT to H level when clock signal CLK is at H level when the output signal of delay circuit 26 is activated.

  Discharge control circuit 68 activates discharge instruction signal DIS in synchronization with the fall of clock signal CLK in accordance with the output signal of delay circuit 26.

  The discharge control circuit 68 may drive the discharge instruction signal DIS to the L level while the clock signal CLK is at the L level, and in the form of a one-shot pulse in synchronization with the fall of the clock signal CLK. Discharge instruction signal DIS may be driven to the H level (corresponding to the dashed line waveform in FIG. 17).

  As described above, according to the fourth embodiment of the present invention, each match line is provided with a discharge transistor that drives the corresponding match line to the ground voltage level when the search operation is completed. Therefore, the precharge voltage generation circuit can be configured by a charge-type circuit, the circuit configuration is simplified, and current consumption can be reduced.

In addition, the same effects as in the first to third embodiments can be obtained.
[Embodiment 5]
FIG. 19 shows a structure of a main part of the content reference memory according to the fifth embodiment of the present invention. The content reference memory shown in FIG. 19 differs from the content reference memory shown in FIG. 15 in the following points. That is, in match amplifier 40, P-channel MOS transistors PQ70 and PQ11 and capacitive element 70 are provided as pull-up current supply sources for match line ML (ML [0]-(ML [n]). Transistor PQ70 is turned on in response to charge instruction signal CHA_n, and capacitive element 70 is charged to power supply voltage VDD level through conductive P-channel MOS transistor PQ70. It is supplied to corresponding match line ML via P channel MOS transistor PQ11 which is selectively turned on in accordance with up instruction signal MLPU_n.

  The other configuration of the content reference memory shown in FIG. 19 is the same as that of the content reference memory shown in FIG. 15, and corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted.

  FIG. 20 is a timing chart showing the search operation of the content reference memory shown in FIG. Hereinafter, the search operation of the content reference memory shown in FIG. 19 will be described with reference to FIG.

  A search cycle for performing a search operation starts from time T1. At the start of this search cycle, first, the precharge instruction signal PRE_n is activated. Accordingly, precharge MOS transistor 14 is turned on, and each match line ML is precharged to precharge voltage VML level.

  At time T2, the search line is activated. In parallel with the activation of the search line, pull-up instruction signal MLPU_n is set to L level. Responsively, MOS transistor PQ11 conducts, and the charge charge of capacitive element 70 is supplied to each match line, and its voltage level rises. When the match line ML is in a miss state, as shown in FIG. 19, the 1-bit drawing current In flows through the 1-bit unit cell UC in the miss state in the entry, and the voltage level decreases.

  During the pull-up operation of the match line ML, the charge of the capacitive element 70 is simply supplied to each match line. When the match line is pulled up, the power supply node and the match line are separated. Therefore, the pull-up current is prevented from flowing from the power supply node to the ground node, and current consumption is reduced.

  At time T3, the match line pull-up operation is completed and the activation of the search line is completed, and the search result is determined and read out. That is, at time T3, pull-up instruction signal MLPU_n is driven to H level, and separation instruction signal MLI is set to H level, and separation gate circuit 30 is turned off. Thereby, according to activation of match amplifier activation signal MAE, each differential amplifier circuit 12 performs differential amplification operation according to the charge confinement method. After this amplification operation, a signal ML_OUT indicating the determination result is output via the latch 16.

  In parallel with the amplification operation of the differential amplifier circuit 12, the charge instruction signal CHA_n is activated, and the capacitor element 70 is charged.

  At time T4, match amplifier activation signal MAE is deactivated, and latch instruction signal LAT is driven to L level. In response, latch 16 is latched and one search cycle is completed.

  In the search cycle starting from time T5, an operation when the match line ML is in the match state is performed. In this case, after the precharge operation by the precharge transistor 14 is completed, when the charge of the capacitive element 70 is supplied to the match line ML via the MOS transistor PQ11 at time T6, the voltage level of the match line ML is charged. Maintained at a voltage level. When the match line ML is in a match state, the increased voltage level is set simply by redistribution of the charge charges of the capacitive element 70. The voltage level is set according to the capacitance ratio of the capacitance value of the capacitive element 70 and the load capacitance of the match line ML, and the voltage amplitude of the match line can be made sufficiently small.

  When the activation of search lines SL and / SL and the pull-up operation of the match line are completed, isolation instruction signal MLI becomes L level and isolation gate circuit 30 enters the cutoff state at time T7. Next, the match amplifier activation signal MAE is activated, and the differential amplifier circuit 12 performs an amplification operation. Next, the latch instruction signal LAT becomes H level, and the latch 16 generates an H level signal ML_OUT indicating a match state. At this time, the charging operation of capacitive element 70 is also performed through MOS transistor PQ70.

  Match line ML is maintained at the voltage level charged through capacitive element 70 in the cycle from the previous time T6. Match line ML is set to precharge voltage VML at an intermediate voltage level by a circuit that generates precharge voltage VML during a precharge operation in the next search cycle starting from time T9. Therefore, the timing of charging the capacitive element 70 may be a period when the pull-up instruction signal MLPU_n is at the H level. The amount of charge required to charge the capacitive element 70 may be an amount of charge that causes the corresponding match line ML to increase in voltage to a voltage level detectable by the differential amplifier circuit 12. Therefore, the charging period of the capacitor 70 can be sufficiently accommodated in one search cycle.

  As a circuit for generating charge instruction signal CHA_n, in the configuration of control circuit 8 shown in FIG. 18, charge instruction signal CHA_n is activated from match amplifier activation circuit 66 at the same timing as match amplifier activation signal MAE. Any configuration may be used. Alternatively, the charge instruction signal CHA_n may be activated at the same timing as the discharge instruction signal for discharging the previous match line to the ground voltage level.

  In the configuration shown in FIG. 19, similarly to the configuration shown in FIG. 16, each match line ML has a discharge transistor (60) for discharging the corresponding match line ML to the ground voltage level in accordance with the discharge instruction signal (DIS). It may be provided. In this case, the circuit that generates the precharge voltage VML is only required to charge the match line. Therefore, the configuration of the intermediate voltage generating circuit for generating this precharge voltage VML is simplified, and the configuration of the intermediate voltage generating circuit is simplified and the current consumption is reduced as in the fourth embodiment.

  As described above, according to the fifth embodiment of the present invention, the charge of the capacitive element is used during the search operation and when the match line is pulled up. Therefore, when this match line is pulled up, the path through which current flows from the power supply node to the ground node is cut off, and current consumption can be reduced. Further, the same effects as those of the first to fourth embodiments are obtained.

[Embodiment 6]
FIG. 21 shows a structure of a main part of the content reference memory according to the sixth embodiment of the present invention. The content reference memory shown in FIG. 21 differs from the content reference memory shown in FIG. 14 in the following points. That is, no separation gate circuit is provided for the differential amplifier circuit 12. A reference voltage VREF is always applied to the negative input of the differential amplifier. Match line ML is always coupled to the positive input of the differential amplifier. In match amplifier 40, P channel MOS transistors PQ10 and PQ72 for charging the match line are connected in series between the power supply node and match line ML. An N channel MOS transistor 60 is provided between match line ML and the ground node to discharge match line ML to the ground voltage level. Discharge instruction signal DIS is applied to the gates of MOS transistors PQ72 and 60. Bias voltage BIAS_P is applied to the gate of P channel MOS transistor PQ10. The bias voltage BIAS_P is supplied from an intermediate voltage generation circuit 45 having the same configuration as that shown in FIG.

  The configuration of the intermediate voltage generation circuit 45 is the same as that of the intermediate voltage generation circuit shown in FIG. 14, and the corresponding parts are denoted by the same reference numerals and detailed description thereof is omitted. Further, the configuration of the unit cell UC of the entry ERY in the memory cell array and the other configuration of the latch amplifier 40 are the same as the configuration of the content reference memory shown in FIG. 14, and the corresponding parts are denoted by the same reference numerals, Detailed description is omitted.

  In the configuration shown in FIG. 21, in intermediate voltage generation circuit 45, in replica entry, 1-bit unit cell UCs is in a miss state, and the remaining unit cells UCh are in a match state. Therefore, the sum of 1-bit extraction current In and off-leak current (m−1) · Ioff flows from MOS transistor P60 to replica match line RML. Here, m indicates the total number of replica unit cells UCh and UCs. The size of the MOS transistor P60 is larger than the size of the MOS transistor PQ10. Therefore, the current Ip flowing through the MOS transistor PQ10 is set to a current level smaller than the current In + (m−1) · Ioff flowing through the match line when the 1-bit drawing current In, the 1-bit miss current Imiss, or the 1-bit miss occurs. The reference voltage VREF is set to a voltage level equal to or lower than VDD / 4.

  FIG. 22 is a timing chart showing a search operation of the content reference memory shown in FIG. The search operation of the content reference memory shown in FIG. 21 will be described below with reference to FIG.

  Before time T1, discharge instruction signal DIS is at the H level. MOS transistor 60 is conductive, and match line ML is maintained at the level of ground voltage GND. At this time, MOS transistor PQ72 is non-conductive, and the pull-up operation of match line ML is stopped.

  At time T1, the search operation cycle starts. Since the match line ML is precharged to the ground voltage level during the search cycle, the search lines SL and / SL are driven to a voltage level corresponding to the search data simultaneously with the start of the search cycle. At the start of this search cycle, discharge instruction signal DIS goes to L level, MOS transistor 60 is turned off, and MOS transistor PQ72 is turned on. Accordingly, pull-up current Ip is supplied to each match line ML via MOS transistors PQ10 and PQ72, and the voltage level rises. At this time, since the discharge current is larger than the pull-up current Ip in the missed match line ML, the voltage level is lowered.

  At time T3, match amplifier activation signal MAE is activated, and latch instruction signal LAT is similarly set to the H level (shown in FIG. 22) to determine the voltage level of match line ML and output the determination result. When a miss occurs, the signal ML_OUT from the latch 16 is set to L level.

  When the search result determination and output are completed at time T4, the match amplifier activation signal MAE is deactivated and the differential amplification operation of the differential amplifier circuit 12 is stopped. Further, the latch instruction signal LAT becomes L level, and the latch 16 enters the latched state. At time T4, discharge instruction signal DIS is driven to the H level in accordance with deactivation of match amplifier activation signal MAE. Accordingly, supply of pull-up current Ip is stopped, and match line ML is discharged to the ground voltage level.

  On the other hand, in the search cycle starting from time T5, the states of search lines SL and / SL are set again according to the next search data. Further, the precharge operation of match line ML is completed, and accordingly pull-up current Ip is supplied from MOS transistors PQ10 and PQ72. When the match line ML is in a match state, there is no discharge path of the match line ML, and its voltage level rises due to the pull-up current Ip.

  When the potential of match line ML becomes sufficiently higher than reference voltage VREF at time T7, match amplifier activation signal MAE is activated, and the search result is determined and the result is output. Even during the search result determination and output, the pull-up current Ip is supplied and the voltage level of the match line ML rises.

  At time T8, the search result determination and output operation are completed, and match amplifier activation signal MAE is deactivated. Discharge instruction signal DIS is driven to the H level, supply of pull-up current Ip to match line ML is stopped, and match line ML is discharged to the ground voltage level.

  In the content reference memory shown in FIG. 21, the precharge transistor (14) shown in FIG. 14 is not used. Therefore, there is no need to perform precharge operation for multiple match lines at the start of the search cycle (only supply of pull-up current with limited current value), and transient current due to simultaneous precharge of multiple match lines is reduced. can do.

  Reference voltage VREF is set to a voltage level equal to or lower than voltage VDD / 4 (in FIG. 22, the voltage level is VDD / 4). Therefore, the pull-up level of the voltage in the high level direction of match line ML in the match state can be set to a voltage level equal to or lower than VDD / 2 (the voltage level of VDD / 2 in FIG. 22). In the differential amplifier circuit 12, the high-level and low-level input signal amplitudes with respect to the reference voltage VREF are made equal. The signal amplitude of the match line ML can be set to VDD / 2 or less, and current consumption can be reduced.

[Example of change]
FIG. 23 is a diagram showing a configuration of a modified example of bias voltage generation circuit 45 of the sixth embodiment of the present invention. In FIG. 23, bias voltage generation circuit 45 includes a unit cell having the same configuration as entry ERY of the memory cell array, and includes replica entry 80 in which each unit cell is set to a match state. The replica entry 80 includes a replica unit cell UCh in which all bits are set to a match state. An off-leakage current Ioff flows in each replica unit cell UCh.

  These replica unit cells UCh include a serial body of MOS transistors N61 and N62 and a serial body of MOS transistors N63 and N64. In each series body, one MOS transistor is set in a non-conducting state as in the unit cell in the match state. An off-leakage current flows in each series body. For one replica unit cell UCh, the total current of off-leakage currents in each series body is the off-leakage current of one unit cell in a matched state.

  These MOS transistors N61 and N62 are the same size as the transistors TR1 and TR2 of the unit cell UC shown in FIG. 21, respectively, and the MOS transistors N63 and N64 are the same as the transistors TR3 and TR4 of the unit cell UC shown in FIG. The size is the same. The replica unit cells UCh of these replica entries 80 are commonly coupled to the replica match line RMLa.

  The bias voltage generation circuit 45 further includes a 1-bit replica unit cell 82. The 1-bit replica unit cell 82 is in the same state as the unit cell UCs in a miss state. In FIG. 23, 1-bit replica unit cell 82 includes a serial body of MOS transistors NT61 and NT612 and a serial body of NT63 and NT64. These MOS transistors NT61 and NT62 are set in a non-conductive state, and MOS transistors NT63 and NT64 are set in a conductive state. These MOS transistors NT61 and NT62 have the same size as transistors TR1 and TR2 of unit cell UC, respectively, and MOS transistors NT63 and NT64 have the same size as transistors TR3 and TR4 of unit cell, respectively. Therefore, a 1-bit miss current Imiss flows through the 1-bit replica match line MLU of the 1-bit replica unit cell 82.

  Bias voltage generating circuit 45 further has a gate and a drain connected to each other, P channel MOS transistor P601 for supplying current from power supply node to replica match line RMLa, and P channel MOS transistor P602 for supplying current Ia to signal line 85. Including. The MOS transistor P602 forms a current mirror circuit with the MOS transistor P601.

  Bias voltage generation circuit 45 further includes a P-channel MOS transistor P604 that supplies current to 1-bit replica unit cell 82, and a P-channel MOS transistor P603 that supplies current Ib to signal line 85. MOS transistor P604 has its gate and drain interconnected. MOS transistor P603 forms a current mirror circuit with P-channel MOS transistor P604.

  MOS transistors P601 and P602 are equal in size (ratio of channel width to channel length) and supply the same current (m · Ioff = Ia; m is the number of replica unit cells UCh) Equal to the number of unit cells in one entry ERY). The size of the MOS transistor P603 is made smaller than that of the MOS transistor P604. Therefore, the mirror current generated by the P-channel MOS transistor 603 is smaller than the 1-bit miss current Imiss (≈In) (Ib <Imiss). A current that is the sum of currents Ia and Ib from MOS transistors P602 and P603 flows through signal line 85. Therefore, the current flowing through the signal line 85 is expressed by the following equation.

Ia + Ib = m · Ioff + Ib
By adjusting the sizes of the transistors P602 and P603, the current flowing through the signal line 85 can be made smaller than the current flowing from the match line via the entry in the 1-bit miss state.

Imiss + (m−1) · Ioff> Ib + m · Ioff> m · Ioff
From the above equation, the following relational expression is derived.

Imiss-Ioff> Ib
The current Ib supplied from the MOS transistor p603 is set so as to satisfy the above relationship. The value of the current flowing through the signal line 85 can be set to a value larger than the off-leak current of the entry in the match state and smaller than the discharge current (1 bit miss current) of the entry at the time of 1 bit miss. The upper limit value of this current Ib is calculated from the above equation by the current In flowing through the path of the conducting transistor of the unit cell in the missed state and the off-leakage current Ioff / 2 flowing through the path of the non-conducting transistor series body in the entry of 1 bit miss. It makes a difference.

  Bias voltage generation circuit 45 further includes an N channel MOS transistor N601 for discharging the current of signal line 85, an N channel MOS transistor N602, and a P channel MOS transistor P605 for supplying current to MOS transistor N602. MOS transistor N601 has its gate and drain interconnected. MOS transistor N602 forms a current mirror circuit with MOS transistor N601. MOS transistor P605 has a gate and a drain connected to each other.

  MOS transistors N601 and N602 are equal in size (ratio of channel width to channel length). Therefore, the current Ic flowing through the MOS transistor N602 is the same magnitude as the current flowing through the signal line 85. Therefore, MOS transistor P605 flows a current having the same magnitude as the current flowing through MOS transistor N602. The MOS transistor P605 has a gate and a drain connected to each other, has a current / voltage conversion function, and generates a bias voltage BIAS_P at the gate. Bias voltage BIAS_P is applied to the gate of MOS transistor PQ10 included in match amplifier 40.

  MOS transistors P605 and PQ10 have the same size. Therefore, the current Id flowing from the MOS transistor PQ10 to the match line ML via the MOSPQ70 is the same magnitude as the current flowing through the signal line 85.

  As a result, it is possible to supply a current having a value smaller than the current of the match line at the time of 1 bit miss and larger than the off-leak current of the entry in the all bit bit match state to each match line ML. Further, since replica entries are used, variations in transistor parameters at the time of manufacturing unit cells of data entry can be reflected in the replica unit cells of this replica entry. As a result, a pull-up current / precharge current having a desired magnitude can be accurately supplied.

  In the configuration shown in FIG. 23, the number of replica unit cells UCh included in the replica entry 80 may be a value (m−1) that is one smaller than the number m of unit cells included in the entry ERY. Thus, the current corresponding to the current flowing through the match line corresponding to the entry in the 1-bit miss state can be generated by the replica entry 80 and the 1-bit replica unit cell 82.

  FIG. 24 schematically shows a structure of control circuit 8 of the content reference memory according to the sixth embodiment of the present invention. In FIG. 24, the control circuit 8 includes a command decoder 20 that decodes an external command CMD, a frequency dividing circuit 90 that divides the clock signal CLK in accordance with a search operation instruction EN from the command decoder 20, and a command decoder 20 A search data input control circuit 92 that generates a latch enable signal LTEN for the search data input circuit 4 according to the search operation EN and the divided clock signal BCLK from the frequency divider circuit 90 is included.

  Search data input circuit 4 is formed of flip-flop circuit 94, and fetches and latches search data SD in accordance with activation of latch enable signal LTEN, and searches line group (search data bus) SLG in accordance with the fetched search data. To drive.

  Control circuit 8 further includes delay circuit 26, match amplifier activation circuit 66, and discharge activation circuit 68, similarly to the configuration of the control circuit shown in FIG. The delay circuit 26 delays the search operation instruction EN by one clock cycle. Match amplifier activation circuit 66 is activated in accordance with the output signal of delay circuit 26, and generates match amplifier activation signal MAE and latch instruction signal LAT in synchronization with the rise of clock signal CLK. Discharge control circuit 68 generates discharge instruction signal DIS in response to the rise of clock signal CLK in accordance with the output signal of delay circuit 26.

  Therefore, by utilizing the control circuit 8 shown in FIG. 24, the search data input circuit 4 can cause the flip-flop circuit 94 to fetch, latch and output the search data for each search cycle.

  Note that, in the configuration of the control circuit 8 shown in FIG. 24, the transition of the search data SD may be detected, and the search operation instruction EN may be generated according to the search data transition detection signal.

  Further, the frequency dividing circuit 90 divides the clock signal CLK by 2 in the timing chart shown in FIG. 22 to generate the divided clock signal CLK. However, the frequency dividing ratio of the frequency dividing circuit 90 and the number of delayed clock cycles of the delay circuit 26 may be set to appropriate values according to the number of clock cycles of one search cycle.

  As described above, according to the sixth embodiment of the present invention, the match line is precharged to the ground voltage level, and at the time of the search operation, the match line has a 1-bit extraction current or 1-bit miss whose current value is limited. A current smaller than the current and larger than the total bit off-leakage current is supplied. Therefore, the voltage amplitude of the match line can be reduced, and the charge current of the match line can be reduced. For search lines SL and / SL, search data is held by flip-flop circuit 90 as shown in FIG. Therefore, when search data having similar bit patterns continues, the number of search lines charged / discharged in the search data bus can be reduced, and accordingly, the charge / discharge current of the search lines can be reduced.

[Embodiment 7]
FIG. 25 shows a structure of a main portion of the content reference memory according to the seventh embodiment of the present invention. In the content reference memory shown in FIG. 25, the configuration of entry ERY in the memory cell array is the same as the configuration of entry ERY described in the first to sixth embodiments, and corresponding parts are denoted by the same reference numerals. Detailed description thereof will be omitted.

  In match amplifier 40, a discharge transistor 60 that discharges match line ML to the ground voltage level in accordance with discharge instruction signal DIS, and a pull-up / detection circuit 100 that generates internal search determination result signal MA_ML are provided at internal node ND70. The pull-up / detection circuit 100 supplies a pull-up current to the match line ML, performs a search determination, and generates an internal search determination result signal according to the determination result.

  Pull-up / detection circuit 100 includes P channel MOS transistors QP71 and QP72 connected in series between a power supply node and internal node ND70, and an N channel MOS transistor connected between internal node ND70 and corresponding match line ML. NOR gate NG1 that receives QN 71, internal search determination result signal MA_ML on internal node ND70, and precharge instruction signal PRE is included. An output signal of NOR gate NG1 is applied to MOS transistor QP72.

  Discharge instruction signal GIS is applied to the gate of MOS transistor QP71, and bias voltage BIAS_N is applied to the gate of MOS transistor QN71.

  Match amplifier 40 further includes a latch 16 that latches output signal MA_ML of pull-up / detection circuit 100 in accordance with latch instruction signal LAT. Therefore, the match amplifier 40 is not provided with a differential amplifier circuit, and its current consumption can be reduced.

  Bias voltage generation circuit 45 includes P channel MOS transistors QP73 and QP74 connected in series between the power supply node and node ND72, a comparator CMP that compares the voltage on node 72 and precharge voltage VML, and node ND72. N channel MOS transistor QN72 having one conduction node connected thereto, and N channel MOS transistors QN75 and QN76 connected in series between the other conduction node of MOS transistor QN72 and the ground node. N channel MOS transistor QN72 receives the output signal of comparator CMP at its gate.

  MOS transistors QP73 and QP74 have their gates coupled to the ground node, and are always kept conductive. The OS transistors QP73 and QP74 are set to have the same size (ratio of channel width to channel length) as the MOS transistors QP71 and QP72 included in the match amplifier 40, respectively.

  MOS transistors QN75 and QN76 have their respective gates coupled to the power supply node, and are always rendered conductive. MOS transistors QN75 and QN76 are equal in size to MOS transistors TR3 and TR4 included in unit cell UC, respectively. Therefore, 1-bit drawing current In flows through MOS transistors QN75 and QN76 at the maximum.

  In the configuration of the bias voltage generation circuit 45, the comparator CMP compares the precharge voltage VML at the intermediate voltage level with the voltage level at the node ND72. When the voltage level of the node ND72 is higher than the precharge (intermediate) voltage VML, the output signal of the comparator CMP becomes high level. Accordingly, the conductance of MOS transistor QN72 increases, the current flowing from node ND72 to MOS transistors QN75 and QN76 increases, and the voltage level of node ND72 decreases. On the other hand, when the voltage level of the node ND72 is lower than the precharge voltage VML, the output signal of the comparator CMP is at a low level. Accordingly, the conductance of MOS transistor QN72 decreases, the amount of current flowing through MOS transistor QN72 decreases, and the potential drop at node ND72 is suppressed. Therefore, the conductance of MOS transistor NQ72 is adjusted by comparator CMP so that node ND72 is maintained at precharge voltage VML level. Precharge voltage VML is at a voltage level that is ½ times or less the power supply voltage.

  In match amplifier 40, MOS transistors QP71 and QP72 have the same size (ratio of channel width to channel length) as MOS transistors QP73 and QP74, respectively. MOS transistors QN71 and QN72 have the same size. The output voltage BIAS_N of the comparator CMP is supplied to the gate of the MOS transistor NQ71. Therefore, in match amplifier 40, signal MA_ML on node ND70 is substantially maintained at precharge voltage VML level when corresponding entry ERY is in a 1-bit miss state. When the voltage level of match line ML reaches the voltage level of node ND70, MOS transistor QN is turned off. Therefore, the voltage level of match line ML does not become higher than the voltage level on node ND70, and accordingly, the voltage level of match line ML is set to be equal to or lower than voltage VML.

  The sizes of the MOS transistors QP71 and QP72 are smaller than the current flowing through the match line at the time of 1-bit miss of the entry (the sum of 1-bit miss current and the off-leak current of the remaining unit cells, Imiss + (m−1) · Ioff) Is set to have the ability to drive

  FIG. 26 is a timing chart showing the search operation of the content reference memory shown in FIG. The search operation of the content reference memory shown in FIG. 25 will be described below with reference to FIG.

  Prior to time T1, precharge instruction signal PRE is at the L level. On the other hand, discharge instruction signal DIS is at the H level, and match line ML is precharged to the ground voltage level. Next, MOS transistor QP71 is in a non-conductive state, and node ND70 is discharged to the ground voltage level and maintained at the ground voltage level as match line ML is discharged.

  Before time T1, discharge instruction signal DIS is at the H level, and match line ML is precharged to the ground voltage level by discharge transistor 60. MOS transistor QP71 is non-conductive, and node ND70 is also at the ground voltage level.

  At time T1, when the search cycle starts, discharge instruction signal DIS is first at L level, discharge transistor 60 is turned off, and MOS transistor QP71 is turned on. Precharge instruction signal PRE becomes H level, and the output signal of NOR gate NG1 becomes L level. In response, current is supplied to node ND70 via MOS transistors QP71 and QP72, and the voltage level rises. Currents from MOS transistors QP71 and QP72 are supplied to match line ML via MOS transistor QN71. When the entry ERY corresponding to the match line ML is in a miss state, the match line ML is discharged through the unit cell UC in the miss state. The currents supplied by MOS transistors QP71 and QP72 are currents of 1 bit miss current or less, and the voltage level of match line ML does not reach precharge voltage VML but is discharged to ground voltage GND level at an early timing.

  MOS transistor QN71 receives bias voltage BIAS_N at its gate, and maintains node ND70 at precharge voltage VML level when 1-bit drawing current In flows through corresponding match line ML. When the number of unit cells in the entry ERY in the miss state is larger than 1 bit, the node ND70 is driven to a voltage level lower than the precharge voltage VML. Therefore, when the corresponding entry is in a miss state, the voltage of node ND70 is at the maximum precharge voltage VML level.

  At time T3, a search determination operation is performed, latch 16 enters a through state in accordance with latch instruction signal LAT, and its output signal ML_OUT becomes L level (the voltage at node ND70 (maximum VML) is the input logic of latch 16). The voltage level is well below the threshold).

  During the latch operation, the precharge instruction signal PRE is deactivated at time T3. Therefore, the voltage level of node ND70 is an input voltage level determined to be the L level of NOR gate NG1, and the output signal of NOR gate NG1 is at the H level. Accordingly, MOS transistor QP72 is rendered non-conductive, and the voltage level of node ND70 further decreases. Thereby, the search result instruction signal ML_OUT from the latch 16 is surely set to the L level.

  By driving the precharge instruction signal PRE to the L level from time T3, the voltage level of the match line ML is lowered. Even when the reduced voltage level of the match line ML does not reach the ground voltage GND, when the latch 16 enters the latch state in the cycle from the time T4, the discharge instruction signal DIS becomes the H level, and the match line ML becomes the ground voltage. Driven to level. In response, signal MA_ML at node ND70 is also discharged to the ground voltage level (MOS transistor QP72 is non-conductive). Thereby, the precharge operation of match line ML and node ND70 is completed.

  In the search cycle T5, a search operation for the next search data is executed. When discharge instruction signal DIS is driven to the L level and precharge instruction signal PRE is driven to the H level, MOS transistors QP71 and QP72 are rendered conductive. Accordingly, a current is supplied to node ND70, and further, a current is supplied from node ND70 to match line ML, and the voltage level of signal MA_ML at node ND70 increases. MOS transistor QN71 receives bias voltage BIAS_N at its gate, and MOS transistors QN72 and QN71 are the same size. Therefore, a maximum of 1 bit miss (extraction) current flows through MOS transistor QN71. When the potential of match line ML in the match state rises, MOS transistor QN71 becomes non-conductive when the source follower operation or when the source / drain voltages are equal. Thereby, the voltage rise of match line ML is suppressed, and match line ML is maintained at the maximum precharge voltage VML level.

  On the other hand, in this state, MOS transistors QP71 and QP72 are in a conductive state, and current is supplied to node ND70. Therefore, the voltage level of signal MA_ML at node ND70 finally rises to the power supply voltage VDD level.

  When the latch instruction signal LAT is set to H level in the clock cycle starting from time T7, the output signal ML_OUT from the latch 16 becomes H level indicating a match state.

  At time T7, even if precharge instruction signal PRE is at L level, signal MA_ML on node ND70 is at a sufficiently high voltage level, and the output signal of NOR gate NG1 is at L level. MOS transistor QP72 can maintain the conductive state, accurately determine the voltage level of signal MA_ML at node ND70, and generate search result instruction signal ML_OUT.

  The MOS transistor QN71 operates in the source follower mode by the bias voltage BIAS_N, and becomes non-conductive when the gate-source voltage becomes equal to the threshold voltage. Therefore, even if the signal MA_ML on the node ND70 rises to the power supply voltage VDD level, when the voltage level of the match line ML rises, the MOS transistor QN71 becomes non-conductive, and the voltage level of the match line ML becomes the precharge voltage. Suppresses rising above VML.

  In the configuration shown in FIG. 25, the load capacity of internal node ND70 of match amplifier 40 is sufficiently smaller than that of match line ML. Therefore, the charging current of internal node ND70 is smaller than the amount of charging current when charging match line ML, and the current consumption during the search operation can be further reduced.

  As described above, according to the seventh embodiment of the present invention, in the match amplifier, the MOS transistor QN71 receiving the bias voltage BIAS_N at the gate causes the potential rise of the match line to be less than the intermediate voltage (VML ≦ VDD / 2). The search result instruction signal is generated by charging the internal node while suppressing the noise. Therefore, the layout area and power consumption of the match amplifier can be reduced, and the current consumption during the search result determination can be sufficiently reduced.

  Note that the configuration of the control circuit shown in FIG. 24 can be used as the circuit for generating the control signal in the seventh embodiment. The circuit for generating the precharge instruction signal PRE may be configured to set the precharge instruction signal PRE to the H level for one clock cycle period in accordance with the search operation instruction EN from the command decoder shown in FIG.

[Embodiment 8]
FIG. 27 shows a structure of a main portion of the content reference memory according to the eighth embodiment of the present invention. The configuration of the content reference memory shown in FIG. 27 is different from the content reference memory shown in FIG. 25 in the following points. That is, in match amplifier 40, a charge-up circuit 110 is provided for supplying charge charges to match line ML in accordance with pull-up current supply instruction signal MLPU_n. Charge-up circuit 110 includes P channel MOS transistors QP81 and QP82 connected in series between a power supply node and match line ML, and capacitive element CQ2 connected to a connection node of these MOS transistors QP81 and QP82. Including.

  The other configuration of the content reference memory shown in FIG. 27 is the same as that of the content reference memory shown in FIG. 25, and corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted.

  FIG. 28 is a timing chart showing an operation during the search operation of the content reference memory shown in FIG. Hereinafter, the search operation of the content reference memory shown in FIG. 27 will be described with reference to FIG.

  Prior to time T1, precharge instruction signal PRE is at the L level, and discharge instruction signal DIS is at the H level. Therefore, match line ML and signal ML_MA of internal node ND70 are both at the ground voltage level (GND level). The latch 16 is in a latched state. In the timing chart shown in FIG. 28, it is assumed that a search result instruction signal ML_OUT at H level is generated.

  At time T1, when the search cycle starts, first, discharge instruction signal DIS becomes L level, MOS transistor 60 is turned off, and MOS transistor QP71 is turned on. At this time, the precharge instruction signal PRE is still at the L level. Therefore, the output signal of NOR gate NG1 is at the H level, and MOS transistor QP72 is in a non-conductive state.

  On the other hand, pull-up current supply instruction signal MLPU_n becomes L level, and charge instruction signal CHA_n becomes H level. Responsively, capacitive element CQ2 is separated from the power supply node, and the charge of capacitive element CQ2 is transmitted to match line ML and node ND70. By adjusting the capacitance value of the capacitive element CQ2, the voltage level of the match line ML can be set to a voltage level lower than the precharge voltage VML at the intermediate voltage level.

  At this time, pull-up current supply instruction signal MLPU_n rises to H level, MOS transistor QP82 is turned off, and the pull-up operation of match line ML by charge-up circuit 110 is completed. By the pull-up operation using the capacitive element CQ2 by the charge-up circuit 110, the signal MA_ML of the match line ML and the node ND70 is driven to a predetermined precharge voltage level at high speed.

  In the search cycle starting from this time T1, between time T1 and time T2, the precharge instruction signal PRE becomes H level, and accordingly, the output signal of the NOR gate NG1 becomes L level, and the MOS transistor QP72 becomes conductive. . Accordingly, a pull-up current is supplied to match line ML via MOS transistors QP71, QP72 and QN71.

  At this time, if the entry ERY corresponding to the match line ML is in a miss state, a current larger than the pull-up current supplied by the pull-up / detection circuit 100 is discharged to the ground node, and the voltage of the match line ML The level drops.

  At time T3, precharge instruction signal PRE is set to L level. At this time, the node ND70 is at L level, the output signal of the NOR gate NG1 becomes H level, and the MOS transistor QP72 is turned off. Node ND70 is discharged from MOS transistor QN71 to the ground voltage level via unit cell UC in the miss state in entry ERY. At this time, the latch instruction signal LAT becomes H level, and the latch 16 enters the through state. Node ND70 is at the ground voltage level, and L-level signal ML_OUT is output from latch 16 in response to internal search instruction signal MA_ML.

  In the cycle starting from time T4, precharge instruction signal T4 again becomes H level. Responsively, match line ML is precharged to the ground voltage level, and node ND70 is also discharged to the ground voltage level (MOS transistor QP72 is non-conductive).

  In the period from time T3 to time T5, the charge instruction signal CHA_n becomes L level, and the capacitive element CQ2 is charged.

  In the search cycle starting from time T5, the same operation as the previous search cycle is performed again. In other words, match line ML and internal node ND70 are charged by capacitive element CQ2 of match line ML, and the respective voltage levels rise. After completion of this charge-up operation, pull-up current supply instruction signal MLPU_n becomes H level, and the charge-up operation is completed.

  Next, the precharge instruction signal PRE becomes H level, the output signal of the NOR gate NG1 becomes L level, and the MOS transistor QP72 becomes conductive. When the entry ERY provided for the match line ML is in a match state, there is no path for discharging the match line ML. Therefore, node ND70 is charged by MOS transistors QP71 and QP72, and the voltage level of internal search instruction signal MA_ML finally rises to power supply voltage VDD level. Even when node ND70 is charged to the power supply voltage level, MOS transistor QN71 prevents the voltage level of match line ML from becoming higher than precharge voltage VML.

  At time T7, even if precharge instruction signal PRE becomes L level, node ND70 is already at H level, and the output signal of NOR gate NG1 is at L level. Therefore, signal MA_ML on node ND70 is maintained at the H level. At time T7, latch instruction signal LAT also goes to H level, latch 16 enters the through state, and H level signal ML_OUT corresponding to signal MA_ML on node ND70 is generated.

  During this period, the match line ML does not have a discharge path and is maintained at the charge voltage VML level. At time T8, the output signal is latched, the latch instruction signal LAT becomes L level, and the latch 16 enters the latched state. In addition, discharge instruction signal DIS goes to L level, match line ML is discharged to the ground voltage level, and node ND70 is also discharged to the ground voltage level. Accordingly, the output signal of NOR gate NG1 attains H level, and MOS transistor QP72 is rendered non-conductive. Thereby, node ND70 and match line ML are surely discharged to the ground voltage level.

  By pulling up match line ML to a predetermined voltage level using capacitive element CQ2 in charge-up circuit 110, the voltage levels of match line ML and internal node ND70 can be changed at high speed, and the search operation is performed. Can be fast. In addition, charging is performed using the capacitive element CQ2, and when the match line ML is charged, the voltage VDD of the power supply node is not consumed, so that generation of power supply noise at the time of match line pull-up is suppressed. Further, the charging of the capacitive element CQ2 may be performed over the clock cycle period between time T3 and T5 and between T7 and time T9. Therefore, the capacitive element CQ2 is slowly charged, and the peak current can be reduced.

  FIG. 29 shows an example of a structure of a circuit for generating a control signal for the content reference memory according to the eighth embodiment of the present invention. In FIG. 29, control circuit 8 includes a command decoder 20 that decodes command CMD in synchronization with clock signal CLK, and a frequency dividing circuit that divides clock signal CLK in accordance with activation of search operation instruction EN from command decoder 20. 90 and a search data input control circuit 92 that generates a search latch instruction signal LTEN for the search data input circuit in accordance with the divided clock signal BCLK of the frequency dividing circuit 90 and the search operation instruction.

  The control circuit 8 further includes a charge-up activation circuit 120 that generates a charge instruction signal CHA_n according to the divided clock signal BCLK of the frequency divider circuit 90 and the search operation instruction EN, and the search operation instruction EN and the clock signal CLK. Accordingly, in the form of a predetermined one-shot pulse, a pull-up activation circuit 122 that generates a pull-up current supply instruction signal MLPU_n and a pull-up activation control circuit 124 that generates a precharge instruction signal PRE are included. This pull-up activation control circuit 124 activates the search operation instruction EN when the search operation instruction EN is activated in response to the fall of the pull-up current supply control signal MLPU_n output from the pull-up activation circuit 122 ( To generate).

  The control circuit 8 further delays the search operation instruction EN for one clock cycle period, and latch activation control for maintaining the latch instruction signal LAT at the H level for a predetermined period according to the output signal of the delay circuit 26 and the clock signal CLK A circuit 126 and a discharge activation circuit 128 that maintains discharge instruction signal DIS at an H level for a predetermined period in response to a fall of latch instruction signal LAT from latch activation control circuit 126 are included.

  The configuration of the frequency dividing circuit 90, the search data input control circuit 92, the command decoder 20 and the delay circuit 26 is the same as the configuration of the control circuit shown in FIG. When the search operation instruction EN is activated, the charge-up activation circuit 120 sets the charge instruction signal CHA_n to the H level during the half clock cycle period of the divided clock signal BCLK.

  The pull-up activation circuit 122 has a configuration of a one-shot pulse generation circuit, and maintains the pull-up current supply instruction signal MLPU_n at an L level for a predetermined period at the start of the search operation. In response to the rise of pull-up instruction signal MLPU_n to H level, pull-up activation control circuit 124 maintains precharge instruction signal PRE at H level until clock signal CLK rises next.

  The latch activation control circuit 126 maintains the latch instruction signal LAT at the H level while the clock signal CLK is at the H level when the output signal of the delay circuit 26 is in the active state. When latch instruction signal LAT falls to L level, discharge activation circuit 128 drives and maintains discharge operation instruction signal DIS to H level until clock signal CLK rises next (delay circuit 26). When activated).

  As described above, according to the eighth embodiment of the present invention, the pull-up operation is further performed on the match line using the charge of the capacitive element. Therefore, in addition to the effects of the seventh embodiment, the match line can be driven to a predetermined voltage level at high speed. Further, when the match line is pulled up, the charge of the capacitive element is used, and when the match line is pulled up, generation of power supply noise is suppressed.

[Embodiment 9]
FIG. 30 shows a structure of a main portion of the content reference memory according to the ninth embodiment of the present invention. The content reference memory shown in FIG. 30 differs from the content reference memory shown in FIG. 27 in the configuration of the bias voltage generation circuit 45 and the latch amplifier 40 in the following points.

  That is, in the bias voltage generation circuit 45, a replica entry 50 including a unit cell in a 1-bit miss state is provided. The internal structure of the replica entry 50 is the same as that of the replica entry 50 shown in FIG. A current is supplied to replica match line RML provided for replica entry 50 through P channel MOS transistor QP93 having a gate and a drain connected to each other. The current IMISS supplied by the MOS transistor QP93 is therefore approximately the same magnitude as the match line current discharged through the replica entry 50 including the 1-bit missed replica unit cell, and a 1-bit miss in the entry ERY. It is equal to the sum of the current Imiss and the off-leakage current flowing through the remaining matched unit cells.

  In this bias voltage generating circuit, a MOS transistor QP93 and a P channel MOS transistor QP92 constituting a current mirror circuit are further provided. The MOS transistor QP92 supplies current to the MOS transistor QP74. The other configuration of this bias voltage generating circuit 45 is the same as that of the bias voltage generating circuit shown in FIG. 27, and the corresponding parts are denoted by the same reference numerals and detailed description thereof is omitted.

  The size of MOS transistor QP92 is made smaller than the size of MOS transistor QP93. Therefore, the current Ip2 flowing through the MOS transistor QP92 is smaller than the current IMISS flowing through the MOS transistor QP93, and is smaller than the match line current at the time of 1 bit miss.

  In match amplifier 40, there is provided a P-channel MOS transistor QP91 that receives the gate voltage BIAS_P of MOS transistor QP93 at its gate and supplies current to MOS transistor QP71. The MOS transistor QP91 is the same size as the MOS transistor QP92. These MOS transistors QP91 and QP92 form a current mirror circuit with the MOS transistor QP93, and a current Ip1 (= Ip2) of the same magnitude flows.

  The other configuration of the match amplifier 40 is the same as that of the match amplifier shown in FIG. 27, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the configuration of the content reference memory shown in FIG. 30, the replica entry 50 is used to generate a bias voltage BIAS_P corresponding to a current equal to or lower than the match line current at the time of 1 bit miss. Therefore, as in the configuration shown in FIG. 21, the current flowing through the unit cell UC can be corrected by the variation in the parameters of the unit cell UC of the entry ERY in the memory cell array. That is, for example, a state is considered in which the current flowing through the P-channel MOS transistor is larger than usual due to variations in process parameters, and the current flowing through the N-channel MOS transistor is small. In this case, in the entry ERY, the miss current flowing through the unit cell UC in the miss state is reduced. However, in this case, also in replica entry 50, current In flowing through the N-channel MOS transistor is reduced, and currents Ip2 and Ip1 flowing through MOS transistors QP92 and QP91 are accordingly reduced. Therefore, in the entry ERY that stores the actual data, even when a search error occurs, the amount of charge current for the match line ML is adjusted according to the fluctuation of the discharge current, and an accurate search operation can be realized.

  As shown in FIG. 30, the replica entry 50 is used to pass a current having the same magnitude as the miss current of the entry ERY that stores 1-bit miss data. Thus, the current Ip1 flowing through the P-channel MOS transistor QP91 can be accurately made smaller than the match line current IMISS (including off-leakage current) at the time of 1 bit miss. Accordingly, it is possible to charge the exact match line regardless of variations in process parameters, and to realize an accurate search operation.

  As described above, according to the ninth embodiment of the present invention, the match voltage of the pull-up / detection circuit in the match amplifier is generated by generating the match line current in the 1-bit miss state using the replica entry in the bias voltage generation circuit. The line charging current is adjusted. Therefore, the search operation can be performed accurately regardless of variations in process parameters. In addition, the same effects as in the eighth embodiment are obtained.

  The effect of the configuration using the replica entry can be similarly obtained in the sixth embodiment shown in FIG.

[Embodiment 10]
FIG. 31 shows a structure of a main portion of the content reference memory according to the tenth embodiment of the present invention. The configuration of the content reference memory shown in FIG. 31 is different from the configuration of the content reference memory shown in FIG. 30 in the following points. That is, a buffer 130 is provided that converts the level of the bias voltage BIAS_N generated from the bias voltage generation circuit 45. The buffer 130 slightly increases the level of the bias voltage BIAS_N to convert it to the bias voltage BIAS_N2, and applies this level-converted voltage BIAS_N2 to the gate of the N-channel MOS transistor QN71 of each matchup 40 as the bias voltage. The other configuration of the content reference memory shown in FIG. 31 is the same as the configuration of the content reference memory shown in FIG. 30, and corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted.

  Bias voltage BIAS_N 2 is set to a voltage level higher than bias voltage BIAS_N from bias voltage generation circuit 45 by voltage ΔV. Here, the voltage ΔV is 100 mV or less. When the gate potential of N channel MOS transistor QN71 falls below a desired value, the conductance of MOS transistor QN71 falls, and the current flowing through match line ML is suppressed. This suppressed current component charges node ND70, and the voltage level of signal MA_ML at node ND70 increases. When the search result is a miss, the match line ML is driven in the direction of the ground voltage level. However, due to this suppression current component, internal node ND70 in match amplifier 40 is not driven to the ground voltage level but becomes H level, which may cause a malfunction that is determined to be a match state. Therefore, the voltage level of bias voltage BIAS_N2 applied to the gate of MOS transistor QN71 is made slightly higher than desired value BIAS_N. Thereby, it is possible to suppress a malfunction due to a decrease in the bias voltage BIAS_N2 due to noise in the ground voltage direction, and an accurate search operation can be realized.

In addition, the same effects as those of the eighth and ninth embodiments can be realized.
FIG. 32 is a diagram showing an example of the configuration of the buffer 130 shown in FIG. 32, buffer 130 includes P channel MOS transistors QP101 and QP102 coupled to a power supply node, N channel MOS transistors QN101 to QN103 connected in series between MOS transistor QP101 and the ground node, and MOS transistor QP102. N channel MOS transistors QN104 to QN106 connected in series between the ground nodes.

  MOS transistors QP101 and QP102 constitute a current mirror circuit. P channel MOS transistor QP101 has its gate and drain interconnected and operates as a master stage of this current mirror circuit. Bias voltage BIAS_N is applied to the gate of MOS transistor QN101. MOS transistor QN104 has its gate and drain connected to each other, and a bias voltage BIAS_N2 after level conversion is generated from the gate. MOS transistors QN102, QN103, QN105, and QN106 each have a gate coupled to a power supply node. These N channel MOS transistors QN101 to QN106 have the same size. On the other hand, the size of the MOS transistor QP101 is made smaller than that of the MOS transistor QP102.

  In the configuration of buffer 130 shown in FIG. 32, MOS transistor QN101 operates as a constant current source in accordance with bias voltage BIAS_N, and supplies current to N channel MOS transistors QN102 and QN103. The current flowing through these MOS transistors QN101 is supplied via the MOS transistor QP101. MOS transistor QP102 generates a mirror current of the current flowing through MOS transistor QP101. The size of the MOS transistor QP102 is larger than that of the MOS transistor QP101. Therefore, the current flowing through the MOS transistor QP102 is larger than the current flowing through the MOS transistor QP101.

  The current from MOS transistor QP102 is discharged to the ground node via MOS transistors QN104-QN106. MOS transistor QN104 has a gate and a drain connected to each other, and generates a current / voltage converted signal, that is, bias voltage BIAS_N2 at its gate. The current flowing through MOS transistor QN104 is larger than the current flowing through MOS transistor QN101. MOS transistors QN101 and QN104 have the same size. Therefore, a bias voltage BIAS_N2 having a higher voltage level than the bias voltage BIAS_N is generated.

  Also in this buffer 130, MOS transistors QN101 to QN106 are formed in the same process as the MOS transistor for match line discharge of the replica entry. Thereby, it is possible to compensate for variations in transistor characteristics due to process variations, and to set the voltage level of the bias voltage BIAS_N2 to a desired value.

  As described above, according to the tenth embodiment of the present invention, the level of the bias voltage applied to the gate of the MOS transistor that supplies current to the match line is increased by the buffer and supplied. Therefore, the search operation can be performed accurately even with respect to noise in the ground direction of the bias voltage.

In addition, the same effects as those of the ninth embodiment are obtained.
[Embodiment 11]
FIG. 33 shows a structure of a main portion of the content reference memory according to the eleventh embodiment of the present invention. The content reference memory shown in FIG. 33 differs from the content reference memory shown in FIG. 31 in the following points. That is, the bias voltage generating circuit 45 is provided with a constant current circuit 140 that generates a bias voltage BIAS_P0 applied to the gate of the MOS transistor QP92. Further, a current conversion circuit 135 is provided which converts the level of the bias voltage BIAS_P0 and applies the level-converted voltage to the gate of the MOS transistor QP91 of the match amplifier 40. The configurations of match amplifier 40 and entry ERY in the memory cell array shown in FIG. 33 are the same as those shown in FIG. 33, and other configurations of bias voltage generation circuit 45 are the same as those shown in FIG. Corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  Constant current circuit 135 includes P channel MOS transistors QP93 and TN71 connected in series between the power supply node and internal node ND73, and N channel MOS transistors TN75 and TN76 connected in series between internal node ND73 and the ground node. And a comparison circuit CMPA that compares the voltage of the internal node ND73 with the intermediate voltage VML. The comparison circuit CMPA adjusts the gate potential of the MOS transistor TN71 according to the comparison result.

  MOS transistor QP93 has its gate and drain interconnected to form a current mirror circuit with MOS transistor QP92. MOS transistors QP92 and QP93 have the same size and flow the same amount of current.

  MOS transistors TN75 and TN76 have their gates coupled to the power supply node, and are always in a conductive state. These MOS transistors TN75 and TN76 have the same size as the transistors TR3 and TR4 or TR1 and TR2 of the unit cell UC, respectively, and flow a 1-bit drawing current In (Imiss).

  Comparison circuit CMPA receives intermediate voltage VML at its positive input, and its negative input is coupled to internal node ND73. By the feedback control of the comparison circuit CMPA and the MOS transistor TN71, the voltage level of the internal node ND73 becomes equal to the intermediate voltage (precharge voltage) VML. Therefore, the voltage of node ND73 is accurately maintained at the precharge voltage VML level even when power supply voltage VDD varies. Accordingly, the 1-bit drawing current In (= Imiss) can be accurately generated without being affected by fluctuations in the power supply voltage.

  Therefore, in the constant current circuit 140, a current having the same magnitude as that when the 1-bit extraction current In (= Imiss) flows through the match line ML by the unit cell in the 1-bit miss state flows through the MOS transistor QP93. Therefore, bias voltage BIAS_P0 generated by MOS transistor QP93 is at a voltage level corresponding to the 1-bit drawing current. The MOS transistor QP92 has the same size as the MOS transistor QP93, and the current Ip2 has the same magnitude as the 1-bit extraction current In (= Imiss).

  The current conversion circuit 135 performs level conversion of the bias voltage BIAS_P0 to slightly increase the voltage level. Thereby, in match amplifier 40, current Ip1 flowing through MOS transistor QP91 can be made smaller than 1-bit extraction current In, and can be made larger than the total current IOFF of the off-leakage currents of all bits. .

  In this bias voltage generation circuit 45, the internal node to which the replica search transistor is connected is maintained at the precharge voltage VML of the match line. As a result, in the match line precharge state, it is possible to stably generate a current as large as the current discharged by the unit cell in the 1-bit miss state, and more accurately limit the match line amplitude and reduce the current consumption. Can be reduced.

Current conversion circuit configuration 1:
FIG. 34 shows an example of the configuration of current conversion circuit 135 shown in FIG. 34, current conversion circuit 135 includes a P channel MOS transistor TP100 coupled to the power supply node and receiving bias voltage BIAS_P0 at its gate, and an N channel MOS transistor TN100 receiving a current from MOS transistor TP100.

  The bias voltage BIAS_P0 is generated from the constant current circuit (140). MOS transistor TN100 has its gate and drain interconnected.

  Current conversion circuit 135 further includes an N-channel MOS transistor TN101 and a P-channel MOS transistor TP101 that supplies current from the power supply node to MOS transistor TN101. The MOS transistor TN101 forms a current mirror circuit with the MOS transistor TN100. MOS transistor TP101 has its gate and drain interconnected.

  A bias voltage BIAS_P is generated at the gate of the MOS transistor TP101, and this bias voltage BIAS_P is applied to the gate of the MOS transistor QP91 of the match pump 40.

  In the bias voltage generating circuit 45, the MOS transistors QP92 and QP93 have the same size (ratio of channel length L to channel width W, W / L), and flow the same current Imiss. MOS transistor TP100 is smaller in size than MOS transistors PQ92 and QP93. Accordingly, the current Ip1 flowing through the MOS transistor TP is smaller than the current Imiss driven by the replica search transistor.

  MOS transistors TN100 and TN101 have the same size, and the same amount of current flows through them. A current is supplied from the MOS transistor TP101 to the MOS transistor TN101. Therefore, a current Ip1 flows through the MOS transistor TP101. MOS transistors TP101 and QP91 are the same in size, and therefore the same current flows in both. As a result, the match amplifier 40 can supply a current smaller than the 1-bit drawing current as a pull-up current to the match line.

Current conversion circuit configuration 2:
FIG. 35 is a diagram showing a configuration of a modification of the current conversion circuit shown in FIG. In the configuration shown in FIG. 35, MOS transistors QP92 and QP93 are each formed of a parallel body of K unit P-channel MOS transistors UPT, and each supply a 1-bit drawing current. On the other hand, the MOS transistor TP101 of the current conversion circuit 135 is formed of a parallel body of J unit P-channel MOS transistors. Here, K> J. The other configuration of the current conversion circuit 135 is the same as the configuration shown in FIG. 34, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  The unit transistor UPT has the channel width and the channel length set to unit values, respectively. Therefore, the total channel width of the MOS transistor TP101 is smaller than the total channel width of each of the MOS transistors QP93 and QP92. Thereby, current Ip1 flowing through MOS transistor TP101 can be made smaller than currents flowing through MOS transistors QP92 and QP93. The relationship (mirror ratio) between the current Imiss (= In) and the current Ip1 can be set simply by adjusting the number of unit transistors. As a result, the match line pull-up current can be set to a desired value without being affected by variations in manufacturing parameters.

Buffer configuration:
FIG. 36 is a diagram showing the configuration of the buffer 130 shown in FIG. In the configuration shown in FIG. 33, the configuration shown in FIG. 32 can be applied as buffer 130, and the buffer shown in FIG. 36 can also be applied to the buffer shown in FIG.

  36, a buffer 130 includes a P-channel MOS transistor TP102 whose gate and drain are interconnected and supplying current from a power supply node, and an N-channel MOS which receives a bias voltage BIAS_N at its gate and is supplied with current from the MOS transistor TP102. Transistor TN102. The bias voltage BIAS_N is supplied from the bias voltage generation circuit (45).

  Buffer 130 is further connected between a P-channel MOS transistor TP103 for supplying power supply node empty current, an N-channel MOS transistor TN103 supplied with current from MOS transistor TP103, and a common source of MOS transistors TN102 and TN103 and the ground. N channel MOS transistor TN104.

  P-channel MOS transistor TP103 forms a current mirror circuit with MOS transistor TP102. MOS transistor TN103 has its gate and drain interconnected. MOS transistor T104 receives activation signal ACT at its gate.

  The MOS transistor TP102 is smaller in size than the MOS transistor TP103, and the MOS transistor TP103 passes a large current (mirror ratio is greater than 1). On the other hand, the MOS transistors TN102 and TN103 have the same size. The MOS transistor TN104 is a transistor that controls activation of the buffer 130 in accordance with the activation signal ACT. The amount of current supplied from the MOS transistor TN103 to the MOS transistor TN103 is larger than the current supplied from the MOS transistor TP102 to the MOS transistor TN102. Therefore, the gate potential of the MOS transistor TN103 is higher than the gate potential of the MOS transistor TN102. Thereby, the bias voltage BIAS_N2 can be made higher than the bias voltage BIAS_N by about 100 mV, for example.

  In addition, the MOS transistors TN102 and TN103 have their sources connected in common to the transistor TN104. As a result, the source potentials of these MOS transistors TN103 and TN104 are the same, and the bias voltage BIAS_N2 can be accurately generated according to the difference in the amount of current flowing through the MOS transistors TN102 and TN103.

  The effect of this buffer 135 is the same as in the case of the tenth embodiment shown in FIG. 31, and it is possible to increase the noise margin against the decrease in the bias voltage.

  In the configuration of the buffer 135 shown in FIG. 36, in order to adjust the mirror ratio by adjusting the size of the MOS transistors TP102 and TP103, a parallel body of unit transistors is used as shown in FIG. The mirror ratio may be adjusted by adjusting the number of mirrors.

[Example of change]
FIG. 37 shows a structure of a modification of the eleventh embodiment of the present invention. The content reference memory shown in FIG. 37 differs from the content reference memory shown in FIG. 33 in the following points. That is, in constant current circuit 140 shown in FIG. 37, a resistance element ZR is provided in place of MOS transistors TN75 and TN76. This resistance element ZR has the same resistance value as the combined on-resistance of MOS transistors TR1, TR2 or TR3, TR4 in the discharge path of the unit cell in a miss state when match line ML is voltage VML.

  The other configuration shown in FIG. 37 is the same as the configuration of the content reference memory shown in FIG. 33, and the corresponding parts are denoted by the same reference numerals and detailed description thereof is omitted.

  The resistance element ZR has a resistance value equal to the combined on-resistance value of the search series MOS transistor in the unit cell, and its resistance value is low. Therefore, even if the resistance element ZR is realized by using metal wiring, the layout area is small and an increase in the circuit layout area is suppressed. By realizing the resistance element ZR with such a metal wiring or the like, it is possible to realize a resistance element with a small variation in process parameters, and thus it is possible to stably generate a constant current of a desired magnitude.

  As described above, according to the eleventh embodiment of the present invention, a constant current circuit is used to flow a 1-bit drawing current in a state where the match line voltage is at the precharge voltage level. The amount of pull-up current supplied to the match line is adjusted. Accordingly, a current equal to or smaller than the current at the time of 1 bit miss can be passed through the match line accurately and stably.

Further, the same effect as in the tenth embodiment can be obtained.
[Embodiment 12]
FIG. 38 shows a structure of a main portion of the content reference memory according to the twelfth embodiment of the present invention. In the content reference memory shown in FIG. 38, the configuration of match amplifier 150 provided corresponding to each match line ML is different from that of the match amplifiers of the previous embodiments. The configuration of match amplifiers provided for each match line ML is the same, and FIG. 38 representatively shows the configuration of match amplifier 150 provided for one match line.

  Match amplifier 150 according to the twelfth embodiment charges corresponding match line ML according to the search result in the previous search cycle, and sets a potential level determination criterion for this match line. That is, the match amplifier 150 includes a sense circuit 152 that detects the potential level of the match line ML, a latch circuit 154 that latches the output signal of the sense circuit 152 according to the search instruction signal SRCH, and a match line ML that corresponds to the search operation. A charge circuit 156 that selectively supplies a charging current I_charge is included. The charging current supply control of the charging circuit 156 is performed according to the output signal ML_OUT of the latch circuit 154.

  Latch circuit 154 receives search instruction signal SRCH at clock input CLK, and enters a through state when search instruction signal SRCH is at the H level, and outputs a signal applied to D input from its Q output.

  Sense circuit 152 is connected between the power supply node and internal signal line MALI and has its gate coupled to corresponding match line ML, and connected between the internal signal line and the ground node, and N channel MOS transistor QN112 having a gate coupled to corresponding match line ML.

  Sense circuit 152 further receives an inverter 163 that receives signal MALI from MOS transistors QP113 and QN112 and provides an output signal to input D of D latch circuit 154, and an inverter 161 that receives an output signal from output Q of D latch circuit 154. Including. Sense circuit 152 further includes a D latch circuit 162 for latching the output signal of inverter 161 at the D input, and N channel MOS transistors QN113 and QN114 connected in series between internal signal line MALI and the ground node. .

  The D latch circuit 162 is in a latch state when the search instruction signal SRCH applied to the clock input CK is at the H level, and is in a through state when the search instruction signal SRCH is at the L level.

  MOS transistor QN113 has its gate coupled to match line ML. MOS transistor QN114 receives an output signal DVTH from output Q of D latch circuit 162 at its gate.

  In sense circuit 152, MOS transistors QP113 and QN112 to QN114 constitute an inverter buffer for detecting the potential of corresponding match line ML. In accordance with output signal DVTH of D-type latch circuit 162, the input logic threshold of this inverter buffer is set. The value is corrected. When MOS transistor QN114 is conductive (when signal DVTH is at H level), the input logic threshold value of this inverter buffer is low, and when MOS transistor QN114 is nonconductive, the input logic threshold value of this inverter buffer. Becomes higher. Therefore, the potential determination criterion of match line ML is adjusted according to the search result in the previous search cycle.

  Charge circuit 156 includes P channel MOS transistors QP110 and QP111 each coupled to a power supply node. These MOS transistors QP110 and QP111 constitute a current mirror circuit. Charge circuit 156 further includes N channel MOS transistors QN110 and QN111 connected between MOS transistor QP110 and the ground node, EXNOR circuit 160 receiving the output signal of D-type latch circuit 154 and search instruction signal SRCH, and MOS transistor P channel MOS transistor QP112 connected between QP111 and match line ML is included. MOS transistor QP112 receives output signal / CHRG of EXNOR circuit 160 at its gate.

  MOS transistors QN110 and QN111 have their gates coupled to the power supply node, and are always conductive. These MOS transistors QN110 and QN111 are equal in size to match line discharging transistors TR3 and TR4 or TR1 and TR2 included in unit cell UC, respectively, and 1-bit miss current Imiss flowing in one unit cell UC The same current flows (here, the off-leakage current in the unit cell in the miss state is ignored; In = Imiss).

  MOS transistor QP110 has its gate and drain interconnected and operates as a master stage of the current mirror circuit. The size of MOS transistor QP110 (ratio of channel width to channel length) is made larger than that of MOS transistor QP111 (the mutual conductance gm (QP111) of MOS transistor QP111 <the mutual conductance gm (QP110) of MOS transistor QP110)). Therefore, when MOS transistor QP112 is turned on, charging current I_charge supplied to corresponding match line ML is set to a current value smaller than 1-bit miss current Imiss (however, a value larger than total off-leakage current IOFF for all bits). To be set).

  Also in charge circuit 156, during the search operation, P channel MOS transistor QP112 is selectively rendered conductive according to the search result (ML_OUT) in the previous search cycle, and charge to match line ML is performed.

  FIG. 39 is a diagram showing a list of operation logics of charge circuit 156 shown in FIG. During the search operation, search instruction signal SRCH is set to H level. When the search result in the previous search cycle indicates a match state and signal ML_OUT is at H level, the output signal of EXNOR circuit 160 is at H level. Accordingly, MOS transistor QP112 is turned off, and charging of match line ML is stopped (current I_charge is off). On the other hand, during the search operation, if the search result in the previous search cycle is a miss and the signal ML_OUT is at L level, the output signal of the EXNOR circuit 160 becomes L level when the search instruction signal SRCH is at H level. In response, MOS transistor QP112 is turned on, and current I_charge is supplied to corresponding match line ML (current I_charge is on).

  In the standby state, search instruction signal SRCH is set to L level. When signal ML_OUT in the previous search cycle is at H level indicating a match state, output signal / CHRG of EXNOR circuit 160 is at L level. Therefore, the MOS transistor QP112 is in a conductive state, and current is supplied to the match line ML. On the other hand, if it is determined in the previous search cycle that there is a miss state, output signal / CHRG of EXNOR circuit 160 is at H level. Therefore, in this state, MOS transistor QP112 is in a non-conductive state.

  Therefore, during the search operation, when the determination result of the previous search cycle is in a miss state and there is a possibility of charging the corresponding match line in the current search cycle, a current is supplied to the corresponding match line ML. On the other hand, in the standby state, in the previous search cycle, the match line in the match state is charged in the standby state and maintained at the H level. On the other hand, the match line in the miss state is not charged during standby, and the corresponding match line ML is maintained at the low level (ground voltage level) during the search operation. This prepares for the state transition of the match line during the next search cycle.

  FIG. 40 is a timing chart representing an operation of match amplifier 150 shown in FIG. The operation of the content reference memory shown in FIG. 38 will be described below with reference to FIG.

  Search data of search lines SL, / SL is switched every clock cycle. Consider a state where match line ML is maintained at the ground voltage level.

  When the search cycle starts at time T10 and the search instruction signal SRCH becomes H level, the output signal of the EXNOR circuit 160 becomes L level and the MOS transistor QP112 becomes conductive as shown in the operation logic diagram of FIG. In the search cycle starting at time T10, when the search data and the stored data of the entry match, the corresponding match line ML has no discharge path, and the voltage level of the match line ML rises. The search instruction signal SRCH is at the H level during the search operation, and the D-type latch circuit 162 is in a latched state. In accordance with search result instruction signal ML_OUT in the previous cycle, signal DVTH output from D-type latch circuit 162 is at the H level. Therefore, input logic threshold value VTH of sense circuit 152 is at a low voltage level. When the match line ML is charged and its voltage level rises from the ground voltage level, the signal transmitted from the sense circuit 150 to the internal signal line MALI in accordance with the input logic threshold value VTH of the low voltage level is an early timing. Becomes H level.

  D-type latch circuit 154 enters a through state when search instruction signal SRCH is at H level, and takes in and outputs a signal on internal signal line MALI given through inverter 163. Therefore, in this state, output signal ML_OUT of D-type latch circuit 154 changes according to the signal on internal signal line MALI when search instruction signal SRCH is at the H level. On the other hand, when the search instruction signal SRCH becomes L level, the D-type latch circuit 154 enters a latch state, latches the fetched signal, and holds the search result.

  Therefore, during the search period in which search instruction signal SRCH is at the H level, when the voltage level of match line ML increases and the voltage level of internal signal line MALI decreases, signal ML_OUT from D-type latch circuit 154 is output from inverter 163. It becomes H level according to the signal. In response, signal / CHRG from EXNOR circuit 160 attains an H level, and charging to match line ML is temporarily stopped.

  When the search period ends and search instruction signal SRCH becomes L level, output signal / CHRG of EXNOR circuit 160 becomes L level again, and charge to match line ML is performed. In this state, the D-type latch circuit 154 is in a latched state. By charging the match line ML, the match line ML is charged to the power supply voltage level. The D-type latch circuit 154 is in a latched state, and its output signal ML_OUT does not change even when the match line ML is charged.

  At this time, the output signal DVTH of the D-type latch circuit 162 is at the H level. Therefore, the input logic threshold value VTH of the sense circuit 152 is in a low state.

  In the search cycle starting from time T11, the search operation for the search data is performed again. In this search cycle, when the search result of the previous cycle is a match state, first, output signal DVTH of D-type latch circuit 162 becomes L level in accordance with the rise of search instruction signal SRCH, and MOS transistor QN114 is turned off. . Accordingly, input logic threshold value VTH of sense circuit 152 is set to a high voltage level.

  Further, in this search cycle, when search instruction signal SRCH becomes H level, output signal / CHRG of EXNOR circuit 160 becomes H level. Accordingly, MOS transistor QP112 is turned off, and the charging operation for match line ML is stopped. According to the search result, match line ML is in a match state, no discharge is performed, and the signal on internal signal line MALI maintains the L level.

  When the search period ends and search instruction signal SRCH becomes L level, D-type latch circuit 154 enters a latching state, and its output signal ML_OUT is maintained at H level. In charge circuit 156, output signal / CHRG of EXNOR circuit 160 is at the L level. Accordingly, match line ML is charged again by MOS transistor QP112, and match line ML maintains the power supply voltage level. In the entry ERY, for example, unit cells UC of 72 bits to 288 bits are connected, and when this match line ML is in a match state, an off-leakage current flows through these match state unit cells. This total off-leakage current cannot be ignored when the number of search data bits is large. The voltage drop of the match line due to the off-leak current of the entry in the match state is suppressed by supplying the charging current I_charge.

  In the search cycle starting from time T12, when the search data does not match the stored data of the entry (in the miss state), when the search instruction signal SRCH becomes H level, the match line ML is in the miss state at the time of this miss. It is discharged through the unit cell UC and its voltage level is lowered. Accordingly, the signal on internal signal line MALI rises to H level, and output signal ML_OUT of D-type latch circuit 154 falls to L level. In charge circuit 156, output signal / CHRG of EXNOR circuit 160 attains an L level, and MOS transistor QP112 is turned on accordingly. Thereby, the current I_charge is once supplied to the match line ML. However, the current I_charge supplied via the MOS transistor QP112 is smaller than the discharge current Imiss of the mismatched match line ML, and the match line ML is maintained at the L level. At this time, in the sense circuit 152, the input logic threshold value VTH is set to a high voltage level. Therefore, the voltage drop of the match line ML is detected at an early timing, and the voltage level of the internal signal line MALI is lowered. The D-type latch circuit 154 is in the through state, and the output signal ML_OUT changes according to the signal of the internal signal line MALI. Even if the match line ML is charged, a discharge current larger than the charge current flows, so that the voltage level thereof is reduced at high speed.

  When search instruction signal SRCH becomes L level, D-type latch circuit 154 enters a latched state, and its output signal ML_OUT is maintained at L level according to the search result of the current search cycle. Accordingly, output signal / CHRG of EXNOR circuit 160 maintains the H level. Therefore, match line ML is maintained in a state of being discharged to the ground voltage level.

  When the search instruction signal SRCH rises to H level in the cycle starting from time T13, the output signal / CHRG of the EXNOR circuit 160 becomes L level and the charging current I_charge for the match line ML is supplied. At this time, the output signal DVTH of the D-type latch circuit 162 becomes H level, and the input logic threshold value VTH of the sense circuit 152 is set to a low voltage level. The charging current I_charge from the charging circuit 156 is smaller than the current Imiss (= In) flowing through the 1-bit missed unit cell. Therefore, the voltage level of match line ML is substantially maintained at the ground voltage level, and the signal of internal signal line MALI is also maintained at the L level. In this state, match line ML and search result instruction signal ML_OUT maintain the same state as the previous search cycle.

  As indicated by the broken-line circle in FIG. 40, the match line ML changes its voltage level when charging from the miss state to the match state and from the match state to the miss state, and is charged and discharged. On the other hand, in search lines SL and / SL, charging / discharging is performed in a cycle in which the bit of the search data changes. Accordingly, if the number of voltage transitions of these search lines and match lines is reduced, current consumption can be reduced accordingly.

  FIG. 41 is a diagram showing charge consumption per search cycle in one column. In FIG. 41, for comparison, charge consumption when match line and search line are precharged to power supply voltage VDD level and when precharged to ground voltage GND is also shown. In the case of this VDD / GND precharge method, the voltage amplitude of the search line and the match line is the power supply voltage VDD.

  In FIG. 41, M and N are the numbers of match lines and search lines, respectively. Cm and Cs indicate the capacity per match line and the capacity per search line, respectively.

  When the number of match lines on which voltage transition is performed is one, this match line is in the VDD precharge system, and at this voltage transition, the match line transitions from the power supply voltage VDD to the ground voltage level. Therefore, in this case, the electric charge consumed is (M−1) · Cm · V. V represents a voltage difference between the power supply voltage VDD and the ground voltage GND.

  When the match line is precharged to the ground voltage GND, the voltage level of the match line that causes this voltage transition changes from the ground voltage level to the power supply voltage level. The remaining match lines are maintained at the ground voltage GND level. Therefore, the electric charge consumed per search cycle is Cm · V. On the other hand, in this embodiment, when a miss and a match occur alternately in one match line, (1/2) · Cm · V of charge is consumed per search cycle. However, if the match (match) or mismatch (miss) state continues and the state transition does not occur, the consumption charge is 0 (the voltage level of the match line does not change).

  When the number of match lines that perform voltage transition is M / 2, the charge consumption per search cycle is (M / 2) · Cm · V in both the VDD precharge method and the ground voltage GND precharge method. is there. In the eleventh embodiment, when misses and matches occur alternately, the electric charge consumed per search cycle is (M / 4) · Cm · V. When misses or matches continue, the consumed charge is zero.

  On the other hand, in the search line, in both the VDD precharge method and the GND precharge method, charge / discharge of the search line is performed in each search cycle, so that N · Cs · V charges are consumed. In this embodiment, when search data matches and does not match alternately, the charge consumed on the search line is (N / 2) · Cs · V. When the search data is continuously the same, the consumption charge is zero.

  As described above, according to the twelfth embodiment of the present invention, the charge consumption in the search cycle is 0 when the match line or the miss line continues in the match line and the search line.

  Usually, during the search operation, the number of match lines in the match state is smaller than that in the miss state. In general, there are a large number of match lines that do not undergo state transition during a search. Therefore, as in the twelfth embodiment, the current consumption can be reduced by selectively charging and discharging the match line based on the search result of the previous cycle.

  In the table shown in FIG. 41, the voltage amplitude of the match line and the search line is the power supply voltage V (= VDD) in the twelfth embodiment. However, the voltage level of match line ML in the match state may be an intermediate voltage level (VDD / 2 or less), as in the configurations shown in the previous sixth to eleventh embodiments.

[Example of change]
FIG. 42 shows a structure of a main portion of the content reference memory according to the twelfth embodiment of the present invention. FIG. 42 shows the configuration of the sense circuit of one match amplifier. In the match amplifier, a charge circuit 156 is provided as in the configuration shown in FIG.

  42, sense circuit 152 includes a differential amplifier circuit 190 that compares the voltage of match line ML with reference voltage Vref. The differential amplifier circuit 190 is formed of a current mirror type differential amplifier circuit, and its operating current is defined according to the bias voltage BIAS. The output signal of differential amplifier circuit 190 is applied to the D input of D-type latch circuit 16. The D-type latch circuit 16 captures in synchronization with the rise of the search instruction signal SRCH and outputs the search result instruction signal ML_OUT. The D-type latch circuit 16 is in a latched state when the search instruction signal SRCH given to the clock input CK becomes L level.

  Sense circuit 152 further includes a transmission gate 188 receiving reference voltage VrefH from high reference voltage generation circuit 182 and a transmission gate 189 receiving reference voltage VrefeL from low reference voltage generation circuit 184.

  Reference voltage generation circuits 182 and 184 are provided in common to the match amplifiers provided on the match lines. The reference voltage VrefH is a voltage level higher than the reference voltage VrefL.

  Transmission gates 188 and 189 are alternatively rendered conductive according to the output signals of D-type latch circuit 180 and inverter 186. That is, when the output signal ML_OD of the D-type latch circuit 180 is at the H level, the transmission gate 188 is turned on and the transmission gate 189 is turned off. On the other hand, when output signal ML_OD of D-type latch circuit 180 is at L level, transmission gate 189 is in a conducting state and transmission gate 188 is in a conducting state. A reference voltage selected by these transmission gates 188 and 189 is used as a match line voltage level determination reference of differential amplifier circuit 190.

  Sense circuit 152 further includes a D-type latch circuit 180 that takes in search result instruction signal ML-OUT output from D-type latch circuit 16 in synchronization with the fall of search instruction signal SRCH, and an output signal of D-type latch circuit 180. And an inverter 186 for inverting. The D-type latch circuit 180 is in a latched state when the search instruction signal SRCH becomes H level. Output signal ML_OD of D-type latch circuit 180 is applied to EXNOR circuit 160 in charge circuit 156 shown in FIG.

  FIG. 43 is a timing chart representing an operation of the match amplifier shown in FIG. Hereinafter, the operation of the match amplifier shown in FIG. 42, particularly the operation of the sense circuit 152 will be described with reference to FIG.

  When the search result of the cycle before the cycle starting from time T10 is in a miss state, the output signal ML_OD of the D-type latch circuit 180 is at the L level. In this state, transmission gate 189 is in a conductive state, and reference voltage VrefL from low reference voltage generation circuit 184 is applied as a reference voltage for differential amplifier circuit 190. At this time, in the pull-up current supply circuit (not shown in FIG. 42), the output signal / CHRG of the EXNOR circuit is at the L level, and current supply to the match line is performed.

  When the search data matches the stored data in the cycle from time T10, the voltage level of match line ML rises. When the voltage level of the match line ML becomes higher than the reference voltage VrefL, the output signal MALI of the differential amplifier circuit 190 becomes H level, and the output signal ML_OUT of the D-type latch circuit 16 becomes H level. In this cycle, when search instruction signal SRCH falls to the L level in synchronization with clock signal CLK, D-type latch circuit 180 enters the through state, and its output signal ML_OD becomes the H level. In order to maintain the voltage level of the match line in the coincidence state, the signal / CHRG maintains the L level. In response to the rise of the output signal ML_OD of the D-type latch circuit 180, the transmission gate 189 is turned off and the transmission gate 188 is turned on. Accordingly, reference voltage VrefH from high reference voltage generation circuit 182 is applied as a reference voltage for differential amplifier circuit 190.

  In the cycle starting from time T11, when the match line ML is in the match state, the state of the match amplifier does not change.

  In the cycle starting from time T12, the clock signal CLK and the search instruction signal SRCH rise to H level, and the search operation is performed. In this cycle, when the search result is in a miss state, the voltage level of the match line ML decreases. At this time, the reference voltage Vref of the differential amplifier circuit 190 is at a high voltage level (VrefH). Accordingly, the output signal MALI of the differential amplifier circuit 190 becomes L level at an early timing after the potential of the match line ML is lowered, and the search result instruction signal ML_OUT from the D-type latch circuit 16 is determined at an early timing.

  In this cycle, when the search instruction signal SRCH becomes L level in synchronization with the fall of the clock signal CLK, the output signal ML_OD of the D-type latch circuit 180 becomes L level. Accordingly, transmission gate 189 is turned on and transmission gate 188 is turned off, and reference voltage Vref of differential amplifier circuit 190 is set to a lower reference voltage VrefL. In the cycle starting from time T12, the search result of the previous search cycle is in a match (match) state, and signal / CHRG is maintained at the H level. Accordingly, the pull-up current is not supplied to the match line.

  In the cycle starting from time T13, the search result of the previous search cycle is a miss, and a pull-up current is supplied at the start of the search operation of this cycle. However, the search result is a miss in this cycle, and the voltage level of the match line ML maintains the L level. Accordingly, the search result instruction signal ML_OUT and the output signal ML_OD of the D-type latch circuit 180 are. Maintain L level.

  By setting the reference voltage Vref of the differential amplifier circuit 190 according to the result of the previous search cycle, the reference voltage of the differential amplifier circuit can be set to a voltage level close to the voltage level of the match line. Thereby, the search result can be determined at an early timing, and the search operation can be speeded up.

  As described above, according to the twelfth embodiment of the present invention, the match line is selectively charged according to the previous search cycle result, and the current consumption can be further reduced. Further, the input logic threshold value of the sense circuit is adjusted according to the search result of the previous search cycle. Therefore, the input logic threshold value can be set to a voltage level close to the voltage level of the match line, and the voltage change of the match line can be detected at an early timing.

[Embodiment 13]
FIG. 44 shows a structure of a main portion of the content reference memory according to the thirteenth embodiment of the present invention. 44, match amplifier 150 includes sense circuit 152, D-type latch circuit 154, and charge circuit 156, as in the previous twelfth embodiment. The charge circuit 156 differs in configuration from the charge circuit 156 shown in FIG. 33 in the following points. That is, P channel MOS transistors QP120 and QP112 are provided in series between the power supply node and match line ML. Bias voltage PBIAS is applied to the gate of MOS transistor QP120, and output signal / CHRG of EXNOR circuit 160 is applied to the gate of MOS transistor QP112.

  In order to generate the bias voltage PBIAS, a replica entry 200 and a bias voltage generation circuit 210 are provided. Replica entry 200 includes replica unit cell UCh having the same configuration as the discharge path of unit cell UC in a match state of entry ERY of the memory cell array.

  Replica unit cell UCh includes N channel MOS transistors QN121 and QN122 connected in series between replica match line RMLb and the ground node, and an N channel MOS transistor connected in series between replica match line RMLb and the ground node. QN123 and QN124 are included. These MOS transistors QN121 to QN124 have the same size (ratio of channel width to channel length) as the transistors TR1 to TR3 of the unit cell UC. Each of these MOS transistors QN121-QN124 receives a ground voltage at its gate and is set in a non-conductive state. Therefore, in this replica unit cell UCh, an off-leakage current 2 · I_off (= Ioff) flows. The magnitude of the off-leak current is the same as the current flowing through the matched unit cell UC. Here, the off-leakage current I_off indicates an off-leakage current that flows in one discharge path of the unit cell.

  Bias voltage generation circuit 210 includes a P-channel MOS transistor QP121 that supplies a current to replica match line RMLb. This MOS transistor QP121 has its gate and drain connected to each other. Bias voltage generation circuit 210 further includes P channel MOS transistors QP122 and QP124. MOS transistor QP122 forms a current mirror circuit with MOS transistor QP121. MOS transistor QP124 is coupled to a power supply node, and has its gate and drain interconnected.

  Bias voltage generation circuit 210 further includes N channel MOS transistors QN125 and QN126 connected in series between MOS transistor QP124 and the ground node, and P channel MOS transistor QP123 forming a current mirror circuit with MOS transistor QP124. MOS transistors QN125 and QN126 have their gates connected to the power supply node, and these MOS transistors QN125 and QN126 are always kept in a conductive state.

  Bias voltage generation circuit 210 further includes N channel MOS transistors QN 127 and 128 and a P channel MOS transistor QP 125. MOS transistor QN127 has a gate and a drain connected to each other and receives a total current IA supplied from MOS transistors QP122 and QP123. MOS transistor QN128 forms a current mirror circuit with MOS transistor QN127. MOS transistor QP125 has a gate and a drain connected to each other, supplies a current from the power supply node to MOS transistor QN128, and converts the supplied current into a voltage to generate bias voltage PBIAS.

  MOS transistors QN125 and QN126 have the same size as TR1 and TR2 or TR3 and TR4 of the transistors in series in unit cell UC of entry ERY. Therefore, in MOS transistors QN125 and QN126, 1-bit drawing current I_miss (= In) having the same magnitude as the current discharged through the transistor serial body in the conducting state in unit cell UC in the missed state flows.

  This 1-bit drawing current I_miss is supplied via the MOS transistor QP124. The MOS transistors QP121-QP125 are all the same size. Therefore, the current supplied by the MOS transistor QP123 is the extraction current I_miss (= In) of the 1-bit unit cell. On the other hand, the MOS transistor QP121 supplies an off-leak current to the m-bit replica unit cell UCh to the replica match line RMLb. Therefore, the supply current is 2 · m · I_off.

  MOS transistor QP122 supplies a mirror current of the current supplied by MOS transistor QP121. Therefore, the total current IA is represented by 2 · I_off · m + I_miss (= m · Ioff + In). This current IA is discharged by MOS transistor QN127, and a mirror current of this current IA flows through MOS transistor QN128. MOS transistor QP125 generates bias voltage PBAIS corresponding to the current flowing through MOS transistor QN128.

  The size of MOS transistor QP120 (mutual conductance gm) is made smaller than the size of MOS transistor QP125 (mutual conductance gm). For example, gm of MOS transistor QP120 is set to a value ½ times gm of MOS transistor QP125. Therefore, current I_charge flowing through MOS transistor QP120 is equal to or less than ½ of current IA. As a result, a current smaller than the 1-bit miss current Imiss or 1-bit extraction current I_miss (= In) and larger than the total off-leakage current IOFF (= 2 · m · I_off) of the entry in the match state is supplied to the match line ML. be able to.

  As shown in FIG. 44, the replica entry 200 can be used to reflect variations in the transistor parameters of the unit cell UC of the entry ERY. That is, MOS transistors QN125 and QN126 are formed so as to receive the same parameter variation as transistors TR1-TR4 of unit cell UC of entry ERY (formed in the vicinity region in the same manufacturing process). The value of this current IA can be adjusted according to the variation of the drawing current I_miss at the time of a miss. For example, when the off-leakage current I_off of the unit cell in the entry storing data increases, the current IA also increases. Accordingly, the current value of the charging current I_charge from the charging circuit 156 can also be increased, and the fluctuation of the off-leak current with respect to the match line ML can be compensated. Therefore, even when match line ML is maintained at H level according to the search result of the previous search cycle, match line ML can be accurately maintained at H level.

  Further, even when the 1-bit drawing current I_miss (= In) is reduced, the total current IA is reduced, and the charging current I_charge can be reduced. Accordingly, it is possible to prevent the rate of decrease in the voltage level of the match line for the entry in the miss state from being slowed down, and to prevent the search cycle from being lengthened.

  As described above, according to the thirteenth embodiment of the present invention, a bias voltage is generated using a replica entry composed of a match unit cell and a replica unit cell corresponding to a unit cell in a 1-bit miss state. The charging current for the match line is generated. Therefore, it is possible to accurately adjust the charging current of the match line by compensating for variations in transistor parameters. The effect of the configuration in which the charging current for the match line is generated using this replica entry can be obtained in the same manner as in the previous tenth and eleventh embodiments, and the desired variation can be accurately compensated by compensating for variations in transistor parameters. A level of current can be generated.

In addition, the same effect as in the eleventh and twelfth embodiments can be obtained.
[Embodiment 14]
FIG. 45 shows a structure of a main part of the content reference memory according to the fourteenth embodiment of the present invention. The configuration of the content reference memory shown in FIG. 45 corresponds to the combination of the tenth and thirteenth embodiments. That is, in FIG. 45, match amplifier 150 is a signal of MOS transistor QP130, QP112 and QN130 connected in series between the power supply node and match line ML, and an internal search result signal MA_ML of the connection node of MOS transistors QP112 and QN130. Includes a D-type latch circuit 154 and an EXNOR circuit 160 that generates a charge instruction signal / CHRG. D-type latch circuit 154 latches the signal applied to the D input in accordance with search instruction signal SRCH. EXNOR circuit 160 receives output signal ML_OUT of D-type latch circuit 154 and search instruction signal SRCH, and generates a charge instruction signal / CHRG for the gate in MOS transistor QP112.

  Bias voltage BIAS_P from bias voltage generation circuit 45 is applied to the gate of MOS transistor QP130. Bias voltage BIAS_N2 from buffer 130 is applied to the gate of MOS transistor QN130. The configurations of bias voltage generating circuit 45 and buffer 130 are the same as those of bias voltage generating circuit 45 and buffer 130 shown in FIG.

  In the memory cell array, a plurality of entries ERY are provided, and a match line ML is provided corresponding to each entry ERY. The entry ERY includes an m-bit unit cell UC. The configuration of this unit cell UC is the same as the configuration of the unit cells in the first to twelfth embodiments, and the CAM cell CC for storing data and the search MOS transistor TR1 for comparing the search data with the stored data. -Includes TR4.

  Bias voltage BIAS_P from bias voltage generation circuit 45 shown in FIG. 45 is applied to the gate of P channel MOS transistor QP 130 in match amplifier 150. The MOS transistor QP130 is smaller than the current (I_miss or Imiss) flowing through the 1-bit miss unit cell in accordance with the bias voltage BIAS_P, and is the sum (IOFF) of the off-leakage current I_off of the m-bit unit cell in the matching state of the corresponding entry. A larger current value is supplied. P channel MOS transistor QP112 and N channel MOS transistor QN130 are connected in series between MOS transistor QP130 and match line ML. MOS transistor QP112 receives charging instruction signal / CHRG from EXNOR circuit 160 at its gate. MOS transistor QN130 receives bias voltage BIAS_N2 from buffer 130. MOS transistors QP130 and QN130 correspond to MOS transistors QP91 and QN71 shown in FIG. 31, respectively.

  In the configuration shown in FIG. 45, MOS transistor QN130 operates in the source follower mode by bias voltage BIAS_N2. Therefore, the voltage level of the corresponding match line ML becomes equal to or lower than the voltage VML (≦ VDD / 2), and the voltage rise of the match line ML is suppressed. Further, when MOS transistor QN130 becomes non-conductive due to an increase in the voltage level of match line ML, internal node MA_ML and the match line are separated. In response, the potential of internal node MA_ML rises at high speed, and determination result signal MA_ML can be driven to a definite state (power supply voltage level) at high speed.

  Also in the configuration shown in FIG. 45, signal / CHRG for MOS transistor QP112 is generated according to search result instruction signal ML_OUT in the previous search cycle. Therefore, supply / cutoff of the charge current to the match line ML corresponding to the search operation can be controlled according to the search / determination result of the previous search cycle.

  FIG. 46 shows an operation of the content reference memory shown in FIG. Hereinafter, the operation of the content reference memory shown in FIG. 45 will be described with reference to FIG.

  In the search operation shown in FIG. 46, one search cycle is set to two cycles of clock signal CLK. However, like the previous embodiment 12, this search cycle may be made equal to one clock cycle period of the clock signal CLK.

  Now, it is assumed that in the cycles CY1 and CY2 of the clock signal CLK, it is determined that a miss state has occurred in the previous search. In this assumption, match line ML is maintained at the ground voltage level, internal search result signal MA_ML is at the ground voltage level, and output signal ML_OUT of D-type latch circuit 154 is at the L level.

  In clock cycle CY3, a search operation is performed according to new search data. In this cycle, when search instruction signal SRCH becomes H level, signal / CHRG from EXNOR circuit 160 becomes L level. Responsively, MOS transistor QP112 is turned on, and the match line ML is charged. When the match line ML is charged, as described in the tenth embodiment, the voltage level is suppressed to the intermediate voltage VML or less by the MOS transistor QN130. MOS transistor QN130 performs a decoupling operation in accordance with bias voltage BIAS_N2 from buffer 130. As a result, the voltage level of the internal search result signal MA_ML increases, and finally increases to the power supply voltage VDD level.

  In clock cycle CY4, when search instruction signal SRCH becomes L level, search result instruction signal ML_OUT output from D-type latch circuit 154 rises to H level. At this time, output signal / CHRG of EXNOR circuit 160 maintains the L level, and the charging operation for the match line is performed. However, due to the source follower operation of MOS transistor QN130, match line ML maintains a voltage level equal to or lower than voltage VML level. That is, the off-leak current of all bit unit cells in the match line ML is used to maintain a predetermined voltage level.

  In clock cycle CY5, the search data changes, and search instruction signal SRCH again goes to L level. At this time, the search result of the previous cycle is the match state, the signal ML_OUT is at the H level, the output signal / CHRG of the EXNOR circuit 160 is at the H level, the MOS transistor QP112 is turned off, and the match line ML is charged. The operation is stopped. In this cycle, when the search result of the search data is in a miss state, the match line ML is discharged and its voltage level is lowered. Accordingly, the voltage level of internal search result signal MA_ML also decreases.

  In clock cycle CY6, when search instruction signal SRCH falls to L level, output signal ML_OUT of D-type latch circuit 154 becomes L level. The output signal / CHRG of the EXNOR circuit 160 maintains the H level, and charging to the match line ML is stopped. Therefore, match line ML is maintained at the ground voltage level.

  Next, a search is performed in the clock cycle CY7 according to the next search data. At this time, if the search result for the search data is in a miss state, even if the output signal / CHRG of the EXNOR circuit 160 is at L level, the charging current is set to the unit cell in the miss state of the entry coupled to the match line ML. The match line ML is maintained at the ground voltage level. Accordingly, the search result instruction signal ML_OUT is also at the L level due to the voltage level of the internal signal line MA_ML.

  In the clock cycle CY8, when the search instruction signal SRCH becomes L level, the MOS transistor QP112 becomes conductive. Accordingly, the match line ML is charged and the voltage level of the match line ML rises. Further, the voltage level of the internal search result signal MA_ML rises.

  In clock cycle CY10, output signal ML_OUT of D-type latch circuit 150 becomes H level. In this case, search instruction signal SRCH is at L level, output signal / CHRG of EXNOR circuit 160 is maintained at L level, and match line ML is charged. Thereby, the match line ML is maintained at the intermediate voltage (precharge voltage) VML level.

  When the search operation is performed again in the clock cycle CY11 and the search result is a match state, the output signal / CHRG of the EXNOR circuit 160 becomes H level, and charging to the match line ML is stopped. When search instruction signal SRCH becomes L level, signal / CHRG becomes L level. Depending on. Charging of match line ML is performed via MOS transistor QN130, and the voltage level of match line ML is maintained.

  The search operation is performed again at clock cycle CY13. When the search result is in a miss state, signal / CHRG is at the H level and no discharge is performed on match line ML. Accordingly, the voltage levels of match line ML and internal signal line MA_ML are lowered to the ground voltage level, and search result instruction signal ML_OUT is lowered to the L level in the next clock cycle CY14. At this time, signal / CHRG is also at the L level again, and charging operation for match line ML is performed.

  Therefore, when the previous search result is a match state, supply of current to the match line ML is stopped during the search operation. Only when the previous search result is a miss, charging current is supplied to the match line during the search operation. Thereby, the number of times the match line ML is charged can be reduced, and current consumption can be reduced. Further, when the search result is in a miss state in the previous cycle, the match line ML is at the ground voltage level, and there is a possibility that the voltage level needs to be raised, current is supplied to the match line during the search operation, Search operation can be performed at high speed.

  Further, it is not necessary to precharge the match line every search cycle, and the current consumption can be reduced. As in the previous tenth embodiment, the amount of charge current for match line ML is adjusted using bias voltages BIAS_P and BIAS_N2, and the charge current is supplied to the match line via MOS transistor QN130. Therefore, the voltage level of the match line ML can be suppressed to a voltage level equal to or lower than the voltage VML. Thereby, the voltage amplitude of the match line can be reduced, and the current consumption during the search operation can be greatly reduced as in the tenth embodiment. In addition, since a match and a miss are detected by charging / discharging the internal signal line MA_ML with a small wiring load, a high-speed search operation can be realized.

  In the fourteenth embodiment, a current conversion circuit may be provided as shown in FIG. 37 to perform level conversion of bias voltage BIAS_P.

[Embodiment 15]
FIG. 47 schematically shows a structure of a content reference memory according to the fifteenth embodiment of the present invention. In FIG. 47, a CAM cell array in which a CAM cell (unit cell) is arranged is divided into two global search blocks GSB1 and GSB2. In the CAM cell array, although not clearly shown, a plurality of entries described so far are provided. Global search block GSB1 includes a plurality of local search blocks SB11 to SB18, and global search block GSB2 includes a plurality of local search blocks SB21 to SB28. In each of these local search blocks SB11-SB18 and SB21-SB28, a match line group MLs composed of a plurality of match lines ML is arranged, and a search line pair group (search data bus) SLPs composed of a plurality of search line pairs is arranged. Be placed. As an example, the match line group MLs includes 1K match lines ML. The search line pair group SLPs includes a 144-bit search line pair SLP.

  Match amplifier groups MA11-MA18 and priority encoders PE11-PE18 are provided for local search blocks SB11-SB18, respectively. Match amplifier groups MA11-MA18 each include match amplifiers arranged corresponding to the match lines of the corresponding local search block. This match amplifier may be the match amplifier shown in any one of the first to thirteenth embodiments, or may be composed of a match amplifier similar to the conventional one. By using the match amplifier shown in the above embodiments, a search operation can be performed at high speed with low current consumption. Even if a match amplifier having the same configuration as that of the conventional one is used, the effect of the configuration of the content reference memory according to the fifteenth embodiment can be obtained.

  Each of the priority encoders PE11 to PE18 selects a match line having the highest priority from the corresponding match amplifier groups MA11 to MA18 according to a predetermined priority rule, and generates information about the selected match line.

  In FIG. 47, the priority (priority order) of the local search block SB11 is the highest, and the priority order decreases sequentially toward the local search block SB18. The global search block GSB1 has a higher priority than the global search block GSB2. Even in the global search block GSB2, priorities are set so that the priorities sequentially decrease from the local search block SB21 toward the local search block SB28.

  For each of the local search blocks SB11 to SB18, search data input circuits FF11 to FF18 configured by flip-flops are provided. The search data input circuits FF11 to FF18 are commonly supplied with search data from the FF circuit FF1 that receives search data SD from the outside. These search data input circuits FF11-FF18 respectively drive search line groups SLs of corresponding local search blocks SB11-SB18 according to the provided search data.

  A search data input circuit (FF circuit) FF1 takes in and outputs given data in accordance with an external clock signal CLKex. Therefore, the search data supplied to the search data input circuits (FF circuits) FF11 to FF18 is updated every cycle of the external clock signal CLKex.

  In global search block GSB1, digital delay circuits DL10-DL18 that sequentially delay external clock signal CLKex are cascade-connected. Delay clock signals output from the digital delay circuits DL10 to DL17 (digital) are respectively supplied as search data fetch clock signals to the search data input circuits FF11 to FF18. Further, according to the delayed clock signal output from the digital delay circuits DL11 to DL18, search, search result determination, and determination result instruction generation operation are executed in each local search block SB11 to SB18. For example, the output signal of digital delay circuit DL11-DL18 is used as search instruction signal SRCH as shown in the previous twelfth embodiment. Thereby, in each local search block SB11-SB18, the start timing is sequentially shifted, and the search, the search result determination, and the search result determination output are performed.

  In global search block GSB2, search data input circuits FF21-FF28 are provided corresponding to local search blocks SB21-SB28, respectively, and match amplifier groups MA21-MA28 and priority encoders PE21-PE28 are provided. In addition, in order to control the search operation of each local search block, cascaded digital delay circuits DL20 to DL28 are provided.

  In order to adjust the delay times of the digital delay circuits DL10-DL18 and DL20-DL28, a delay control circuit 220 is provided.

  The delay control circuit 220 detects a phase difference between the external clock signal CLKex and the internal clock signal CLKin, and generates a delay control signal corresponding to the phase difference, and a cascaded digital delay circuit DL1- DL8 and an inverter buffer IVB that inverts an output signal of the final stage digital delay circuit DL8 and supplies the inverted signal to the first stage digital delay circuit DL1. A ring oscillator is formed by inverter buffer IVB and digital delay circuits DL1-DL8. An internal clock signal CLKin is generated from the digital delay circuit DL8.

  Digital phase difference detection circuit 222 adjusts the delay time of digital delay circuits DL1-DL8 so that the phases of external clock signal CLKex and internal clock signal CLKin are equal, and is provided corresponding to each local search block accordingly. The delay times of the digital delay circuits DL10-DL18 and DL20-DL28 are adjusted.

  Further, the global search block GSB2 receives the search data input circuit (FF circuit) FF2 that receives the search data output from the search data input circuit (FF circuit) FF1, the output signal of the priority encoder PE18, and the external clock signal CLKex. A gate circuit 225 is provided.

  The priority encoder PE18 is an encoder having the lowest priority in the global search block. Therefore, when the signal output from the priority encoder PE18 is at the L level, it indicates that no stored data matching the search data was found in the global search block GSB1. Therefore, in the global search block GSB2, the search operation is executed when no match is detected in the global search block GSB1.

  An output signal of the gate circuit 225 is supplied as a clock signal to the digital delay circuits DL20 to DL28. When the gate circuit 225 is enabled (when the output signal of the priority encoder PE18 is at L level), the local search blocks SB21 to SB28 of the global search block GSB2 sequentially operate according to the clock signal supplied through the gate circuit 225. The search operation is performed with the start timing shifted.

  Similarly, the search data input circuit (FF circuit) FF2 takes in the search data provided from the FF circuit FF1 in accordance with the output signal of the gate circuit 225, and inputs the search data of the local search blocks SB21 to SB28 using the taken-in data as search data. Apply to circuits FF21-FF28.

  FIG. 48 is a timing chart showing the operation of the delay control circuit 220 shown in FIG. Hereinafter, the operation of the delay control circuit 220 shown in FIG. 47 will be described with reference to FIG.

  As described above, the digital phase difference detection circuit 222 makes the phase of the external clock signal CLKex and the internal clock signal CLKin equal. The delay time of the digital delay circuits DL1-DL8 is adjusted.

  When the phases of clock signals CLKex and CLKin are equal, the output signal of inverter buffer IVB changes in synchronization with the change of external clock signal CLKex in accordance with internal clock signal CLKin. Here, the delay time of the inverter buffer IVB is set to a value that can be ignored as compared with the delay time of the digital delay circuits DL1 to DL8. When the output signal of the inverter buffer IVB changes, the digital delay circuits DL1-DL8 change their logic states with a delay time d, respectively. Therefore, when the internal clock signal CLKin and the external clock signal CLKex have the same phase, the cycle time Tc of the internal clock signal CLKin is d · 2 · 8 and the internal clock signal CLKin and Are equal in period).

  The digital delay circuits DL1-DL8 and the digital delay circuits DL10-DL18 and DL20-DL28 have the same configuration. Therefore, the same delay time as that of the digital delay circuits DL1-DL8 can be set in the digital delay circuits DL10-DL18 and DL20-DL28.

  These digital delay circuits DL1-DL8, DL10-DL18, and DL20-DL28 are each composed of, for example, a buffer circuit (two-stage inverter) having a variable current source capable of changing the operating current, and a digital phase difference detection circuit The operating current value is adjusted according to the phase difference information detected by 222, and the delay time d is adjusted accordingly.

  As described above, the clock signal for defining the operation cycle for the local search blocks SB11 to SB18 is supplied using the digital delay circuits DL10 to DL18. As a result, in the global search block GSB1, the search operation and the search result determination operation can be performed with respect to the local search blocks SB11 to SB18 sequentially shifted by the delay time d of the digital delay circuits DL10 to DL18. The current can be reduced. The same applies to the global search block GSB2.

  Further, the search line is divided for each local search block, the wiring load capacity of the search line can be reduced, and the charge / discharge current of the search line can be reduced. Further, the search line can be driven at a high speed according to the search data.

  FIG. 49 is a timing chart showing an operation of the content reference memory shown in FIG. The operation of the content reference memory shown in FIG. 47 will be described below with reference to FIG.

  As shown in FIG. 49, when the external clock signal CLKex becomes H level, the output signal from the search data input circuit (FF circuit) FF1 is updated and determined. Next, in accordance with the output signal of digital delay circuit DL10, search data input circuit FF11 for local search block SB11 takes in the applied data, and drives search data line group SLPs therein according to the search data. Next, after the elapse of the delay time d of the digital delay circuit DL11, the match amplifier group MA11 and the priority encoder PE11 are activated according to the output signal of the digital delay circuit DL11, and the search data and the stored data are compared and the search result is determined. .

  In parallel with the match line driving in the local search block SB11, in the local search block SB12, the search data input circuit FF12 takes in the data provided in accordance with the output signal of the digital delay circuit DL11, and the corresponding search data line group SLPs is retrieved. Drive according to this search data. Subsequently, a search operation is performed internally after time d according to the output signal of the digital delay circuit DL12.

  Thereafter, search operations are sequentially executed in the local search blocks SB11... SB17 (not shown). Search data input circuits FF11-FF17 take in the search data provided from search data input circuit FF1 in synchronization with the rise of the output signal of the corresponding digital delay circuit (the rise of external clock signal CLKex), and enter the latch state. . In the local search block SB18 at the final stage, the search data input circuit FF18 is in a latched state according to the output signal of the digital delay circuit DL17 (not shown) at the previous stage, and drives the search line group SLBs according to the search data. Next, after the elapse of time d, the match amplifier group MA18 is activated.

  The priority is sequentially lowered from the search block SB11 toward the local search block SB18. If a match state is detected in any of the local search blocks of global search block GSB1, the output signal of priority encoder PE18 at the final stage becomes H level, and the output signal of gate circuit 225 is fixed at L level. Accordingly, transmission of the clock signal to global search block GSB2 is prohibited, and the search operation is stopped. At this time, the search data input circuit (FF circuit) FF2 does not latch the supplied search data.

  The search line is divided into a plurality of global blocks. When a match is detected in a global search line block with a high priority, the search operation for the global search line block with a low priority is stopped. Thereby, current consumption can be reduced.

  FIG. 50 is a diagram illustrating an example of the configuration of the priority encoders PE11 to PE18 and PE21 to PE28. In FIG. 50, description will be made using the reference numerals of the priority encoder PE as representative of the configuration of the priority encoders PE11 to PE18 and PE21 to PE28. In FIG. 50, the arrangement of priority encoders with the highest priority is shown as an example.

  In FIG. 50, determination result outputs MLOUTa to MLOUTn correspond to search result instruction signals output from the match amplifiers of the corresponding match amplifier group for each match line, respectively.

  Priority encoder PE includes gate circuits GTa-GTn provided corresponding to match line determination result outputs MLOUTa-MLOUTn, and OR gates OGa-OGn for receiving output signals of gate circuits GTa-GTn, respectively. Each of the gate circuits GTb to GTn receives the output signal of the preceding OR gate OGa-OG (n−1) as a complementary input, and receives the output signal of the match amplifier corresponding to the non-inverting input. The output signal of the final-stage OR gate OGn is given to the priority encoder PE of the next priority. The complementary input of gate circuit GTa is coupled to the ground node.

  As for the priority order, the output MLOUTa is the highest and the output MLOUTn is the lowest. Each of gate circuits GTa-GTn outputs an H level signal when search result instruction MLOUT from the corresponding match line is at the H level indicating the match state and the output signal of the corresponding OR gate is at the L level. To do. Each of these gate circuits GTa-GTn fixes its output signal at L level when its complementary input signal becomes H level.

  The complementary input of the gate circuit GTa is fixed at the ground voltage level (for the highest priority priority encoder). However, when a local search block of higher priority is provided for this priority encoder PE, the complementary input of the gate circuit GTa of the priority encoder PE is replaced with the ground voltage, and the last stage of the preceding priority encoder The output signal of the OR gate OGn is supplied.

  The match line data MLDTa-MLDTn output from the gate circuits GTa-GTn may be further encoded, and information specifying the match line address in the match state may be generated. Further, data may be read from the corresponding word line by driving the word line of the table memory to the selected state using these match line data MLDTa-MLDTn as the word line drive signal (gate circuit GTa -The output of GTn is coupled to the word line of the table memory).

  In the priority encoder PE shown in FIG. 50, for example, consider a state in which output signals MLOUTb and MLOUTc are both at the H level. Signal MLOUTa is set to L level. At this time, the output signal of gate circuit GTa is at L level, and the output signal of OR gate OGa is at L level. Therefore, the match line data MLDTb from the gate circuit GTb is at the H level. When match line data MLDTb becomes H level, the output signal of OR gate OGb becomes H level. In this state, gate circuit GTc maintains its output signal MLDTc at L level even if corresponding match line data MLOUTc is at H level. The output signals of the OR gates with lower priorities are all at the H level, and accordingly the outputs of the gate circuits with lower priorities are at the L level. Therefore, when a match state is detected in a match line with a high priority, match line information for the match line with the highest priority is driven to an active state, and the remaining match line data is set to a state indicating a miss state. .

  A priority encoder as shown in FIG. 50 as an example is used for priority encoders PE11 to PE18 shown in FIG. As a result, in the priority encoders PE11 to PE18 shown in FIG. 47, when the priority encoder having a higher priority level detects a match state, all the match line data output by the priority encoder having a lower priority level are in the L-level miss state. (The output signal of the OR gate is set to H level).

  The output signal of the OR gate at the final stage of the priority encoder PE18 becomes H level when a match state is detected in the global search block GSB1. Accordingly, the output signal of gate circuit 225 shown in FIG. 47 is fixed at L level, and transmission to the clock signal for global search block GSB2 is prohibited. Since the search operation in the global search block GSB2 is prohibited, the number of operating local search blocks can be reduced, and current consumption can be suppressed.

  In the configuration shown in FIG. 47, global search blocks GSB1 and GSB2 each include eight local search blocks. However, the number of local search blocks included in one global search block is not limited to eight, and other numbers of local search blocks may be used. Further, more global search blocks GSB1 and GSB2 may be provided. The number of digital delay circuits included in the delay control circuit 220 is set according to the number of local search blocks included in the global search block.

  Note that the circuit that generates the bias voltage or the reference voltage may be provided in common in the global search block, or may be provided in each global search block. As the control signal for controlling the active search operation of the local search block, as shown in the eleventh to fourteenth embodiments, when the search instruction signal SRCH is used, the signal output from the digital delay circuit is used as the search instruction. What is necessary is just to use as a signal. When using other match amplifier activation signals, precharge instruction signals, etc., the operation timing is adjusted based on the output signal of the corresponding digital delay circuit, and the operation control signal for each local search block Should be generated.

[Embodiment 16]
FIG. 51 schematically shows a structure of a main portion of the content reference memory according to the sixteenth embodiment of the present invention. FIG. 51 representatively shows match amplifier 200 provided corresponding to match line ML. Unit cells UC are coupled in parallel to match line ML. In FIG. 61, 73-bit search data of search lines SL [0], / SL [0] -SL [42], / SL [72] is shown as an example.

  In unit cell UC, in the configuration shown in FIG. 51, the CAM cell for storing data is an SRAM cell. This SRAM cell is connected to the gates of MOS transistors TR1 and TR3 provided close to match line ML. MOS transistors TR2 and TR4 are coupled to search lines SL [0] and / SL [0], respectively. In unit cell UC, an SRAM cell may be coupled to MOS transistors TR2 and R4, and search lines SL [0] and / SL [0] may be coupled to MOS transistors TR1 and TR3. Further, instead of the SRAM cell SMC, two memory cells may be used, and a unit cell configuration for storing ternary data may be used. The configuration of unit cell UC is not limited to the configuration shown in FIG. 51, and the configuration of unit cells shown in FIGS. 2 and 3 in the first embodiment may be used.

  Match amplifier 200 includes a precharge circuit 210 and an isolation gate circuit 30. Precharge circuit 210 precharges match line ML and reference voltage node NDa to precharge voltage VML level equal to or lower than the intermediate voltage level in accordance with precharge instruction signal MLPRE. Isolation gate circuit 30 separates match line ML and reference voltage node NDa from internal nodes (first and second nodes) NDb and NDc, respectively, according to isolation instruction signal MLI.

  Precharge circuit 210 includes N channel MOS transistors 211 and 212 transmitting precharge voltage VML to match line ML and reference voltage node NDa in accordance with precharge instruction signal MLPRE, respectively. Isolation gate circuit 30 includes transfer gates TGa and TGb provided for match line ML and reference voltage node NDa, respectively.

  Match amplifier 200 further includes an amplifier circuit 12 and a latch 16. Amplifier circuit 12 is activated in response to activation of match amplifier activation signal MAE, and differentially amplifies signals ML_MA and MLREF of internal nodes NDb and NDc. The latch 16 latches the output signal of the amplifier circuit 12 in accordance with the latch instruction signal LAT.

  Amplifying circuit 12 has a configuration similar to that of differential amplifier 12 shown in FIG. 10, and differentially amplifies and latches voltages ML_MA and MLREF on internal nodes NDb and NDc. The latch 16 has the same configuration as that of the latch shown in FIG. 10 and enters the through state when the latch instruction signal LAT is at the H level, and generates the search result instruction signal ML_OUT in accordance with the output signal of the amplifier circuit 12.

  Match amplifier 200 further includes capacitive elements C1_A and C1_B provided in internal node NDb (first internal node) and internal node NDc (second internal node), respectively. Capacitance element C1_A boosts the voltage level of internal node NDb by charger pump operation (capacitive coupling) in accordance with boost instruction signal MLUP. Capacitance element C1_B is connected between internal node NDc and the power supply node. The capacitive element C1_B has the same capacitance value as that of the capacitive element C1_A, and is provided to balance the capacitances of the internal nodes NDb and NDc.

  FIG. 52 is a timing chart showing an operation of the content reference memory shown in FIG. Hereinafter, the search operation of the content reference memory shown in FIG. 51 will be described with reference to FIG.

  Before the search operation starts, match line ML is at the ground voltage GND level. Isolation instruction signal MLI is at H level, and isolation gate circuit 30 is in a conductive state. The latch instruction signal LAT is at L level, the latch 16 is in a latched state, and outputs an H level signal ML_OUT as an example.

  At time T1, the search cycle begins. In accordance with the start of the search operation, precharge instruction signal MLPRE is at the H level for a half cycle period of clock signal CLK. Responsively, match line ML and reference voltage node NDa are precharged to intermediate voltage VML level. The precharge voltage VML is a voltage level between the intermediate voltage VDD / 2 and the ground voltage level. By the precharge operation by precharge circuit 210, voltages ML_MA and MLREF of internal nodes NDb and NDc are also precharged to an intermediate voltage level, respectively.

  When clock signal CLK falls to L level at time T2, precharge instruction signal MLPRE is accordingly set to L level. In response, precharge circuit 210 is deactivated, and the precharge operation of match line ML and reference voltage node NDa is completed. After completion of this precharge operation, search data is transmitted to search lines SL and / SL (generally indicating SL [0], / SL [0] -SL [72], / SL [72]), The voltage level changes according to the search data. When the search data does not match the data stored in the unit cell UC coupled to the match line ML (when in a miss state), the match line ML is discharged through at least one unit cell UC, and the voltage level is lowered. To do. As the voltage level of match line ML decreases, the level of voltage ML_MA on internal node NDb also decreases. Voltage MLREF of internal node NDc is at intermediate voltage VML level.

  Next, when the voltage level of match line ML is sufficiently lowered, isolation instruction signal MLI becomes L level at time T3, and isolation gate circuit 30 is rendered non-conductive.

  In response to the transition of isolation gate circuit 30 to the non-conductive state, boost instruction signal MLUP is then driven to the H level. Internal node NDb is in a floating state (match amplifier activation instruction signal MAE is in an inactive state). Therefore, the level of the voltage ML_MA on the node NDb increases due to the capacitive coupling by the capacitive element C1_A. The step-up level of voltage ML_MA on internal node NDb may be less than half of the absolute value | VML−GND | of the difference between intermediate voltage VML and ground voltage GND. Therefore, at the time of a miss, the voltage difference between the voltages ML_MA of the nodes NDb and NDc and the precharge voltage VML is reliably maintained by this boosting operation.

  Next, the match amplifier activation signal MAE is activated. In response, amplifier circuit 12 is activated to differentially amplify and latch these voltages ML_MA and MLREF. In the miss state, voltage MLREF on node NDc is driven to power supply voltage VDD level, while voltage ML_MA on internal node NDb is driven to the ground voltage level. When the amplification operation of the amplifier circuit 12 is activated, the latch instruction signal LAT then becomes H level. Accordingly, the latch 16 enters the through state, and the search result instruction signal ML_OUT from the latch 16 becomes L level, indicating a miss state.

  At time T4, the search operation is completed, and search lines SL and / SL are precharged to the ground voltage level. Further, the latch instruction signal LAT is driven to the L level, and the latch 16 is maintained in the latched state. When the latch 16 enters the latch state, the match amplifier activation signal MAE is deactivated and the amplifier circuit 12 is deactivated. Next, boost command signal MLUP is driven to L level, and then isolation command signal MLI is driven to H level to set isolation gate circuit 30 in a conductive state. When boosting instruction signal MLUP is driven to the L level, the voltage level of internal node NDb decreases due to capacitive coupling of capacitive element C1_A. However, when isolation gate circuit 30 is turned on, the voltage level is maintained at the ground voltage level due to charges from match line ML at the ground voltage level.

  Voltage MLREF at internal node NDc substantially maintains power supply voltage VDD level amplified by amplifier circuit 12.

  When the next search cycle starts at time T5, precharge instruction signal MLPRE goes to H level, and match line ML and reference voltage node NDa are precharged to precharge voltage VML level.

  At time T6, search data is transmitted to search lines SL and / SL, and the voltage levels of search lines SL and / SL change.

  If the search data matches the data held in all unit cells UC of the corresponding entry, there is no discharge path for match line ML, and match line ML is maintained at the precharge voltage VML level.

  When clock signal CLK rises to H level at time T7, isolation instruction signal MLI is driven to L level, and isolation gate circuit 30 is turned off. Subsequently, boost instruction signal MLUP is driven to the H level. Accordingly, the voltage level of voltage ML_MA on internal node NDb rises higher than precharge voltage VML due to capacitive coupling of capacitive element C1_A. Accordingly, a voltage difference is generated between these internal nodes NDb and NDc. In accordance with the activation of the match amplifier activation signal MAE, the amplifier circuit 12 can accurately differentially amplify and latch these voltages ML_MA and MLREF. Next, when the latch instruction signal LAT is driven to the H level, the latch 16 enters the through state, and the output signal ML_OUT is driven to the H level indicating the match state.

  When clock signal CLK falls to L level at time T8, the coincidence determination period is completed, latch instruction signal LAT becomes L level, and then match amplifier activation signal MAE is inactivated. As a result, the boost instruction signal MLUP is driven to the L level, and then the separation instruction signal MLI is driven to the H level. In response, isolation gate circuit 30 is rendered conductive, and internal node NDb is coupled to match line ML.

  When isolation gate circuit 30 is rendered conductive and match line ML and internal node NDb are coupled, the voltage on match line ML and signal voltage ML_MA on internal node NDb are at the same voltage level. In FIG. 52, this voltage change is not particularly shown. At the start of the next search cycle, internal node NDb and match line ML are driven to the precharge voltage VML level according to precharge instruction signal MLPRE (the parasitic capacitance of match line ML is greater than the parasitic capacitance of internal node NDb). Therefore, when the separation gate circuit 30 is turned on, the voltage ML_MA is lowered to a voltage level substantially close to the precharge voltage VML). In this case, isolation gate circuit 30 may have a decoupling function and be able to transmit maximum intermediate voltage VML (the difference between the H level of isolation instruction signal MLI and the threshold voltage of isolation gate TGa). Is set to the level of the intermediate voltage VML).

  FIG. 53 schematically shows a whole structure of the content reference memory according to the sixteenth embodiment of the present invention. The configuration of the content reference memory shown in FIG. 53 is substantially the same as the configuration of the content reference memory shown in FIG. 1, and only the reference numbers are different. That is, in the memory cell array 1, the unit cells UC are arranged in a matrix, and the memory cell array 1 is divided into a plurality of entries ERY. A match line ML is arranged corresponding to each entry ERY, and a match amplifier 200 is provided corresponding to each match line ML.

  The match determination circuit 2 is configured by the match amplifier 200 provided corresponding to each match line ML. The intermediate voltage generation circuit 222 transmits the intermediate voltage VML as a precharge voltage to these match amplifiers 200 in common.

  Control circuit 200 performs operation control so as to realize an operation specified by command CMD applied in synchronization with clock signal CLK.

  54 schematically shows an example of a configuration of control circuit 220 shown in FIG. The control circuit shown in FIG. 54 has substantially the same configuration as the control circuit shown in FIG. 54, the control circuit 220 has a command decoder 20, a precharge activation circuit 230, a search line live activation circuit 232, a delay circuit 234, and a match amplifier activation circuit 236, as in the configuration shown in FIG. including.

  The command decoder 20 decodes an external command CMD in synchronization with the clock signal CLK. Precharge activation circuit 230 generates precharge instruction signal MLPRE in accordance with search operation instruction EN from command decoder 20 and clock signal CLK. The search line drive activation circuit 232 maintains the search line activation signal SLEN for activating the search line in the active state during the L level of the clock signal CLK when the search operation instruction EN is activated. The delay circuit 234 delays the search operation instruction EN for one clock cycle period of the clock signal CLK.

  When the clock signal CLK rises to the H level when the output signal of the delay circuit 234 is activated, the match amplifier activation circuit 236 isolates the instruction signal MLI, the boost instruction signal MLUP, the match amplifier activation signal MAE, and the latch instruction signal. The LAT is activated sequentially in this order. Next, when the clock signal CLK falls, the match amplifier activation circuit 236 first deactivates the latch instruction signal LAT and then deactivates the match amplifier activation signal MAE, and then the boost instruction signal MLUP and the separation instruction signal Deactivate MLI sequentially.

  This match amplifier activation circuit 236 is constituted by, for example, a set / reset flip-flop train, and after driving these set / reset flip-flops sequentially into a set state, they are sequentially driven into an inactive state. With this configuration, the control signal for match amplifier 200 shown in FIG. 52 can be activated / deactivated in a predetermined sequence.

  As described above, according to the sixteenth embodiment of the present invention, the match line and the amplification circuit of the match amplifier are separated, and the amplification operation is performed in a state where charges are confined. The boosting capacitive element of the internal node (first node) connected to the amplifier circuit does not need to boost the entire match line, can be reduced in size, and can reduce the area occupied by the match amplifier. it can. In addition, the boost instruction signal generation unit (match amplifier activation circuit 236) that drives the capacitor element only needs to drive a small capacitor, and the load is small, so that current consumption can be reduced. Further, the amplification operation is performed in accordance with the charge confinement method, the load of the amplifier circuit is small, the load capacity of the node that performs full swing is small, and the current consumption during the amplification operation can be reduced. Further, the amplification operation can be performed at high speed.

  In the timing chart shown in FIG. 52, match line ML is precharged to the intermediate voltage level only at the start of the search. However, a configuration may be used in which the precharge operation is performed in the standby state before the search, and the precharge operation is completed at the start of the search operation.

[Embodiment 17]
FIG. 55 schematically shows a structure of a main portion of the content reference memory according to the seventeenth embodiment of the present invention. The content reference memory shown in FIG. 15 differs from the content reference memory shown in FIG. 51 in the following points. That is, in match amplifier 200, capacitive element C2_A is connected to internal node NDb coupled to match line ML. The other electrode of the capacitor C2_A is connected to the ground. The capacitive element C2_A functions as a capacitor that accumulates the charge transmitted from the match line ML. On the other hand, a capacitive element C2_B is provided for the internal node NDc that generates the reference voltage. Capacitance element C2_B receives reference voltage step-down instruction signal REFDOWN at the other electrode, and lowers reference voltage MLREF of internal node NDc by capacitive coupling (charger pump operation).

  Other configurations of the content reference memory shown in FIG. 55 are the same as those shown in FIG. 51, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 56 is a timing chart showing a search operation of the configuration shown in FIG. The operation of the circuit shown in FIG. 55 will be described below with reference to FIG.

  The operation from time T1 to time T3 is the same as the search operation of the sixteenth embodiment shown in FIG. That is, before the search data is transferred to search lines SL and / SL, match line ML and reference voltage node NDa are charged to a voltage level equal to or lower than intermediate voltage VDD / 2 (match line precharge at time T1). By the instruction signal MLPRE). At this time, the internal node NDc is also precharged to the precharge voltage VML level that is equal to or lower than the intermediate voltage VDD / 2 because the isolation gate circuit 30 is in a conductive state.

  Search data is transferred at time T2. At the time of a miss, the match line ML is discharged and its voltage level is lowered. Since isolation gate circuit 30 is conductive, the level of voltage ML_MA at internal node NDb decreases. On the other hand, the reference voltage MLREF on the internal node NDc is maintained at the precharge voltage VML level.

  At time T3, isolation instruction signal MLI is driven to an L level, and isolation gate circuit 30 is set to a non-conductive state. Next, the reference voltage step-down instruction signal REFDOWN is driven from the H level to the L level. Accordingly, voltage MLREF of internal node NDc decreases due to capacitive coupling of capacitive element C2_B. The capacitance value of the capacitive element C2_B is a capacitance value at which the voltage level of the internal node NDc is ½ or less of the difference | VML−GND | between the precharge voltage VML and the ground voltage GND.

  The voltage level of voltage MLREF at internal node NDc does not exceed the potential of voltage ML_MA at internal node NDb. Next, the match amplifier activation signal MAE is activated, and the amplifier circuit 12 is activated. Due to the differential amplification operation of amplifier circuit 12, voltage ML_MA on internal node NDb is driven to the ground voltage level, while reference MLREF on internal node NDc is driven to the power supply voltage VDD level and latched. Next, when the latch instruction signal LAT is activated and the latch 16 is set to the through state, the output signal ML_OUT is driven to an L level indicating a miss state.

  At time T4, this determination operation is completed, and the latch instruction signal LAT is driven to the L level. Accordingly, the latch 16 enters the latch state, and the output signal ML_OUT is maintained at the L level. Next, the match amplifier activation signal MAE is driven to the L level to inactivate the amplifier circuit 12.

  Thereafter, the reference voltage step-down instruction signal REFDOWN is driven to L level. At this time, the internal node NDc is in a floating state, and the voltage MLREF at the node NDc slightly increases. However, next, isolation instruction signal MLI is driven to H level, and isolation gate circuit 30 is rendered conductive. Therefore, the voltage increase due to the capacitive coupling is compensated by the charge redistribution, and the internal node NDc is maintained substantially at the power supply voltage VDD level. In this case, the voltage level of the reference voltage MLREF may be maintained at a voltage level higher than the power supply voltage VDD. The reference voltage MLREF is accurately precharged to the precharge voltage VML level by the precharge instruction signal MLPRE in the next search cycle, and the search operation is performed, so that no particular problem occurs.

  Reference voltage step-down instruction signal REFDOWN may be driven to the H level when match amplifier activation signal MAE is in the active state of the H level. In this state, since internal node NDc is not in a floating state, a voltage change due to capacitive coupling of capacitive element C2_B is immediately absorbed by amplifier circuit 12.

  The next search cycle starts from time T5. That is, precharge instruction signal MLPRE goes to H level, and match line ML, reference node NDa, and internal nodes NDb and NDc are precharged to precharge voltage VML level, respectively.

  At time T6, the search data is transferred to search lines SL and / SL. During this search operation, the match state is established and the match line ML is not discharged. That is, match line ML is maintained at precharge voltage VML level. Therefore, in match amplifier 200, voltages ML_MA and MLREF of internal nodes NDb and NDc are also maintained at the precharge voltage VML level.

  At time T7, separation instruction signal MLI is driven to L level, and separation gate circuit 30 is set to a non-conductive state. Next, the reference voltage step-down instruction signal REFDOWN is driven to L level. Due to capacitive coupling of the capacitive element C2_B, the voltage level of the voltage MLREF on the internal node NDc decreases. On the other hand, voltage ML_MA on internal node NDb is at precharge voltage VML level. Therefore, a voltage difference is generated between internal nodes NDb and NDc. By activating match amplifier activation signal MAE, amplifier circuit 12 differentially amplifies the voltages at nodes NDb and NDc. Accordingly, voltage ML_MA is driven to power supply voltage VDD level, and voltage MLREF is driven to the ground voltage level. Next, the latch instruction signal LAT is driven to the H level. In response, the latch 16 enters the through state. The output signal ML_OUT of the latch 16 becomes H level, indicating a match, and an accurate determination operation can be performed.

  When this search / determination operation is completed, search lines SL and / SL are driven to the ground voltage level at time T8. Further, the latch instruction signal LAT is driven to the L level. In response, latch 16 enters the latch state, and its output signal ML_OUT is maintained at the H level. Next, the match amplifier activation signal MAE is driven to the L level. Thereafter, reference voltage step-down instruction signal REFDOWN is driven to H level, and then separation instruction signal MLI is driven to H level. Accordingly, isolation gate circuit 30 is rendered conductive, and internal node NDc and reference voltage node NDa are connected. Even in this case, even if the voltage level of the node NDc rises due to the capacitive coupling of the capacitive element C2_B due to the rise of the reference voltage step-down instruction signal REFDOWN, charge redistribution is performed when the isolation gate circuit 30 becomes conductive. Internal node NDc is maintained at the ground voltage level.

  The search / determination operation is completed by a series of these operations. From time T9, the next search operation is prepared.

  Also in the seventeenth embodiment, only at the start of the search operation, match line precharge instruction signal MLPRE is driven to the H level for a predetermined period (half clock cycle period) to precharge match line ML and reference voltage node NDa. Is doing. However, this precharge operation may be performed in a standby state where the search operation is not performed (period after search lines SL and / SL are driven to the ground voltage level).

  Also in the seventeenth embodiment, as in the sixteenth embodiment, the sense operation (amplification operation) is performed with the isolation gate circuit 30 confining charges in the internal nodes NDb and NDc. The load capacity of internal nodes NDb and NDc is smaller than the load capacity of the entire match line ML to which unit cell UC is connected. Therefore, the capacitance value of capacitive element C2_B that lowers the voltage level of voltage MLREF at internal node NDc can be made sufficiently small. Thereby, the layout area of the match amplifier 200 can be reduced.

  In addition, the capacitive element C2_A of the internal node NDb is provided for capacity balance between the internal nodes NDb and NDc. Therefore, the capacitance value of the capacitor C2_A only needs to be equal to the capacitance value of the capacitor C2_B, and the layout area can be sufficiently reduced. Further, the load capacity of the nodes NDb and NDc is small, the drive capacity of the amplifier circuit 12 is small, and a sense operation can be performed at high speed with low power consumption.

  The overall configuration of the CAM according to the seventeenth embodiment is the same as the configuration of the CAM shown in FIG.

  FIG. 57 schematically shows a structure of a portion for generating a control signal in the seventeenth embodiment of the invention. The configuration of the control signal generation circuit 220 shown in FIG. 17 is different from that of the control signal generation circuit 220 shown in FIG. 54 in the following points. That is, match amplifier activation circuit 240 that activates the match amplifier according to the output signal of delay circuit 234 generates reference voltage step-down instruction signal REFDOWN instead of pull-up instruction signal MLUP. The match amplifier activation circuit 240 is activated in response to the output signal of the delay circuit 230 in synchronization with the clock signal CLK, and includes a separation instruction signal MLI, a reference voltage step-down instruction signal REFDOWN, a sense amplifier activation signal MAE, and The latch instruction signal LAT is sequentially activated / deactivated. Reference voltage step-down instruction signal REFDOWN has a waveform obtained by inverting the polarity of pull-up instruction signal MLUP in the control signal generation circuit shown in FIG. Therefore, match amplifier activation circuit 240 of the seventeenth embodiment can be realized by a configuration similar to that of match amplifier activation circuit 236 shown in FIG. 54 (the inverted signal of pull-up instruction signal MLUP is used as a reference voltage step-down instruction). Signal REFDOWN).

  57 is the same as the configuration of the control signal generation circuit shown in FIG. 54, and corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted.

  As described above, according to the seventeenth embodiment of the present invention, the match line voltage and the comparison reference voltage are confined in the internal node in the match amplifier that detects the voltage level of the match line. This reference voltage level is lowered by capacitive coupling by a voltage level equal to or lower than 1/2 of the precharge voltage VML, and a sensing operation is performed. Therefore, at the time of search determination, a voltage difference is generated between the match line and the reference voltage node, and the determination operation can be performed accurately. Further, the driving load of the amplifier circuit in the match amplifier is sufficiently small, and the layout area of the match amplifier can be reduced. In addition, the sensing operation can be performed at low speed with low power consumption.

[Embodiment 18]
FIG. 58 schematically shows a structure of a main portion of the CAM according to the eighteenth embodiment of the present invention. In the configuration of the CAM shown in FIG. 58, the configuration of the match amplifier 200 is different from the configuration of the match amplifier 200 shown in FIG. That is, the capacitor C3_B is connected to the reference voltage node NDa. Capacitance element C3_B lowers the precharge voltage level of reference voltage node NDa by capacitive coupling in accordance with level down instruction signal RFDWN. Capacitance elements are not provided in internal nodes NDb and NDc. The configuration of the match amplifier 200 shown in FIG. 58 is the same as that of the match amplifier 200 shown in FIG. 55, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted. The arrangement of unit cells UC including the CAM cell is also the same as the arrangement of unit cells UC for the CAM match line ML shown in FIG.

  In the CAM configuration shown in FIG. 58, the precharge level VML (VML <VDD / 2) of the reference voltage node NDa is lowered by a certain voltage level during the search operation. Thereafter, the isolation gate circuit 30 confines the potential of the match line ML and the charge of the reference voltage reduced in level to the internal nodes NDb and NDc. Thus, the sensing operation is performed at high speed with low power consumption.

  FIG. 59 is a timing chart representing an operation of the match amplifier shown in FIG. In the search cycle from time T1 to time T4, an operation waveform when the search result is a miss is shown. In the search cycle from time T5 to time T8, an operation waveform when the search result is a match is shown. Hereinafter, the operation of the match amplifier 200 shown in FIG. 58 will be described with reference to FIG.

  The search cycle starts at time T1. Accordingly, precharge instruction signal MLPRE is driven to the H level. Thereby, match line ML and reference voltage node NDa are precharged to precharge voltage VML level by precharge circuit 210. At this time, isolation gate circuit 30 is conductive (separation instruction signal MLI is at H level), and internal nodes NDb and NDc are also precharged to precharge voltage VML level.

  At time T2, the match line precharge instruction signal MLPRE becomes L level, and the search operation starts. On the other hand, search lines SL and / SL are driven according to the search data. When a miss occurs, the match line ML is discharged. At this time, the level down instruction signal REFDWN is driven to the L level in accordance with the start of the search operation. Accordingly, the voltage level of the reference voltage node NDa decreases from the precharge voltage VML due to capacitive coupling of the capacitive element C3_B. The amount of voltage level drop at reference voltage node NDa is ½ or less of the difference between precharge voltage VML and ground voltage GND. Therefore, even if the voltage MLREF falls, the voltage MLREF is at a voltage level higher than the voltage ML_MA of the match line ML.

  Voltage changes at match line ML and reference voltage node NDa are transmitted to internal nodes NDb and NDc through isolation gate circuit 30, respectively.

  At time T3, separation instruction signal MLI is driven to L level, and separation gate circuit 30 is turned off. After the separation gate circuit 30 shifts to the non-conductive state, the level down instruction signal REFDWN is driven to the H level. The voltage level of the reference voltage node NDa increases due to capacitive coupling of the capacitive element C3_B. However, isolation gate circuit 30 is non-conductive, and voltage MLREF at internal node NDc is maintained at the voltage level dropped at time T2.

  Next, the match amplifier activation signal MAE is activated. Amplifier circuit 12 is activated, and differentially amplifies voltages MLREF and ML_MA of internal nodes NDb and NDc. Accordingly, since it is in a miss state, voltage MLREF is driven to power supply voltage VDD level, while voltage ML_MA is driven to the ground voltage level. Next, the latch instruction signal LAT is driven to the H level, and the latch 16 enters the through state. Accordingly, the output signal ML_OUT of the latch 16 is driven to L level, indicating a miss state.

  When the search operation is completed at time T4, latch instruction signal LAT is driven to L level, and then match amplifier activation signal MAE is driven to L level. Accordingly, the latch 16 enters the latch state, and the amplifier circuit 12 enters the inactive state. Next, after deactivating match amplifier activation signal MAE, isolation instruction signal MLI is driven to H level, and isolation gate circuit 30 is driven to a conductive state.

  Match line ML is discharged to the ground voltage level, and voltage ML_MA of internal node NDb is maintained at the ground voltage level even when isolation gate circuit 30 is turned on. Internal node NDc is connected to reference voltage node NDa. Charges are redistributed between internal node NDb and reference voltage node NDa. In this case, the voltage level depends on the ratio between the parasitic capacitance of the reference voltage node NDa (capacitance value and wiring capacitance of the capacitive element C3_B) and the parasitic capacitance of the internal node NDc (gate capacitance and coupling capacitance of the transistor of the amplifier circuit 12). Changes. 59 shows a state where voltage MLREF is maintained at power supply voltage VDD level. When the voltage level of the reference voltage node NDa increases due to capacitive coupling when the isolation gate circuit 30 is in a non-conducting state, the voltage increase amount becomes larger than the voltage drop amount (the reference voltage node is higher at the time of boosting than at the time of voltage dropping). The parasitic capacitance coupled to the voltage node NDa is small). Therefore, even if isolation gate circuit 30 conducts and charge redistribution is performed between nodes NDc and NDa, it is assumed that the amount of change in voltage is small and that nodes NDa and NDc are maintained at the power supply voltage level. it can.

  There is no particular problem even if the voltage MLREF changes to a voltage level between the precharge voltage VML and the power supply voltage VDD after the separation gate circuit 30 is turned on (at the start of the next search cycle, the reference voltage node NDa is Precharge voltage is precharged to VML level).

  From time T5, the next search cycle starts, and precharge instruction signal MLPRE is driven to the active state. Accordingly, match transistor ML and reference voltage node NDa are precharged to precharge voltage VML level by MOS transistors 211 and 212 of precharge circuit 210.

  At time T6, search data is transmitted to search lines SL and / SL, and the voltage level changes. In the match state, there is no discharge path on the match line ML. Therefore, match line ML is maintained at precharge voltage VML level. On the other hand, level down instruction signal REFDWN is driven to the L level in accordance with the start of the search operation. Accordingly, the voltage level of reference voltage node NDa decreases due to capacitive coupling of capacitive element C3_B. The amount of decrease in the voltage level of reference voltage node NDa is a voltage level between precharge voltage VML and ground voltage GND. Isolation gate circuit 30 is conductive, and the voltage levels of match line ML and reference voltage node NDa are transmitted to internal nodes NDb and NDc, respectively.

  At time T7, separation instruction signal MLI is driven to L level in synchronization with the rise of clock signal CLK. Accordingly, isolation gate circuit 30 is turned off. Thereby, charges are confined in internal nodes NDb and NDc. After the separation gate circuit 30 shifts to the non-conductive state, the level down instruction signal REFDWN is driven to the H level. In this case, the voltage level of the reference voltage node NDa changes due to capacitive coupling of the capacitive element C3_B. However, isolation gate circuit 30 is non-conductive, and the voltage level of voltage MLREF at internal node NDc does not change.

  Next, sense amplifier activation signal MAE is activated, and voltages ML_MA and MLREF of internal nodes NDb and NDc are differentially amplified. As a result, voltage ML_MA is driven to power supply voltage VDD level and voltage MLREF is driven to ground voltage level.

  Next, the latch instruction signal LAT is driven to the H level, and the latch 16 is set to the through state. Accordingly, the output signal ML_OUT of the latch 16 is driven to the H level indicating the match state.

  At time T8, the determination operation is completed, the latch instruction signal LAT is driven to the L level, and the latch 16 enters the latch state. The output signal ML_OUT of the latch 16 is maintained at the H level. Thereafter, sense amplifier activation signal MAE is deactivated, and then isolation instruction signal MLI is deactivated (driven to H level). In response, isolation gate circuit 30 is rendered conductive, and internal nodes NDb and NDc are coupled to match line ML and reference voltage node NDa, respectively. In this case, the match line ML is at the precharge voltage VML level, and the voltage level of the voltage ML_MA decreases according to the capacitance ratio between the internal node NDb and the match line ML. In FIG. 59, this voltage change is not clearly shown.

  Similarly, voltage level of voltage MLREF is set according to the capacitance ratio of internal node NDc and reference voltage node NDa. However, this voltage change is not clearly shown for this voltage MLREF.

  Even when the isolation gate circuit 30 is turned on and the voltage levels of the nodes NDa, NDb, and NDc change, there is no particular problem with respect to the next search operation. This is because match line ML, reference voltage node NDa and internal nodes NDb and NDc are precharged to precharge voltage VML level by precharge instruction signal MLPRE at the start of the next search cycle.

  In the configuration according to the eighteenth embodiment of the present invention, no internal capacitance element is provided at internal nodes NDb and NDc. Therefore, no capacitive element for balancing the capacitance is required for internal nodes NDb and NDc. As a result, the layout area of the match amplifier 200 can be further reduced. Further, no capacitive element is provided in internal nodes NDb and NDc (excluding parasitic capacitance). Therefore, during the amplification operation of the amplifier circuit 12, the capacity of the node that fully swings can be reduced, and the current consumption can be reduced.

  Further, the voltage drop at reference voltage node NDa by step-down instruction signal REFDWN is performed in parallel with the period during which search data is transmitted to search lines SL and / SL. Therefore, the sense operation by the amplifier circuit 12 can be performed immediately after the separation gate circuit 30 shifts to the non-conductive state. Thereby, the sense operation start timing by the match amplifier 200 can be advanced.

  FIG. 60 schematically shows a structure of a portion for generating the CAM control signal shown in FIG. 60, control signal generation circuit 220 differs from the control signal generation circuit shown in FIG. 57 in the following points. That is, match amplifier activation circuit 250 sequentially activates / deactivates isolation instruction signal MLI, sense amplifier activation signal MAE, and latch instruction signal LAT in accordance with the output signal of delay circuit 234 and clock signal CLK.

  Step-down activation circuit 252 drives reference voltage step-down instruction signal REFDWN to L level and H level in accordance with isolation instruction signal MLI and search operation activation signal SLEN. That is, step-down activation circuit 252 drives step-down operation instruction signal REFDWN to L level when search operation activation signal SLEN is activated and the search operation starts. The step-down activation circuit 252 drives the step-down operation instruction signal REFDWN to H level when the isolation instruction signal MLI becomes L level. This step-down activation circuit 252 can be realized using, for example, a set / reset flip-flop.

  In accordance with the delay enable signal from the delay circuit 234, the match amplifier activation circuit 250 synchronizes with the clock signal CLK after a lapse of one clock cycle after applying the search operation command CMD, and in a predetermined sequence, the separation instruction signal MLI and the sense amplifier Activation signal MAE and latch instruction signal LAT are activated / deactivated.

  The other configuration of the control signal generation circuit 220 shown in FIG. 60 is the same as that of the control signal generation circuit shown in FIG. 57, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  As described above, according to the eighteenth embodiment of the present invention, the voltage level of the reference voltage node for generating the match reference voltage of the match line is lowered by capacitive coupling, and then charge confinement is performed to match the voltage level of the match line. Have a sense of Therefore, it is not necessary to provide a capacitive element at the sense node of the amplifier circuit that performs this sensing operation, and the layout area is reduced. In addition, the load capacity of the amplifier circuit that performs the sensing operation is reduced, and high-speed sensing and low power consumption can be realized.

[Embodiment 19]
FIG. 61 shows a structure of a main part of the CAM according to the nineteenth embodiment of the present invention. 61 also representatively shows a unit cell UC and a corresponding match amplifier 200 related to one match line ML. Corresponding to each match line ML, a match amplifier having the same configuration as match amplifier 200 shown in FIG. 61 is provided.

  The match amplifier 200 shown in FIG. 61 differs from the match amplifier 200 shown in FIG. 58 in the following points. That is, a step-down circuit 260 is provided for lowering the voltage level of precharge voltage VML of reference voltage node NDa in accordance with level down instruction signal RFDWN with respect to reference voltage node NDa. This step-down circuit 260 includes a capacitive element C4 and N-channel MOS transistors 261 and 262 that control charging / discharging of the capacitive element C4.

  N channel MOS transistor 262 discharges one electrode node NDd of capacitive element C4 to the ground voltage level in accordance with precharge instruction signal MLPRE. MOS transistor 261 couples one electrode node NDd of capacitive element C4 to reference voltage node NDa in accordance with level down instruction signal RFDWN. Therefore, reference voltage node NDa is precharged to precharge voltage VML by MOS transistor 212 of precharge circuit 210. The amount of stored charge at reference voltage node NDa is determined by the parasitic capacitance of reference voltage node NDa and the voltage level of precharge voltage VML. Node NDd is precharged to the ground voltage level. By coupling the capacitive element C4 to the reference voltage node NDa, the charge transfer between the reference voltage node NDa and the capacitive element C4 causes the precharge voltage VML of the reference voltage node NDa to be changed to the reference voltage node NDa and the internal node NDc. Is reduced according to the capacitance value of the parasitic capacitance and the capacitance value of the capacitive element C4.

  The other configuration of match amplifier 200 shown in FIG. 61 is the same as that of match amplifier 200 shown in FIG. 58. Corresponding portions are allotted with the same reference numerals, and detailed description thereof is omitted. Further, the configuration and arrangement of the unit cells coupled to match line ML are also the same as the configuration shown in FIG. 58, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 62 is a timing chart representing an operation of match amplifier 200 shown in FIG. Hereinafter, the operation of the match amplifier 200 shown in FIG. 61 will be described with reference to FIG.

  First, in the search cycle from time T1 to time T4, a miss determination is performed. In the search cycle from time T5 to time T9, a match state is identified.

  When the search cycle starts at time T1, precharge instruction signal MLPRE goes high. In response, precharge circuit 210 precharges match line ML and reference voltage node NDa to the voltage level of precharge voltage VML (VDD / 2 or less). At this time, isolation gate circuit 30 is also conductive, and internal nodes NDb and NDc are also precharged to precharge voltage VML level.

  In step-down circuit 260, MOS transistor 262 is turned on in accordance with precharge instruction signal MLPRE, node NDd is coupled to the ground node, and the charge of capacitive element C4 is discharged.

  When the search operation starts at time T2, search lines SL and / SL are driven according to the search data. In the miss state, match line ML is discharged and its voltage level is lowered. At this time, level down instruction signal RFDWN is driven to H level. In response, MOS transistor 261 conducts in voltage down converter 260, and one electrode node NDd of capacitive element C4 is coupled to reference voltage node NDa. Accordingly, capacitive element C4 is charged by the accumulated charge at reference voltage node NDa. The voltage level at nodes NDa and NDc decreases due to the movement of charges. This voltage drop amount is a voltage level between precharge voltage VML and ground voltage GND (about VML / 2), and the voltage level of nodes NDa and NDc is the voltage level between ground voltage and precharge voltage VML. Become.

  On the other hand, internal node NDb is coupled to match line ML via isolation gate circuit 30, and the level of voltage ML_MA decreases as the voltage of match line ML decreases.

  When clock signal CLK rises at time T3, isolation instruction signal MLI is driven to the L level, and isolation gate circuit 30 is turned off. Next, level down instruction signal RFDWN is driven to the L level, and MOS transistor 261 is turned off. In this state, charges corresponding to voltages ML_MA and MLREF are confined in internal nodes NDb and NDc, respectively.

  Next, match amplifier activation signal MAE is activated to differentially amplify voltages ML_MA and MLREF of internal nodes NDb and NDc. During this differential amplification, the voltage drop at nodes NDa and NDc due to the capacitance value of capacitive element C4 is at a voltage level between precharge voltage VML and ground voltage GND. Therefore, a voltage difference that can be sensed by the amplifier circuit 12 is generated between the nodes NDc and NDb, and the sensing operation can be performed accurately. After completion of the sensing operation, the latch instruction signal LAT becomes H level and the output signal ML_OUT of the latch 16 becomes L level, indicating a miss state.

  When this search / determination operation is completed, driving of search lines SL and / SL is completed at time T4, and search lines SL and / SL are driven to the ground voltage level. On the other hand, latch instruction signal LAT goes to L level, and then match amplifier activation signal MAE is inactivated. The latch 16 enters the latch state, and the output signal ML_OUT is maintained at the L level. On the other hand, amplifier circuit 12 maintains an inactive state, and nodes NDb and NDc are maintained at the ground voltage and power supply voltage levels to be in a floating state.

  . Thereafter, when isolation instruction signal MLI is driven to H level, isolation gate circuit 30 is rendered conductive. In response, internal nodes NDb and NDc are connected to match line ML and reference voltage node NDa, respectively. Match line ML is at the ground voltage level, and voltage ML_MA is maintained at the ground voltage level. On the other hand, level down instructing signal RFDWN is at L level, reference voltage node NDa is in a floating state, and voltage MLREF on internal node NDc is maintained substantially at power supply voltage VDD level (node NDc due to charge movement). And the voltage level of NDa may be driven to a voltage level lower than the power supply voltage VDD level).

  One electrode node NDd of capacitive element C4 is maintained at the charged voltage level in the cycle starting from time T2.

  The search cycle starts again from time T5, and precharge instruction signal MLPRE is activated (driven to H level). In response, match line ML and internal node NDb are precharged to the precharge voltage VML level. Reference voltage node NDa and internal node NDc are also precharged to precharge voltage VML level. Capacitance element C4 has one electrode node NDd discharged to ground voltage level through MOS transistor 262.

  The search operation from time T6 is started. In this case, the voltage levels of search lines SL and / SL change according to the search data. In the match state, the match line ML is not discharged, and the match line ML is maintained at the precharge voltage VML level. On the other hand, in parallel with this search operation, level down instruction signal RFDWN becomes H level, and one electrode node NDd of capacitive element C3 is coupled to reference voltage node NDa via MOS transistor 261. Accordingly, the voltage level of reference voltage node NDa and internal node NDc decreases due to the movement of charges. The amount of decrease in voltage MLREF is an intermediate voltage level between precharge voltage VML and ground voltage GND.

  Therefore, at time T7, in synchronization with the rise of clock signal CLK, separation instruction signal MLI is at L level, and subsequently level down instruction signal RFDWN is driven to L level. Accordingly, one electrode node NDd of capacitive element C4 is separated from reference voltage node NDa. Isolation gate circuit 30 is rendered non-conductive, and charges are confined in internal nodes NDb and NDc. In this case, the precharge voltage of internal node NDb is at the VML level, and voltage MLREF of internal node NDc is an intermediate voltage level between precharge voltage VML and ground voltage GND. Therefore, a sufficient voltage difference is generated between these nodes NDb and NDc.

  Subsequently, when the match amplifier activation signal MAE is activated, the voltages ML_MA and MLREF are differentially amplified by the amplifier circuit 12. As a result, voltage ML_MA on internal node NDb is driven to the power supply voltage VDD level, and voltage MLREF on internal node NDc is driven to the ground voltage level and latched.

  Subsequently, the latch instruction signal LAT is driven to the H level. In response, the latch 16 enters the through state, and its output signal ML_OUT becomes H level.

  At time T8, the search / determination operation is completed, and latch instruction signal LAT and match amplifier activation signal MAE are sequentially driven to the L level. Amplifying circuit 12 is deactivated, and internal nodes NDb and NDc enter a floating state at power supply voltage VDD and ground voltage GND levels, respectively.

  Thereafter, isolation instruction signal MLI is raised to H level, and isolation gate circuit 30 is set to a conductive state. Accordingly, internal node NDb is coupled to match line ML, and internal node NDc is coupled to reference voltage node NDa. The capacity of match line ML is larger than the parasitic capacity of node NDb. Therefore, when the separation gate circuit 30 does not have a decoupling function, charge distribution is performed between the match line ML at the precharge voltage VML level and the internal node NDb at the power supply voltage level according to the capacitance value thereof. Is done. In this case, the voltage level of internal node NDb falls from the power supply voltage level, but this voltage change is not clearly shown in FIG. When charge redistribution occurs, match line ML is higher than precharge voltage VML, while voltage ML_MA on internal node NDb is at a voltage level lower than power supply voltage VDD. When charge transfer occurs, the voltage level of match line ML is finally equal to the voltage level of voltage ML_MA on internal node NDb.

  However, if the difference between the voltage level of isolation instruction signal MLI and the threshold voltage of isolation gates TGa and TGb of isolation gate circuit 30 is slightly higher than precharge voltage VML, these isolation gates TGa and TGb Operates as a decoupled transistor. In this case, match line ML is maintained at precharge voltage VML level, while voltage ML_MA on internal node NDb is maintained at power supply voltage VDD level.

  In capacitance element C4, after the completion of the search / determination operation, level down instruction signal RFDWN is at the L level, and electrode node NDd is maintained in the charged state.

  In the nineteenth embodiment, the voltage level of reference voltage node NDa is lowered by charge redistribution by capacitive element C4 in the step-down circuit. Therefore, the voltage drop level of reference voltage node NDa does not depend on the voltage level of power supply voltage VDD, and reference voltage node NDa can be set to a voltage level set by the capacitance value of stable capacitive element C4 (instruction) The amplitude of the signal RFDWN or REFDOWN is the power supply voltage VDD level). Therefore, the sensing operation can be performed more stably.

  That is, when the voltage level of the comparison reference voltage MLREF changes depending on the power supply voltage VDD during the search operation, the voltage difference between the internal nodes NDb and NDc when the voltage level of the match line ML is confined changes. . For this reason, the voltage difference between the sense nodes of the amplifier circuit 12 varies, there is a possibility that the sense margin is lowered, and an accurate sense operation cannot be guaranteed. Charge is redistributed using the capacitive element C4, and the voltage level of the comparison reference voltage MLREF is set. This voltage change amount is determined by the capacitance value of the capacitive element C4 and the capacitance values of the parasitic capacitances of the nodes NDa and NDc, and does not depend on the amplitude of the voltage drop instruction signal, that is, the power supply voltage. As a result, the voltage level of the node NDc can be accurately set at the start of the amplification operation of the amplifier circuit 12, and a high-speed and stable sense operation can be realized.

  The configuration of the control signal generating circuit 220 shown in FIG. 60 can be used as the configuration of the circuit for generating the control signal in the nineteenth embodiment. The control signal RFDWN is generated by inverting the signal polarity of the level down instruction signal REFDWN from the step-down activation circuit 252 shown in FIG.

  Also in the nineteenth embodiment, precharge instruction signal MLPRE may be activated in a standby state in which a search operation is not performed.

  As described above, according to the nineteenth embodiment of the present invention, the level of the comparison reference voltage is set by charge redistribution using the capacitive element. Therefore, the voltage level of the comparison reference voltage during the sensing operation can be set accurately, and a stable sensing operation can be ensured. Further, the sensing operation is performed by the charge confinement method, and the same effect as in the previous eighteenth embodiment can be obtained.

[Embodiment 20]
FIG. 63 schematically shows a structure of a main portion of the CAM according to the twentieth embodiment of the present invention. In FIG. 63, n match lines ML [i] -ML [i + n] are provided in the CAM cell array. Each of these match lines is connected to a unit cell UC. In FIG. 63, only the unit cell UC for the match line ML [i] is representatively shown.

  Match amplifiers 200i-200 (i + n) are provided for match lines ML [i] -ML [i + n], respectively. Each of these match amplifiers 200i-200 (i + n) includes a precharge circuit 270 that precharges a corresponding match line, an amplifier circuit 12, and a latch 16 that latches the output of the amplifier circuit 12. Amplifying circuit 12 amplifies the potentials on internal nodes NDb and NDc in response to match amplifier activation signal MAE, as in the previous embodiments. The latch 16 enters the through state and the latch state in accordance with the latch instruction signal LAT, and latches the output signal of the corresponding amplifier circuit 12.

  Precharge circuit 270 includes only precharge transistor 211 that precharges corresponding match line ML (ML [i] −ML [i + n]) to precharge voltage VML. In each of the match amplifiers 200i-200 ((i + n)), the precharge transistor (212) is not individually provided.

  In these match amplifiers 200i-200 (i + n), an isolation gate circuit 30 is provided in the previous stage of the amplifier circuit 12. In FIG. 63, in match amplifiers 200 (i + 1) -200 (i + n), amplifier circuit 12 is shown as a circuit having complementary and positive control nodes and an output node that outputs a complementary signal. These amplifying circuits 12 have the same configuration in the match amplifier. Complementary match amplifier activation signal ZMAE is applied to the complementary control node of amplification circuit 12 of match amplifiers 200 (i + 1) -200 (i + n) via an inverter.

  A main step-down circuit 300 is provided in common to these match amplifiers 200i-200 (i + n). Main voltage down converter 300 includes a capacitive element C5 and MOS transistors 301-303. MOS transistor 301 precharges output node MND0 to precharge voltage VML level in accordance with precharge instruction signal MLPRE. MOS transistor 302 couples output node MND0 to one electrode node MND1 of capacitive element C5 in accordance with step-down instruction signal RFDWN. MOS transistor 303 discharges one electrode node MND1 of capacitive element C5 to the ground voltage level in accordance with precharge instruction signal MLPRE. Output node MND0 of main voltage down converter 300 is commonly connected to reference voltage node NDa of match amplifiers 200i-200 (i + n). The capacitance value of the capacitive element C5 is not more than ½ times the combined parasitic capacitance of the reference voltage node NDa. The precharge voltage VML and the ground voltage GND are applied to these match amplifiers 200i-200 (i + n). Causes a voltage drop at a voltage level between (VML / 2).

  The timing chart of the operation at the time of CAM search and determination shown in FIG. 63 is the same as the timing chart shown in FIG. Further, as the configuration of the control circuit that generates various control signals, the same configuration as the control signal generation circuit shown in FIG. 60 can be used. Therefore, the search and determination operation of CAM according to the twentieth embodiment of the present invention shown in FIG. 63 is the same as the search and determination operation of the nineteenth embodiment, and thus the description thereof is omitted.

  In the case of the configuration of the CAM shown in FIG. 63, a circuit for dropping the comparison reference voltage MLREF at the time of detecting the voltage level of the match line to a voltage level intermediate between the precharge voltage VML and the ground voltage GND 200i-200 (i + n). As a result, the layout area can be reduced as compared with a configuration in which a step-down circuit is provided for each match amplifier. In addition, the same effect as in the eighteenth embodiment can be obtained.

[Embodiment 21]
FIG. 64 schematically shows a structure of the CAM according to the twenty-first embodiment of the present invention. The CAM shown in FIG. 64 differs from the CAM shown in FIG. 63 in the following points. That is, in each of match amplifiers 200i-200 (i + n), an N channel MOS transistor 310 that is turned on in response to an equalize instruction signal MLEQ is provided between internal nodes NDb and NDc. The other configuration of the CAM shown in FIG. 64 is the same as the configuration of the CAM shown in FIG. 63, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  It is necessary to restore the match line ML, the internal voltage ML_MA, and the comparison reference voltage MLREF to the precharge voltage VML by using the match amplifier 200i-200 (i + n) by using the equalizing MOS transistor 310. Reduce time.

  FIG. 65 is a timing chart showing the search operation of the CAM shown in FIG. Hereinafter, the operation of the DAM shown in FIG. 64 will be described with reference to FIG.

  In the timing chart shown in FIG. 65, the precharge operation is performed in the standby state. That is, precharge instruction signal MLPRE is maintained in an active state except for a period in which a test operation is performed and search lines SL and / SL are driven according to the search data.

  Also in the timing chart shown in FIG. 65, the search / determination cycle from time T1 to T4 is an operation in the case of a miss state, and a match state is detected in the search / determination cycle from time T5 to time T8.

  Prior to time T1, precharge instruction signal MLPRE is at H level, and match line ML and internal nodes NDb and NDc are precharged to precharge voltage VML level. At this time, also in main voltage down converter 300, one electrode node MND1 of capacitive element C5 is discharged to the ground voltage level by precharge instruction signal MLPRE.

  Further, equalize instruction signal MLEQ is at H level, and equalizing MOS transistor 310 is in a conductive state. Therefore, voltages ML_MA and MLREF are equalized to precharge voltage VML level.

  At time T1, the search cycle starts. First, match line precharge instruction signal MLPRE is deactivated (driven to L level), and equalize instruction signal MLEQ is also deactivated (driven to L level). Thereby, the precharge operation and the equalize operation in the match line ML (ML [i] −ML [i + n]) are finished. Match line ML is in a floating state at precharge voltage VML level.

  Then, search lines SL and / SL are driven according to the search data. If the search result is a miss, match line ML is discharged to the ground voltage level. In parallel with this search operation, step-down instruction signal RFDWN becomes H level, and one electrode node MND1 of capacitive element C5 is coupled to reference voltage node NDa of match amplifiers 200i-200 (i + n) via output node MND0. Accordingly, in each of match amplifiers 200i-200 (i + n), the voltage level of reference voltage node NDa decreases. Since isolation gate circuit 30 is still conductive, the voltage level of voltage MLREF at internal node NDc of match amplifiers 200i-200 (i + n) also drops from precharge voltage VML.

  When the voltage difference between voltage ML_MA on match line ML and comparison reference voltage MLREF is sufficiently increased, separation instruction signal MLI is driven to L level at time T3. Accordingly, isolation gate circuit 30 is rendered non-conductive in each of match amplifiers 200i-200 (i + n), and charges are confined in internal nodes NDb and NDc.

  When isolation instruction signal MLI is set to L level, step-down instruction instruction signal RFDWN is also driven to L level, and MOS transistor 302 is turned off in main voltage-down converter 300. Accordingly, one electrode node MND1 of capacitive element C5 has a voltage level set by charge redistribution.

  At this time T3, the voltage level of the match line ML is sufficiently driven to a voltage level corresponding to the search result. Therefore, the search operation is terminated at this timing, and search lines SL and / SL are deactivated (driven to the ground voltage level).

  In this state, precharge instruction signal MLPRE is activated again to precharge match line ML to precharge voltage VML level. In main step-down circuit 300, one electrode node MND1 of capacitive element C5 is discharged to the ground voltage level via MOS transistor 303. Each reference voltage node NDa is charged to the precharge voltage VML level by the MOS transistor 301 of the main step-down circuit 300.

  After driving isolation instruction signal MLI to L level, match amplifier activation signal MAE is activated, and then latch instruction signal LAT is driven to H level. Accordingly, sense operation is performed by amplifier circuit 12 in each of match amplifiers 200i-200 (i + n), and output signal ML_OUT of latch 16 attains an L level in the match amplifier in a miss state. Thereafter, at time T4, latch instruction signal LAT is driven to L level in accordance with the fall of clock signal CLK, and subsequently sense activation signal MAE is driven to L level, thereby completing the sensing operation.

  Thereafter, isolation instruction signal MLI becomes H level, and isolation gate circuit 30 is rendered conductive in each of match amplifiers 200i-200 (i + n). Accordingly, in each of match amplifiers 200i-200 (i + n), internal node NDb is coupled to corresponding match line ML [i] -ML [i + n], and reference voltage node NDa is coupled to internal node NDc. At this time, the equalize instruction signal MLEQ becomes H level, and the equalizing MOS transistor 310 is turned on. Therefore, in each of match amplifiers 200i-200 (i + n), voltages ML_MA and MLREF of nodes NDb and NDc driven to power supply voltage VDD level and ground voltage GND level are driven to precharge voltage VML level at high speed.

  When the search operation starts again from time T5, the match line precharge instruction signal MLPRE becomes L level, the equalize instruction signal MLEQ becomes L level, and the match line ML enters a floating state at the precharge voltage VML level. Further, step-down instruction signal RFDWN becomes H level, and one electrode node MND1 of capacitive element C5 in main step-down circuit 300 is coupled to each reference voltage node NDa of match amplifiers 200i-200 (i + n). Accordingly, in each of match amplifiers 200i-200 (i + n), voltage MLREF at node NDc is driven to a voltage level lower than precharge voltage VML.

  A search operation is performed, and the voltage levels of search lines SL and / SL are driven to a voltage level corresponding to the search data. In the match state, match line ML is at the precharge voltage VML level. The voltage MLREF is a voltage level between the precharge voltage VML and the ground voltage GND by the step-down operation, and a sufficient potential difference between the sense nodes of the amplifier circuit 12 is guaranteed.

  At time T7, the search operation is completed, and then a determination operation is performed. That is, isolation instruction signal MLI is driven to L level, and isolation gate 30 is set to a non-conductive state in each of match amplifiers 200i-200 (i + n). Accordingly, match lines ML [i] -ML [i + n] are separated from nodes NDb of corresponding match amplifiers 200i-200 (i + n), respectively. In this state, the search operation is completed, and search lines SL and / SL are driven to the ground voltage level.

  When separation instruction signal MLI is driven to L level, step-down instruction signal RFDWN is again driven to L level, and one electrode node MND1 of capacitive element C5 is separated from output node MND0 of main step-down circuit 300.

  In this state, match amplifier activation signal MAE is activated, and amplifier circuit 12 performs a differential amplification operation. Next, the latch instruction signal LAT is driven to the H level, the latch 16 enters the through state, and the output signal ML_OUT is driven to the H level indicating the match state.

  In parallel with this sensing operation, match line precharge instruction signal MLPRE again goes to the H level, match line ML is driven to the precharge voltage VML level, and one electrode node MND1 of capacitive element C5 in main voltage down converter 300. Is discharged to the ground voltage level via the MOS transistor 303. In match amplifiers 200i-200 (i + n), all isolation gate circuits 30 are in a non-conductive state, and this precharge operation has no adverse effect on the amplification operation of amplifier circuit 12.

  Next, when the voltage level of the output signal ML_OUT of the latch 16 is determined, the search operation ends at time T8. That is, latch instruction signal LAT is driven to L level, and then match amplifier activation signal MAE is inactivated. Thereafter, isolation instruction signal MLI becomes H level, and isolation gate circuit 30 is rendered conductive in each of match amplifiers 200i-200 (i + n). Accordingly, match lines ML [i] -ML [i + n] are coupled to internal nodes NDb of corresponding match amplifiers 200i-200 (i + n), respectively. In each of match amplifiers 200i-200 (i + n), internal node NDc is coupled to reference voltage node NDa.

  The reference voltage node NDa is precharged to the precharge voltage VML level by the MOS transistor 301 of the main step-down circuit 300 by the precharge instruction signal MLPLE. Therefore, in these match amplifiers 200i-200 (i + n), the voltage levels of internal nodes NDb and NDc change due to the movement of charges. At this time, the match line equalize instruction signal MLEQ becomes H level, the equalizing MOS transistor 310 is turned on, and the voltage levels of the nodes NDb and NDc are driven to the precharge voltage VML level at high speed.

At time T9, the determination cycle is completed and a standby state is entered.
As described above, in the standby state, the match nodes 200i-200 (i + n) equalize the internal nodes using the equalizing MOS transistors 310. In parallel with the sensing operation, the precharge operation of the match line and the reference voltage node NDa is performed in a state where the isolation gate circuit is in a non-conductive state. As a result, the internal nodes of match amplifiers 200i-200 (i + n) and the match lines can be precharged at high speed. As a result, the time required for precharging the internal nodes of the match amplifiers 200i-200 (i + n) can be reduced, the search / determination cycle period can be shortened, and high-speed determination / search can be realized. .

  FIG. 66 schematically shows a structure of a portion for generating the CAM control signal shown in FIG. 66, control signal generation circuit 400 includes a command decoder 402 that decodes command CMD and generates search operation instruction EN according to the decoding result, and delay circuit 408 that delays search operation instruction EN. The command decoder 402 takes in the command CMD when the clock signal CLK rises, and decodes the fetched command. The delay circuit 408 delays the search operation instruction EN from the command decoder 402 for one cycle period of the clock signal CLK.

  Control signal generation circuit 400 further includes a precharge activation circuit 406 that generates match line precharge instruction signal MLPRE, a search line drive activation circuit 404 that generates search operation activation signal SLEN, and signals MLI and MAE. And a match amplifier activation circuit 410 for generating LET.

  The search line drive activation circuit 404 activates the search operation activation signal SLEN for one cycle period of the clock signal CLK when the search operation instruction EN from the command decoder 402 is activated. The search data input circuit 4 is enabled according to the activation of the search operation activation signal SLEN, and drives the search line according to the search data SD.

  The precharge activation circuit 406 deactivates the precharge instruction signal MLPRE in accordance with the activation of the search operation instruction signal EN from the command decoder 402, and the search operation activation signal SLEN from the search line drive activation circuit 404 is inactivated. In response to the activation, precharge instruction signal MLPRE is activated.

  Match amplifier activation circuit 410 sequentially activates / deactivates isolation instruction signal MLI, sense amplifier activation signal MAE, and latch instruction signal LAT in a predetermined sequence in accordance with the output signal of delay circuit 408.

  Control signal generation circuit 400 further includes a step-down activation circuit 412 for generating step-down instruction signal RFDWN and an equalization activation circuit 414 for generating equalization instruction signal MLEQ. Step-down activation circuit 412 inactivates step-down instruction signal RFDWN (drives to L level) in response to the fall of isolation instruction signal MLI from match amplifier activation circuit 410, and responds to activation of search operation instruction EN. The step-down instruction signal RFDWN is driven to the H level.

  Equalize activation circuit 414 drives equalize instruction signal MLEQ to H level in response to the rise of isolation instruction signal MLI, and drives equalize instruction signal MLEQ to L level in accordance with activation of search operation instruction EN.

  As described above, according to the twenty-first embodiment of the present invention, the sense node for confining charges is equalized during standby. Therefore, after the search operation is completed, the match line and the sense nodes (internal nodes NDb and NDc) can be driven to the predetermined precharge voltage VML level at high speed when the search operation is started. Thereby, the sense operation start timing of the match amplifier can be advanced, and the determination period can be shortened. In addition, the same effects as in the twentieth embodiment are also achieved.

  The configuration in which the equalize transistor is provided for the sense nodes (internal nodes NDb and NDc) of amplifier circuit 12 may be applied to the configurations shown in FIGS. 16 to 19 shown in FIG.

  The present invention can be applied to a content reference memory that searches for stored information in accordance with search data and determines whether the stored information matches or does not match. In particular, it is possible to realize a router with a small occupation area and reduced power consumption by using a configuration for decoding a IP address and setting a transfer path in a communication router having a wide bit width of search data. . Alternatively, the content reference memory according to the present invention may be used in a circuit configuration for determining a cache miss / hit in a cache controller or the like.

It is a figure which shows roughly the whole structure of the content reference memory according to Embodiment 1 of this invention. It is a figure which shows an example of a structure of the unit cell shown in FIG. It is a figure which shows the other structure of the unit cell shown in FIG. It is a figure which shows roughly the structure of the principal part of the content reference memory according to Embodiment 1 of this invention. FIG. 5 is a timing chart showing an operation of the content reference memory shown in FIG. 4. FIG. 5 is a diagram illustrating an example of a specific configuration of the match amplifier illustrated in FIG. 4. FIG. 2 is a diagram schematically showing a configuration of a control circuit shown in FIG. 1. It is a figure which shows roughly the structure of the principal part of the content reference memory according to Embodiment 2 of this invention. FIG. 9 is a timing chart showing an operation of the content reference memory shown in FIG. 8. It is a figure which shows roughly the structure of the example of a change of the content reference memory according to Embodiment 2 of this invention. It is a figure which shows roughly the whole structure of the content reference memory according to Embodiment 3 of this invention. It is a figure which shows roughly the structure of the principal part of the content reference memory according to Embodiment 3 of this invention. FIG. 13 is a timing chart showing an operation of the content reference memory shown in FIG. 12. It is a figure which shows schematically the structure of the principal part of the content reference memory of the modification of Embodiment 3 of this invention. It is a figure which shows schematically the structure of the principal part of the content reference memory according to the modification 2 of Embodiment 3 of this invention. It is a figure which shows roughly the structure of the principal part of the content reference memory according to Embodiment 4 of this invention. FIG. 17 is a timing diagram illustrating an operation of the content reference memory illustrated in FIG. 16. It is a figure which shows roughly the structure of the control circuit used in Embodiment 4 of this invention. It is a figure which shows roughly the structure of the principal part of the content reference memory according to Embodiment 5 of this invention. FIG. 20 is a timing chart showing an operation of the content reference memory shown in FIG. 19. It is a figure which shows roughly the structure of the principal part of the content reference memory according to Embodiment 6 of this invention. FIG. 22 is a timing chart showing an operation of the content reference memory shown in FIG. 21. It is a figure which shows roughly the structure of the example of a change of the bias voltage generation part of the content reference memory according to Embodiment 6 of this invention. It is a figure which shows roughly the structure of the control circuit of the content reference memory according to Embodiment 6 of this invention. It is a figure which shows roughly the structure of the principal part of the content reference memory according to Embodiment 7 of this invention. FIG. 26 is a timing diagram illustrating an operation of the content reference memory illustrated in FIG. 25. It is a figure which shows roughly the structure of the principal part of the content reference memory according to Embodiment 8 of this invention. FIG. 28 is a timing diagram illustrating an operation of the content reference memory illustrated in FIG. 27. It is a figure which shows roughly the structure of the control signal generation part of the content reference memory according to Embodiment 8 of this invention. It is a figure which shows roughly the structure of the principal part of the content reference memory according to Embodiment 9 of this invention. It is a figure which shows roughly the structure of the principal part of the content reference memory according to Embodiment 10 of this invention. FIG. 32 is a diagram illustrating an example of a configuration of a buffer illustrated in FIG. 31. It is a figure which shows the structure of the principal part of the content reference memory according to Embodiment 11 of this invention. It is a figure which shows an example of a structure of the current converter circuit shown in FIG. FIG. 34 is a diagram showing another configuration of the current conversion circuit shown in FIG. 33. FIG. 34 is a diagram illustrating an example of a configuration of a buffer illustrated in FIG. 33. It is a figure which shows the structure of the principal part of the content reference memory of the example of a change of Embodiment 11 of this invention. It is a figure which shows roughly the structure of the principal part of the content reference memory according to Embodiment 12 of this invention. FIG. 35 is a diagram showing a list of operation logics of the charge circuit shown in FIG. 34. FIG. 39 is a timing chart showing an operation of the content reference memory shown in FIG. 38. FIG. 39 is a diagram showing a list of charges consumed per search cycle of the content reference memory shown in FIG. 38. It is a figure which shows the structure of the principal part of the example of a change of Embodiment 12 of this invention. FIG. 43 is a timing chart showing an operation of the match amplifier shown in FIG. 42. It is a figure which shows roughly the structure of the principal part of the content reference memory according to Embodiment 13 of this invention. It is a figure which shows roughly the structure of the principal part of the content reference memory according to Embodiment 14 of this invention. FIG. 46 is a timing chart showing an operation of the content reference memory shown in FIG. 45. It is a figure which shows roughly the whole structure of the content reference memory according to Embodiment 15 of this invention. FIG. 48 is a timing chart showing an operation of the delay control circuit of the content reference memory shown in FIG. 47. FIG. 48 is a timing chart showing an operation of the content reference memory shown in FIG. 47. It is a figure which shows an example of a structure of the priority encoder shown in FIG. It is a figure which shows the structure of the principal part of CAM according to Embodiment 16 of this invention. FIG. 52 is a timing diagram showing an operation of the match amplifier shown in FIG. 51. It is a figure which shows roughly the whole structure of CAM according to Embodiment 16 of this invention. FIG. 52 is a diagram schematically showing a configuration of a portion for generating a control signal shown in FIG. 51. It is a figure which shows the structure of the principal part of CAM according to Embodiment 17 of this invention. FIG. 56 is a timing chart showing an operation of the match amplifier shown in FIG. 55. It is a figure which shows schematically the structure of the part which generate | occur | produces the control signal shown in FIG. It is a figure which shows the structure of the principal part of CAM according to Embodiment 18 of this invention. FIG. 59 is a timing chart showing an operation of the match amplifier shown in FIG. 58. FIG. 59 is a diagram schematically showing a configuration of a portion for generating a control signal shown in FIG. 58. It is a figure which shows roughly the structure of the principal part of CAM according to Embodiment 19 of this invention. FIG. 62 is a timing chart showing an operation of the match amplifier shown in FIG. 61. It is a figure which shows the structure of the principal part of CAM according to Embodiment 20 of this invention. It is a figure which shows roughly the structure of the principal part of CAM according to Embodiment 21 of this invention. FIG. 65 is a timing chart showing an operation of the match amplifier shown in FIG. 64. FIG. 62 is a diagram schematically showing a configuration of a part for generating a control signal shown in FIG. 61.

Explanation of symbols

  1 memory cell array, 2 search result detection / output circuit, 4 search data input circuit, 6 intermediate voltage generation circuit, 8 control circuit, 10 match amplifier, UC unit cell, TR1-TR4 MOS transistor, 12 differential amplifier circuit, 16 latch , 14 P-channel MOS transistor, 30 isolation gate circuit, 12a differential amplifier, 12b activation transistor, 42 intermediate voltage generation circuit, 45 bias voltage generation circuit, 50 replica entry, UCs, UCh replica unit cell, CQ0, CQ1 capacitance element 55 P-channel MOS transistor, 60 discharge transistor, 70 capacitive element, N61-N63 N-channel MOS transistor, PQ10, PQ72, PQ11, PQ70 P-channel MOS transistor, 80 replica unit 82, 1 bit replica unit cell, 40 match amplifier, QP71, QP72 P channel MOS transistor, ND1 NOR gate, QP71-QP74 P channel MOS transistor, QN71-QN76 N channel MOS transistor, CQ2 capacitive element, 110 charge-up circuit, 100 pull-up / detection circuit, 50 replica entry, 130 buffer, 150 match amplifier, 152 sense circuit, 154 D-type latch circuit, 156 charge circuit, 160 EXNOR circuit, 200 replica entry, 210 bias voltage generation circuit, GSB1, GSB2 global Search block, SB11-SB18, SB21-SB28 Local search block, MA11-MA18, MA21-MA28 Match amplifier Group, PE11-PE18, PE21-PE28 priority encoder, DL1-DL8, DL10-DL18, DL20-DL28 digital delay circuit, 220 delay control circuit, 222 digital phase difference detection circuit, FF11-FF18, FF21-FF28 search data input circuit , FF1, FF2 Search data input circuit (FF circuit), 200, 200i-200 (i + n) Match amplifier, 210 Precharge circuit, 211, 212 Precharge MOS transistor, C1_A, C1_B, C2_A, C2_B, C3_B, C4 C5 capacitance element, 260 step-down circuit, 261, 262 MOS transistor, 300 main step-down circuit, 301, 302, 303 MOS transistor, 270 precharge circuit, 310 MO for equalization Transistor.

Claims (31)

  1. A plurality of entries, each having a plurality of content reference memory cells;
    A plurality of match lines arranged corresponding to each of the entries, to which the content reference memory cells of the corresponding entry are coupled,
    A search data bus coupled in parallel to each entry and transferring search data in parallel to each entry, and coupled to each of the match lines, each of which corresponds to an intermediate value between a power supply voltage and a ground voltage A precharge circuit that precharges to the following precharge voltage level, an amplifier circuit that compares the voltage of the corresponding match line with a reference voltage of a voltage level equal to or lower than the precharge voltage, and generates a signal indicating the comparison result; A content reference memory comprising a plurality of match amplifiers including a separation gate for separating a corresponding match line and the amplifier circuit before the amplifier circuit is activated.
  2. The content reference memory further includes a reference voltage generation circuit that generates the reference voltage and transmits the reference voltage to each match amplifier,
    The content reference memory according to claim 1, wherein the separation gate separates the reference voltage generation circuit and the amplification circuit before the activation of the amplification circuit.
  3.   3. The content reference memory according to claim 1, wherein the reference voltage generation circuit generates the reference voltage and the precharge voltage at the same voltage level.
  4. In the content reference memory, a precharge cycle in which the precharge circuit is activated, a comparison cycle in which data stored in each entry is compared with search data on the search data bus, and the amplifier circuit are activated. A match determination cycle,
    4. The content reference memory according to claim 1, wherein each match amplifier further includes a pull-up current supply circuit that supplies a current to a corresponding match line during the comparison cycle. 5.
  5.   The pull-up current supply circuit is configured such that when the 1-bit content reference memory cell of each entry becomes conductive, the content reference memory cell of each entry is smaller than the 1-bit miss current flowing through the corresponding match line. The content reference memory according to claim 4, wherein a current larger than an off-leakage current flowing through a corresponding match line in a conductive state is supplied.
  6. The reference voltage is at the same voltage level as the precharge voltage,
    Each of the match amplifiers further includes a capacitor element that is charged with the reference voltage when the precharge circuit is in operation, and that holds the charge voltage when the amplifier circuit is not in operation and transmits the charge voltage to the amplifier circuit through a corresponding isolation gate. The content reference memory according to claim 1, comprising:
  7.   7. The content reference memory according to claim 4, wherein each of the match amplifiers further includes a discharge circuit that discharges a corresponding match line to a voltage level lower than the precharge voltage when the match determination cycle is completed. .
  8. A plurality of entries, each having a plurality of content reference memory cells;
    A plurality of match lines arranged corresponding to each of the entries, to which the content reference memory cells of the corresponding entry are coupled,
    A search data bus coupled in parallel to each entry and transferring search data in common to each entry; and
    An amplifier circuit coupled to each match line, each of which compares the voltage of the corresponding match line with a reference voltage and generates a signal indicating the comparison result, and the corresponding match line is grounded after the amplification operation of the amplifier circuit is completed A plurality of match amplifiers including a precharge circuit that precharges to a voltage level, and a pull-up current supply circuit that supplies a current having a current value limited to a match line corresponding to the inactivation of the precharge circuit; Content reference memory.
  9. The content reference memory further has the same configuration as the match line discharge path of the entry, and has a replica entry having a plurality of replica cells that replicate a state in which a 1-bit content reference memory cell is turned on, A current generation circuit including a replica match line coupled to each replica cell of the replica entry, and a current source for supplying a current to the replica match line;
    The content reference memory according to claim 8, wherein the pull-up current supply circuit includes a transistor element that causes a mirror current of a current supplied from the current source to flow through a corresponding match line.
  10. The content reference memory further has the same configuration as the match line discharge path of the entry, and the replica reference entry of the entry in which the content reference memory cells of all bits are made non-conductive, and the content reference memory cell A 1 bit replica cell that is turned on, a replica match line coupled to each content reference memory cell of the replica entry, and a first current mirror type that supplies current to the replica match line A current source, a second current mirror type current source that supplies current to the replica cell, and a mirror current supplied by the first and second current mirror type current sources; A current generation circuit including a current / voltage conversion unit that generates a bias voltage by converting the voltage into a voltage;
    The content reference memory according to claim 8, wherein the pull-up current supply circuit includes a transistor element that converts a bias voltage from the current / voltage conversion unit into a current having a magnitude smaller than or equal to the mirror current.
  11. A plurality of entries, each having a plurality of content reference memory cells;
    A plurality of match lines arranged corresponding to each of the entries, to which the content reference memory cells of the corresponding entry are coupled,
    A search data bus coupled in parallel to each of the entries and transferring search data in parallel to each of the entries, and coupled to each of the match lines, each of which is precharged to precharge the corresponding match line to a ground voltage level. Supplying a current having a limited current value to a matching circuit corresponding to a deactivation state of the precharge circuit and an upper limit value of a voltage level of the corresponding matching line, and a voltage of the matching line And a plurality of match amplifiers including a pull-up current supply / determination circuit that generates a signal of a voltage level corresponding to the voltage level, and the limited current amount is such that a one-bit content reference memory cell of one entry is rendered conductive. Sometimes the current value flowing through the corresponding match line is smaller than the current value flowing through the corresponding match line, and the corresponding reference line flows when all the reference memory cells in the corresponding entry are made non-conductive. A content reference memory that is larger than the current.
  12. The content reference memory further includes a first current source transistor element that generates a current corresponding to a current flowing through a corresponding match line when the 1-bit content reference memory cell of the entry is rendered conductive. A source, a second current source transistor element that forms a current mirror circuit with the first current source transistor element, a first load transistor element supplied with current from the second current source transistor element, and an intermediate A reference voltage equal to or lower than a voltage level is compared with a voltage at a connection node of the second current source transistor element and the first load transistor element, and a signal corresponding to the comparison result is output to the gate of the first load transistor element. Having the same current drive capability as the discharge circuit of the content reference memory cell, and the first load transistor element. Further comprising a current generating circuit which includes a discharge element for discharging a current,
    The pull-up current supply / determination circuit is coupled in series with the first transistor element that forms a current mirror circuit with the first current source transistor element, and the output signal of the comparison circuit. The content reference memory of claim 11, further comprising: a second transistor element that causes a current to flow through a corresponding match line according to.
  13.   The pull-up current supply / determination circuit further includes a third transistor element coupled between the first and second transistor elements, and a voltage and a pull-up of a connection node between the second and third transistor elements. 13. The content according to claim 12, further comprising: a gate circuit that drives a gate of the third transistor element in accordance with an instruction signal, wherein a signal indicating a detection result is generated at a connection node of the second and third transistor elements. memory.
  14.   The content of Claim 12 or 13 further provided with the buffer circuit which adjusts the level of the output signal of the said comparison circuit so that the current drive capability of the said 2nd transistor element may become large, and applies it to the gate of the said 2nd transistor element. Reference memory.
  15. The first current source transistor element has a current / voltage conversion function;
    The content reference memory further includes a current conversion circuit that converts a level of a voltage generated by the first current source transistor element so that an amount of current flowing through the first transistor element is reduced. Item 14. The content reference memory according to item 12 or 13.
  16. The constant current source is:
    A replica entry having a plurality of replica cells replicating a state in which the 1-bit content reference memory cell of the entry is rendered conductive;
    The content reference memory according to claim 11, further comprising a replica match line coupled in common to the replica cells and supplied with current from the first current source transistor element.
  17. The constant current source is:
    A replica cell that replicates the discharge path of the 1-bit content reference memory cell in the conductive state;
    A third transistor element having the same conductivity type as the second transistor element connected between the first current source transistor element and the replica cell;
    A comparison in which the voltage at the connection node between the replica cell and the third transistor element is compared with an intermediate voltage defining the upper limit value of the match line, and the gate voltage of the third transistor element is adjusted according to the comparison result 13. The content reference memory of claim 12, comprising a circuit.
  18.   18. The content reference memory according to claim 17, wherein the replica cell is configured by a resistance element having a resistance value equal to a combined on-resistance of a discharge path of the 1-bit content reference memory cell.
  19. A plurality of entries, each having a plurality of content reference memory cells;
    A plurality of match lines arranged corresponding to each of the entries, to which the content reference memory cells of the corresponding entry are coupled,
    A search data bus coupled in parallel to each of the entries and transferring search data in parallel to each of the entries, and coupled to each of the match lines, each having a voltage level corresponding to the voltage level of the corresponding match line A detection circuit that generates a signal, a latch circuit that latches a signal according to the voltage level of the match line of the previous coincidence detection cycle, and a current is selectively supplied to the match line corresponding to the search operation according to the latch signal of the latch circuit A content reference memory comprising a plurality of match amplifiers including a charge circuit for supply.
  20.   20. The content reference memory according to claim 19, wherein the detection circuit changes a determination reference value of a voltage level of a corresponding match line in accordance with a latch signal of the latch circuit.
  21.   The charge circuit leaks through the corresponding match line when all bit content reference memory cells are non-conductive when less than a 1-bit miss current flowing through the corresponding match line when one bit content reference memory cell is conductive in one entry. 20. The content reference memory of claim 19, wherein the content reference memory supplies a current greater than the current.
  22.   The content reference memory according to any one of claims 19 to 21, wherein the charge circuit includes an upper limit clamp setting transistor element that prevents a voltage of a corresponding match line from rising to a predetermined level or higher.
  23. Each is coupled to a plurality of content reference memory cells each storing reference data and the plurality of content reference memory cells, and is driven in a predetermined voltage level direction by a corresponding content reference memory cell according to a match search result with the search data A plurality of search blocks including a plurality of entries, and a search data bus coupled in common to the plurality of entries and transferring the search data in parallel.
    A plurality of search data input circuits provided corresponding to the search blocks, each supplying search data to the search data bus of the corresponding search block, and the plurality of search blocks and search data input circuits sequentially activated according to a clock signal A content reference memory comprising an activation control circuit for converting to a memory.
  24. The plurality of search blocks are divided into a plurality of prioritized global blocks,
    The content reference memory according to claim 23, wherein the activation control circuit maintains a global block with a low priority in an inactive state when a match is detected in a global block with a high priority.
  25. A plurality of entries, each having a plurality of content reference memory cells;
    A plurality of match lines provided corresponding to each of the entries, to which the content reference memory cells of the corresponding entry are coupled,
    A search data bus coupled in parallel to each of the entries and transferring search data in parallel to each entry, and arranged corresponding to each of the plurality of match lines, each having a reference voltage node and a corresponding match line A precharge circuit for precharging to a voltage level equal to or lower than an intermediate voltage between a power supply voltage and a ground voltage; a first node receiving a voltage of a corresponding match line; and a second node coupled to the reference voltage node An amplifier circuit that compares the voltages of the first and second nodes and generates a signal indicating the comparison result, a corresponding match line and the reference voltage node before activation of the amplifier circuit, An isolation gate that separates the first and second nodes of the amplifier circuit, and a capacity for boosting the first node according to the boost instruction signal after the separation gate is separated and before the amplifier circuit is activated. A content reference memory comprising a plurality of match amplifiers including a quantity element.
  26. A plurality of entries, each having a plurality of content reference memory cells;
    A plurality of match lines provided corresponding to each of the entries, to which content reference memory cells of the corresponding entry are coupled,
    A search data bus coupled in parallel to each of the entries and transferring search data in parallel to each of the entries, and arranged corresponding to each of the plurality of match lines, each corresponding to a power supply voltage and ground A precharge circuit that precharges to a precharge voltage level equal to or lower than an intermediate voltage between the voltage, a first node that receives the voltage of the corresponding match line, and a voltage at the precharge voltage level is changed using a capacitive element. And a second node that receives the sense reference voltage generated in this manner, compares the voltages of the first and second nodes, and generates a signal indicating the comparison result, and the activity of the amplifier circuit A content reference memory comprising a plurality of match amplifiers including isolation gates that confine charges in the first and second nodes prior to fabrication.
  27. The precharge circuit further precharges the second node to a precharge voltage level equal to or lower than the intermediate voltage via the isolation gate,
    Each match amplifier
    A capacitive element provided between the second node and the isolation gate and performing a charger pump operation in accordance with a step-down instruction signal to reduce the voltage level of the second node to generate the sense reference voltage; 27. The content reference memory according to claim 26, wherein the step-down instruction signal is activated after the separation operation of the separation gate and before activation of the amplifier circuit.
  28. The precharge circuit further precharges a reference voltage line coupled to the second node through the isolation gate to a voltage level equal to or lower than the intermediate voltage,
    Each match amplifier
    The capacitor further includes a capacitive element that is provided on the reference voltage line and reduces a voltage level of the reference voltage node by a charger pump operation according to a step-down instruction signal, and the step-down instruction signal is supplied to the precharge operation before the separation operation of the separation gate. 27. The content reference memory of claim 26, wherein the content reference memory is activated after completion of.
  29. The precharge circuit further precharges a reference voltage line coupled to the second node through the isolation gate to a voltage level equal to or lower than the intermediate voltage,
    Each of the match amplifiers includes a capacitive element, a first transistor that precharges the capacitive element to a ground voltage level during the precharge operation, and a second transistor that couples the capacitive element to the reference voltage line according to a step-down instruction signal. 27. The content reference memory according to claim 26, further comprising: a transistor, wherein the step-down instruction signal is activated before the isolation gate is confined.
  30. A main step-down circuit that is provided in common to the plurality of match amplifiers and supplies the sense reference voltage to a second node of each of the match amplifiers;
    The main step-down circuit is
    A capacitive element;
    A first transistor that precharges the capacitive element to a ground voltage level during the precharge operation and an output node coupled to the plurality of match pumps are precharged to a voltage level equal to or lower than the intermediate voltage level during the precharge operation. And a third transistor that couples the output node to the capacitor after completion of the precharge operation, the output node passing through the isolation gate of each match amplifier. 27. The content reference memory of claim 26, coupled to two nodes.
  31.   31. The content reference memory according to claim 30, wherein each match amplifier further includes an equalize transistor that electrically short-circuits the first and second nodes after the amplification operation of the amplifier circuit is completed.
JP2006308145A 2006-04-25 2006-11-14 Content addressable memory Withdrawn JP2007317342A (en)

Priority Applications (2)

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JP2006308145A JP2007317342A (en) 2006-04-25 2006-11-14 Content addressable memory

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
JP2006308145A JP2007317342A (en) 2006-04-25 2006-11-14 Content addressable memory
US11/730,969 US20070247885A1 (en) 2006-04-25 2007-04-05 Content addressable memory
US12/720,561 US8164934B2 (en) 2006-04-25 2010-03-09 Content addressable memory
US13/419,217 US8310852B2 (en) 2006-04-25 2012-03-13 Content addressable memory
US13/621,078 US8638583B2 (en) 2006-04-25 2012-09-15 Content addressable memory
US14/151,606 US9042148B2 (en) 2006-04-25 2014-01-09 Content addressable memory
US14/691,125 US9620214B2 (en) 2006-04-25 2015-04-20 Content addressable memory with reduced power consumption and increased search operation speed

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009110616A (en) * 2007-10-31 2009-05-21 Kanazawa Univ Content addressable memory device
JP2010277642A (en) * 2009-05-28 2010-12-09 Renesas Electronics Corp Semiconductor device
US8400803B2 (en) 2010-03-02 2013-03-19 Renesas Electronics Corporation Content addressable memory device
US8891272B2 (en) 2012-03-14 2014-11-18 Renesas Electronics Corporation Content addressable memory system

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009110616A (en) * 2007-10-31 2009-05-21 Kanazawa Univ Content addressable memory device
JP2010277642A (en) * 2009-05-28 2010-12-09 Renesas Electronics Corp Semiconductor device
US8400803B2 (en) 2010-03-02 2013-03-19 Renesas Electronics Corporation Content addressable memory device
US8780599B2 (en) 2010-03-02 2014-07-15 Renesas Electronics Corporation Content addressable memory device
US9159376B2 (en) 2010-03-02 2015-10-13 Renesas Electronics Corporation Content addressable memory device
US8891272B2 (en) 2012-03-14 2014-11-18 Renesas Electronics Corporation Content addressable memory system

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