JP2010277642A5 - - Google Patents
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- JP2010277642A5 JP2010277642A5 JP2009128979A JP2009128979A JP2010277642A5 JP 2010277642 A5 JP2010277642 A5 JP 2010277642A5 JP 2009128979 A JP2009128979 A JP 2009128979A JP 2009128979 A JP2009128979 A JP 2009128979A JP 2010277642 A5 JP2010277642 A5 JP 2010277642A5
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- entry
- voltage
- generates
- match
- memory array
- Prior art date
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Claims (1)
各エントリに対応して配置され、各々が対応のエントリの連想メモリセルに結合されるともに所定のプリチャージ電圧にプリチャージされ、各々が対応のエントリの参照データと与えられた検索データとの一致／不一致に応じた電圧を伝達する複数のマッチ線、
各エントリに対応して配置され、各々が対応のエントリのマッチ線の電圧を参照電圧と比較し、該比較結果に応じた信号を出力する複数のマッチアンプ、
前記メモリアレイと同一半導体基板に形成されるモニタ用トランジスタを含み、前記モニタ用トランジスタを流れる電流に応じた信号を生成する電流モニタ回路、および
前記電流モニタ回路の出力信号に従って発生電圧のレベルを調整して、前記プリチャージ電圧および前記参照電圧のうちの少なくとも１つの電圧を発生する電源回路を備える、半導体装置。 A memory array including a plurality of associative memory cells each arranged in a row direction and having a plurality of entries for storing reference data;
Arranged corresponding to each entry, each coupled to the associative memory cell of the corresponding entry and precharged to a predetermined precharge voltage, each matching the reference data of the corresponding entry and the provided search data / Multiple match lines that transmit voltage according to mismatch
A plurality of match amplifiers arranged corresponding to each entry, each of which compares a match line voltage of a corresponding entry with a reference voltage and outputs a signal corresponding to the comparison result;
A current monitor circuit that includes a monitor transistor formed on the same semiconductor substrate as the memory array, and that generates a signal corresponding to the current flowing through the monitor transistor; A semiconductor device comprising a power supply circuit that generates at least one of the precharge voltage and the reference voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009128979A JP5578344B2 (en) | 2009-05-28 | 2009-05-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009128979A JP5578344B2 (en) | 2009-05-28 | 2009-05-28 | Semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2010277642A JP2010277642A (en) | 2010-12-09 |
| JP2010277642A5 true JP2010277642A5 (en) | 2012-03-22 |
| JP5578344B2 JP5578344B2 (en) | 2014-08-27 |
Family
ID=43424474
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009128979A Expired - Fee Related JP5578344B2 (en) | 2009-05-28 | 2009-05-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5578344B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017097940A (en) * | 2015-11-26 | 2017-06-01 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004165649A (en) * | 2002-10-21 | 2004-06-10 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device |
| JP2007317342A (en) * | 2006-04-25 | 2007-12-06 | Renesas Technology Corp | Content addressable memory |
| JP2008099032A (en) * | 2006-10-12 | 2008-04-24 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device |
-
2009
- 2009-05-28 JP JP2009128979A patent/JP5578344B2/en not_active Expired - Fee Related
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