JP5568320B2 - Inspection apparatus and inspection method - Google Patents

Description

  The present invention relates to an inspection apparatus and an inspection method for inspecting a substrate.

  In the semiconductor inspection apparatus, an inspection object (wafer) is provided using FOUP. This FOUP can be inspected after verifying and approving the identifier information and wafer presence slot (shelf) information. The apparatus sequentially performs inspections specified by inspection information instructions (inspection target slot (shelf) information and recipe (inspection conditions)) after inspection becomes possible. Even if the recipe information is not finalized, it is possible to know the approximate value of the required FOUP processing time simply by inputting the processing number information. Before the FOUP and recipe information actually reach the hand, Arrangements for manufacturing equipment and the like can be scheduled. As a result, it becomes possible to make an arrangement plan that can reduce the waiting time for FOUP processing (device waiting time), the processing FOUP waiting time of the device, and the like, and it is possible to arrange lots with high efficiency.

JP 2001-345241 A

  Although what was disclosed by Unexamined-Japanese-Patent No. 2001-345241 is known as a thing regarding prediction of lot processing time, what was disclosed by the previous term gazette is processing inside the apparatus in the state where all the information was gathered. Time prediction is possible. For this reason, the time required for processing the next lot (before FOUP arrival) to be processed after the operation lot is completed cannot be calculated in advance, so that it is not sufficient. In addition, since the apparatus disclosed in the previous publication is an apparatus for processing the wafer surface, the time for moving to the first processing unit is always constant. Therefore, when considering backside processing, the time to reverse the wafer (in the case of backside processing) before moving from the FOUP to the first processing unit and reverse the wafer (in the case of backside processing) before returning to the FOUP after processing. In the case of inspection, it is necessary to include it in the lot time.

  In order to achieve the above object, the first feature of the present invention is that, when there is no recipe designation, the required time can be arbitrarily combined in the range from the standard processing (shortest) for the front surface to the high density processing (longest) for the back surface. It is to be able to calculate and notify a plurality of patterns of predicted times.

  A second feature of the present invention includes a substrate storage container having an inversion function and a processing unit, and the processing unit takes into account the storage of the substrate storage container from the load in consideration of the inversion of the substrate storage container. It is to calculate the time required to unload the container.

  A third feature of the present invention is that the processing unit uses a fixed coefficient.

  A fourth feature of the present invention is that two equations are used according to the inversion of the substrate.

  According to a fifth aspect of the present invention, there is provided a storage unit, wherein the processing unit calculates an inspection time, and the inspection time is classified into a plurality of time coefficients and stored in the storage unit. There is.

  A sixth feature of the present invention is that it has a display unit, and the display unit displays the time calculated by the processing unit.

  A seventh feature of the present invention resides in that a reversing mechanism is provided separately from the substrate storage container.

  According to the present invention, it is possible to calculate the time required for device processing for the next lot in addition to the prediction of the time required for device processing for the current lot for an inspection device during lot processing without recipe information. This makes it easy to arrange high-efficiency lots for FOUPs, thereby reducing the waiting time for FOUP processing.

FIG. The horizontal sectional view seen from the top plate side of an inspection device. Processing flow from FOUP loading to unloading. Wafer continuous processing flow for processing the wafer surface. Wafer continuous processing flow with wafer back side as processing target. (Wafer transfer arm with reversing function) Wafer continuous processing flow with wafer back side as processing target. (Independent reversing unit: long inspection time) Wafer continuous processing flow with wafer back side as processing target. (Independent reversing unit: short inspection time) FOUP occupation time calculation information notification GUI. FOUP occupation time calculation information notification GUI (notification example). Lot required time calculation flow. Inspection device wafer processing flow. Device management processing time DB virtual value table. Example of calculation instruction from HOST and calculation result notification from device. Inspection pattern.

  FIG. 1 shows the configuration of the inspection apparatus. The inspection apparatus places a sample (including a substrate such as a wafer), a transport system 1111 that moves in the scanning direction, an irradiation optical system 1112 that irradiates the substrate with light 1110, and light 102 (scattered light, A detection optical system 1113 for detecting reflected light, an inspection processing system 1114 for inspecting a sample from the detection result, and an input / output system 1115 for displaying and inputting various information.

  More specifically, the transport system 1111 includes a placement unit 1116 on which the substrate is placed, and a scanning unit 1117 on which the placement unit is mounted and moved. The irradiation optical system 1112 includes a light source 1 that generates light, and an optical element 1118 that is disposed between the substrate and the light source 1 and guides light to the substrate. The detection optical system 1113 includes a photodetector 1119 that detects light from the sample, but may include an optical element that is disposed between the substrate and the photodetector 1119 and guides light from the substrate to the photodetector. . The inspection processing system 1114 includes a defect processing unit 1120 that inspects defects of the sample from the detection result of the photodetector. The input / output system 1115 includes a display unit 1121 for displaying inspection results and defect information, and an input unit 1122 for inputting inspection conditions and the like.

  In the inspection device, if no recipe is specified, the FOUP required time can be calculated in multiple patterns from the standard processing (shortest) for the “front” target to the high-density processing (longest) for the “back” target. -Enable notification.

  Hereinafter, an embodiment in which the present invention is applied to an inspection apparatus will be described with reference to the drawings.

  As shown in FIG. 3, the apparatus occupies the time required for [FOUP LOAD] + ([WAFER LOAD] + [WAFER INSPECTION] + [WAFER UNLOAD]) × number of processed sheets + [FOUP UNLOAD]. By predicting this time in advance, it is possible to efficiently schedule the FOUP arrangement for the next device and reduce the FOUP processing waiting time. [FOUP LOAD] and [FOUP UNLOAD] calculate the prediction time with a fixed coefficient. The fixed coefficient indicates a time constant that can be calculated and managed in advance by the hardware configuration of the apparatus and control software.

  Since [WAFER LOAD] time and [WAFER UNLOAD] time vary greatly depending on whether or not the wafer is reversed, two formulas are prepared. In Type 2, since there are two types of inspection surfaces (front / back), back surface inspection = wafer reversal, and front surface inspection = wafer reversal does not occur. In addition, since the time required for inversion varies depending on the equipment, it can be used with versatility. For example, in the case where the wafer reversing mechanism is an independent unit, the time required to move and install the wafer to the reversing unit, the reversing time, and the time to move the wafer from the transformation unit are required. If the arm has a reversing mechanism, only the reversing time needs to be considered.

  [WAFER INSPECTION] The time is classified into a plurality of time coefficients and managed according to the required inspection accuracy and the performance of the apparatus. For example, the coefficient r1 is applied to the a recipe and the inspection object is managed as the wafer back surface, and the coefficient r1 is applied to the b recipe as the inspection object is managed as the wafer surface. Further, in the state where no recipe is specified, the estimated time of all the time coefficients managed (six patterns shown in FIG. 14), or one preset representative coefficient, or the first candidate and the second candidate It is possible to notify an arbitrary number of predicted times. A detailed description of the prediction time notification will be described later.

  FIG. 10-C10 [FOUP LOAD time] processing flow will be described with reference to FIG.

  [FOUP LOAD] starts when FOUP is installed in the device. Figure 2-106 (FOUP) is installed in Figure 2-107 (load port). The device fixes the FOUP with a saddle shape mechanism (hereinafter clamped) and reads the FOUP identification unique information (ID). The read value is notified to the device management system (hereinafter referred to as HOST) and ID verification is performed. This ID verification may be performed by the operator without notifying the HOST. Next, after horizontally moving the FOUP in the direction of FIG. 2-122 and docking with FIG. 2-123 (gate), the apparatus opens the FOUP door (simultaneously with FIG. 2-123 (gate)). Thereafter, the result of scanning the wafer arrangement information (hereinafter referred to as a slot map) is notified to the HOST, and the slot map is verified. This slot map verification may be performed by the operator without notifying the HOST. With these procedures, the FOUP is ready for inspection processing.

  These are described by taking, as an example, the operation of a GEM (Generic Equipment Model) 300 compatible device compliant with SEMI (Semiconductor Equipment and Materials International) E30, E87, and the like. However, it is not necessary to comply with this standard as long as it is a semiconductor inspection apparatus that transports materials using a container having the same form as FOUP.

  FIG. 10-C60 [FOUP UNLOAD time] processing flow will be described with reference to FIG.

  The apparatus closes the FOUP door (simultaneously with FIG. 2-123 (gate)) when all wafer processing is complete. After that, FOUP and Fig. 2-123 (gate) are undocked and moved to the delivery position. The unloading operation is performed by the FOUP unloading robot or manually by the instruction of the HOST that has received the unloadable state transition notification notified at this timing or an earlier timing. At this timing or earlier, the device releases the FOUP clamp.

  FOUP unloading robot or manpower unloads the FOUP whose clamp is released. The device notifies the HOST of the FOUP carry-in ready state transition after carrying out the FOUP.

  FIG. 10-C30 [wafer LOAD time] processing flow will be described with reference to FIG.

  In the case of the surface object inspection, the apparatus transfers the wafer taken out from FIG. 2-106 (FOUP) according to FIG. 2-114 (Arm1) to FIG. 2-109 (PA). A wafer that has been pre-aligned according to FIG. 2-109 (PA) is taken out from FIG. 2-109 (PA) according to FIG. 2-114 (Arm1) and transferred to FIG. 2-105 (Chamba).

  In the case of the back surface inspection, the apparatus transfers the wafer taken out from FIG. 2-106 (FOUP) according to FIG. 2-114 (Arm1) to FIG. 2-111 (reversing unit). The wafer reversed to the back surface by FIG. 2-111 (reversing unit) is taken out by FIG. 2-114 (Arm1) and transferred to FIG. 2-109 (PA). A wafer that has been pre-aligned according to FIG. 2-109 (PA) is taken out from FIG. 2-109 (PA) according to FIG. 2-114 (Arm1) and transferred to FIG. 2-105 (Chamba).

  The flow of WAFER LOAD processing when the apparatus does not have an independent wafer reversing unit (FIG. 2-111 (reversing unit)) and the wafer transfer arm has a reversing function will be described with reference to FIG. The apparatus inverts the wafer taken out from FIG. 2-106 (FOUP) according to FIG. 2-114 (Arm1 “with inversion function”) to the back side and transfers it to FIG. 2-109 (PA). A wafer pre-aligned by FIG. 2-109 (PA) is taken out from FIG. 2-109 (PA) by FIG. 2-115 (Arm2 “no inversion function”) and transferred to FIG. 2-105 (Chamba).

  FIG. 10-C50 [wafer UNLOAD time] processing flow will be described with reference to FIG.

  In the case of the surface target inspection, the apparatus takes out the processed wafer from FIG. 2-105 (Chamba) according to FIG. 2-115 (Arm2) and transfers it to FIG. 2-106 (FOUP).

  In the case of back side object inspection, the apparatus takes out the processed wafer from FIG. 2-105 (Chamba) according to FIG. 2-115 (Arm2) and transfers it to FIG. 2-111 (reversing unit). The wafer reversed to the surface by FIG. 2-111 (reversing unit) is transferred to FIG. 2-106 (FOUP) by FIG. 2-115 (Arm2).

  The flow of the WAFER UNLOAD process in the case where the apparatus does not have an independent wafer reversing unit (FIG. 2-111 (reversing unit)) and the wafer transfer arm has a reversing function will be described with reference to FIG. The apparatus takes out the processed wafer from FIG. 2-105 (Chamba) with reference to FIG. 2-114 (Arm1 “with inversion function”), and after inversion to the surface, transfers it to FIG. 2-106 (FOUP).

  Flow of Chamba wafer exchange processing by continuous processing.

  When a wafer processed in FIG. 2-115 (Arm2) is taken out from FIG. 2-105 (Chamba) in FIG. 10-C50 [wafer UNLOAD time] processing and the next processing wafer exists on FIG. 2-114 (Arm1) Transferred to Figure 2-105 (Chamba).

The flow of surface target wafer continuous processing (LOAD INSPECTION UNLOAD) will be described with reference to FIG. The first wafer is WF, the middle wafer is WM, and the last wafer is WL.
[A] WF is transferred from FOUP to PA in FIG. 4-Arm1 (1) time. After the pre-aligner time (Fig. 4-PA (1)) has passed, it will be transferred to Chamba in Fig. 4-Arm1 (2) time.
[B] Next wafer (WM) is transferred from FOUP to PA in Fig. 4-Arm1 (3) time, and after pre-aligner time (Fig. 4-PA (2)) has passed to Chamba, Fig. 4-Arm1 (4) time Will be reprinted. At this time, it waits in front of Chamba until the processing of the preceding wafer is completed. The preceding wafer is taken out from the Chamba by the Arm 2 after completion of the processing (FIG. 4—Arm 2 (1) or (2) time start), and the next processing wafer that has been waiting is transferred from the Arm 1 to the Chamba instead. (Up to this timing is the time of FIG. 4-Arm1 (4) or (6).) Subsequently, the processed wafer is transferred to the FOUP by Arm2 (FIG. 4-Arm2 (1) or (2) time). If there is a wafer to be processed (WM), the procedure from [B] is repeated. If there is no wafer to be processed next (the wafer currently being processed is WL), [C] is displayed.
[C] Arm2 waits for the completion of WL processing before Chamba. The preceding wafer is taken out from Chamba by Arm2 after the processing is completed, and transferred to FOUP in FIG. 4-Arm2 (3) time.
(A) Time required for WAFER LOAD INSPECT UNLOAD when processing wafer n is 1 (b) Time required for WAFER LOAD INSPECT UNLOAD when processing wafer n is 2 (c) WAFER LOAD INSPECT UNLOAD when processing wafer n is 3 or more Time required (a) Arm1 (1) + PA (1) + Arm1 (2) + Chamba (1) + Arm2 (1)
(B) Arm1 (1) + PA (1) + Arm1 (2) + Chamba (1) + Chamba (g) + Chamba (2) + Arm2 (2)
(C) Arm1 (1) + PA (1) + Arm1 (2) + Chamba (1) + Chamba (g) + Chamba (2) +… Chamba (g) + Chamba (n) + Arm2 (n)
Chamba (g): “Time to take out inspection complete wafer and transfer next inspection wafer to Chamba”

The flow of back surface target wafer continuous processing (LOAD INSPECTION UNLOAD) when a wafer transfer arm having a reversing function is installed in Arm1 in the apparatus will be described with reference to FIG. The first wafer is WF, the middle wafer is WM, and the last wafer is WL.
[A] WF is taken out from the FOUP in FIG. After the pre-aligner time (Fig. 5-PA (1)) has passed, it will be transferred to Chamba in Fig. 5-Arm2 (1) time.
[B] The next wafer (WM) is taken out from FOUP by Arm1 (in FIG. 5-Arm1 (2) time), reversed from the front surface to the back surface, and then transferred to the PA. After the pre-aligner time (Fig. 5-PA (2)) has passed, it will be transferred to Chamba in Fig. 5-Arm2 (2) time. At this time, it waits in front of Chamba until the processing of the preceding wafer is completed. The preceding wafer is taken out by Arm1 after the processing is completed, and the next processing wafer that has been waiting is transferred from Arm2 to Chamba instead. (The time until this time is FIG. 5-Arm2 (2) or (3)). Subsequently, the processed wafer is reversed by Arm1 (from the back surface to the front surface) and then transferred to the FOUP. (FIG. 5—Arm1 (3) or (5) time) When there is a wafer to be processed next (WM), the procedure from [B] is repeated. If there is no wafer to be processed next (the wafer currently being processed is the final wafer WL), [C] is displayed.
[C] Arm1 waits for the completion of WL processing before Chamba. After the processing is completed, the WL wafer is taken out from Chamba by Arm1 (FIG. 5-Arm1 (6) time), reversed (from the back surface to the front surface), and then transferred to the FOUP.
(A) Time required for WAFER LOAD INSPECT UNLOAD when processing wafer n is 1 (b) Time required for WAFER LOAD INSPECT UNLOAD when processing wafer n is 2 (c) WAFER LOAD INSPECT UNLOAD when processing wafer n is 3 or more Time required (a) Arm1 (1) + PA (1) + Arm2 (1) + Chamba (1) + Arm1 (3)
(B) Arm1 (1) + PA (1) + Arm2 (1) + Chamba (1) + Chamba (g) + Chamba (2) + Arm1 (4)
(C) Arm1 (1) + PA (1) + Arm2 (1) + Chamba (1) + Chamba (g) + Chamba (2) +… + Chamba (g) + Chamba (n) + Arm1 (6)
Chamba (g): “Time to take out inspection complete wafer and transfer next inspection wafer to Chamba”

The flow of back surface target wafer continuous processing (LOAD INSPECTION UNLOAD) when an independent wafer reversing unit is installed in the apparatus will be described with reference to FIG. This will be described as an inspection time exceeding the time for preparing the next wafer (required for the reversing process). The first wafer is WF, the middle wafer is WM, and the last wafer is WL.
[A] WF is taken out from FOUP in FIG. 6-Arm1 (1) time and transferred to RevU (independent inversion unit). In RevU, the WF is reversed from the front side to the back side in FIG. 6 RevU (1) time. The wafer inverted on the back side is transferred from RevU to PA by Arm1 in Fig. 6-Arm1 (2) time, and transferred to Chamba in Fig. 6-Arm1 (3) time after the pre-aligner time (Fig. 6-PA (1)) has elapsed. It will be posted.
[B] The next wafer (WM) is taken out from the FOUP in FIG. 6-Arm1 (4) time and transferred to the RevU (independent inversion unit). In RevU, the WM is reversed from the front surface to the back surface in the time shown in FIG. 6-RevU (2). The wafer flipped to the back side is transferred from RevU to PA by Arm1 in Fig. 6-Arm1 (5) time, and after pre-aligner time (Fig. 6-PA (2)) to Chamba, in Fig. 6-Arm1 (6) time Reprinted. At this time, it waits in front of Chamba until the processing of the preceding wafer is completed. The preceding wafer is taken out by Arm2 after the processing is completed, and the next processing wafer that has been waiting is transferred from Arm1 to Chamba instead. (The time until this timing is FIG. 6-Arm1 (6) or (9) time). Subsequently, the processed wafer is transferred to RevU (independent inversion unit) at Arm2 (FIG. 6-Arm2 (1) time). . In RevU, the wafer is reversed from the back surface to the front surface in time shown in FIG. 6-RevU (3). The wafer inverted to the surface is transferred from RevU to FOUP by Arm2 in FIG. 6-Arm2 (2) time. (FIG. 6—Arm2 (2) or (4) time) When there is a wafer to be processed next (WM), the procedure from [B] is repeated. If there is no wafer to be processed next (the wafer currently being processed is the final wafer WL), [C] is displayed.
[C] Arm2 waits for the completion of WL processing before Chamba. WL is taken out from Chamba by Arm2 (Fig. 6-Arm2 (5) time) after completion of processing, and transferred to RevU (independent inversion unit). In RevU, the wafer is reversed from the back surface to the front surface in FIG. 6 RevU (6) time. The wafer inverted to the surface is transferred from RevU to FOUP by Arm2 in FIG. 6-Arm2 (6) time.
(A) Time required for WAFER LOAD INSPECT UNLOAD when processing wafer n is 1 (b) Time required for WAFER LOAD INSPECT UNLOAD when processing wafer n is 2 (c) WAFER LOAD INSPECT UNLOAD when processing wafer n is 3 or more Time required (a) Arm1 (1) + RevU (1) + Arm1 (2) + PA (1) + Arm1 (3) + Chamba (1) + Arm2 (1) + RevU (3) + Arm2 (2)
(B) Arm1 (1) + RevU (1) + Arm1 (2) + PA (1) + Arm1 (3) + Chamba (1) + Chamba (g) + Chamba (2) + Arm2 (3) + RevU (5) + Arm2 (4)
(C) Arm1 (1) + RevU (1) + Arm1 (2) + PA (1) + Arm1 (3) + Chamba (1) + Chamba (g) + Chamba (2) +… + Chamba (g) + Chamba (n) + Arm2 (5) + RevU (6) + Arm2 (6)
Chamba (g): “Time to take out inspection complete wafer and transfer next inspection wafer to Chamba”

The flow of back surface target wafer continuous processing (LOAD INSPECTION UNLOAD) when an independent wafer reversing unit is installed in the apparatus will be described with reference to FIG. This will explain a case where the wafer transfer sequence is optimized as an inspection time that is shorter than the next wafer preparation (reversal processing time). The first wafer is WF, the intermediate wafer 1 is WM1, the intermediate wafer 2 is WM2, and the last wafer is WL.
[A] The device takes out WF from FOUP with Arm1, and then takes out WM1 with Arm2. WF is transferred to RevU (Independent Inversion Unit) in FIG. 7-Arm1 (1) time. In RevU, WF is reversed from front to back in Fig. 7-RevU (1) time. The wafer reversed to the back surface is transferred from RevU to PA by Arm1 in FIG. 7-Arm1 (2) time. Transfer WM1 from Arm2 to RevU during pre-aligner time. (The time until this timing is FIG. 7-Arm2 (1) time.) WF is transferred to Chamba in FIG. 7-Arm1 (3) time after the pre-aligner time (FIG. 7-PA (1)) has elapsed. Subsequently, WM1 inverted on the back surface is transferred from RevU to PA by Arm2 (FIG. 7-Arm2 (2)).
[B] The next wafer (WM2) is taken out by Arm1 and transferred to RevU (Fig. 7-Arm1 (4) time), and pre-aligned WM1 is taken out from PA by Arm1 and shown in front of Chamba. Transferred in 7-Arm1 (5) time. At this time, it waits in front of Chamba until the processing of the preceding wafer is completed. The preceding wafer is taken out by Arm2 after the processing is completed, and the next processing wafer that has been waiting is transferred from Arm1 to Chamba instead. (The time until this is Figure 7-Arm1 (5) time.) Subsequently, the RevU wafer (WM2) is taken out by Arm1, and the processed wafer is RevU (independent inversion) by Arm2 (Figure 7-Arm2 (3) time). The next processing wafer (WM2) is transferred to the PA in Arm1 (6) time. In RevU, the wafer is reversed from the back surface to the front surface in FIG. 7-RevU (4) time. The wafer inverted to the surface is transferred from RevU to FOUP by Arm1 in FIG. 7-Arm2 (5) time. If there is a wafer to be processed next (WMn), the procedure [B] is repeated. If there is no wafer to be processed next (the wafer currently being processed is the final wafer WL), [C] is displayed.
[C] Arm2 waits for the completion of WL processing before Chamba. WL is taken out from Chamba by Arm2 (Fig. 7-Arm2 (10) time) after completion of processing, and transferred to RevU (independent inversion unit). In RevU, the wafer is reversed from the back surface to the front surface in FIG. 7-RevU (8) time. The wafer inverted to the surface is transferred from RevU to FOUP by Arm2 in FIG. 7-Arm2 (11) time.
(A) Time required for WAFER LOAD INSPECT UNLOAD when processing wafer n is 1 (b) Time required for WAFER LOAD INSPECT UNLOAD when processing wafer n is 2 (c) WAFER LOAD INSPECT UNLOAD when processing wafer n is 3 or more Time required (a) Arm1 (1) + RevU (1) + Arm1 (2) + PA (1) + Arm1 (3) + Chamba (1) + Arm2 (1) + RevU (3) + Arm1 (2)
(B) Arm1 (1) + Arm2 (0) + RevU (1) + Arm1 (2) + PA (1) + Arm1 (3) + Chamba (1) + Chamba (g) + Chamba (2) + Arm2 (3) + RevU (5) + Arm2 (4 )
(C) Arm1 (1) + Arm2 (0) + RevU (1) + Arm1 (2) + PA (1) + Arm1 (3) + Chamba (1) + Chamba (g) + Chamba (2) + ... + Chamba (g) + Chamba (n) + Arm2 (10) + RevU (8) + Arm2 (11)
Arm2 (0): “Time to take out the second one after taking out the first one”
Chamba (g): “Time to take out inspection complete wafer and transfer next inspection wafer to Chamba”

  FIG. 10-C40 [wafer inspection] processing flow will be described with reference to FIGS.

  As shown in FIG. 11-S1, the wafer to be inspected is placed on FIG. 2-113 (inspection stage) in FIG. 2-105 (Chamba) by the wafer transfer arm to perform wafer inspection (FIG. 11-S2). As shown in the flow of FIG. 10-C40, this inspection time is calculated by the inspection processing time in FIG. 2-100 (arithmetic unit) using the time managed in the DB by the inspection pattern. When the recipe is determined, the calculation result of one pattern is obtained. When the recipe is not specified, the inspection pattern is classified and the number of DB management is performed. The inspection patterns are managed in advance in FIG. 2-100 (inspection pattern DB) by classifying the apparatus adjustment values of recipes that affect the processing time when the apparatus performs inspection processing according to the processing time. When the inspection process is completed, the wafer to be inspected is collected by the wafer transfer arm from FIG. 2-113 (inspection stage) as shown in FIG. 11-S3.

  Based on the above description, a notification example when the present invention is used under the following conditions will be described with reference to FIGS. 2, 8, 12, and 14.

  In the example of this explanation, the apparatus manages the DB as three classifications of Normal, Middle, and High, and sets all the information (six patterns shown in FIG. 14) to be notified, and FIG. 2-107 (1) (load port A : FOUP of LPa) is under inspection processing, FOUP of Fig. 2-107 (2) (load port B: LPb) is waiting for inspection processing (lot reserved) and Fig. 2-107 (3) (load port C: LPc) Assumes no FOUP.

  2-103 (keyboard) or 2-104 (mouse), the operator inputs only the number of wafers to be processed at the load port C (no recipe information). 2-100 (arithmetic unit) performs arithmetic processing from this input, and the arithmetic result is displayed on FIG. 2-101 (console display) as FIG. 8-FOUP occupation time calculation information notification GUI. FIG. 8-Information displayed on the FOUP occupation time calculation information notification GUI is as follows.

  Fig. 8-LPa_R: Recipe information, Fig. 8-LPa_C: Number of processed wafers, Fig. 8-LPa_V: FOUP occupation time information (unprocessed wafer processing time and FOUP UNLOAD time), Fig. 8-LPa_m: Wafer status display (processing wait / 8-LPb_R: Recipe information, 8-LPb_C: Number of processed wafers, 8-LPb_V: FOUP occupation time information (unprocessed wafer processing time with LPa inspection completion time added, and FOUP UNLOAD Time), FIG. 8-LPb_m: wafer status display (processing wait / processed / not subject), FIG. 8-LPc_R: blank (because there is no recipe information), FIG. 8-LPc_C: number of processed wafers, FIG. 8-LPc_V: FOUP occupancy time information (LPa and LPb completion time, ie, time when LPc FOUP can start processing), Fig. 8-LPc_m (Table N): FOUP LOAD / UNLOAD time and surface inspection of specified number of wafers for inspection pattern Normal WAFER LOAD INSPECTION UNLOAD time in processing time Accumulated FOUP occupation time information, Fig. 8-LPc_m (Table M): FOUP LOAD / UNLOAD time and FOUP occupation time information integrating the surface inspection of the specified number of wafers with the processing time of the inspection pattern Middle and WAFER LOAD INSPECTION UNLOAD, Fig. 8-LPc_m (Table H): FOUP LOAD / UNLOAD time and FOUP occupancy time information obtained by integrating the WAFER LOAD INSPECTION UNLOAD time with the processing time of inspection pattern High for surface inspection of the specified number of wafers, Fig. 8-LPc_m (back N ): FOUP LOAD / UNLOAD time and FOUP occupancy time information obtained by integrating WAFER LOAD INSPECTION UNLOAD time with the inspection pattern Normal processing time for backside inspection of the specified number of wafers, Fig. 8-LPc_m (Back M): FOUP LOAD / UNLOAD time And FOUP occupancy time information obtained by integrating the time of WAFER LOAD INSPECTION UNLOAD with the processing time of the inspection pattern Middle for the surface inspection of the specified number of wafers, Fig. 8-LPc_m (Back H): FOUP LOAD / UNLOAD time and surface inspection for the specified number of wafers FOUP occupied time by integrating the time WAFER LOAD INSPECTION UNLOAD processing time of the inspection pattern High information calculation results are notified by displaying respectively.

  The notification for the calculation request from the HOST will be described with reference to FIG. 12, FIG. 13 and FIG. This is a notification example of the result of arithmetic processing using the virtual numerical values shown in FIG.

  Equipment status is LPa: FOUP present / inspection (recipe: Recipe_FN (table normal inspection) / 5 unprocessed wafers), LPb: FOUP present / waiting inspection (recipe: Recipe_RH (back high inspection) / 12 unprocessed wafers) , LPc: Requests the required time calculation request for processing five wafers whose recipe is undetermined without FOUP from the HOST to the apparatus (FIG. 13-H2Erequest). The apparatus notifies the HOST of the calculation result (FIG. 13-E2Hreply). A case in which this content is notified by the FOUP occupation time calculation information notification GUI is shown in FIG. 9-GUI. The right dotted line frame part of FIG.8 and FIG.9 shows the example of notification when prediction time has set 2 patterns of surface / Normal and surface / Middle.

  In FIG. 9-GUI, ● represents an inspected wafer, ○ represents a wafer under inspection, and ◎ represents a wafer awaiting inspection.

100 Inspection pattern DB and arithmetic unit 101 Output device (console display)
103 Input device (keyboard)
104 Input device (mouse)
105 Inspection device (Chamba)
106 FOUP
107 Load port 108 Transport device 109 Pre-alignment (PA)
110 controller (inspection pattern DB and arithmetic unit)
111 Inversion unit 113 Inspection stage 114 Handling arm 1 (Arm1)
115 Handling Arm 2 (Arm2)
116 Moving device 122 Shutter 123 Gate 131 Docking direction 132 Undocking direction
WF First processed wafer
WM (WM1, WM2) Intermediate processing wafer
WL Last processed wafer (F-> f), (M [1 | 2]-> m [1 | 2]), (L-> l) Reverse from front (f-> F), (m [1 | 2]-> M [1 | 2]), (l-> L) Reversed from the back

Claims (5)

In an inspection device for inspecting a substrate,
A processing unit,
The processor is
Determine whether the substrate is reversed by the substrate storage container having a reversing function,
Obtaining the loading time of the substrate and the unloading time of the substrate based on the presence or absence of the inversion,
Furthermore, obtaining the occupation time required from loading the substrate storage container to unloading the substrate storage container,
The occupying time includes the loading time, the inspection time for inspecting the substrate, and the unloading time. The inspection apparatus according to claim 1,
The processing unit uses a fixed coefficient to obtain the loading time of the substrate storage container and the unloading time of the substrate storage container,
The inspection apparatus, wherein the fixed coefficient is a constant that can be obtained in advance by the processing unit. The inspection apparatus according to claim 1, further comprising a storage unit,
The inspection time is classified into a plurality of time coefficients, stored in the storage unit,
2. The inspection apparatus according to claim 1, wherein the time coefficient is for managing the inspection time that changes in accordance with required inspection accuracy. The inspection apparatus according to claim 1,
Having a display,
Wherein the display unit, the inspection apparatus and displaying the resulting et time by the processing unit. The inspection apparatus according to claim 1,
The inspection apparatus according to claim 1, wherein the substrate storage container switches the reversing operation according to the occupation time.

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