JPH0477241U - - Google Patents
Info
- Publication number
- JPH0477241U JPH0477241U JP12134090U JP12134090U JPH0477241U JP H0477241 U JPH0477241 U JP H0477241U JP 12134090 U JP12134090 U JP 12134090U JP 12134090 U JP12134090 U JP 12134090U JP H0477241 U JPH0477241 U JP H0477241U
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- lot
- average processing
- test
- processing time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 235000012431 wafers Nutrition 0.000 claims 9
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
第１図は本考案を示すブロツク図、第２図は一
実施例を示すブロツク図、第３図は一実施例の動
作を示すフローチヤート図である。
２……ウエハプローバ、４……平均処理時間算
出部、６……ロツトウエハ枚数設定部、８……ロ
ツトテスト終了時刻算出分、１０……デイスプレ
ー装置。
FIG. 1 is a block diagram showing the present invention, FIG. 2 is a block diagram showing one embodiment, and FIG. 3 is a flowchart showing the operation of one embodiment. 2...Wafer prober, 4...Average processing time calculation section, 6...Rot wafer number setting section, 8...Rot test end time calculation, 10...Display device.
Claims (1)
発生するウエハプローバと、ウエハプローバから
の信号を入力し、１枚のウエハのテストに要する
平均処理時間を算出する平均処理時間算出部と、
ロツトに含まれるウエハ枚数が設定されるロツト
ウエハ枚数設定部と、平均処理時間算出部で算出
された平均処理時間とロツトウエハ枚数設定部に
設定されたウエハ枚数とからそのロツトのテスト
終了時刻を算出するロツトテスト終了時刻算出部
と、算出されたロツトテスト終了時刻を表示する
デイスプレー装置とを備えたウエハテスト終了時
刻予告装置。 a wafer prober that generates a signal each time a test of one wafer is completed; an average processing time calculation unit that receives the signal from the wafer prober and calculates the average processing time required to test one wafer;
The test end time for the lot is calculated from the lot wafer number setting section where the number of wafers included in the lot is set, the average processing time calculated by the average processing time calculation section, and the number of wafers set in the lot wafer number setting section. A wafer test end time notification device comprising a lot test end time calculation section and a display device for displaying the calculated lot test end time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12134090U JPH0477241U (en) | 1990-11-19 | 1990-11-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12134090U JPH0477241U (en) | 1990-11-19 | 1990-11-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0477241U true JPH0477241U (en) | 1992-07-06 |
Family
ID=31869199
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12134090U Pending JPH0477241U (en) | 1990-11-19 | 1990-11-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0477241U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011142197A (en) * | 2010-01-07 | 2011-07-21 | Hitachi High-Technologies Corp | Inspection device and inspection method |
-
1990
- 1990-11-19 JP JP12134090U patent/JPH0477241U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011142197A (en) * | 2010-01-07 | 2011-07-21 | Hitachi High-Technologies Corp | Inspection device and inspection method |