JP5561453B2 - AD converter, mechanical quantity detector, and electronic equipment. - Google Patents

Description

  The present invention relates to an AD conversion device, a mechanical quantity detection device, and an electronic apparatus.

  The gyro sensor is a sensor that measures a rotation speed (rotational angular velocity) with respect to a rotational motion around a certain rotation axis. The “vibration gyro sensor” widely used today detects the angular velocity using the “Coriolis force”.

  For example, in a vibrating gyroscope that operates using the piezoelectric effect, when an AC voltage is applied to a gyro element (vibrating body such as a crystal), a Coriolis force is generated, and a current is generated according to the rotation rate and angular velocity. The current signal is amplified inside the gyro sensor, and a voltage proportional to the angular velocity is output. The output voltage of the gyro sensor is converted into a digital signal by an A / D converter and taken into a microcomputer, and various controls are performed by the microcomputer. For example, a gyro sensor is mounted on an electronic device such as a mobile phone or a digital camera, and is used for camera shake correction or the like.

Recently, there is a digital output gyro sensor module in which a gyro sensor is packaged together with an analog front end circuit and an A / D conversion circuit.
JP 2002-174520 A

  FIG. 16 is a diagram illustrating a configuration example of a conventional sensor system. An AD converter is connected between the sensor module (mechanical quantity detector) and the microcomputer, and the AD converter is composed of an anti-alias filter and an AD converter circuit.

  Here, a continuous-time low-pass filter is used as the anti-alias filter. That is, the anti-alias filter is composed of components such as resistors, capacitors, transistors, and operational amplifiers. For this reason, there is a problem in that the gain characteristics and phase characteristics of the anti-alias filter tend to vary due to variations in accuracy of these components, and adjustment is difficult.

  In addition, since the sampling timing (chip enable signal) of the AD conversion circuit is determined by the microcomputer, the proportion of the control operation of the AD conversion circuit in the microcomputer task cannot be ignored, which increases the system load. It was.

  Further, when the microcomputer determines the sampling timing of the AD conversion circuit, sampling jitter occurs, and it may be difficult to improve the AD conversion accuracy. Therefore, even if the detection accuracy of the sensor module is high, it may be difficult to maintain high detection accuracy for the entire sensor system including the sensor module and the AD converter.

  The present invention has been made in view of the problems as described above, and makes it possible to easily adjust an anti-alias filter and maintain high detection accuracy as a whole sensor system and a mechanical quantity. An object is to provide a detection device.

(1) The present invention
The analog signal of the detection result of the physical quantity detection device for detecting the dynamics volume outputs an AD converter for converting a digital signal,
A discrete-time filter that performs sampling by sampling an analog signal of the detection result; and
An AD conversion unit that performs an AD conversion process for converting an analog signal filtered by the discrete-time filter into a digital signal;
The discrete time filter is:
Filter processing as an anti-alias filter for the AD conversion processing is performed based on a synchronous clock signal output from the mechanical quantity detection device.

The dynamics amount detecting device may be, for example, an acceleration sensor or an angular velocity sensor (gyro sensor).

  The discrete-time filter may perform the filtering process by sampling the analog signal of the detection result with the synchronous clock signal, or perform the filtering process by sampling the analog signal of the detection result with the clock signal obtained by dividing the synchronous clock signal. You may go.

  When an anti-alias filter for AD conversion processing is configured as a continuous-time filter using components such as resistors, capacitors, transistors, and operational amplifiers, the gain characteristics and phase characteristics of the anti-alias filter are affected by variations in the accuracy of these components. Difficult to adjust and difficult to adjust. However, according to the present invention, since the anti-alias filter is configured as a discrete-time filter that operates based on a synchronous clock signal with relatively high frequency accuracy and low jitter, variations in gain characteristics and phase characteristics of the anti-alias filter are reduced. Can be small. Therefore, according to the present invention, it is possible to easily adjust the anti-alias filter and maintain high detection accuracy as the entire sensor system.

(2) The AD converter of the present invention
A filter clock generator for generating a filter clock signal for sampling the analog signal of the detection result by the discrete-time filter based on the synchronous clock signal;
The filter clock generator is
The filter clock signal obtained by dividing the synchronous clock signal based on a set value from the outside may be generated.

  For example, the filter clock generation unit includes a clock frequency dividing circuit that divides the synchronous clock signal to generate the filter clock signal, and the frequency dividing ratio of the clock frequency dividing circuit is variably set from the outside. It may be.

  According to the present invention, the cutoff frequency of the discrete-time filter can be adjusted to a desired frequency by setting the frequency of the filter clock signal from the outside. Therefore, even when the AD conversion processing cycle by the AD converter is changed, the function as an anti-alias filter can be secured by adjusting the cutoff frequency of the discrete-time filter in accordance with the cycle change.

(3) The AD converter of the present invention
An AD conversion control unit that controls the timing of the AD conversion processing based on the synchronous clock signal may be included.

  The AD conversion control unit may control the timing of AD conversion processing with a synchronous clock signal, or may control the timing of AD conversion processing with a clock signal obtained by dividing the synchronous clock signal.

  According to the present invention, since the AD conversion control unit controls the timing of AD conversion processing by the AD conversion unit, the ratio of the control operation of the AD conversion unit in the task of the external microcomputer can be further reduced. Therefore, the load on the system can be further reduced.

  In addition, when the microcomputer determines the sampling timing of the AD conversion unit, it is difficult to improve the accuracy of AD conversion because sampling jitter occurs. However, according to the present invention, the synchronous clock signal output from the mechanical quantity detection device can be reduced. Since the timing of the AD conversion processing is controlled based on this, the detection processing of the entire sensor system can be performed with the frequency accuracy of the synchronous clock signal.

(4) In the AD converter of the present invention,
The AD conversion control unit
You may make it control so that the said AD conversion process is performed with the period based on the setting value from the outside.

  For example, the AD conversion control unit includes a counter circuit that performs a counting operation based on the synchronous clock signal, controls the timing of the AD conversion processing based on the count value of the counter circuit, and counts the counter circuit May be variably set from the outside.

  Further, for example, the AD conversion apparatus includes an AD conversion control clock generation unit that generates an AD conversion control clock signal for operating the AD conversion control unit based on the synchronous clock signal, and the AD conversion control clock generation The unit may include a clock frequency dividing circuit that divides the synchronous clock signal to generate the AD conversion control clock signal, and the frequency dividing ratio of the clock frequency dividing circuit may be variably set from the outside. .

  According to the present invention, it is possible to easily change the period of AD conversion processing by the AD conversion unit based on a set value from the outside. Therefore, the AD conversion processing cycle is shortened when it is desired to increase the AD conversion accuracy by a set value from an external microcomputer, and the AD conversion processing cycle is lengthened when the AD conversion accuracy may be lowered. Thus, the ratio of the control operation of the AD conversion unit in the task of the microcomputer can be changed in real time. Therefore, the system load can be brought close to the optimum state.

(5) In the AD converter of the present invention,
The discrete time filter may be a switched capacitor filter.

(6) In the AD converter of the present invention,
n discrete time filters provided corresponding to each of the n (n ≧ 2) mechanical quantity detection devices;
a filter selection unit that sequentially selects one analog signal in time division from n analog signals filtered by the n discrete-time filters;
The AD converter is
Performing the AD conversion processing on the analog signals sequentially selected by the filter selection unit in a time-sharing manner,
The n discrete time filters are:
The n analog signals obtained by filtering the n analog signals respectively detected by the n mechanical quantity detection devices at substantially the same timing are sequentially selected by the filter selection unit in a time division manner. Even if the phase delay is adjusted.

  According to the present invention, one AD conversion unit can perform AD conversion processing in a time division manner on the detection results of n pieces of mechanical quantity detection devices. Therefore, it is possible to reduce the number of parts used in the AD converter and the area of the chip.

(7) The present invention
An AD conversion device according to any of the above,
The mechanical quantity detection device;
An electronic apparatus comprising: a processing unit that performs processing based on a digital signal obtained by AD-converting an analog signal of the detection result by the AD conversion device.

(8) The present invention
A vibrator that vibrates based on a driving signal and outputs an analog signal modulated according to a mechanical quantity applied from the outside;
A synchronous clock generation circuit for generating a synchronous clock signal having the same frequency as the drive signal;
Synchronous detection for performing analog detection on the analog signal output from the vibrator or the amplified signal based on the synchronous clock signal and generating an analog signal including a signal component demodulated according to a dynamic quantity Circuit,
A discrete-time filter that performs filtering by sampling an analog signal output by the synchronous detection circuit; and
An AD conversion unit that performs an AD conversion process for converting an analog signal filtered by the discrete-time filter into a digital signal;
The discrete time filter is:
Based on the synchronous clock signal, a mechanical quantity detection characterized by performing a filter process as a filter for attenuating an unnecessary signal generated by the synchronous detection and a filter process as an anti-alias filter for the AD conversion process Device.

The mechanical quantity detection device
Including an amplifier circuit for amplifying an analog signal output from the vibrator;
The synchronous detection circuit is
You may make it perform the said synchronous detection with respect to the signal which the said amplifier circuit outputs.

  When an anti-alias filter for AD conversion processing is configured as a continuous-time filter using components such as resistors, capacitors, transistors, and operational amplifiers, the gain characteristics and phase characteristics of the anti-alias filter are affected by variations in the accuracy of these components. Difficult to adjust and difficult to adjust. However, according to the present invention, since the anti-alias filter is configured as a discrete-time filter that operates based on the synchronous clock signal, variations in gain characteristics and phase characteristics of the anti-alias filter can be reduced. Therefore, according to the present invention, it is possible to easily adjust the anti-alias filter and maintain high detection accuracy as the entire sensor system.

  In addition, according to the present invention, the discrete-time filter functions as both a filter for attenuating unnecessary signals generated by synchronous detection and an anti-alias filter for AD conversion processing. Therefore, it is possible to reduce the number of parts and the chip area used in the mechanical quantity detection device.

(9) The mechanical quantity detection device of the present invention includes:
A filter clock generator for generating a filter clock signal for sampling the analog signal of the detection result by the discrete-time filter based on the synchronous clock signal;
The filter clock generator is
The filter clock signal having a frequency corresponding to a set value from the outside may be generated.

(10) The mechanical quantity detection device of the present invention includes:
An AD conversion control unit that controls the timing of the AD conversion processing based on the synchronous clock signal may be included.

(11) In the mechanical quantity detection device of the present invention,
The AD conversion control unit
You may make it control so that the said AD conversion process may be performed with the period which divided the said synchronous clock by the frequency division ratio corresponding to the setting value from the outside.

(12) In the mechanical quantity detection device of the present invention,
The discrete time filter may be a switched capacitor filter.

(13) The present invention provides:
A mechanical quantity detection device according to any of the above,
And a processing unit that performs processing based on a detection result of the mechanical quantity detection device.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. 1. AD converter 1-1. FIG. 1 is a diagram for explaining a mechanical quantity detection device that generates an analog signal that is a target of AD conversion processing by the AD conversion apparatus of the present embodiment.

  The mechanical quantity detection device (sensor module) 10 detects the mechanical quantity by the vibrator 110 that vibrates based on the drive signals 102 and 104, and outputs a detection data signal 12 (analog signal of the detection result). The drive signals 102 and 104 may be oscillation signals output from the oscillation circuit 100 (for example, an oscillation circuit using a crystal oscillator or a ceramic resonator), for example.

  The vibrator 110 oscillates at the oscillation frequency of the oscillation circuit 100 (frequency of the drive signals 102 and 104 (drive frequency)), thereby detecting, as the differential signals 112 and 114, for example, mechanical quantities such as angular velocity and acceleration. . Here, the differential signals 112 and 114 are signals obtained by modulating the drive signals 102 and 104 with a degree of modulation corresponding to the dynamic quantity. For example, the transducer 110 has differential signals 102 and 104 that are amplitude-modulated (AM-modulated) with a phase shift of ± π / 2 from the driving signals 102 and 104 by a force (Coriolis force) applied in a direction orthogonal to the vibration direction. Is output.

  The preamplifier 120 differentially amplifies the differential signals 102 and 104 and outputs an amplified signal 122.

  The phase of the oscillation clock 106 is delayed by π / 2 by the phase adjustment circuit 150 and the synchronous clock signal 14 is output.

  The synchronous detection circuit 130 performs synchronous detection (narrowly defined) by using a synchronous clock signal 14 (clock signal having a driving frequency) obtained by delaying the oscillation clock 106 output from the oscillation circuit 100 by π / 2 with respect to the AM-modulated amplified signal 122. And synchronous detection signal 132 is output. Here, a detection signal is generated in a frequency band near DC by synchronous detection, but at the same time, an unnecessary signal is generated in a frequency band twice the drive frequency. That is, the synchronous detection signal 132 includes a detection signal component in a frequency band near DC and an unnecessary signal component in a frequency band twice the driving frequency.

  The synchronous detection filter 140 functions as a low-pass filter that generates the detection data signal 12 (analog signal) obtained by removing this unnecessary signal component from the synchronous detection signal 132. The synchronous detection filter 140 may be a continuous time filter or a discrete time filter. For example, the synchronous detection filter 140 can be configured as a switched capacitor filter (SCF) operated by the synchronous clock signal 14.

  When the oscillation circuit 100 is configured as an oscillation circuit using a crystal oscillator, the jitter of the drive signals 102 and 104 is extremely small. Further, the jitter of the synchronous clock signal 14 synchronized with the drive signals 102 and 104 is extremely small. Therefore, the mechanical quantity detection device 10 (sensor module) can generate the detection data signal 12 with high detection accuracy.

1-2. First Configuration Example of AD Converter FIG. 2 is a diagram for describing a first configuration example of the AD converter according to the present embodiment.

  The AD conversion apparatus 20-1 performs processing for converting an analog signal as a detection result output from the sensor module 10 into a digital signal.

  The sensor module 10 is a mechanical quantity detection device that detects a mechanical quantity by a vibrator that vibrates based on a drive signal, and is configured as shown in FIG. 1, for example. As the sensor module 10, an angular velocity sensor (gyro sensor) module, an acceleration sensor module, or the like can be considered.

  The AD conversion apparatus 20-1 includes a discrete-time antialias filter 200, an AD conversion unit 300, and a filter clock generation unit 400.

  The discrete-time anti-alias filter 200 is arranged in front of the AD conversion unit 300, and performs a filtering process by sampling an analog signal (detection data signal 12 in FIG. 1) output from the sensor module 10. The discrete-time antialias filter 200 performs filter processing as an antialias filter for the AD conversion processing by the AD conversion unit 300 based on the synchronous clock signal 14 (synchronous clock signal 14 in FIG. 1) output from the sensor module 10. The analog signal 202 attenuated to such an extent that the noise returning to the frequency band near DC by sampling of the AD converter 300 can be ignored in advance is output. The discrete time antialias filter 200 may be, for example, a switched capacitor filter (SCF).

  The AD conversion unit 300 performs AD conversion processing for converting the analog signal 202 filtered by the discrete-time antialias filter 200 into an N-bit digital signal 22. The AD conversion unit 300 controls the timing of AD conversion processing by a chip enable signal (CE) 31 and a clock signal 32 output from the microcomputer 30. That is, for example, the AD conversion unit 300 samples the analog signal 202 in synchronization with the clock signal 32 in a period in which the chip enable signal (CE) 31 is at a low level, and performs an AD conversion process to generate the digital signal 22. To do.

  The AD conversion unit 300 can be configured by various known types of AD conversion circuits such as a flash type (parallel comparison type), a pipeline type, a successive approximation type, and a delta sigma type.

  The microcomputer 30 changes the chip enable signal (CE) 31 from the high level to the low level and then captures the digital signal 22. After the AD converter 300 waits until the AD conversion process is completed, the chip enable signal (CE) 31 is changed from the low level to the high level, and the digital signal capturing is completed. That is, the chip enable signal (CE) 31 controls the period of AD conversion processing by the AD converter 300 by the microcomputer 30.

  Based on the synchronous clock signal 14, the filter clock generation unit 400 generates a filter clock signal 402 for the discrete-time anti-alias filter 200 to sample the analog signal 12 detected by the sensor module 10.

  FIG. 3 is a diagram for explaining a configuration example of the filter clock generation unit in the first configuration example of the AD conversion apparatus.

  The filter clock generation unit 400 can be configured by, for example, preset data 410, a down counter 420, a decoder 430, and the like.

  For example, the down counter 420 performs a process of down-counting in synchronization with the rising edge of the synchronous clock signal 14.

  The decoder 430 performs processing for decoding the count value 422 of the down counter 420 and generating the filter clock signal 402. Further, when the count value 422 of the down counter 420 is 0, the load signal 432 is generated. When the down counter 420 detects the load signal 432 in synchronization with the rising edge of the synchronous clock signal 14, the down counter 420 loads the preset data 410 and repeats the down-counting process until the count value 422 becomes zero.

  That is, the filter clock generation unit 400 repeats the process in which the down counter 420 counts down from the value (m−1) of the preset data 410 to 0, thereby dividing the synchronous clock signal 14 by m and generating the filter clock signal 402. Functions as a clock divider circuit to be generated.

When the preset data 410 is 2 ^k−1 −1 (k ≧ 2), when the down counter 420 (binary counter) counts down to 0, it automatically returns to 2 ^k−1 −1. If the most significant bit signal 420 is the filter clock signal 402 (the ^2k-1 frequency ^- divided clock signal of the synchronous clock signal 14), the decoder 430 is unnecessary.

  In general, when an anti-alias filter for AD conversion processing by the AD conversion unit 300 is configured as a continuous-time filter using components such as a resistor, a capacitor, a transistor, and an operational amplifier, the anti-alias filter is caused by variations in accuracy of these components. The gain characteristics and phase characteristics of these are likely to vary and are difficult to adjust. However, according to the AD conversion apparatus of the present embodiment, the anti-alias filter is configured as the discrete-time anti-alias filter 200 that operates based on the synchronous clock signal 14 with relatively high frequency accuracy and small jitter. Variations in gain characteristics and phase characteristics can be reduced. Therefore, according to the AD conversion apparatus of this embodiment, it is possible to easily adjust the anti-alias filter and maintain high detection accuracy as the entire sensor system.

1-3. Second Configuration Example of AD Converter FIG. 4 is a diagram for describing a second configuration example of the AD converter according to the present embodiment.

  The AD conversion apparatus 20-2 has a configuration in which the filter clock generation unit 400 of the AD conversion apparatus 20-1 in FIG.

  The filter clock generation unit 450 generates a filter clock signal 452 having a frequency corresponding to the set value 34 from the microcomputer 30.

  Since the configuration other than the filter clock generation unit 450 of the AD conversion device 20-2 is the same as the configuration of the AD conversion device 20-1 of FIG.

  FIG. 5 is a diagram for describing a configuration example of the filter clock generation unit in the second configuration example of the AD conversion apparatus.

  The filter clock generation unit 450 can be configured by, for example, a down counter 420, a decoder 430, a selector 460, and the like. The configuration of the decoder 430 is the same as that of the decoder 430 in FIG.

  Since the down counter 420 has the same configuration as the down counter 420 of FIG. 3, the same number is assigned, but when the load signal 432 is detected in synchronization with the rising edge of the synchronous clock signal 14, the preset data set value 34 is loaded. This processing is different from the processing of the down counter 420 in FIG. That is, the downcount cycle of the downcounter 420 changes according to the preset data set value 34. As a result, the frequency division ratio of the divided clock signal 434 output from the decoder 430 also changes according to the preset data setting value 34.

  The selector 460 selects either the synchronous clock signal 14 or the divided clock signal 434 according to the preset data setting value 34 to generate the filter clock signal 452. For example, if the preset data setting value 34 for generating the filter clock signal 452 obtained by dividing the synchronous clock signal 14 by m is m-1, the selector 460 causes the synchronous clock signal 14 when the preset data setting value 34 is 0. When the preset data set value 34 is 1 or more, the divided clock signal 434 may be selected.

  That is, the filter clock generation unit 450 generates a filter clock signal 452 having a frequency corresponding to the preset data value 34 input from the microcomputer 30.

When the preset data set value 34 is 2 ^k−1 −1 (k ≧ 2), when the down counter 420 (binary counter) counts down to 0, it automatically returns to 2 ^k−1 −1. If the signal of the most significant bit of the down counter 420 is the divided clock signal 434 (the ^2k-1 divided clock signal of the synchronous clock signal 14), the decoder 430 is unnecessary.

  According to the AD conversion apparatus of this embodiment, the cutoff frequency of the discrete-time antialias filter 200 is set to a desired frequency by setting the frequency of the filter clock signal 452 (division ratio with respect to the synchronous clock signal 14) from the outside. Can be adjusted. Therefore, even when the period of the AD conversion processing by the AD conversion unit 300 is changed, the function as an anti-alias filter is secured by adjusting the cutoff frequency of the discrete-time anti-alias filter 200 in accordance with the period change. be able to.

1-4. Third Configuration Example of AD Converter FIG. 6 is a diagram for describing a third configuration example of the AD converter according to the present embodiment.

  In the AD conversion apparatus 20-3, an AD conversion control unit 500 is added to the AD conversion apparatus 20-1 in FIG.

  The AD conversion control unit 500 controls the timing of AD conversion processing by the AD conversion unit 300 based on the synchronous clock signal 14. More specifically, the AD conversion control unit 500 generates a chip enable signal (CE) 502 and a strobe signal 24 of the AD conversion unit 300 in synchronization with the synchronous clock signal 14, and performs AD conversion processing by the AD conversion unit 300. Control timing. That is, the AD conversion control unit 500 changes the chip enable signal (CE) 502 from a high level to a low level, waits until the AD conversion unit 300 finishes the AD conversion process, and then waits for the chip enable signal (CE). 502 is changed from the low level to the high level. In addition, the AD conversion unit 300 outputs the digital signal 22 with the rising edge or the falling edge of the strobe signal 24 as a trigger. The microcomputer 30 receives the digital signal 22 using the strobe signal 24. That is, instead of the microcomputer 30 controlling the timing of AD conversion processing as in the AD conversion apparatus 20-1 in FIG. 2, the AD conversion control unit 500 controls the period of AD conversion processing by the AD conversion unit 300.

  The digital signal 22 output from the AD conversion unit 300 is transmitted to the port of the microcomputer 30 in synchronization with the strobe signal 24. When the port becomes full, the microcomputer 30 generates an interrupt and takes in the AD conversion result. In other words, the microcomputer 30 does not need to wait while the AD conversion unit 300 performs the AD conversion process, so that the CPU (not shown) can execute other tasks.

  Furthermore, when a DMA (Direct Memory Access) controller is incorporated in the microcomputer 30 and the port to which the digital signal 22 is input becomes full and an interrupt occurs, the DMA controller occupies the bus and stores the data stored in the port. If the process of transferring to the memory is performed, the load on the CPU due to the AD conversion process can be eliminated.

  The configuration other than the AD conversion control unit 500 of the AD conversion device 20-3 is the same as that of the AD conversion device 20-1 in FIG.

  FIG. 7 is a diagram for describing a configuration example of the AD conversion control unit in the third configuration example of the AD conversion apparatus.

  The AD conversion control unit 500 can be configured by, for example, preset data 510, a timer (down counter) 520, a state machine 530, a decoder 540, and the like.

  For example, the timer 520 performs a process of measuring the time corresponding to the preset data 510 by down-counting in synchronization with the rising edge of the synchronous clock signal 14. The timer 520 generates a measurement time end signal 522 every time the time corresponding to the preset data 510 is measured.

  The state machine 530 changes the state (state) using the measurement time end signal 522 generated by the timer 520 as a trigger. The state machine 530 outputs a state signal 532 indicating the current state.

  The decoder 540 performs a process of decoding the state signal 532 and generating a chip enable signal (CE) 502 and a strobe signal 24 of the AD conversion unit 300 when the state machine 530 is in a predetermined state.

  The AD conversion unit 300 outputs the digital signal 22 by using the rising edge or the falling edge of the strobe signal 24 as a trigger during a period in which the chip enable signal (CE) 502 is at a low level.

  According to the AD conversion apparatus of this embodiment, since the AD conversion control unit 500 controls the timing of AD conversion processing by the AD conversion unit 300, the proportion of the control operation of the AD conversion unit 300 in the task of the external microcomputer 30 Can be made smaller. Therefore, the load on the system can be further reduced.

  Further, when the microcomputer 30 determines the sampling timing of the AD conversion unit 300, sampling jitter is generated, so that it is difficult to improve the accuracy of AD conversion. However, according to the AD conversion apparatus of this embodiment, the sensor module 10 is Since the AD conversion processing timing is controlled based on the output synchronous clock signal 14, the detection processing of the entire sensor system can be performed with the frequency accuracy of the synchronous clock signal 14.

1-5. Fourth Configuration Example of AD Converter FIG. 8 is a diagram for describing a fourth configuration example of the AD converter according to the present embodiment.

  The AD conversion device 20-4 has a configuration in which the filter clock generation unit 400 and the AD conversion control unit 500 of the AD conversion device 20-3 in FIG. 6 are replaced with a filter clock generation unit 450 and an AD conversion control unit 550, respectively. Yes.

  The filter clock generation unit 450 has the same configuration as the filter clock generation unit 450 described in FIG. 4 and FIG.

  The AD conversion control unit 550 performs control so that the AD conversion processing by the AD conversion unit 300 is performed at a cycle corresponding to the set value (frequency division ratio with respect to the synchronous clock signal 14) 36 from the microcomputer 30.

  The configurations other than the filter clock generation unit 450 and the AD conversion control unit 550 of the AD conversion device 20-4 are the same as those of the AD conversion device 20-3 in FIG. .

  FIG. 9 is a diagram for describing a configuration example of the AD conversion control unit in the fourth configuration example of the AD conversion apparatus.

  The AD conversion control unit 550 can be configured by, for example, a timer (down counter) 520, a state machine 530, a decoder 540, and the like. The configurations of the state machine 530 and the decoder 540 are the same as those of the state machine 530 and the decoder 540 of FIG.

  The timer 520 has the same configuration as the timer 520 in FIG. 7 and is therefore given the same number. However, in the process of loading the preset data setting value 36 in synchronization with the rising edge of the synchronous clock signal 14, the timer 520 in FIG. It is different from processing. That is, the down-count cycle of the timer 520 changes according to the preset data setting value 36. As a result, the period during which the chip enable signal (CE) 552 of the AD converter 300 output from the decoder 540 is low and the strobe signal 24 also change according to the preset data setting value 36.

  That is, the AD conversion control unit 550 performs control so that the AD conversion processing by the AD conversion unit 300 is performed in a cycle corresponding to the preset data setting value (frequency division ratio with respect to the synchronous clock signal 14) 36 input from the microcomputer 30. To do.

  According to the AD conversion apparatus of this embodiment, the AD conversion processing cycle by the AD conversion unit 300 can be easily changed based on the set value 36 from the external microcomputer 30. Accordingly, the AD conversion processing cycle is shortened when it is desired to increase the AD conversion accuracy by the set value 36 from the microcomputer 30, and the AD conversion processing cycle is lengthened when the AD conversion accuracy may be lowered. Thus, the ratio of the control operation of the AD conversion unit 300 in the task of the microcomputer 30 can be changed in real time. Therefore, the system load can be brought close to the optimum state.

  In addition, according to the AD conversion apparatus of the present embodiment, even when the AD conversion processing cycle by the AD conversion unit 300 is changed, the frequency of the filter clock signal 452 is set from the outside according to the change, thereby providing a discrete time type. The cutoff frequency of the anti-alias filter 200 can be adjusted to a desired frequency. Therefore, even when the AD conversion processing cycle by the AD conversion unit 300 is changed, the discrete-time antialias filter 200 can function as an optimal antialias filter.

1-6. Fifth Configuration Example of AD Conversion Device FIG. 10 is a diagram for describing a fifth configuration example of the AD conversion device of the present embodiment.

  The AD conversion apparatus 20-5 includes n (n ≧ 2) discrete-time antialias filters 200-1 to 200-n, an AD conversion unit 300, n filter clock generation units 450-1 to 450-n, The AD conversion control unit 550, the multiplexer 700, and the like are included.

  The discrete-time anti-alias filters 200-1 to 200-n are provided corresponding to each of the n sensor modules 10-1 to 10-n, and detections output from the sensor modules 10-1 to 10-n, respectively. The resulting analog signals 12-1 to 12-n are sampled and filtered.

  The filter clock generation units 450-1 to 450-n are discrete-time antialias filters 200-1 to 200-n based on the synchronous clock signals 14-1 to 14-n output from the sensor modules 10-1 to 10-n, respectively. 200-n performs processing for generating filter clock signals 452-1 to 452-n for sampling the analog signals 12-1 to 12-n, respectively. The filter clock generators 450-1 to 450-n respectively output filter clock signals 452-1 to 452-n having frequencies corresponding to the set values 34-1 to 34-n from the microcomputer 30. It may be configured to generate. For example, each of the filter clock generation units 450-1 to 450-n may have the same configuration as that in FIG.

  The AD conversion control unit 550 controls the timing of AD conversion processing by the AD conversion unit 300 based on one of the synchronous clock signals 14-1 to 14-n (for example, the synchronous clock signal 14-1). More specifically, the AD conversion control unit 550 generates the chip enable signal (CE) 552 and the strobe signal 24 of the AD conversion unit 300 in synchronization with the synchronous clock signal 14-1, for example, and the AD conversion unit 300 Controls the timing of AD conversion processing. In addition, the AD conversion control unit 550 controls the AD conversion processing by the AD conversion unit 300 to be performed at a period corresponding to the set value 36 (frequency division ratio with respect to the synchronous clock signal 14-1) 36 from the microcomputer 30. It may be configured. For example, the AD conversion control unit 550 may have the same configuration as that in FIG.

  Further, the AD conversion control unit 550 may generate the data selection signal 554 of the multiplexer 700. For example, the AD conversion control unit 550 may generate the data selection signal 554 in the decoder 540 having the configuration shown in FIG.

  The multiplexer 700 functions as a filter selection unit, and one analog signal is time-divided from n analog signals 202-1 to 202-n that are respectively filtered by the discrete-time antialias filters 200-1 to 200-n. Are sequentially selected to generate a selected analog signal 702. Here, the multiplexer 700 sequentially selects one analog signal in time division from the analog signals 202-1 to 202-n in accordance with the data selection signal 554, and generates a selected analog signal 702. For example, the multiplexer 700 may be configured such that the analog signals 202-1 to 202-n are selected when the data selection signal 554 has a value of 0 to n-1.

  The AD conversion unit 300 performs AD conversion processing for converting the selected analog signal 702 selected by the multiplexer 700 into an N-bit digital signal 22.

  That is, the AD conversion apparatus 20-5 performs AD conversion on the analog signals 12-1 to 12-n as the detection results of the sensor modules 10-1 to 10-n in order in a time division manner, and outputs the digital signal 22.

  FIG. 11 is a timing chart for explaining the operation timing of the AD converter of the fifth configuration example.

  As described with reference to FIG. 10, the AD conversion apparatus 20-5 performs AD conversion on the analog signals 12-1 to 12-n as detection results of the sensor modules 10-1 to 10-n sequentially in a time-sharing manner, so that the digital signal 22 Is output.

For example, the target of the AD converting analog signals 12-1 to 12-n of the sensor module 10-1 to 10-n of the detection result of the time division at time _t 0 ~t _1. Therefore, the analog signals 202-1 to 202-n obtained by filtering the analog signals 12-1 to 12-n by the anti-alias filters 200-1 to 200-n are, for example, time t _{1 to} t ₂ , time t ₂ ~t _3, ···, so that the target of the AD conversion at time _t 4 ~t _5, the data selection signal 554 of the multiplexer 700, the time _t 1 ~t _2, time _t 2 _~t 3, · .., 0, 1,..., N−1 at times t _{4 to} t ₅ , respectively.

Here, the multiplexer 700 so selects the analog signal 202-1 at time _t 1 ~t ₂ in accordance with the data selection signal 554, the analog signal at time _t 1 ~t ₂ 202-1 analog signal at time _t 0 ~t ₁ 12-1 needs to be a filtered signal. Therefore, the phase delay pd1 of the anti-alias filter 200-1 is adjusted to be approximately equal to t ₁ -t ₀ .

Further, the multiplexer 700 so selects the analog signal 202-2 at time _t 2 ~t ₃ in accordance with the data selection signal 554, an analog signal in the analog signal 202-2 at time _t 0 ~t ₁ at time _t 2 ~t ₃ 12 -2 needs to be a filtered signal. Therefore, the phase delay pd2 of the anti-alias filter 200-2 is adjusted so as to be approximately equal to t ₂ −t ₀ . Similarly, the phase delay pdn of the anti-alias filter 200-n is adjusted so as to be substantially equal to t _n −t ₀ .

Next, the sensor module 10-1 to 10-n of the detection result of the analog signal 12-1 to 12-n are respectively the time _t 6 ~t ₇ at time _t 5 ~t _6, time _t 7 _~t 8, ·· -, subject to the AD conversion at time _t 9 _{~t 10,} AD conversion processing is performed in time division.

  Here, for example, the phase delay of the anti-alias filters 200-1 to 200-n is adjusted by changing the frequency of the filter clock signals 452-1 to 452-n (that is, changing the switching period of the SCF circuit). You may do it. Further, for example, the phase delay of the anti-alias filters 200-1 to 200-n may be adjusted by changing the capacitance value of the SCF circuit.

  According to the AD conversion apparatus of this embodiment, one AD conversion unit 300 performs time-division AD conversion processing on the detection results 12-1 to 12-n of the n sensor modules 10-1 to 10-n. It can be carried out. Therefore, it is possible to reduce the number of parts and the chip area used in the AD converter according to the present embodiment.

2. Mechanical Quantity Detection Device FIG. 12 is a diagram for explaining a configuration example of the mechanical quantity detection device of the present embodiment.

  The mechanical quantity detection device (sensor module) 800 detects the mechanical quantity by the vibrator 820 that vibrates based on the drive signals 812 and 814, and outputs a detection data signal 802 (digital signal). The drive signals 812 and 814 may be oscillation signals output from an oscillation circuit 810 (for example, an oscillation circuit using a crystal oscillator or a ceramic resonator), for example.

  The oscillation circuit 810 performs processing for generating an oscillation clock 816 synchronized with the drive signals 812 and 814. The oscillation circuit 810 functions as an oscillation clock generation circuit.

  When a driving signal 812 and a driving signal 814 having an opposite phase with a phase shift of π are input to the vibrator 820, a vibrating piece (not shown) vibrates. This vibration is referred to as drive vibration. And when an angular velocity arises in a vibration piece, Coriolis force works in the direction orthogonal to drive vibration. Due to the Coriolis force, a detection target vibration whose phase is delayed by π / 2 with respect to the drive vibration is generated. The vibrator 820 converts the vibration into current or voltage using the piezoelectric effect and outputs analog signals (differential signals 822 and 824). At this time, in addition to the signal due to the vibration to be detected, a signal in which a signal due to leakage of drive vibration is superimposed is output as the analog signal.

  As described above, the vibrator 820 outputs modulated analog signals (differential signals 822 and 824) whose phases are shifted by π / 2 from the drive signals 812 and 814 in accordance with the angular velocity applied from the outside.

  The preamplifier 830 differentially amplifies the differential signals 822 and 824 and outputs an amplified signal 832.

  The synchronous detection circuit 840 performs synchronous detection (multiplication in a narrow sense) on the AM-modulated amplified signal 832 using a synchronous clock signal 882 obtained by delaying the phase of the oscillation clock 816 output from the oscillation circuit 810 by π / 2. The synchronous detection signal 842 is output. The phase adjustment circuit 880 delays the oscillation clock 816 by π / 2. Here, a detection signal is generated in a frequency band near DC by synchronous detection, but at the same time, an unnecessary signal is generated in a frequency band twice the drive frequency. That is, the synchronous detection signal 842 includes a detection signal component in a frequency band near DC and an unnecessary signal component in a frequency band twice the driving frequency.

  The discrete time filter 850 functions as a low pass filter. The discrete-time filter 850 also functions as an anti-alias filter that reduces noise that returns to a frequency band near DC by sampling of the AD conversion circuit 860 to a level that can be ignored in advance. The discrete time filter 850 may be, for example, a switched capacitor filter (SCF).

  The AD conversion circuit 860 performs AD conversion processing for converting the analog signal 852 filtered by the discrete time filter 850 into an N-bit digital signal 862. The AD conversion circuit 860 can be configured by various known types of AD conversion circuits such as a flash type (parallel comparison type), a pipeline type, a successive approximation type, and a delta sigma type.

  The AD conversion control circuit 870 controls the timing of AD conversion processing by the AD conversion circuit 860 based on the synchronous clock signal 882. More specifically, the AD conversion control circuit 870 generates a chip enable signal (CE) 872 and a clock signal 874 of the AD conversion circuit 860 based on the synchronous clock signal 882, and timing of AD conversion processing by the AD conversion circuit 860. To control. That is, the AD conversion control circuit 870 changes the chip enable signal (CE) 872 from the high level to the low level, waits until the AD conversion circuit 860 finishes the AD conversion process, and then waits for the chip enable signal (CE). 872 is changed from low level to high level. That is, the AD conversion control circuit 870 controls the timing of AD conversion processing by the AD conversion circuit 860.

  Further, the AD conversion control circuit 870 may convert the digital signal 862 output from the AD conversion circuit 860 into serial data 802 and transmit it to the port of the microcomputer 900 together with the strobe signal 804. When the port becomes full, the microcomputer 900 generates an interrupt and takes in the AD conversion result. In other words, the microcomputer 900 does not need to wait while the AD conversion circuit 860 performs the AD conversion processing, so that the CPU (not shown) can execute other tasks.

  The configuration of the circuit (806) that performs AD conversion processing on the analog signal 842 output from the synchronous detection circuit 840 is the same as, for example, the AD conversion devices 20-1 to 20-5 described with reference to FIGS. It may be replaced with a configuration.

  In general, when an anti-alias filter for AD conversion processing by the AD conversion circuit 860 is configured as a continuous-time filter using components such as resistors, capacitors, transistors, and operational amplifiers, the anti-alias filter is caused by variations in accuracy of these components. The gain characteristics and phase characteristics of these are likely to vary and are difficult to adjust. However, according to the mechanical quantity detection device of the present embodiment, the anti-alias filter is configured as the discrete-time filter 850 that operates based on the synchronous clock signal 882 with relatively high frequency accuracy and small jitter. Variations in gain characteristics and phase characteristics can be reduced. Therefore, according to the mechanical quantity detection device of the present embodiment, it is possible to easily adjust the anti-alias filter and maintain high detection accuracy as the entire sensor system.

  Further, according to the mechanical quantity detection device of the present embodiment, the discrete-time filter 850 functions as both a low-pass filter function and an anti-alias filter function for AD conversion processing. Therefore, it is possible to reduce the number of parts and the chip area used in the mechanical quantity detection device of the present embodiment.

  Further, according to the mechanical quantity detection device of this embodiment, the clock signal supplied to the discrete time filter 850 and the AD conversion circuit 870 is not supplied from the microcomputer 900 but based on the synchronous clock signal 882. Generated. Therefore, the detection accuracy of the mechanical quantity detection device of this embodiment can be ensured by the frequency accuracy of the synchronous clock signal 882. In addition, since it is not necessary to supply a clock signal from the microcomputer 900, the number of pins can be reduced when the mechanical quantity detection device of the present embodiment is realized with one chip.

  FIG. 13A and FIG. 13B are diagrams for explaining the adjustment of the sampling timing by the phase adjustment circuit in the configuration example of the mechanical quantity detection device.

  FIG. 13A is a diagram illustrating an example of waveforms of the input signal 832 and the synchronous clock signal 882 of the synchronous detection circuit 840.

  This is because the input signal 832 of the synchronous detection circuit 840 leaks drive vibration whose phase is advanced by π / 2 with respect to the detected vibration in addition to the detection target signal (modulation signal) 834 in the frequency band of the synchronous clock signal 882. The unnecessary signal 836 generated in this way is included. The unnecessary signal 836 is advanced in phase by π / 2 with respect to the detection target signal 834.

  FIG. 13B is a diagram illustrating an example of the waveform of the output signal 842 of the synchronous detection circuit 840.

  The output signal 842 of the synchronous detection circuit 840 includes a detection target signal 844 in a frequency band near DC, and includes an unnecessary signal 846 in a frequency band twice the frequency (driving frequency) of the synchronous clock signal 882. The unnecessary signal is removed by canceling the positive component and the negative component by the discrete-time filter 850.

  According to the mechanical quantity detection device of this embodiment, when the discrete-time filter 850 samples the output signal 842 of the synchronous detection circuit 840, it accompanies an unnecessary signal in a frequency band twice the frequency of the synchronous clock signal 882. The aliasing noise can be effectively attenuated. Therefore, it is possible to improve the detection accuracy of the entire sensor system.

3. Electronic Device FIG. 14 shows an example of a block diagram of the electronic device of this embodiment. The electronic apparatus 1000 includes a microcomputer 910, an input unit 920, a memory 930, a power generation unit 940, an output unit 950, an analog output sensor module 960, and an AD converter 970.

  The input unit 920 is for inputting various data.

  The sensor module 960 detects a mechanical quantity by a vibrator that vibrates based on the drive signal, and performs processing to output an analog signal as a detection result to the AD converter 970.

  The AD conversion device 970 performs processing for converting an analog signal as a detection result output from the sensor module 960 into a digital signal.

  The microcomputer 910 performs various processes based on the data input by the input unit 920. In addition, the microcomputer 910 performs detection result analysis processing and the like based on a digital signal obtained by AD conversion of the analog signal of the detection result of the sensor module 960 by the AD conversion device 970.

  The memory 930 is a work area for the microcomputer 910 and the like.

  The power generation unit 940 is for generating various power sources used in the electronic device 1000.

  The output unit 950 is for outputting the analysis processing result of the microcomputer 910 and the like.

  By incorporating the AD converter of this embodiment as the AD converter 970, an electronic device with high cost performance can be provided.

  FIG. 15 illustrates another example of a block diagram of the electronic device of this embodiment. The electronic apparatus 1100 has a configuration in which the analog output sensor module 960 and the AD converter 970 of the electronic apparatus 1000 in FIG. 14 are replaced with a digital output sensor module 980.

  The sensor module 980 performs a process of detecting a mechanical quantity using a vibrator that vibrates based on the drive signal and outputting a digital signal as a detection result to the microcomputer 910. The microcomputer 910 performs detection result analysis processing based on the digital signal of the detection result of the sensor module 980.

  Since the configuration of the electronic device 1100 other than the sensor module 980 is the same as the configuration of the electronic device 1000 of FIG.

  By incorporating the mechanical quantity detection device of this embodiment as the sensor module 980, an electronic device with high cost performance can be provided.

  Electronic devices that can use this embodiment shown in FIG. 14 and FIG. 15 include devices that perform posture detection and posture control of moving bodies and robots, head-mounted displays used in virtual reality, and head posture angles. Various electronic devices such as a game machine using a tracker, a 3D game pad, a digital camera, a mobile phone, a portable information terminal, and a car navigation system can be considered.

  In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.

  The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

The figure for demonstrating the mechanical quantity detection apparatus which produces | generates the analog signal used as the target of AD conversion processing by the AD converter of this embodiment. The figure for demonstrating the 1st structural example of the AD converter of this embodiment. The figure for demonstrating the structural example of the filter clock generation part in the 1st structural example of AD converter. The figure for demonstrating the 2nd structural example of the AD converter of this embodiment. The figure for demonstrating the structural example of the filter clock generation part in the 2nd structural example of AD converter. The figure for demonstrating the 3rd structural example of the AD converter of this embodiment. The figure for demonstrating the structural example of the AD conversion control part in the 3rd structural example of an AD converter. The figure for demonstrating the 4th structural example of the AD converter of this embodiment. The figure for demonstrating the structural example of the AD conversion control part in the 4th structural example of an AD converter. The figure for demonstrating the 5th structural example of the AD converter of this embodiment. The timing chart for demonstrating the operation timing of the AD converter of a 5th structural example. The figure for demonstrating the structural example of the mechanical quantity detection apparatus of this embodiment. FIG. 13A and FIG. 13B are diagrams for explaining the adjustment of the sampling timing by the phase adjustment circuit in the configuration example of the mechanical quantity detection device. An example of a block diagram of an electronic apparatus including an AD conversion device. An example of the block diagram of the electronic device containing a mechanical quantity detection apparatus (sensor module). The figure which shows the structural example of the conventional sensor system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Mechanical quantity detection apparatus (sensor module), 10-1 to 10-n sensor module, 12 detection data signal, 12-1 to 12-n detection data signal, 14 synchronous clock signal, 14-1 to 14-n synchronous clock Signal, 20-1 to 20-5 AD converter, 22 digital signal, 24 strobe signal, 30 microcomputer, 31 chip enable signal, 32 clock signal, 34 preset data setting value, 34-1 to 34-n preset data setting Value, 36 preset data setting value, 100 oscillation circuit, 102 drive signal, 104 drive signal, 106 oscillation clock, 110 oscillator, 112 differential signal, 114 differential signal, 120 preamplifier, 122 amplified signal, 130 synchronous detection circuit, 132 Synchronous detection signal, 140 Synchronous detection Filter, 150 phase adjustment circuit, 200 discrete-time antialias filter, 200-1 to 200-n discrete-time antialias filter, 202 analog signal, 202-1 to 202-n analog signal, 300 AD converter, 400 Filter clock generation unit, 402 Filter clock signal, 410 preset data, 420 down counter, 422 count value, 430 decoder, 432 load signal, 450 filter clock generation unit, 450-1 to 450-n filter clock generation unit, 452 Filter clock Signal, 452-1 to 452-n filter clock signal, 460 selector, 500 AD conversion control unit, 502 chip enable signal, 510 preset data, 520 timer, 522 measurement time end signal, 530 state machine, 532 state signal, 540 decoder, 550 AD conversion control unit, 552 chip enable signal, 554 data selection signal, 700 multiplexer, 702 selection analog signal, 800 mechanical quantity detection device (sensor module), 802 serial data, 804 Strobe signal, 810 oscillation circuit, 812 drive signal, 814 drive signal, 816 oscillation clock, 820 vibrator, 822 differential signal, 824 differential signal, 830 preamplifier, 832 amplified signal, 834 detection target signal, 836 unnecessary signal, 840 Synchronous detection circuit, 842 Synchronous detection signal, 844 Detection target signal, 846 Unnecessary signal, 850 Discrete time filter, 852 Analog signal, 860 AD conversion unit, 862 Digital signal, 870 AD conversion control Path, 872 chip enable signal, 874 clock signal, 880 phase adjustment circuit, 882 synchronization clock signal, 900 microcomputer, 910 microcomputer, 920 input section, 930 memory, 940 power generation section, 950 output section, 960 sensor module, 970 AD converter, 980 sensor module, 1000 electronic device, 1100 electronic device

Claims (11)

An AD converter that converts an analog signal of a detection result output by a mechanical quantity detection device that detects a mechanical quantity into a digital signal,
A discrete-time filter that performs sampling by sampling an analog signal of the detection result; and
An AD converter that performs an AD conversion process for converting the analog signal filtered by the discrete-time filter into a digital signal;
An AD conversion control unit that controls the timing of the AD conversion processing based on the synchronous clock signal ,
The discrete time filter is:
An AD conversion apparatus that performs filter processing as an anti-alias filter for the AD conversion processing based on a synchronous clock signal output from the mechanical quantity detection device. In claim 1,
A filter clock generator for generating a filter clock signal for sampling the analog signal of the detection result by the discrete-time filter based on the synchronous clock signal;
The filter clock generator is
An AD conversion apparatus that generates the filter clock signal obtained by dividing the synchronous clock signal based on an externally set value. In claim 1 or 2 ,
The AD conversion control unit
An AD conversion apparatus, wherein the AD conversion processing is controlled to be performed at a cycle based on a set value from the outside. In any one of Claims 1 thru | or 3 ,
The AD converter according to claim 1, wherein the discrete-time filter is a switched capacitor filter. In any one of Claims 1 thru | or 4 ,
n discrete time filters provided corresponding to each of the n (n ≧ 2) mechanical quantity detection devices;
a filter selection unit that sequentially selects one analog signal in time division from n analog signals filtered by the n discrete-time filters;
The AD converter is
Performing the AD conversion processing on the analog signals sequentially selected by the filter selection unit in a time-sharing manner,
The n discrete time filters are:
The n analog signals obtained by filtering the n analog signals respectively detected by the n mechanical quantity detection devices at substantially the same timing are sequentially selected by the filter selection unit in a time division manner. An AD converter characterized in that a phase delay is adjusted. An AD converter according to any one of claims 1 to 5 ,
The mechanical quantity detection device;
An electronic device comprising: a processing unit that performs processing based on a digital signal obtained by AD-converting the analog signal of the detection result by the AD conversion device. A vibrator that vibrates based on a driving signal and outputs an analog signal modulated according to a mechanical quantity applied from the outside;
A synchronous clock generation circuit for generating a synchronous clock signal having the same frequency as the drive signal;
Synchronous detection for performing analog detection on the analog signal output from the vibrator or the amplified signal based on the synchronous clock signal and generating an analog signal including a signal component demodulated according to a dynamic quantity Circuit,
A discrete-time filter that performs filtering by sampling an analog signal output by the synchronous detection circuit; and
An AD converter that performs an AD conversion process for converting the analog signal filtered by the discrete-time filter into a digital signal;
An AD conversion control unit that controls the timing of the AD conversion processing based on the synchronous clock signal ,
The discrete time filter is:
Based on the synchronous clock signal, a mechanical quantity detection characterized by performing a filter process as a filter for attenuating an unnecessary signal generated by the synchronous detection and a filter process as an anti-alias filter for the AD conversion process apparatus. In claim 7 ,
Based on the synchronous clock signal, the discrete-time filter includes a filter clock generation unit that generates a filter clock signal for sampling the analog signal output by the synchronous detection circuit,
The filter clock generator is
A mechanical quantity detection device that generates the filter clock signal having a frequency corresponding to a set value from the outside. In claim 7 or 8 ,
The AD conversion control unit
An apparatus for detecting a mechanical quantity, wherein the AD conversion process is performed in a cycle in which the synchronous clock is divided by a division ratio corresponding to an externally set value. In any one of Claims 7 thru | or 9 ,
The discrete time filter is a switched capacitor filter. The mechanical quantity detection device according to any one of claims 7 to 10 ,
And a processing unit that performs processing based on a detection result of the mechanical quantity detection device.

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