JP5543253B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a high ESD tolerance and a method for manufacturing the same.

  In recent years, ESD (Electrostatic discharge) countermeasures for semiconductor devices having a MOS (Metal-Oxide-Semiconductor) structure have become a problem. For example, Patent Document 1 discloses a power MOS transistor whose task is to increase the resistance to ESD. In the power MOS transistor, a p + impurity diffusion buried layer is formed in the p epi layer below the drain electrode and the source electrode, respectively, and a p impurity diffusion layer connecting the buried layers to each other is formed in the p epitaxial layer. Is provided. Such a configuration makes it difficult for a break current (breakdown current) to flow in the vicinity of the source region, thereby improving the ESD tolerance.

JP 2002-353441 A

  However, in the case of the power MOS transistor disclosed in Patent Document 1, although the n + layer is formed in the drain region, the p + layer (anode layer) is not formed and the ESD tolerance is low. Further, when a p + layer is formed for such a structure, it cannot be avoided that a transistor is destroyed due to thermal runaway of a parasitic thyristor formed by an n + layer, a p + layer, and an epitaxial layer existing on the drain side and the source side, respectively. There was a problem.

  For example, in an Nch type LDMOS (Lateral Double diffused MOS), a parasitic NPN transistor including a source side n + layer, a p body layer, a drain side n + layer, and an n epitaxial layer is formed as a drain side p + layer, an n epitaxial layer, and a source side p + layer. When operating before the parasitic PNP transistor composed of the p body layer, the LDMOS transistor is destroyed by the secondary breakdown caused by the thermal runaway of the parasitic NPN transistor. Therefore, in the prior art disclosed in Patent Document 1, it is difficult to configure a semiconductor device such as an LDMOS having a high ESD tolerance.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor device that does not break down due to the operation of a parasitic thyristor and a method for manufacturing the same.

A semiconductor device according to the present invention is formed on a semiconductor layer of a first conductivity type, an oxide film formed on the semiconductor layer so as to protrude from a surface of the semiconductor layer, and on the semiconductor layer across the oxide film. A gate electrode, a drain electrode and a source electrode formed on the surface of the semiconductor layer at positions sandwiching the gate electrode, and a drain side p + layer and an n + connected to the drain electrode and formed in the semiconductor layer A layer, a source-side p + layer and an n + layer formed in the semiconductor layer connected to the source electrode, and a second conductivity type formed in the semiconductor layer so as to surround the source-side p + layer and the n + layer a semiconductor device comprising a and the body layer, wherein the opposite at least away from the layer of the second conductivity type and the same type of said drain-side p + layer and the n + layer below and the layer Characterized in that it comprises an adjusting layer of the second conductivity type formed inside the conductor layer.

The semiconductor device according to the present invention includes a first conductive type semiconductor layer, an oxide film formed on the semiconductor layer so as to protrude from a surface of the semiconductor layer, and the semiconductor layer on the oxide film. A formed gate electrode, a drain electrode and a source electrode formed on the surface of the semiconductor layer at positions sandwiching the gate electrode, and a drain side p + layer formed in the semiconductor layer connected to the drain electrode And the n + layer, the source side p + layer and the n + layer formed in the semiconductor layer connected to the source electrode, and the drain side p + layer and the n + layer so as to surround the surface. a drain drift layer of a second conductivity type, a semiconductor device including, downward apart from the layer of the first conductivity type and the same type of the at least the drain side p + layer and the n + layer One such layer and opposite to, characterized in that it comprises an adjusting layer of the first conductivity type formed in the interior of the semiconductor layer.

According to another aspect of the present invention, there is provided a semiconductor device manufacturing method comprising: forming an oxide film projecting from a surface of the semiconductor layer on a semiconductor layer of a first conductivity type; and forming a gate over the oxide film on the semiconductor layer. A gate electrode forming step for forming an electrode; a body layer forming step for forming a body layer of a second conductivity type in the semiconductor layer on one side of the gate electrode; and a source side p + layer and an n + in the body layer Forming a p + layer n + layer forming a layer and forming a drain side p + layer and an n + layer on the surface of the semiconductor layer on the other side of the gate electrode, wherein at least the drain side adjusting layer formed stearyl for forming a control layer of the second conductivity type within said semiconductor layer from the layer of the second conductivity type and the same type opposite to the distant and the layer below of the p + layer and the n + layer Characterized in that it comprises a flop between the p + layer n + layer formation step and the body layer forming step.

Further, the semiconductor device manufacturing method according to the present invention includes an oxide film forming step of forming an oxide film protruding from the surface of the semiconductor layer on the semiconductor layer of the first conductivity type, and straddling the oxide film on the semiconductor layer. A gate electrode forming step for forming a gate electrode; a drain drift layer forming step for forming a drain drift layer of a second conductivity type in the semiconductor layer on one side of the gate electrode; and a drain in the drain drift layer A p + layer n + layer forming step including forming a side p + layer and an n + layer and forming a source side p + layer and an n + layer on the surface of the semiconductor layer on the other side of the gate electrode. , first conductive inside of at least the drain side p + layer and the n + away from the layer of the second conductivity type and the same type of the layers beneath and the layer facing to the semiconductor layer Characterized in that it comprises an adjusting layer forming step of forming a mold adjusting layer between the p + layer n + layer formation step and the drain drift layer formed step.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, it is possible to prevent destruction due to the operation of the parasitic thyristor.

It is sectional drawing of the semiconductor device of a 1st Example. It is the figure which represented on the cross section of the semiconductor device the equivalent circuit of the parasitic PNP transistor and parasitic NPN transistor which are formed of the n + layer, the p + layer, the n type epitaxial layer, the p type body region, and the p type adjustment layer. FIG. 2 is a cross-sectional view in each manufacturing process of the semiconductor device of FIG. 1. FIG. 2 is a cross-sectional view in each manufacturing process of the semiconductor device of FIG. 1. FIG. 2 is a cross-sectional view in each manufacturing process of the semiconductor device of FIG. 1. It is sectional drawing of the semiconductor device of a 2nd Example.

  Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

<First embodiment>
FIG. 1 is a cross-sectional view of a semiconductor device 100 of this embodiment. The semiconductor device 100 is an n-type (hereinafter referred to as the first conductivity type) LDMOS structure semiconductor device. For example, an n + type buried layer 102 containing, for example, arsenic (As) as an impurity is formed on the surface of a p-type (hereinafter referred to as the second conductivity type) semiconductor substrate 101 made mainly of silicon. . An n-type epitaxial layer 103 is formed on the surface of the n + type buried layer 102.

  A LOCOS oxide film 104 is formed on the surface of the n-type epitaxial layer 103 by partial oxidation by a LOCOS (local oxidation of silicon) method. The LOCOS oxide film 104 is formed between the gate electrode 105 and the drain electrode 110, and is formed for the purpose of relaxing the electric field between them.

  For example, a gate electrode 105 made of polycrystalline silicon by n + type phosphorus doping is formed so as to cover a part of the LOCOS oxide film 104 via a gate oxide film 105s. A plurality of gate electrodes (not shown) having the same configuration as that of the gate electrode 105 are formed on the surface of the n-type epitaxial layer 103 at regular intervals.

  A p-type body region 106 is formed in the n-type epitaxial layer 103 below the source electrode 110L. The p-type body region 106 is used to implant boron ions into the n-type epitaxial layer 103 under the conditions of, for example, 20 keV and 5E13 / cm 2 using the gate electrode 105 as a mask, and then to broaden the distribution of boron ions that are implanted ions. The drive-in process is performed.

  An n + layer 108R is formed in the n-type epitaxial layer 103 below the drain electrode 110. An n + layer 108L is formed in the n-type epitaxial layer 103 below the source electrode 110L. The n + layers 108R and 108L are formed by ion implantation using a resist (not shown) removed on the n-type epitaxial layer 103 and the gate electrode 105 as a mask.

  A p + layer 109R is formed in the n-type epitaxial layer 103 below the drain electrode 110. A p + layer 109L is formed in the p-type body region 106 below the source electrode 110L. The p + layer 109R is formed to constitute a parasitic PNP transistor (consisting of the p + layer 109R, the n-type epitaxial layer 103, the p-type body region 106, and the p + layer 109L). By forming the parasitic PNP transistor, for example, an electric field generated in a part of the n + layer 108R is relieved. Therefore, if the p + layer 109R is formed, the semiconductor device 100 can have a high ESD tolerance. The p + layers 109R and 109L are formed by high dose ion implantation. Hereinafter, the p + layer 109R is also referred to as a p-type anode layer 109R. The p + layer 109L is also referred to as a p-type body electrode layer 109L.

  An insulating film 111 is formed on the surfaces of the n-type epitaxial layer 103, the LOCOS oxide film 104 and the gate electrode 105. The insulating film 111 is subjected to a planarization process such as CMP (Chemical Mechanical Planrizaition) as necessary.

  A contact electrode 110R is formed connected to a part of the n + layer 108R and the p + layer 109R. Further, a contact electrode 110L is formed so as to be connected to part of the n + layer 108L and the p + layer 109L. The contact electrodes 110R and 110L include a rectangular contact hole (not shown) including a boundary portion between the n + layer 108R and the p + layer 109R, and a rectangular contact hole including a boundary portion between the n + layer 108L and the p + layer 109L (see FIG. (Not shown) is formed on the insulating film 111, and a metal material mainly composed of tungsten, for example, is formed on the insulating film 111.

  A p-type adjustment layer 107 is formed in the n-type epitaxial layer 103 below the p + layer 109R so as to face the p + layer 109R. The p-type adjustment layer 107 is formed by implanting ions such as boron into the n-type epitaxial layer 103 before forming the n + layer 108R and the p + layer 109R. The p-type adjustment layer 107 is formed by sandwiching a part of the n-type epitaxial layer 103 between the p + layer 109R. Hereinafter, a portion of the n-type epitaxial layer 103 between the p-type adjustment layer 107 and the p + layer 109R is referred to as a drain current path 103r. The concentration of the drain current path 103r is, for example, 2.0E15 / cm 3, and the concentration of the p-type adjustment layer 107 is higher than that.

  Note that the formation position of the p-type adjustment layer 107 is not limited to the position shown in FIG. 1. If it is in the n-type epitaxial layer 103, the p-type adjustment layer 107 is shifted from the position shown in FIG. It may be formed. Further, the size and shape of the p-type adjustment layer 107 are not limited to the case shown in FIG. In FIG. 1, the p-type adjustment layer 107 is formed only below the p + layer 109R, but may extend to the lower part of the n + layer 108R, or may be formed only at a position corresponding to the lower part of the n + layer 108R. May be. As long as the drain current path 103r is formed, the size of the p-type adjustment layer 107 may be larger or smaller than the size shown in FIG.

  FIG. 2 is a diagram showing an equivalent circuit of the parasitic PNP transistor 120 and the parasitic NPN transistor 121 on the cross section of the semiconductor device 100.

  The parasitic PNP transistor 120 is formed of a p + layer 109R, an n-type epitaxial layer 103, a p-type body region 106, and a p + layer 109L. The parasitic NPN transistor 121 is formed of an n + layer 108L, a p-type body region 106, an n-type epitaxial layer 103, and an n + layer 108R.

  By forming the p-type adjustment layer 107 in the n-type epitaxial layer 103 below the p + layer 109R, a drain current path 103r is formed between the p-type adjustment layer 107 and the p + layer 109R. By forming the drain current path 103r, the current passing width in the drain region is narrowed, and as a result, the base resistance value of the parasitic PNP transistor 120 is increased. As a result, the potential between the base and the emitter of the parasitic PNP transistor 120 rises before the parasitic NPN transistor 121 operates, and the parasitic PNP transistor 120 operates before the parasitic NPN transistor 121.

  Since the parasitic PNP transistor 120 operates first, holes are injected into the n-type epitaxial layer 103, and the conductivity in the vicinity of the n + layer 108R can be lowered. As a result, the electric field generated by the ESD is distributed over a wide range without being concentrated on a part of the n + layer 108R, so that the semiconductor device 100 can be prevented from being broken.

  3 to 5 are cross-sectional views in each manufacturing process of the semiconductor device 100. Hereinafter, each manufacturing process of the semiconductor device 100 having the N-type LDMOS structure will be described with reference to these drawings.

  First, for example, an n + type buried layer 102 containing, for example, arsenic (As) as an impurity is formed on the surface of a p type semiconductor substrate 101 made mainly of silicon, and an n type epitaxial layer is formed on the surface of the n + type buried layer 102. 103 is formed (FIG. 3A).

  Next, a LOCOS oxide film 104 is formed on a part of the surface of the n-type epitaxial layer 103 by the LOCOS method (FIG. 3B).

  Next, the surface of the n-type epitaxial layer 103 is oxidized to form a gate oxide film 105s, and then the gate electrode 105 made of polycrystalline silicon is covered with a part of the LOCOS oxide film 104 by, for example, n + type phosphorus doping. Thus, it is formed on the surface of the n-type epitaxial layer 103 (FIG. 3C).

  Next, the drain side region (FIG. 5 (h)) is covered with a resist 120, and boron ions are implanted into the n-type epitaxial layer 103 under the conditions of, for example, 20 keV and 5E13 / cm 2 using the resist 120 and the gate electrode 105 as a mask. Thereafter, a drive-in process for expanding the distribution of ion-implanted boron ions is performed to form the p-type body region 106 (FIG. 4D).

  Next, a resist 120 is formed in a region from the gate electrode 105 to the source side (FIG. 5 (h)) and a partial region on the drain side (FIG. 5 (h)). Ions are implanted into the n-type epitaxial layer 103 to form the p-type adjustment layer 107 (FIG. 4E). At this time, the p-type adjustment layer 107 is formed so that a part of the n-type epitaxial layer 103 is sandwiched between the p-type adjustment layer 107 and the p + layer 109R (FIG. 5G) formed in a later step. An acceleration voltage for ion implantation of the adjustment layer 107 is set. As a result, a drain current path 103r (FIG. 5H) is formed between the p-type adjustment layer 107 and the p + layer 109R. The concentration of the drain current path 103r is, for example, 2.0E15 / cm 3, and ion implantation is performed so that the concentration of the p-type adjustment layer 107 is higher than that.

  Next, a resist 120 is formed in partial regions on the source side and the drain side (FIG. 5H), and then ion implantation is performed on the n-type epitaxial layer 103 and the p-type body region 106 using the resist 120 as a mask. Then, n + layers 108R and 108L are formed (FIG. 4F).

  Next, a resist 120 is formed in partial regions on the source side and the drain side (FIG. 5H), and then high dose ions are implanted into the n-type epitaxial layer 103 and the p-type body region 106 using the resist 120 as a mask. Then, p + layers 109R and 109L are formed (FIG. 5G). Thereby, the batting contact between the n + layer 108R and the p + layer 109R (the overlapping portion of the n + layer 108R and the p + layer 109R in FIG. 5G), and the batting contact between the n + layer 108L and the p + layer 109L (in FIG. 5G). n + layer 108L and p + layer 109L).

  Next, an insulating film 111 is formed on the surfaces of the n-type epitaxial layer 103, the LOCOS oxide film 104, and the gate electrode 105 (FIG. 5G). The insulating film 111 is subjected to a planarization process such as CMP as necessary. Further, a rectangular contact hole (not shown) including the boundary between the n + layer 108R and the p + layer 109R and a rectangular contact hole (not shown) including the boundary between the n + layer 108L and the p + layer 109L are formed. Contact electrodes 110R and 110L are formed on the insulating film 111 by forming, for example, a metal material mainly made of tungsten on the insulating film 111 (FIG. 5G). Through the above steps, the semiconductor device 100 is formed.

  In the conventional LDMOS semiconductor device, the parasitic NPN transistor 121 (FIG. 2) precedes the parasitic PNP transistor 120 (FIG. 2) due to variations in impurity concentration and the positional relationship between layers such as the P + layer and the n + layer. There was a case to work. When the parasitic NPN transistor 121 operates first, the electric field is concentrated at the end of the n + layer below the drain electrode, and the LDMOS is destroyed due to secondary breakdown due to thermal runaway. In contrast, according to the semiconductor device 100 of the present embodiment, the base resistance value of the parasitic PNP transistor 120 is increased by forming the p-type adjustment layer 107 in the n-type epitaxial layer 103 below the p + layer 109R. As a result, the potential between the base and the emitter of the parasitic PNP transistor 120 is raised before the parasitic NPN transistor 121 operates, and the parasitic PNP transistor 120 is operated before the parasitic NPN transistor 121. As a result, holes are injected into the n-type epitaxial layer 103, the conductivity in the vicinity of the n + layer 108R can be lowered, and the electric field generated by ESD is distributed over a wide range without concentrating on a part of the n + layer 108R. The destruction of the semiconductor device 100 can be prevented.

  The present embodiment is an example in the case of an n-type LDMOS, and is an example in which a p-type adjustment layer 107 is formed in an n-type epitaxial layer 103, but in the case of a p-type LDMOS, that is, a p-type. Even when an n-type adjustment layer is formed on the epitaxial layer, the effects as described above can be obtained. In the case of the p-type LDMOS, the p-type adjustment layer 107 shown in FIG. 1 is not formed, and the n-type adjustment layer is disposed below the n + layer 108R to face the n + layer 108R. Form inside.

<Second embodiment>
FIG. 6 is a cross-sectional view of the semiconductor device 200 of this embodiment. Differences from the first embodiment will be mainly described. The semiconductor device 200 is a high voltage Nch type MOSFET.

  The n + layer 108L and the p + layer 109L are formed on the surface of the p-type (hereinafter referred to as the first conductivity type) semiconductor substrate 201 on the source side of the semiconductor device 200, but the p-type body region is formed. It has not been. An n-type (hereinafter referred to as second conductivity type) drain drift layer 203 is formed on the surface of the p-type semiconductor substrate 201 on the drain side. , N + layer 108R, p + layer 109R, and p-type adjustment layer 207 are formed.

  The p-type adjustment layer 207 is formed by sandwiching a part of the n-type drain drift layer 203 between the p + layer 209R. Hereinafter, a portion of the n-type drain drift layer 203 existing between the p-type adjustment layer 207 and the p + layer 209R is referred to as a drain current path 203r. The concentration of the drain current path 103r is, for example, 2.0E16 / cm 3, and the concentration of the p-type adjustment layer 107 is higher than that.

  Hereinafter, a method for manufacturing the semiconductor device 200 will be described. First, the LOCOS oxide film 204 is formed on the surface of the p-type semiconductor substrate 201, and then, for example, phosphorus is ion-implanted into the p-type semiconductor substrate 201 to form the n-type drain drift layer 203. Next, a gate oxide film 205s is formed on the surface of the p-type semiconductor substrate 201, and a gate electrode 205 made of N + type phosphorus-doped polycrystalline silicon is formed on the gate oxide film 205s.

  Next, a resist (not shown) is formed in a region extending from the gate electrode 205 to the source side and in a partial region on the drain side, and ions such as boron are implanted into the n-type drain drift layer 203 using the resist as a mask. Thus, the p-type adjustment layer 207 is formed. At this time, the ion implantation of the p-type adjustment layer 207 is performed so that the p-type adjustment layer 207 is formed with a part of the n-type drain drift layer 203 sandwiched between the p + layer 209R formed in a later step. Set the acceleration voltage. As a result, a drain current path 203r is formed between the p-type adjustment layer 207 and the p + layer 209R. The concentration of the drain current path 203r is, for example, 2.0E16 / cm 3, and ion implantation is performed so that the concentration of the p-type adjustment layer 207 is higher. The subsequent manufacturing method is the same as the conventional manufacturing method.

  In the semiconductor device 200 of this embodiment, a p + layer 209R is formed on the surface of the n-type drain drift layer 203 on the drain side for the purpose of having a high ESD tolerance in a high breakdown voltage Nch type MOSFET. In the n-type drain drift layer 203, a p-type adjustment layer 207 is formed with a part of the n-type drain drift layer 203 sandwiched between the p + layer 209R.

  By forming the p-type adjustment layer 207, the base resistance of the parasitic PNP transistor (consisting of the p + layer 209R, the n-type drain drift layer 203, the p + layer 209L, and the p-type body region 209L) is controlled, and the parasitic NPN transistor (n + layer) 208L, consisting of the p-type semiconductor substrate 201, the n-type drain drift layer 203, and the n + layer 208R), the potential between the base and the emitter of the parasitic PNP transistor is raised to make the parasitic PNP transistor a parasitic NPN. Operate before the transistor.

  As a result, holes are injected into the drain current path 203r, the conductivity in the vicinity of the n + layer 208R can be lowered, and the electric field generated by ESD is distributed over a wide range without being concentrated on a part of the n + layer 208R. Destruction of the device 200 can be prevented. Note that the position, size, and shape of the p-type adjustment layer 207 are not limited to those shown in FIG.

  The present embodiment is an example in the case of an nch type MOSFET, and is an example in which a p type adjustment layer 207 is formed in an n type drain drift layer 203. Even when an n-type adjustment layer is formed in the drain drift layer, the above-described effects can be obtained. In the case of a pch-type MOSFET, the p-type adjustment layer 207 shown in FIG. 6 is not formed, and the n-type adjustment layer is opposed to the n + layer 208R below the n + layer 208R to form the p-type drain drift layer 203. Form inside.

100, 200 Semiconductor device 101 p-type semiconductor substrate 102 n + type buried layer 103 n-type epitaxial layer 104 LOCOS oxide film 105 gate electrode 106 p-type body region 107 p-type adjustment layer 108R, 108L n + layer 109R, 109L p + layer 110R, 110L Contact electrode 111 Insulating film 120 Parasitic PNP transistor 121 Parasitic NPN transistor

Claims (8)

A first conductivity type semiconductor layer;
An oxide film formed on the semiconductor layer so as to protrude from the surface of the semiconductor layer;
On the semiconductor layer, a gate electrode formed across the oxide film,
A drain electrode and a source electrode respectively formed on the surface of the semiconductor layer at a position sandwiching the gate electrode;
A drain-side p + layer and an n + layer connected to the drain electrode and formed in the semiconductor layer;
A source-side p + layer and an n + layer connected to the source electrode and formed in the semiconductor layer;
A body layer of a second conductivity type formed in the semiconductor layer so as to surround the source side p + layer and the n + layer,
A second conductivity type adjustment layer formed at least inside the semiconductor layer so as to be separated from the layer of the same type as the second conductivity type in the drain side p + layer and the n + layer and facing the layer; A semiconductor device including the semiconductor device.   The semiconductor device according to claim 1, wherein the first conductivity type is an N type, and the second conductivity type is a P type. A first conductivity type semiconductor layer;
An oxide film formed on the semiconductor layer so as to protrude from the surface of the semiconductor layer;
On the semiconductor layer, a gate electrode formed across the oxide film,
A drain electrode and a source electrode respectively formed on the surface of the semiconductor layer at a position sandwiching the gate electrode;
A drain-side p + layer and an n + layer connected to the drain electrode and formed in the semiconductor layer;
A source-side p + layer and an n + layer connected to the source electrode and formed in the semiconductor layer;
A drain drift layer of a second conductivity type formed in the semiconductor layer so as to surround the drain side p + layer and the n + layer,
A first conductivity type adjustment layer formed at least inside the semiconductor layer so as to be separated from the same type as the first conductivity type of the drain side p + layer and n + layer and facing the layer; A semiconductor device including the semiconductor device.   4. The semiconductor device according to claim 3, wherein the first conductivity type is a P-type, and the second conductivity type is an N-type. An oxide film forming step of forming an oxide film protruding from the surface of the semiconductor layer on the first conductivity type semiconductor layer;
A gate electrode forming step of forming a gate electrode on the semiconductor layer across the oxide film;
A body layer forming step of forming a second conductivity type body layer on the surface of the semiconductor layer on one side of the gate electrode;
A p + layer n + layer forming step of forming a source side p + layer and an n + layer in the body layer and forming a drain side p + layer and an n + layer in the semiconductor layer on the other side of the gate electrode. A manufacturing method comprising:
An adjustment that forms a second conductivity type adjustment layer in the semiconductor layer at a distance from the same layer as the second conductivity type in at least the drain-side p + layer and the n + layer and facing the layer. the semiconductor device manufacturing method characterized by comprising a layer forming step between the p + layer n + layer formation step and the body layer forming step.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the first conductivity type is an N type, and the second conductivity type is a P type. An oxide film forming step of forming an oxide film protruding from the surface of the semiconductor layer on the first conductivity type semiconductor layer;
A gate electrode forming step of forming a gate electrode on the semiconductor layer across the oxide film;
A drain drift layer forming step of forming a drain drift layer of a second conductivity type on the surface of the semiconductor layer on one side of the gate electrode;
A p + layer n + layer forming step of forming a drain side p + layer and an n + layer in the drain drift layer and forming a source side p + layer and an n + layer in the semiconductor layer on the other side of the gate electrode. A device manufacturing method comprising:
Adjustment that forms an adjustment layer of the first conductivity type in the semiconductor layer at least away from the same type as the first conductivity type of the drain side p + layer and n + layer and facing the layer. the semiconductor device manufacturing method characterized by comprising a layer forming step between the p + layer n + layer formation step and the drain drift layer formed step.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the first conductivity type is P-type, and the second conductivity type is N-type.

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