JP5526965B2 - Power supply control device and failure detection method - Google Patents

Description

  The present invention relates to a power supply control device that uses a switching element to control power supply to a connected load, and can detect a failure of any of the plurality of switching elements by using a plurality of switching elements in parallel. The present invention relates to a power supply control device and a failure detection method in the power supply control device.

  A switching element using a semiconductor is used as a device for controlling power feeding to a device (load). At this time, it is necessary to take measures to prevent overcurrent to the switching element and the load. There may be a protection function that detects an abnormality based on the temperature around the switching element or the amount of current and automatically turns off the switching element when the abnormality is detected. For example, an IPS (Intelligent Power Switch) device incorporating a FET (Field Effect Transistor) and a protection function may be used.

  As a protection element, for example, Patent Document 1 has a function of detecting a load current flowing from a semiconductor switch to a load, and determining whether or not there is an abnormality using the detected current value and a temperature equivalent value calculated from the current value. A power supply apparatus is disclosed.

JP 2009-142146 A

  As shown in the device disclosed in Patent Document 1, a method of detecting an abnormality in a switching element based on a current value flowing to a load by feeding is common.

  However, when the amount of current flowing to the load is relatively large, when a configuration is employed in which a plurality of switching elements are used in parallel to reduce the amount of heat generated, even if one switching element fails, the other If the switching element is normal, the amount of current flowing to the load is the same as that before the failure, so an abnormality cannot be detected.

  In the case where a plurality of switching elements are used in parallel, when only one of them fails and the other is normal as described above, current concentrates on the normal switching elements and the power supply device itself ignites. there is a possibility. Therefore, in the case of the configuration used in parallel, it is necessary to detect even if only one of them fails.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a power supply control device and a failure detection method capable of detecting a failure in any one of a plurality of switching elements in parallel. To do.

A power supply control device according to the present invention is a power supply control device that is interposed between a DC power supply and a load and controls power supply to the load. A plurality of switching devices connected in parallel between one terminal of the power supply and the load an element, and control means for each control on / off of the plurality of switching elements, a measuring means for measuring the voltage value at the load side terminal of the plurality of switching elements, before Symbol plurality of switching elements, the control all from the oN state by means, when being off to each other at different time points, and respectively when being turned off at the same time, by measuring the voltage value by said measuring means, each time point obtained by measuring based on the voltage value at, and a detection means for detecting a failure of any of the plurality of switching elements, said control means, said switch after measurement by said measuring means All grayed element as back on, further, the period of each switching element is off and said Citea Rukoto to be shorter than the allowable interruption time of the load.

In the power supply control device according to the present invention, the switching element is an FET.

Fault detection knowledge method according to the present invention is interposed between the DC power source and a load, the power supply control apparatus for controlling the power supply to the load, in parallel a plurality of switching elements between the one terminal and the load of the power supply A method of detecting a failure of any of the plurality of switching elements when connected, wherein the plurality of switching elements are individually turned on at different points in time from the state in which all the switching elements are turned on . is off for a short period than allowable interruption time, the voltage value at the load side terminal of the plurality of switching elements when being turned off individually to each measurement, the plurality of switching elements allowable instantaneous of the load a short period only turned off at the same time than the interruption time by measuring the voltage value at the load side terminal of the plurality of switching elements while being turned off at the same time, the plurality of switching elements all Back to on, based on the voltage values each measured, and detecting a failure of any of the plurality of switching elements.

In the present invention, a plurality of switching elements are connected in parallel in a power supply control device that is interposed between a DC power supply and a load and controls on / off of power feeding to the load, and each switching element is different. Each switching element fails based on the voltage value at the load-side terminal of the switching elements connected in parallel at the time of turning off each at the timing and while turning off all at the same time Is detected.
Even when a plurality of switching elements are individually turned off, the voltage values from the DC power source should be maintained by the switching elements that are on because they are connected in parallel. Can be detected. Since the failure is detected by measuring the voltage value, the failure can be detected without affecting the power to the load.
In the present invention, for example, an FET is used as the switching element. And it is preferable that the capacitance of each FET is sufficient to withstand the amount of current to the load.

  In the present invention, the period during which the switching elements are turned off separately and the period during which the switching elements are simultaneously turned off are shorter than the allowable instantaneous interruption time of the load. As a result, even when power is being supplied to the load by the power supply control device, it is possible to detect a failure without affecting the load. There is no need to turn off each load to detect a failure.

  In the case of the present invention, the switching elements are connected in parallel and used to reduce the amount of current in each switching element to reduce the amount of heat generation, and further, at the point of time when each of the terminals on the load side is turned off. By measuring and using the voltage value, it is possible to individually detect the failure of each switching element.

2 is a block diagram illustrating a configuration of a power supply control system and an internal configuration of a power supply control device according to Embodiment 1. FIG. 3 is a time chart of a gate voltage controlled by a switch control circuit based on control from a control unit in the first embodiment. 6 is an explanatory diagram illustrating an example of the content of a criterion for failure detection by a control unit in Embodiment 1. FIG. 6 is a time chart of a gate voltage controlled by a switch control circuit based on control from a control unit in the second embodiment. 10 is an explanatory diagram illustrating an example of the content of a criterion for failure detection by a control unit according to Embodiment 2. FIG. 10 is a time chart of a gate voltage controlled by a switch control circuit based on control from a control unit in the third embodiment. 10 is an explanatory diagram illustrating an example of the content of a criterion for failure detection by a control unit according to Embodiment 3. FIG.

Hereinafter, the present invention will be specifically described with reference to the drawings showing embodiments thereof.
In the following embodiments, an example in which the power supply control device according to the present invention is used in a power supply control system that performs power supply control of a vehicle-mounted load mounted on a vehicle will be described.

(Embodiment 1)
FIG. 1 is a block diagram showing the configuration of the power supply control system and the internal configuration of the power supply control device according to the first embodiment. The power supply control system includes a battery 1, a fuse (fuse box) 2 connected to the battery 1, and a power supply control device 3 that controls power supply from the battery 1 to a load 4 to be subjected to power supply control. The positive voltage side (+ B) of the battery 1 is connected to the power supply control device 3 via the fuse 2, and the load 4 is connected to the power line connected to the power supply control device 3. The load 4 is a plurality of ECUs (Electronic Controller Units) that receive power from the power source. Each ECU is connected to the power line in a bus shape, and power supply is controlled as a whole by the power supply control device 3.

  The power supply control device 3 includes a control unit 30 using a CPU (Central Processing Unit), a switch unit 33 in which two FETs 31 and 32 are connected in parallel, and a switch control circuit 34 that controls the gate voltages of the FETs 31 and 32. And a voltage measurement circuit 35 that measures the output voltage from the switch unit 33.

  The control unit 30 uses a CPU to read and execute a control program stored in the built-in ROM, thereby controlling on / off of the FET 31 and the FET 32. The control unit 30 is not limited to a configuration using a CPU alone, and may be a microcomputer.

  An ACC signal and an IGON / IGOFF signal from an accessory switch and an ignition switch (not shown) are input to the control unit 30. The controller 30 further receives a signal from a battery sensor that measures the remaining amount of the battery 1. The control unit 30 executes switch control processing based on signals from these switches and sensors, and outputs a control signal for controlling on / off of the FET 31 and FET 32 to the switch control circuit 34. Basically, the control unit 30 turns on both the FET 31 and the FET 32 when starting the power supply to the load 4 and turns off both when stopping the power supply. Further, the control unit 30 receives a signal from the voltage measurement circuit 35, and executes a failure detection process described later based on the voltage measurement result indicated by the signal.

  The switch unit 33 includes an FET 31 and an FET 32 connected in parallel. In the first embodiment, the drains of the two FETs 31 and 32 are both connected to the positive side (fuse 2) of the battery 1 and the source is connected to the load 4. The drain may be connected to the load 4 and the source battery 1.

  The switch control circuit 34 controls the gate voltages of the FET 31 and the FET 32 of the switch unit 33 based on a control signal from the control unit 30.

  The voltage measurement circuit 35 measures the voltage value between the switch unit 33 and the load, that is, the source voltage of the FET 31 and the FET 32 and notifies the control unit 30 of the voltage value.

  In the power supply control device 3 configured as described above, the control unit 30 executes a failure detection process for the switch unit 33. The control unit 30 determines whether one or both of the FET 31 and the FET 32 of the switch unit 33 are out of order periodically (for example, once a minute) during power supply to the load 4 by the power supply control device 3. . The control unit 30 causes the switch control circuit 34 to instantaneously interrupt the FET 31 and the FET 32 at different timings and at the same timing by a specific method to be described later, and measures the voltage at each timing by the voltage measurement circuit 35 to detect a failure. Detect.

  And the control part 30 which performs a failure detection process raises an alarm, when the failure of either or both of FET31 and FET32 is detected. Specifically, the control unit 30 outputs an instruction signal to alarm means including a speaker and a lamp (not shown), emits a warning sound to the driver through the speaker, and notifies the driver of a short circuit occurrence warning through the lamp. Configure.

  Details of the failure detection method using the switch control circuit 34 and the voltage measurement circuit 35 by the control unit 30 will be described.

  FIG. 2 is a time chart of the gate voltage controlled by the switch control circuit 34 based on the control from the control unit 30 in the first embodiment. FIG. 2 shows the time axis on the horizontal axis and the H (High) / L (Low) of the gate voltage on the vertical axis.

  When the period arrives, the control unit 30 reduces the gate voltages of the FET 31 and the FET 32 to Low for a very short time and turns them off, and whether the voltage value measured by the voltage measurement circuit 35 is High or Low during that period. Judging.

As shown in FIG. 2, the control unit 30 switch control circuit 34 turns off as Low for a period of a gate voltage t _w1 of FET 31, during the period of t _w1, similarly the gate voltage of FET32 so overlapping t _Set to Low only for the period of _w1 . Note that the length of the period in which the gate voltage of the FET 31 is low and the period in which the gate voltage of the FET 21 is low need not be the same at t _w1 . However, the period t _w1 , that is, the length of the period during which the gate voltage of the FET 31 or the FET 32 is set to Low is set to be within 2 milliseconds in the present embodiment in order to make it shorter than the instantaneous interruption allowable time of the load 4. The load 4 must be configured to allow momentary interruption using a reverse connection diode or the like.

Control unit 30, t1 time point during the period in which the gate voltage only has to Low of FET 31, t2 time point during the overlap period of time t _w1 that the Low the FET 31 and FET32 both the gate voltage and the gate voltage of FET32 only The voltage value is measured by the voltage measurement circuit 35 at each time point t3 during the period when the voltage is low. The correspondence between the results obtained by measurement and the detection results is as follows.

  FIG. 3 is an explanatory diagram illustrating a content example of a criterion for failure detection by the control unit 30 in the first embodiment.

  As shown in FIG. 3, when the voltage value measured by the voltage measurement circuit 35 is High at the time t1 during the period when only the gate voltage of the FET 31 is Low, it is determined to be normal. This is because the FET 31 is in the off state at the time t1, but the output voltage should be maintained at High if the FET 32 is normal because the FET 32 is on. On the other hand, when the voltage value measured at the time point t1 is Low, it is determined that the FET 32 is in a failure state while being turned off.

  If the voltage value measured by the voltage measurement circuit 35 is High at the time t2 during the period when the gate voltages of both the FET 31 and the FET 32 are Low, one of the FET 31 and the FET 32 is in the on state and has failed. It is judged that This is because both the FET 31 and the FET 32 should be turned off at the time t2, and the output voltage should be low. Of course, when the voltage value measured at the time point t2 is Low, it is determined to be normal because it is in a state to be achieved.

  When the voltage value measured by the voltage measurement circuit 35 is High at time t3 during the period when only the gate voltage of the FET 32 is Low, it is determined to be normal as in the case of the FET 31. On the other hand, when the voltage value measured at the time point t3 is Low, it is determined that the FET 31 is in a failure state while being turned off.

Thus, by configuring the power supply control device 3, it is possible to detect the failure of each of the FET 31 and the FET 32. In addition, since the failure is detected by connecting in parallel and turning off for a time shorter than the allowable instantaneous interruption time and measuring the voltage value during that time, even if power is being supplied from the power supply control device 3 to the load 4, It is possible to detect a failure without affecting it.
According to the present invention, a failure can be detected without using an element for detecting the amount of heat generated in each FET 31 and FET 32, but failure prediction based on these temperatures may also be used.

(Embodiment 2)
In the second embodiment, the details of the failure detection method by the control unit 30 are different from the method in the first embodiment. That is, the periods during which the FET 31 and the FET 32 are turned off are different. Hereinafter, the same reference numerals are assigned to components shared with the first embodiment, and detailed description thereof is omitted.

  FIG. 4 is a time chart of the gate voltage controlled by the switch control circuit 34 based on the control from the control unit 30 in the second embodiment. 4 shows the time axis on the horizontal axis and the H / L of the gate voltage on the vertical axis, as in FIG. 2 of the first embodiment.

As illustrated in FIG. 4, the control unit 30 repeats twice that the switch control circuit 34 turns off the gate voltages of the FET 31 and the FET 32 as Low for the period of t _w2 . In this case, the control unit 30 includes a second period t _w2 of the gate voltage and Low of FET 31, thereby controlling so as to coincide with the first period t _w2 to Low gate voltage of the FET 32. Thereby, only one side can be turned on (or off) and both can be turned off.

Even the second embodiment, a period of a Low gate voltage of the FET 31, the length of the period for the Low gate voltage of FET21 may or may not be the same at t _w2. However, the length of time t _w2 to Low gate voltage of FET31 or FET32, since shorter than short break allowable time any load 4, in the present embodiment is as within 2 milliseconds. The load 4 must be configured to allow momentary interruption using a reverse connection diode or the like.

Control unit 30, t4 time point during the period t _w2 of the gate voltage only has to Low of FET 31, t5 time points during the overlap period t _w2 that the Low the FET 31 and FET32 both the gate voltage and the gate voltage of FET32 only The voltage value is measured by the voltage measurement circuit 35 at each time point t6 in the period _tw2 in which is set to Low. The correspondence between the results obtained by measurement and the detection results is as follows.

  FIG. 5 is an explanatory diagram illustrating a content example of a criterion for failure detection by the control unit 30 according to the second embodiment.

  As shown in FIG. 5, when the voltage value measured by the voltage measurement circuit 35 is High at time t4 during the period when only the gate voltage of the FET 31 is Low, it is determined to be normal. This is because the FET 31 is in the OFF state at the time t4, but the output voltage should be maintained at High if the FET 32 is normal because the FET 32 is ON. On the other hand, when the voltage value measured at the time point t4 is Low, it is determined that the FET 32 is in a failure state while being turned off.

  If the voltage value measured by the voltage measurement circuit 35 is High at time t5 during the period when the gate voltages of both the FET 31 and the FET 32 are Low, one of the FET 31 and the FET 32 has failed while being on. It is judged that This is because both the FET 31 and the FET 32 should be turned off at the time t5, and therefore the output voltage should be low. Of course, when the voltage value measured at time t5 is Low, it is determined to be normal because it is in a state to be achieved.

  When the voltage value measured by the voltage measurement circuit 35 is High at time t6 during the period when only the gate voltage of the FET 32 is Low, it is determined to be normal as in the case of the FET 31. On the other hand, when the voltage value measured at the time point t6 is Low, it is determined that the FET 31 is in a failure state while being turned off.

  Thus, by configuring the power supply control device 3, it is possible to detect the failure of each of the FET 31 and the FET 32. In addition, since the failure is detected by connecting in parallel and turning off for a time shorter than the allowable instantaneous interruption time and measuring the voltage value during that time, even if power is being supplied from the power supply control device 3 to the load 4, An actual failure can be detected without affecting it.

(Embodiment 3)
In the first and second embodiments, the two FETs 31 and 32 are connected in parallel to detect each failure. However, the present invention is not limited to this, and a configuration using three or more FETs may be used. Embodiment 3 shows an example of a failure detection method when three FETs are connected in parallel.

  The third embodiment is different from the method in the first embodiment in that the internal structure of the switch unit using three FETs is a parallel connection of three FETs and the details of the failure detection method by the control unit 30 associated therewith. Therefore, the illustration and detailed description of the internal configuration of the power supply control device are omitted, and the same reference numerals are given to the components shared with the first embodiment, and the third embodiment will be described below.

  FIG. 6 is a time chart of the gate voltage controlled by the switch control circuit 34 based on the control from the control unit 30 in the third embodiment. 6 shows the time axis on the horizontal axis and the H / L of the gate voltage on the vertical axis, as in FIG. 2 of the first embodiment.

As shown in FIG. 6, the control unit 30 controls the gate voltages of the three FETs (FET 31, FET 32, and third FET) by the switch control circuit 34, respectively, and turns them off as a period of _tw3. Is repeated three times to create a period in which only the FET 31 is in the on state, a period in which only the FET 32 is in the on state, a period in which only the third FET is in the on state, and a period in which all are off.

Also in the third embodiment, the lengths of the periods during which the gate voltages of the three FETs are set to Low do not have to be the same at _tw3 , and each length is made shorter than the instantaneous interruption allowable time of the load 4.

Control unit 30, t7 time point during the period t _w3 only FET31 is turned on (gate voltage is High), t8 time points during the period t _w3 only FET32 is turned on (gate voltage is High), and third Only at the time t9 during the period _tw3 when only the FETs are on (gate voltage is high) and at the time t10 during the period _tw3 when all three FETs are off (gate voltage is low). The voltage value is measured by the measurement circuit 35. The correspondence between the results obtained by measurement and the detection results is as follows.

  FIG. 7 is an explanatory diagram illustrating a content example of a criterion for failure detection by the control unit 30 in the third embodiment.

  As shown in FIG. 7, when the voltage value measured by the voltage measurement circuit 35 is High at time t7 during the period when only the gate voltage of the FET 31 is High, all three FETs are in this stage. Is judged normal. On the other hand, when the voltage value measured at the time t7 is Low, it is determined that the FET 31 is in a failure state while being turned off.

  Similarly, for the FET 32 and the third FET, it is possible to determine whether the FET 32 is normal or an off-failure based on the voltage values at the time t8 and the time t9.

  If the voltage value measured by the voltage measurement circuit 35 is High at time t10 during the period when the gate voltages of all three FETs are Low, one of the FETs is faulty while being on. It is judged. This is because at the time of t10, all three FETs should be turned off and the output voltage should be low. Of course, when the voltage value measured at the time t10 is Low, it is determined to be normal because it is in a state to be achieved.

  In this way, even in the configuration using three or more FETs, any failure is caused by measuring the voltage value when only one of the control units 30 is in the on state (or off state). Can be detected.

  The disclosed embodiments are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 Battery (Power)
3 Power supply control device 30 Control unit (control means, detection means)
31, 32 FET (switching element)
33 Switch part 35 Voltage measurement circuit

Claims (3)

In a power supply control device that is interposed between a DC power supply and a load and controls power supply to the load,
A plurality of switching elements connected in parallel between one terminal of the power source and the load;
Control means for controlling each on / off of the plurality of switching elements;
Measuring means for measuring a voltage value at a load-side terminal of the plurality of switching elements;
Before SL plurality of switching elements, all from the ON state by the control means, when it is off to each other at different time points, and measuring a voltage value by each, said measuring means when being turned off at the same time And detecting means for detecting a failure of any of the plurality of switching elements based on the voltage value at each time point obtained by measurement ,
The control means is configured to return all the switching elements to ON after measurement by the measurement means, and further, the period during which each switching element is OFF is shorter than the allowable instantaneous interruption time of the load. A power supply control device. The power supply control device according to claim 1, wherein the switching element is an FET. A power supply control apparatus that is interposed between a DC power supply and a load and controls power supply to the load, and when a plurality of switching elements are connected in parallel between one terminal of the power supply and the load A method for detecting any failure in an element,
Wherein the plurality of switching elements, all the on state, the separately at different times, then off for a short period than allowable interruption time of the load,
The voltage value at the load side terminal of the plurality of switching elements when being turned off individually to each measurement,
Simultaneously turning off the plurality of switching elements for a period shorter than an allowable instantaneous interruption time of the load ;
Measure the voltage value at the load side terminals of the plurality of switching elements while being simultaneously turned off,
Turning all of the plurality of switching elements back on;
A failure detection method comprising detecting a failure of any of the plurality of switching elements based on each measured voltage value.

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