JP5525791B2 - Battery charging system - Google Patents

Description

  The present invention relates to a battery charging system.

  This application claims priority to US Provisional Application No. 61 / 195,778 “Battery Charging Systems”, filed Oct. 9, 2008, which is incorporated herein by reference in its entirety.

  In general, a conventional battery charge system such as a Li-Ion battery charge system has three charge periods: a precharge period, a constant current (CC) charge period, and a constant voltage (CV) charge period. FIG. 1 illustrates a charge profile 100 of a conventional battery charge system over three periods.

  As shown in FIG. 1, the charge profile 100 includes a battery cell charge current profile 102 and a battery cell voltage profile 104. The charge current profile 102 varies with the voltage profile 104 during the three charge periods described above. During the precharge period, the battery cell is charged with a small precharge current as shown in the charge current profile 102, and the battery cell voltage can increase slowly as shown in the voltage profile 104. When the battery cell voltage reaches the CC mode voltage threshold indicated in the voltage profile 104, the battery charge system transitions to the CC charge period. During the CC charging period, the battery cell is charged with a constant current as shown in the charge current profile 102, and the battery cell voltage can increase rapidly as shown in the voltage profile 104. When the battery cell voltage increases to the CV mode voltage threshold indicated in the voltage profile 104, the battery charge system transitions to a CV charge period. During the CV charge period, the battery cell is charged with a gradually decreasing current as shown in the charge current profile 102 while keeping the voltage of the battery cell constant at a value equal to the voltage threshold of the CV mode. Can be done.

The power loss of the charge switch in the battery charge system can be expressed by the formula I _CC * (V _IN −V _BATT ). Here, I _CC is a constant current, and (V _IN −V _BATT ) is a voltage difference between a power supply voltage such as an alternating current (AC) voltage adapter or a universal serial bus (USB) port and a battery cell voltage. ing. In a battery charging system using a linear charger, when the battery cell voltage is relatively low, the value of I _CC * (V _IN −V _BATT ) is relatively high, and therefore, a thermal issue occurs during the CC charging period. ) May occur. This thermal problem may trigger a thermal protection mechanism of the battery charge system that stops charging until the temperature of the battery charge system has cooled sufficiently. Under some circumstances, the battery charge system stops charging after a relatively short period of time. This in turn causes the battery charge system to cause rapid vibrations between charging and not charging, reducing the efficiency of the battery charging system.

  In one configuration of the present invention, a circuit for charging a battery includes a switch capable of managing a current flowing through the switch, and a first amplifier coupled to the switch, wherein the first amplifier includes: The current can be adjusted according to the amount of power loss associated with the switch.

  The features and advantages of embodiments of the claimed subject matter will become apparent as the following detailed description proceeds, and by reference to the drawings. The same reference numbers indicate the same parts.

1 illustrates a charge profile for a conventional battery charge system. It is a block diagram of an example of the battery charge system in one embodiment of the present invention. It is a block diagram of an example of the battery charge system in other embodiments of the present invention. FIG. 3 illustrates a charge profile for a battery charge system in one embodiment of the present invention. FIG. 6 illustrates a flowchart performed by a battery charge system in one embodiment of the present invention. FIG. 6 illustrates a flowchart performed by a battery charge system in another embodiment of the present invention.

  Next, an embodiment of the present invention will be described. While the invention will be described in conjunction with these embodiments, it is not intended that the invention be limited to these embodiments. Rather, it covers alternatives, modifications and equivalents within the spirit and scope of the invention as defined by the appended claims.

  Furthermore, numerous specific details are set forth in order to provide an understanding of the present invention in accordance with the following detailed description of the invention. However, it will be understood by those of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure features of the present invention.

  FIG. 2 illustrates a block diagram of a battery charge system 200 for power loss control in one embodiment of the present invention.

In this embodiment, the first reference voltage V _SET is provided to a non-inverting input terminal of an amplifier 202, which is an operational amplifier (OPA), for example. Further, the inverting input terminal and the output terminal of the OPA 202 are respectively coupled to the source terminal and the gate terminal of the transistor 206, which is an NMOS (N-Metal-Oxide-Semiconductor) transistor, for example. In addition, resistor 210 is coupled between the source terminal of NMOS transistor 206 and ground.

Since the inverting input voltage of the OPA 202 is equal to the non-inverting input voltage, the source voltage of the NMOS transistor 206 is equal to the reference voltage V _SET . If the gate current of the NMOS transistor 206 and the inverting input current of the OPA 202 are ignored, the first reference current I _REF1 is generated according to Equation (1).

Here, R ₂₁₀ represents the resistance of the resistor 210.

Further, the second reference voltage V _SET ′ is provided to the non-inverting input terminal of the amplifier 204, which is an operational amplifier (OPA), for example. In one embodiment, the second reference voltage V _SET ′ may be equal to the first reference voltage V _SET . Further, the inverting input terminal and the output terminal of the OPA 204 are respectively coupled to the source terminal and the gate terminal of the transistor 208, which is an NMOS transistor, for example. In addition, resistor 212 is coupled between the source terminal of NMOS transistor 208 and ground.

Similarly, the inverting input voltage of the OPA 204 is equal to the non-inverting input voltage of the OPA 204, so that the source voltage of the NMOS transistor 208 can be equal to the reference voltage V _SET . If the gate current of the NMOS transistor 208 and the inverted input current of the OPA 204 are ignored, the second reference current I _REF2 is generated according to Equation (2).

Here, R ₂₁₂ represents the resistance of the resistor 212.

  In one embodiment, the battery charge system 200 includes a first current mirror comprised of transistors 214 and 216, which are PMOS (P-Metal-Oxide-Semiconductor) transistors, for example. In one embodiment, PMOS transistors 214 and 216 are matched or identical. The first current mirror is coupled between an NMOS transistor 206 and a transistor 218, for example a PNP transistor. The base terminal and collector terminal of PNP transistor 218 are coupled to ground. The battery charge system 200 includes a second current mirror composed of transistors 220 and 222, which are PMOS transistors, for example. In one embodiment, PMOS transistors 220 and 220 are matched or identical. The second current mirror is coupled between an NMOS transistor 208 and a transistor 224, for example a PNP transistor. PNP transistor 224 is cascaded with PNP transistor 218, and the base terminal of PNP transistor 224 is coupled to the emitter terminal of PNP transistor 218. The collector terminal of PNP transistor 224 is coupled to ground.

If the base current of the PNP transistors 218 and 224 is ignored, the current I _REF1 ′ flowing through the PNP transistor 218 is equal to the first reference current I _REF1 . Therefore, the emitter-base voltage V _EB1 of the PNP transistor 218 is given according to the equation (3).

Here, V _T represents, for example, the thermal voltage at a given temperature of each of the PNP transistors 218 and 224. I _S, for example, the base of the PNP transistor 218 and 224 respectively of the PNP transistor - represents the reverse saturation current of the emitter diode.

Similarly, if the base current of the PNP transistor 224 is ignored, the current I _REF2 ′ flowing through the PNP transistor 224 is equal to the second reference current I _REF2 . Therefore, the emitter-base voltage V _EB2 of the PNP transistor 224 is given according to the equation (4).

Since the base terminal of the PNP transistor 218 is coupled to ground and the base terminal of the PNP transistor 224 is coupled to the emitter terminal of the PNP transistor 218, the emitter voltage V _A of the PNP transistor 224 is given by equation (5) Given.

In one embodiment, the battery charge system 200 further comprises a charge current sensor 230, eg, a PMOS transistor, coupled to a charge switch 252, eg, a charge FET (field effect transistor). In one embodiment, the charge FET 252 may be a PMOS transistor. The gate terminal and source terminal of charge FET 252 are coupled to the gate terminal and source terminal of PMOS transistor 230, respectively. Thus, charge FET 252 and PMOS transistor 230 have the same gate-source drive voltage. In one embodiment, PMOS transistor 230 is K times smaller than charge FET 252. Therefore, if the short channel modulation effect can be ignored, the current I _SEN may be K times smaller than the charge current I _CHG . The current I _SEN is given according to equation (6).

  The battery charge system 200 further includes an amplifier 234, for example, an operational transconductance amplifier (OTA) having a transconductance gain. In one embodiment, the transconductance gain of OTA 234 is

Set to The input voltage is provided to the non-inverting input terminal of the OTA 234, and the voltage of the battery cell 258 is provided to the inverting input terminal of the OTA 234. Voltage difference between the voltage of the input voltage and the battery cell 258 can be converted into the bias current _{I DC} by OTA234. The bias current _IDC is given according to equation (7).

Here, _VIN represents an input voltage. V _BATT represents the voltage of the battery cell 258 (in other words, the battery cell voltage).

In one embodiment, transistor 232, for example a PNP transistor, is coupled to PMOS transistor 230 to receive sensing current I _SEN . The base terminal and collector terminal of PNP transistor 232 are coupled to ground. Further, the transistor 236 is, for example, a PNP transistor, for receiving a bias current _{I DC,} and is coupled to OTA234. The PNP transistor 236 is cascaded with the PNP transistor 232, the base terminal of the PNP transistor 236 is coupled to the emitter terminal of the PNP transistor 232, and the base terminal of the PNP transistor 232 is coupled to ground.

Neglecting the base current of PNP transistors 232 and 236, the current flowing through PNP transistor 232 is equal to sensing current I _SEN . Therefore, emitter-base voltage V _EB3 of PNP transistor 232 is given according to equation (8).

Here, _{V T,} for example, represents the thermal voltage at a given temperature in each of the PNP transistor of the PNP transistors 218,224,232, and 236. I _S, for example, the base of the PNP transistor 218,224,232, and 236 respectively of the PNP transistor - represents the reverse saturation current of the emitter diode.

Similarly, ignoring the base current of the PNP transistor 236, the current flowing through the PNP transistor 236 is equal to the bias current _{I DC.} Therefore, emitter-base voltage V _EB4 of PNP transistor 236 is given according to equation (9).

Since the base terminal of the PNP transistor 232 is coupled to the ground, and the base terminal of the PNP transistor 236 is coupled to the emitter terminal of the PNP transistor 232, the emitter voltage V _B of the PNP transistor 236 is given by the equation (10) Is given according to

Where P _CHG is

And represents the power loss of the charge FET 252.

In one embodiment, the battery charge system 200 includes an error amplifier 240, for example an OPA, to keep the power loss P _CHG of the charge FET 252 at a predetermined power loss threshold P _SET . The non-inverting input terminal of OPA 240 is coupled to the emitter terminal of PNP transistor 236, and the inverting input terminal of OPA 240 is coupled to the emitter terminal of PNP transistor 224. _A voltage difference V _DEF1 between the non-inverting input voltage V _B and the inverting input voltage V _A is given according to the equation (11).

Where P _SET is

And represents a predetermined power loss threshold of the battery charge system 200. In one embodiment, the predetermined power loss threshold value P _SET may be programmed by adjusting the resistance of resistor R ₂₁₀ . According to a voltage difference _{V DEF1} OPA240 via the diode 242 to generate a first driving current _{I DRV1} to the charge FET 252.

In one embodiment, the battery charge system 200 also includes an error amplifier 244, eg, OPA, to keep the battery cell voltage V _BATT at a predetermined voltage threshold. In addition, a resistor 248 and a resistor 250 coupled in series are connected between the positive electrode and the negative electrode of the battery cell 258. The non-inverting input terminal of OPA 244 is coupled to the node between resistor 248 and resistor 250. Therefore, the non-inverting input voltage V _C of OPA 244 is given according to equation (12).

Here, R ₂₄₈ represents the resistance of the resistor 248. R ₂₅₀ represents the resistance of the resistor 250. In addition, the reference voltage V _REF is provided to the inverting input terminal of the OPA 244. In one embodiment, the reference voltage V _REF is set according to Equation (13).

Here, V _PRE represents a predetermined voltage threshold value.

Therefore, the voltage difference V _DEF2 between the non-inverting input voltage V _C and the inverting input voltage V _REF is given according to the equation (14).

According to a voltage difference _{V DEF2,} via a diode 246, OPA244 can generate a second drive current _{I DRV2} to the charge FET 252.

In addition, resistor 254 is coupled between the gate terminal and source terminal of charge FET 252. The voltage between the source and gate of the charge FET 252 is approximately equal to the voltage at the resistor 254. A constant current source 256 is coupled in series with the resistor 254 to provide a constant current I _CC to the resistor 254.

When a charger (not shown) is plugged into the battery charge system 200, if the voltage V _BATT of the battery cell 258 is _{below a} predetermined voltage threshold, the voltage difference V _DEF2 is It becomes negative according to 14). Thus, the second drive current _{I DRV2} to the charge FET252 produced by OPA244 is considerably smaller. Therefore, the second drive current I _DRV2 can be ignored. Furthermore, the diode 246 can prevent reverse current flowing to the output terminal of the OPA 244. Therefore, the drive current of the charge FET 252 is not affected by the OPA 244. Charge FET252 is mainly controlled by the first driving current _{I DRV1} output from OPA240. Therefore, the battery cell 258 is charged by the constant power loss control of the charge FET 252.

When the power loss P _CHG of the charge FET 252 is larger than the predetermined power loss threshold value P _SET during the constant power loss charging period, the voltage difference V _DEF1 becomes a positive value according to the equation (11). Accordingly, the first drive current _{I DRV1} output from OPA240 is increased. Since the current I _CC is constant, the voltage drop V ₂₅₄ at the resistor 254 decreases according to equation (15).

Here, R ₂₅₄ represents the resistance of the resistor 254. Since the source-gate voltage of the charge FET 252 is decreased, the charge current I _CHG and the power loss P _CHG are also decreased.

When the power loss P _CHG of the charge FET 252 is lower than the predetermined power loss threshold value P _SET , the voltage difference V _DEF1 becomes a negative value according to the equation (11). Accordingly, the first drive current _{I DRV1} output from OPA240 is decreased. Since the current I _CC is constant, the voltage drop V ₂₅₄ at the resistor 254 increases according to equation (15). As the source-gate voltage of the charge FET 252 increases, therefore, the charge current I _CHG and power loss P _CHG also increase.

As a result, the power loss _PCHG is kept at a substantially constant value. Therefore, no thermal problem occurs in the battery charge system 200 during the constant power loss charge period.

When the battery cell voltage V _BATT approaches the predetermined voltage threshold, the voltage difference V _DEF2 approaches 0 according to the equation (14). Thus, the second drive current _{I DRV2} output from OPA244 is gradually increased, it will not be able to ignore. Therefore, the voltage drop V 254 at resistor ₂₅₄ is given by equation (16).

If the second drive current I _DRV2 is still increasing, the voltage drop V ₂₅₄ decreases. The charge current I _CHG also decreases. The non-inverting input voltage reduced results of _{V B} of OPA240, power dissipation _{P CHG} is reduced. Accordingly, the first drive current _{I DRV1} produced by OPA240 is decreased. While the first driving current _{I DRV1} is reduced, since the second drive current _{I DRV2} is increased, the voltage drop _{V 254} does not increase in spite of the reduction of the first drive current _{I DRV1.} Therefore, when the battery cell voltage V _BATT approaches a predetermined voltage threshold, the first drive current I _DRV1 gradually decreases.

When the battery cell voltage _{V BATT} is greater than or equal to a predetermined voltage threshold, the first drive current _{I DRV1} output from OPA240 it is considerably smaller. Therefore, the first drive current I _DRV1 can be ignored. Furthermore, the diode 242 can prevent reverse current flowing to the OPA 240. Thereafter, the charge FET252 is primarily controlled by the second driving current _{I DRV2} output from OPA244. Therefore, the battery cell 258 is charged under constant voltage control. Therefore, a smooth transition from constant power loss control to constant voltage control is achieved.

When the battery cell voltage V _BATT increases to a predetermined voltage threshold value or more during the constant voltage charging period, the voltage difference V _DEF2 becomes a negative value according to the equation (14). Thus, the second drive current _{I DRV2} produced by OPA244 increases. Since the current I _CC is constant, the voltage drop V ₂₅₄ in the resistor 254 calculated by equation (17) decreases.

Therefore, the source-gate voltage of the charge FET 252 decreases, and therefore the charge current I _CHG decreases. The charge current I _CHG decreases, but the battery cell voltage V _BATT increases more and more slowly. Therefore, battery cell voltage V _BATT is kept approximately equal to predetermined voltage threshold value V _PRE .

In addition, a first drive current _{I DRV1} generated respectively by OPA240 and OPA244 when the second driving current _{I DRV2} almost zero, the voltage drop _{V 254} across resistor 254,

It becomes.

  The input voltage of each charger is a constant value within a voltage range of, for example, 4.5 v to 5.5 v,

Is set equal to the maximum value of the range, for example 5.5 v. Therefore, the charge FET 252 is regulated within a corresponding range.

Advantageously, the battery charge system 200 can perform constant power loss control of the charge FET 252 when the battery cell voltage V _BATT is lower than a predetermined voltage threshold. When the battery cell voltage V _BATT is equal to or greater than a predetermined voltage threshold, the battery charge system 200 can perform constant voltage control of the battery cell 258. For example, when the voltage difference between the input voltage of the power source that is an AC adapter of the USB port and the battery cell voltage is relatively large, the conventional battery charging system is configured to perform a constant current charging period as illustrated in FIG. Thermal problems can occur. Compared to the conventional battery charging system, the battery charging system 200 does not cause a thermal problem during all charging periods even if the voltage difference between the input voltage of the power source and the battery cell voltage V _BATT is relatively large. . Furthermore, the battery charging system 200 may be used for charging over-drained battery cells. When the battery cell voltage V _BATT is relatively low, the charge current is also relatively low due to the precharge of the battery cell 258. In addition, the battery cell voltage _{V BATT} is increased, the charge current is also increased to the power loss _{P CHG} charge FET252 reaches a predetermined power dissipation threshold _{P SET.} Therefore, the overall charge speed is relatively fast.

  FIG. 3 shows a block diagram of an example of a battery charge system 300 with power loss control in accordance with one embodiment of the present invention. Elements having the same reference numerals as in FIG. 2 have similar functions and will not be described again here. FIG. 3 is described in combination with FIG.

In FIG. 3, transistor 318, for example an NPN transistor, is coupled to NMOS transistor 206 to receive reference current I _REF1 . Further, transistor 324, for example an NPN transistor, is coupled to NMOS transistor 208 to receive reference current I _REF2 . The base terminal and collector terminal of the NPN transistor 318 are connected to the input voltage _VIN . The base terminal of the NPN transistor 324 is connected to the emitter terminal of the NPN transistor 318. Therefore, NPN transistor 324 is cascaded with NPN transistor 318. The collector terminal of the NPN transistor 324 is connected to the input voltage _VIN .

The base current of NPN transistors 318 and 324 is negligible. Therefore, the current flowing through the NPN transistor 318 is equal to the first reference current _IREF1 . Therefore, the base-emitter voltage V _BE1 of the NPN transistor 318 is given according to the equation (18).

Here, V _T represents the thermal voltage of each NPN transistor, eg, NPN transistors 318 and 324, at a given temperature in battery charge system 300. I _S, for example, based in each of the NPN transistors are NPN transistors 318 and 324 - represents the reverse saturation current of the emitter diode.

Similarly, the base current of NPN transistor 324 is negligible. Therefore, the current flowing through the NPN transistor 324 is equal to the second reference current _IREF2 . Therefore, the base-emitter voltage V _BE2 of the NPN transistor 324 is given according to the equation (19).

Since the base terminal of the NPN transistor 318 is connected to the input voltage _VIN, and the base terminal of the NPN transistor 324 is connected to the emitter terminal of the NPN transistor 318, the emitter voltage V _A of the NPN transistor 324 is expressed by the equation (20 ).

Where P _SET is

And represents a predetermined power loss threshold of the battery charge system 300. In one embodiment, the predetermined power loss threshold P _SET is programmable by adjusting the resistance of resistor R ₂₁₀ .

In one embodiment, the battery charge system 300 includes a first current mirror comprised of transistors 314 and 316, for example NMOS transistors. In one embodiment, transistors 314 and 316 are matched or identical. The first current mirror is coupled, for example, between a PMOS transistor 230 and a transistor 332 that is an NPN transistor. The base terminal and collector terminal of the NPN transistor 332 are connected to the input voltage _VIN . The battery charge system 300 further includes a second current mirror composed of transistors 320 and 322, which are NMOS transistors, for example. In one embodiment, transistors 320 and 322 are matched or identical. The second current mirror is coupled between the output terminal of the OTA 234 and a transistor 336, for example an NPN transistor. The NPN transistor 336 is cascaded with the NPN transistor 332, and the base terminal of the NPN transistor 336 is connected to the emitter terminal of the NPN transistor 332. The collector terminal of the NPN transistor 336 is connected to the input voltage _VIN .

In the case where the current I _SEN ′ flowing through the NPN transistor 332 is equal to the sensing current I _SEN flowing through the NMOS transistor 314, the base currents of the NPN transistor 332 and the NPN transistor 336 are negligible. Therefore, the base-emitter voltage V _BE3 of the NPN transistor 332 is given according to the equation (21).

Here, V _T represents the thermal voltage of each of the NPN transistors 318, 324, 332, and 336, for example, at a given temperature in the battery charge system 300. I _S, for example, the base of the NPN transistors 318,324,332, and 336 respectively of the transistor - represents the reverse saturation current of the emitter diode.

Similarly, the base current of NPN transistor 336 is negligible. When the current I _DC ′ flowing through the NPN transistor 336 is equal to the bias current I _DC flowing through the NMOS transistor 320, the base-emitter voltage V _BE4 of the NPN transistor 336 is given according to equation (22).

Since the base terminal of the NPN transistor 332 is connected to the input voltage _VIN, and the base terminal of the NPN transistor 336 is connected to the emitter terminal of the NPN transistor 332, the emitter voltage V _B of the NPN transistor 326 is expressed by equation (23). Is given according to

Where P _CHG is

And represents the power loss of the charge FET 252.

In one embodiment, the non-inverting input terminal of OPA 240 is coupled to the emitter terminal of NPN transistor 324. The inverting input terminal of OPA 240 is coupled to the emitter terminal of NPN transistor 336. Therefore, the voltage difference V _DEF1 between the non-inverting input voltage V _B and the inverting input voltage V _A is given according to the equation (24).

According to a voltage difference _{V DEF1,} OPA240, via the diode 242 to generate a first driving current _{I DRV1} to the charge FET 252.

  Accordingly, the battery charge system 300 can utilize the same process of performing constant power loss control of the charge FET 252 and / or performing constant voltage control of the battery cell 258 in the battery charge system 200 of FIG.

  FIG. 4 illustrates a charge profile 400 during the entire charging process in a battery charging system, such as the battery charging system 200 of FIG. 2, according to one embodiment of the present invention. FIG. 4 is described in combination with FIG. The charge profile 400 includes a power loss profile 402 of the charge FET 252, a charge current profile 404 of the battery cell 258, and a voltage profile 406 of the battery cell 258. The power loss profile 402 varies with the charge current profile 404 and the voltage profile 406.

When the charger is plugged into the battery charge system 200, if the voltage V _BATT of the battery cell 258 is lower than a predetermined voltage threshold value V _PRE , the voltage difference V _DEF2 is a negative value according to equation (14). Become. Thus, the second drive current _{I DRV2} output from OPA244 to the charge FET252 is small, thus the second drive current _{I DRV2} is negligible. Therefore, the charge FET252 is primarily controlled by the first driving current _{I DRV1} output by OPA240. Therefore, the battery cell 258 is charged by the constant power loss control of the charge FET 252.

If the battery cell voltage V _BATT is relatively low during the constant power loss charging period, the charge current I _CHG is also set so as to keep the power loss P _CHG of the charge FET 252 substantially equal to the predetermined power loss threshold value P _SET. small. As the battery cell voltage V _BATT increases, the charge current also increases so as to keep the power loss P _CHG approximately equal to the predetermined power loss threshold value P _SET .

When the battery cell voltage V _BATT is close to the predetermined voltage threshold value V _PRE shown in FIG. 4, the voltage difference V _DEF2 approaches zero according to the equation (14). As a result, the second drive current I _DRV2 gradually increases and can no longer be ignored. At the same time, the first drive current _{I DRV1} produced by OPA240 gradually decreases. When the voltage V _BATT of the battery cell 258 approaches the predetermined voltage threshold value V _PRE , the first driving current I _DRV1 decreases until it becomes relatively small and can be ignored. Therefore, the charge FET252 is primarily controlled by the second driving current _{I DRV2} output from OPA244, the battery cell 258 is charged under the constant voltage control.

During the constant voltage charging period, the charging current I _CHG gradually decreases to zero. Therefore, the battery cell voltage V _BATT increases more and more slowly. Therefore, battery cell voltage V _BATT is kept approximately equal to predetermined voltage threshold value V _PRE . Since the battery cell voltage V _BATT is substantially constant, at the same time, the power loss P _CHG decreases with the charge current I _CHG .

  FIG. 5 illustrates a flowchart of operations performed by a battery charging system, eg, the battery charging system 200 of FIG. 2, according to one embodiment of the present invention. FIG. 5 is described in combination with FIG.

In block 502, the battery charge system begins generating charge current to the battery, eg, the battery cell 258, via the charge switch 252. If the battery voltage V _BATT is less than the predetermined voltage threshold V _PRE (block 504), the power loss P _CHG of the charge switch 252 is compared to the predetermined power loss threshold P _SET at block 506. At block 508, the charge current I _CHG flowing through the charge switch 252 is adjusted according to the comparison result to keep the power loss P _CHG of the charge switch 252 constant.

In one embodiment, the drive current to charge switch 252 is generated according to the comparison result. When the power loss P _CHG of the charge switch 252 is larger than the predetermined power loss threshold value P _SET , the charge current I _CHG is reduced by the drive current. When the power loss P _CHG of the charge switch 252 is smaller than a predetermined power loss threshold, the charge current I _CHG increases with the drive current.

If the battery voltage V _BATT is equal to or greater than the predetermined voltage threshold V _PRE , the battery voltage V _BATT is compared to the predetermined voltage threshold V _{PRE at} block 510. At block 512, the charge current I _CHG flowing through the charge switch 252 is adjusted according to the comparison result to control (eg, keep constant or substantially constant) the battery voltage V _BATT .

In one embodiment, the drive current is generated to the charge switch 252 according to the comparison result. When the battery voltage V _BATT is greater than the predetermined voltage threshold V _PRE , the charge current I _CHG decreases with the drive current.

  FIG. 6 illustrates a flowchart 600 of a method for comparing a predetermined power loss threshold with a power loss of a charge switch in a battery charge system, eg, the battery charge system 200 in FIG. 2, according to one embodiment of the present invention. Show. FIG. 6 is described in combination with FIG. 5 and FIG.

In block 602, the first current I ₁ varies with the charge current flowing through the charge switch 252 is generated. The first current I ₁ is given by equation (25).

Here, I _CHG represents a charge current flowing through the charge switch 252. K represents a scaling parameter based on the relative sizes of the charge switch 252 and the current sensor 230. In one embodiment, the first current I ₁ is generated by a current sensor 230 (eg, a PMOS transistor) whose source terminal and gate terminal are connected to the source terminal and gate terminal of the charge switch 252 respectively. Since the size of the PMOS transistor 230 is K times smaller than the size of the charge switch 252, the first current I ₁ is K times the charge current I _CHG when the short-channel modulation effect is negligible. small.

At block 604, the voltage at the charge switch 252 is converted to the second current I ₂ by equation (26).

Here, G _m represents a conversion parameter. In one embodiment, the second current I ₂ is generated by an amplifier, such as an OTA 234, coupled between the source and drain terminals of the charge switch 252. The transconductance gain of OTA234 is set to a value of the conversion parameter _{G m.}

In block 606, for example, a first voltage V _EB1 between the emitter and base of the transistor of PNP transistor 232 is generated according to equation (27) according to the first current I ₁ .

Here, V _T1 represents the thermal voltage of the PNP transistor 232 at a given temperature. I _S1 represents the reverse saturation current of the base-emitter diode of the PNP transistor 232.

In block 608, for example, a second voltage V _EB2 between the emitter and base of the transistor of PNP transistor 236 is generated according to equation (28) according to the second current I ₂ .

Here, V _T2 represents the thermal voltage of the PNP transistor 236 at a given temperature. I _S2 represents the reverse saturation current of the base-emitter diode of the PNP transistor 236. I _S2 is equal to I _S1 .

In block 610, for example, a third voltage V _EB3 between the emitter and base of the transistor of PNP transistor 218 is generated according to equation (29) according to the first reference current I _REF1 .

Here, V _T3 represents the thermal voltage of the PNP transistor 218 at a given temperature. I _S3 represents the reverse saturation current of the base-emitter diode of the PNP transistor 218. V _T3 is equal to V _T1 . I _S3 is equal to I _S1 .

In block 612, for example, a fourth voltage V _EB4 between the emitter and base of the transistor of PNP transistor 224 is generated according to equation (30) according to the second reference current I _REF2 .

Here, V _T4 represents the thermal voltage of the PNP transistor 224 at a given temperature. I _S4 represents the reverse saturation current of the base-emitter diode of the PNP transistor 224. V _T4 is equal to V _T1 . I _S4 is equal to I _S1 .

Thereafter, in block 614, the voltage difference V _DIF is calculated according to equation (31).

Where P _CHG is

And represents the power loss of the charge FET 252. P _SET is

And represents a predetermined power loss threshold.

At block 616, the power loss P _CHG of the charge switch 252 is compared to a predetermined power loss threshold P _SET according to the voltage difference V _DIF . When the voltage difference V _DIF is a positive value, the power loss P _CHG of the charge switch 252 is larger than a predetermined power loss threshold value P _SET . When the voltage difference V _DIF is a negative value, the power loss P _CHG of the charge switch 252 is smaller than a predetermined power loss threshold value P _SET .

  Thus, for example, a battery charge system, such as the battery charge systems 200, 300 of FIGS. 2 and 3, will now be described. In one embodiment, the battery charge system includes a charge switch 252 that controls a charge current flowing through the charge switch 252 and a first error amplifier 240 coupled to the charge switch 252. The first error amplifier 240 is used to adjust the charge current so as to keep the power loss of the charge switch 252 relatively constant when the battery voltage is lower than a predetermined voltage threshold. The battery charge system also includes a second error amplifier 244 coupled to the charge switch 252. The second error amplifier 244 is used to adjust the charge current to keep the battery voltage relatively constant when the battery voltage is equal to or greater than a predetermined voltage threshold. Furthermore, the battery charging system may be used to charge a plurality of batteries.

When the battery voltage is lower than a predetermined voltage threshold, the battery cell 258 is charged by the constant power loss control of the charge switch 252. The first error amplifier 240 compares the power loss of the charge switch 252 with a predetermined power loss threshold value, and generates a drive current to the charge switch 252 according to the comparison result of the power loss. When the power loss P _CHG of the charge switch 252 is greater than a predetermined power loss threshold, the charge current I _CHG flowing through the charge switch 252 is reduced by the drive current. When the power loss P _CHG of the charge switch 252 is smaller than a predetermined power loss threshold, the charge current I _CHG flowing through the charge switch 252 increases due to the drive current.

If the battery cell voltage is greater than or equal to a predetermined voltage threshold, the battery cell 258 is charged under constant voltage control. The second error amplifier 244 compares the voltage of the battery with a predetermined voltage threshold value, and generates a drive current to the charge switch 252 according to the voltage comparison result. When the battery cell voltage V _BATT is larger than the predetermined voltage threshold V _PRE , the charge current I _CHG decreases with the drive current.

Advantageously, if the voltage difference between the power supply and the battery cell voltage V _BATT is large, there is no thermal problem in the battery charge system 200 or 300 during the entire charge period. Further, the battery charging system can be used for charging excessively drained battery cells. If the battery voltage is quite low, the charge current is small due to the battery precharge. In addition, when the battery voltage increases, the charge current also increases until the power loss of the charge switch reaches a predetermined power loss threshold. Therefore, the overall charge speed is fast.

  In the present specification, the embodiments are described. However, the embodiments are merely examples, and are not intended to limit the present invention described here. It will be apparent to those skilled in the art that many other embodiments are possible without departing significantly from the spirit and scope of the invention as defined in the appended claims. Further, although elements of the invention have been described in the singular or defined in the claims, the plural is contemplated unless expressly stated to be singular.

V _BATT battery cell voltage V _REF reference voltage V _SET first reference voltage V _SET 'second reference voltage I _CC constant current I _REF1 first reference current I _REF2 second reference current I _DRV1 first drive current I _DRV2 second drive current I _CHG charge current I _SEN sensing current P _CHG charge switch power loss P _SET predetermined power loss threshold V _PRE predetermined voltage threshold 200 battery charge system 202, 204, 240, 244 OPA (amplifier)
234 Operational transconductance amplifier (OTA)
252 Charge switch

Claims (18)

A switch that can manage the current flowing through the switch;
A first amplifier coupled to the switch;
Comprising
Said first amplifier in accordance with the amount of power loss associated with the switch, Ri adjustable der the current,
A circuit component coupled to the first amplifier;
The circuit component is capable of generating a first voltage to the first amplifier;
The first voltage varies with the amount of power loss based on a first current that varies with the current flowing through the switch and a second current that varies with the voltage between the switches,
The first amplifier performs a comparison between the first voltage and a predetermined value, and generates a driving current to the switch according to a result of the comparison;
The circuit components are:
A first transistor;
A second transistor;
Comprising
The first current flows through the first transistor;
The second current flows through the second transistor;
The first transistor and the second transistor generate the first voltage determined by a sum of an emitter-base voltage of the first transistor and an emitter-base voltage of the second transistor, and the first voltage the to enter into the first amplifier, the circuit characterized by that it is connected to each other. The circuit of claim 1, wherein the first amplifier performs a comparison between the amount of power loss and a predetermined value, and generates a drive current to the switch according to a result of the comparison. Further comprising a diode coupled between the first amplifier and the switch;
The circuit of claim 1, wherein the diode is capable of preventing a reverse current from the switch to the first amplifier. Further comprising a current source coupled to the switch;
The circuit of claim 1, wherein the current source is capable of providing the switch with a drive current for managing the current through the switch. Further comprising a transistor coupled to the switch;
The transistor is capable of generating the first current;
Driving voltage of the transistor circuit according to claim 1, characterized in that matching to the driving voltage of the switch. A second amplifier coupled to the switch;
The circuit according to claim 1 , wherein the second amplifier is capable of converting the voltage between the switches into the second current. A method of controlling a switch,
Controlling the current flowing through the switch;
Using an amplifier to regulate the current flowing through the switch according to the amount of power loss associated with the switch;
Generating a first voltage to the amplifier, the first voltage being a first current that varies with the current flowing through the switch and a second current that varies with the voltage between the switches; Varying with the amount of power loss based on, and
The amplifier performs a comparison between the first voltage and a predetermined value;
Generating a drive current to the switch according to the result of the comparison;
Generating the first voltage by controlling the first current through a first transistor and controlling the second current through a second transistor;
Equipped with,
The first transistor and the second transistor generate the first voltage determined by a sum of an emitter-base voltage of the first transistor and an emitter-base voltage of the second transistor, and the first voltage the to enter into the amplifier, the method of controlling the switch, characterized in that it is connected to each other. Performing a comparison between the amount of power loss and a predetermined value;
Generating a drive current to the switch according to the result of the comparison;
The method of controlling a switch according to claim 7 , further comprising: 8. The method of controlling a switch of claim 7 , further comprising preventing reverse current from the switch to the amplifier. Generating a first current using a transistor;
The method of claim 7 , wherein a driving voltage of the transistor matches a driving voltage of the switch. 8. The method of controlling a switch according to claim 7 , further comprising the step of converting the voltage across the switch into the second current. A battery charging system,
A charge switch for managing the charge current to the battery;
A first amplifier coupled to the charge switch;
A second amplifier coupled to the charge switch;
Comprising
The first amplifier can adjust the charge current according to the amount of power loss associated with the charge switch when the battery voltage is lower than a predetermined voltage threshold;
Second amplifier, the voltage of the battery, when it reaches the predetermined voltage threshold, Ri adjustable der the charge current in accordance with said voltage of said battery,
A circuit component coupled to the first amplifier;
The circuit component is capable of generating a first voltage to the first amplifier;
The first voltage varies with the amount of power loss based on a first current that varies with the charge current flowing through the charge switch and a second current that varies with the voltage between the charge switches,
The first amplifier performs a comparison between the first voltage and a predetermined value, and generates a drive current to the charge switch according to a result of the comparison;
The circuit components are:
A first transistor;
A second transistor;
Comprising
The first current flows through the first transistor;
The second current flows through the second transistor;
The first transistor and the second transistor generate the first voltage determined by a sum of an emitter-base voltage of the first transistor and an emitter-base voltage of the second transistor, and the first voltage the to enter into the first amplifier, a battery charging system characterized that it is connected to each other. The battery of claim 12 , wherein the first amplifier performs a comparison between the amount of power loss and a predetermined value, and generates a drive current to the charge switch according to a result of the comparison. Charge system. 13. The second amplifier according to claim 12 , wherein the second amplifier performs a comparison between the voltage of the battery and the predetermined voltage threshold, and generates a drive current to the charge switch according to the comparison. Battery charging system. A diode coupled between the first amplifier and the charge switch;
The battery charge system according to claim 12 , wherein the diode is capable of preventing a reverse current from the charge switch to the first amplifier. A diode coupled between the second amplifier and the charge switch;
The battery charging system according to claim 12 , wherein the diode is capable of preventing a reverse current from the charge switch to the second amplifier. Further comprising a transistor coupled to the charge switch;
The transistor is capable of generating the first current;
The battery charge system according to claim 12 , wherein a drive voltage of the transistor matches a drive voltage of the charge switch. A third amplifier coupled to the charge switch;
The battery charging system according to claim 12 , wherein the third amplifier is capable of converting the voltage between the charge switches into the second current.

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