JP5519745B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a technique effective when applied to a packaging technique in a method for manufacturing a semiconductor integrated circuit device (or a semiconductor device).

  In Japanese Unexamined Patent Publication No. 2007-214237 (Patent Document 1), in a packaging process of a resin-sealed package with few external leads such as a single transistor, a resin burr on a lead is detected by a simple Burr identification method. A technique for solder plating after removal by laser and water jet is disclosed.

In Japanese Patent Application Laid-Open No. 2001-102510 (Patent Document 2), in a packaging process of a resin-sealed package such as an IC package, tie bars are cut after the resin is sealed, and resin burrs between the remaining leads are removed. A technique for solder plating after removal by a CO ₂ laser is disclosed.

  In Japanese Patent Laid-Open No. 2000-299400 (Patent Document 3), a non-leaded flat package is punched with a sealing material between leads in order to prevent a short circuit between leads during mounting. A technique is disclosed in which a metal film that is removed by a mold and the exposed lead is coated with a metal film that enhances solder adherence is disclosed.

JP 2007-214237 A JP 2001-102510 A JP 2000-299400 A

  In mounting a QFN (Quad Flat Non-Leaded Package) type plastic package (see FIG. 28) that requires high reliability such as in-vehicle use, it has become clear that there are the following problems. Since the side surface of the lead 4 is almost covered by the inter-lead resin protrusion 54, the solder fillet is not formed well during reflow mounting. Therefore, if this resin protrusion 54 between leads is mechanically removed by a punching die, there is a problem in the accuracy of the punching die, and there is a high possibility of inducing cracks and terminal deformation of the package body. In order to avoid this, if a space between the punching die and the package body is set, a resin residue is generated, and the inter-resin resin protrusion 54 cannot be completely removed. As a result, the side surfaces of the leads cannot be sufficiently exposed, and the surface treatment for improving the soldering at the time of mounting such as solder plating cannot be performed sufficiently.

  The present invention has been made to solve these problems.

  An object of the present invention is to provide a manufacturing process of a highly reliable semiconductor integrated circuit device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, the present invention relates to a QFN type plastic-encapsulated semiconductor integrated circuit device using a multiple lead frame having a tie bar for bundling the outer ends of a plurality of leads. After the sealing resin filled in between is removed by a laser, surface treatment for improving soldering during mounting such as solder plating is performed.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, in a method of manufacturing a semiconductor integrated circuit device of QFN type plastic sealing using a multiple lead frame having a tie bar for bundling the outer ends of a plurality of leads, the space between the mold cavity outer periphery and the tie bar is filled. After removing the sealing resin with a laser, a sufficient solder layer is formed on the side surface of the lead by performing surface treatment to improve soldering during mounting such as solder plating. The mounting reliability can be improved.

It is a package top view which shows an example of the QFN type package structure of the semiconductor integrated circuit device manufactured by the manufacturing method of the semiconductor integrated circuit device of one embodiment of this invention. It is a package bottom view which shows an example of the package structure of the semiconductor integrated circuit device manufactured by the manufacturing method of the semiconductor integrated circuit device of one embodiment of this invention. FIG. 3 is a package cross-sectional view corresponding to the X-X ′ cross section of FIGS. 1 and 2. 1 is an enlarged top view of a unit device region of a lead frame used in a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention; 1 is an enlarged perspective top view of a unit device region of a lead frame during a process (before a resin sealing body separation process) of a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention; FIG. 5 is an enlarged top view corresponding to nine unit device regions of a lead frame used in the method for manufacturing a semiconductor integrated circuit device of one embodiment of the present invention. 1 is an overall top view of a lead frame used in a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention. 1 is an overall top view of a lead frame during a process (during die bonding) of a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention; 1 is an overall top view of a lead frame in the middle of a process (sealing process completion) of a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention; 1 is a plan circuit layout diagram of an example of a semiconductor chip used in a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention; 1 is a main process block flow diagram of a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention; FIG. 2 is a top view of one element process (sealing step) of a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention (in this top view, the upper mold is removed for easy understanding). It is sectional drawing of the metal mold | die and device corresponding to the A-A 'cross section of FIG. It is sectional drawing of the metal mold | die and device corresponding to the B-B 'cross section of FIG. It is sectional drawing of the metal mold | die and device corresponding to the C-C 'cross section of FIG. 1 is a partially enlarged top view of a unit device region of a lead frame during a process (sealing process completion) of a manufacturing method of a semiconductor integrated circuit device according to an embodiment of the present invention; It is a lead frame partial front view for demonstrating the process in the one-element process (the resin lead part protrusion removal process by a laser) of the manufacturing method of the semiconductor integrated circuit device of one embodiment of this invention. It is sectional drawing of the device corresponding to the D-D 'cross section of FIG. It is a lead frame partial front view for demonstrating the process in the one-element process (electrolytic residual resin removal process) of the manufacturing method of the semiconductor integrated circuit device of one embodiment of this invention. FIG. 20 is a cross-sectional view of the device corresponding to the D-D ′ cross section of FIG. 19. FIG. 20 is another cross-sectional view of the device corresponding to the D-D ′ cross section of FIG. 19. It is a lead frame partial front view for demonstrating the process in the one-element process (water jet residual resin removal process) of the manufacturing method of the semiconductor integrated circuit device of one embodiment of this invention. 1 is a partially enlarged top view of a unit device region of a lead frame in the middle of a process of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention (water jet residual resin removal process completed); 1 is a partially enlarged top view of a unit device region of a lead frame during a process (before cutting a tie bar) of a manufacturing method of a semiconductor integrated circuit device according to an embodiment of the present invention; It is a lead frame partial front view for demonstrating the mode of processing in one element process (tie bar cutting process) of the manufacturing method of the semiconductor integrated circuit device of one embodiment of the invention of this application. It is a fragmentary perspective view of the resin sealing body (semiconductor integrated circuit device package) in the one element process (after resin sealing body isolation | separation process) of the manufacturing method of the semiconductor integrated circuit device of one embodiment of this invention. FIG. 27 is a partial perspective view of a wiring board and a semiconductor integrated circuit device package showing a state when the resin sealing body of FIG. 26 is mounted on the wiring board. It is a whole package perspective view for demonstrating the problem of the conventional QFN type | mold package structure.

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) A lead frame having a plurality of unit device regions, in which a semiconductor chip is fixed in each unit device region, is set in a mold, and each of the semiconductor chips is sealed with a sealing resin, Forming a resin sealing body in the unit device region;
Here, each unit device area includes:
(I) a substantially rectangular die pad to which the semiconductor chip is fixed;
(Ii) a plurality of leads extending from the outside of each side of the die pad so as to form substantially the same plane as the bottom surface of the resin sealing body and projecting from the side surface of the resin sealing body;
(Iii) a tie bar that connects the vicinity of the outer ends of the plurality of leads;
(Iv) An inter-resin resin protrusion that fills between the plurality of leads and protrudes from the side surface of the resin sealing body;
Further, the manufacturing method of the semiconductor integrated circuit device includes the following steps:
(B) After the step (a), the step of removing the inter-resin resin protrusion by irradiating the inter-resin resin protrusion in each unit device region with a laser beam;
(C) After the step (b), forming a solder layer on the exposed surface of the plurality of leads in each unit device region;
(D) After the step (c), the plurality of leads and the tie bars are separated by cutting the outer end portions of the plurality of leads in each unit device region, and the resin sealing is performed. Cutting and separating the body from the lead frame.

  2. In the method of manufacturing a semiconductor integrated circuit device according to the item 1, in the step (b), the resin burrs on the plurality of leads are removed by irradiating the plurality of leads with the laser light.

3. The method for manufacturing a semiconductor integrated circuit device according to the item 1 or 2 further includes the following steps:
(E) A step of performing electrolytic treatment in an aqueous solution with the plurality of leads as cathodes on the surfaces of the plurality of leads after the step (b) and before the step (c).

  4). 4. The method of manufacturing a semiconductor integrated circuit device according to the item 3, wherein a water jet process is performed on the surfaces of the plurality of leads after the step (e) and before the step (c).

  5. 5. In the method for manufacturing a semiconductor integrated circuit device according to any one of items 1 to 4, the sealing in the step (a) is performed by transfer molding.

  6). 6. The method of manufacturing a semiconductor integrated circuit device according to any one of 1 to 5, wherein the laser light is near infrared light.

  7). 7. The method for manufacturing a semiconductor integrated circuit device according to any one of 1 to 6, wherein the laser beam is obtained from a YAG laser.

  8). 8. In the method for manufacturing a semiconductor integrated circuit device according to any one of 1 to 7, the wavelength of the laser beam is 1064 nm.

  9. 9. In the method for manufacturing a semiconductor integrated circuit device according to any one of 1 to 8, the total number of leads protruding from the resin sealing body is 20 or more and 150 or less per sealing body.

  10. 9. In the method of manufacturing a semiconductor integrated circuit device according to any one of 1 to 8, the total number of leads protruding from the resin sealing body is 40 or more and 150 or less per sealing body.

  11. 9. In the method of manufacturing a semiconductor integrated circuit device according to any one of items 1 to 8, the total number of leads protruding from the resin sealing body is 50 or more and 150 or less per sealing body.

  12 12. In the method for manufacturing a semiconductor integrated circuit device according to any one of 1 to 11, the protruding length of the plurality of leads is 0.1 mm or more and 0.5 mm or less.

  13. 12. In the method for manufacturing a semiconductor integrated circuit device according to any one of 1 to 11, the protruding length of the plurality of leads is 0.2 mm or more and 0.4 mm or less.

  14 14. The manufacturing method of a semiconductor integrated circuit device according to any one of 1 to 13, wherein a pitch of the plurality of leads is 0.2 mm or more and 0.8 mm or less.

  15. 15. The method for manufacturing a semiconductor integrated circuit device according to any one of 1 to 14, wherein the resin sealing body has a thickness of 0.3 mm or more and 1.2 mm or less.

  16. 16. In the method for manufacturing a semiconductor integrated circuit device according to any one of 1 to 15, the width of the resin sealing body is 3 mm or more and 10 mm or less.

  17. 17. In the method of manufacturing a semiconductor integrated circuit device according to any one of 1 to 16, the material of the main part of the lead frame is copper as a main component.

  18. 18. In the method of manufacturing a semiconductor integrated circuit device according to 1 to 17, the lead frame has a thickness of 0.1 mm or more and 0.3 mm or less at a thick portion.

  19. 19. In the method for manufacturing a semiconductor integrated circuit device according to any one of items 1 to 18, the solder layer is lead-free.

  20. 20. In the method for manufacturing a semiconductor integrated circuit device according to any one of 1 to 19, the sealing resin is halogen-free.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  2. Similarly, in the description of the embodiment, etc., regarding the material, composition, etc., “X consisting of A” etc. is an element other than A unless specifically stated otherwise and clearly not in context. It is not excluded that one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say.

  In addition, “copper”, “gold”, “epoxy resin”, “tin”, etc. are not particularly limited to pure members, unless explicitly stated otherwise. , Members having these as main constituent elements shall be shown.

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  5. “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor integrated circuit device (same as a semiconductor device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer, an SOI substrate, an LCD glass substrate and the like. Needless to say, a composite wafer such as a semiconductor layer is also included. The wafer divided into individual integrated circuit devices is called a “semiconductor chip” or simply “chip”. In the present application, the semiconductor as the substrate mainly refers to a silicon-based semiconductor, but may be a GaAs-based or other compound-based semiconductor.

  6). The definition of the QFN type plastic package in the present application will be specifically described in the section 1 of the details of the embodiment.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

1. Description of semiconductor integrated circuit device package structure and the like by the method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present application (mainly FIGS. 1 to 3 and FIG. 28)
FIG. 1 is a package top view showing an example of a QFN type package structure of a semiconductor integrated circuit device manufactured by the method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 2 is a package bottom view showing an example of the package structure of the semiconductor integrated circuit device manufactured by the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present invention. FIG. 3 is a package cross-sectional view corresponding to the XX ′ cross section of FIGS. 1 and 2 (corresponding substantially to the XX ′ cross section of FIG. 5). FIG. 28 is a perspective view of the entire package for explaining the problems of the conventional QFN type package structure. Based on these, the package structure of the semiconductor integrated circuit device according to the method of manufacturing a semiconductor integrated circuit device of one embodiment of the present application will be described.

  First, the QFN type plastic package will be described. The QFN type plastic package is a plastic package similar to QFP (Quad Flat Package), but originally, as shown in FIG. 28, the distance from the bottom end of the side surface 2d corresponding to each side of the package top surface 2a is 0. A large number of leads 4 projecting about 1 to 0.5 millimeters are provided, and the gap between them is sealed by an inter-lead resin projecting portion 54. Therefore, there is an advantage that the mounting area can be saved as compared with QFP having leads that extend relatively long from the side surface of the package.

  However, in the state where the side surface of the lead 4 is almost covered with the resin, the solder reflow mounting cannot be performed well. In practice, the inter-lead resin protruding portion 54 is mechanically cut using a punching die or the like. For example, a part or all of the side surface of the lead 4 is exposed. Accordingly, a QFN type plastic package in which the inter-resin resin protrusion 54 is removed by some method will be described below.

  First, the upper surface of the package will be described. As shown in FIG. 1, the upper surface 2a of the package has a substantially rectangular shape (in this case, a substantially square shape). The corner chamfer 2c is octagonal, but the size of the corner chamfer 2c is small compared to the package delivery, so it can be basically seen as a rectangle (square or rectangular). Leads 4 protrude, for example, by about 0.3 mm from the bottom surface end of side surface 2d corresponding to each side of package top surface 2a. A bumper 7 for visual inspection at the time of cooling and mounting projects from the bottom end of the corner chamfer 2c.

  Next, the lower surface of the package will be described. As shown in FIG. 2, the lower surface 3b of the die pad is exposed at the center of the lower surface 2b of the package for heat dissipation. The shape of the lower surface 3b of the die pad is generally almost the same as the planar shape of the package. In this case, the die pad is almost square (generally a rectangle including a rectangle) and has four sides 3d. A part of the suspension lead 9 (lead for suspending the die pad) is exposed in the vicinity of the bumper 7.

  Next, the X-X ′ cross section of FIGS. 1 and 2 will be described. As shown in FIG. 3, the upper surface 3a of the die pad 3 at the center of the bottom surface 2b of the package (resin sealing body) 2 is formed on the semiconductor chip 1 via a silver paste layer (DAF or the like), for example. The back surface 1b is fixed. A lead 4 protrudes from the bottom end of each side surface 2 d of the resin sealing body 2, and a gold wire 6 containing gold as a main component between the bonding pad on the top surface 1 a of the semiconductor chip 1 and the inner end of the lead 4. Connected with. Visible between the lead 4 and the die pad 3 is a bus bar 5. One feature of the QFN type plastic package compared with the QFP is that the lower surface 4b of the lead 4 and the lower surface 2b of the sealing body 2 form substantially the same plane, and the lead 4 has an outer end portion 4d. Until the bottom end of the side surface 2d of the sealing body 2 protrudes substantially linearly. Since the lower surface of the lead frame coincides with the lower surface of the package due to the manufacturing method, the lower surface 3b of the die pad 3 usually constitutes the center of the lower surface 2b of the package.

  Examples of basic dimensions of the package described here are as follows, for example. Lead thickness is about 0.2 mm (preferable range is 0.1 mm or more and 0.3 mm or less), and lead pitch is about 0.5 mm (preferable range is 0.2 mm or more, 0.8 mm) The lead protrusion length (L in FIG. 24) is about 0.3 mm (the preferred range is 0.1 mm to 0.5 mm, and the most preferred range is 0.2 mm to 0.00 mm). 4 mm or less), the package width (width of the sealing body) is about 8 mm (preferably 3 mm or more and 10 mm or less), and the package thickness (thickness of the sealing body) is about 0.8 mm ( A preferable range is 0.3 mm or more and 1.2 mm or less), and the number of leads (number of pins) is about 64 (a useful range when applied is a range of about 20 or more and 150 or less, but 40 More than this is suitable, 5 It is particularly suitable and is) in the above.

2. Description of structure of lead frame used in manufacturing method of semiconductor integrated circuit device of one embodiment of the present application (mainly FIGS. 4 to 7)
FIG. 4 is an enlarged top view of a unit device region of a lead frame used in the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present invention. FIG. 5 is an enlarged perspective top view of the unit device region of the lead frame during the process (before the resin sealing body separating step) of the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention. FIG. 6 is an enlarged top view corresponding to nine unit device regions of a lead frame used in the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present invention. FIG. 7 is an overall top view of a lead frame used in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present invention. Based on these, the structure of the lead frame used in the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present application will be described. The lead frame material is a copper-based material containing, for example, copper containing tin and nickel as a main component, but it may be a Zr-added copper-based material, an iron-added copper-based material, or other copper-based materials. . Here, the lead frame is patterned by etching. Although it can be punched out, etching is superior in precision of microfabrication and is effective in combination with half-etching.

  First, the overall structure of the lead frame 12 will be described with reference to FIGS. As shown in FIG. 7, unit device regions 8 are arranged in a matrix on a so-called multiple lead frame 12. Guide frame holes 26 (or pilot holes) to be fed are provided in the frame portions 12 c on both sides of the lead frame 12. Further, slits 19 for absorbing warpage are provided between the unit device region rows in the longitudinal direction. Provided at the boundary of each unit device region 8 are openings 17 and 18 used when removing unnecessary resin members such as runners and gates in the sealing process.

  Next, the inside of the unit device area 8 will be further described in detail. As shown in FIG. 4, the central portion is the die pad 3, and the suspension lead 9 is fixing it to the peripheral bumper 7. A warpage preventing slit 16 is provided at the peripheral portion so that the die pad 3 is not warped by thermal stress. The suspension lead 9 also plays a role of holding the bus bar 5, and the entire bus bar 5 and the half-etched portion 15 of the suspension lead 9 are half-etched from the back side (the bottom surface of the bus bar 5 is If the inner end of the lead 4 or the lower part of the periphery of the die pad is also half-etched, it is effective for preventing omission). In order to improve the wire bonding property, for example, a bonding metal layer 14 containing silver or the like as a main component is formed on the tip portion of the upper surface of the lead 4 by plating or the like. The vicinity of the outer end 4 d of the plurality of leads 4 is connected by a tie bar 11. A linear opening row 13 is provided between the tie bar 11 and the lead frame body. Here, the two-dot broken line is a projected pattern of the punching mold 21 for separating the tie bar portion from the sealing body after resin sealing. Similarly, the broken line at each corner is a projection pattern of the punching die 22 for separating the bumper 7 from the peripheral lead frame body.

  Next, the relationship between the semiconductor chip, the sealing body, the bonding wire, and the cut portion in the internal structure of the unit device region 8 will be described. As shown in FIG. 5, the semiconductor chip 1 is attached to the center of the die pad 3. A large number of bonding pads on the semiconductor chip 1 and most of the leads 4 (silver-plated portions 14) are connected by bonding wires. On the other hand, bonding wires are also connected between some of the leads 4 and the bus bars 5. Here, the boundary of the resin sealing body 2 (also the boundary of the mold cavity) is indicated by a dotted line. On the other hand, a broken line 24 indicates a cut portion when the resin sealing body 2 is separated from the lead frame main body. Further, the gate portion at the time of resin injection is indicated by an arrow 25.

3. Description of processing flow of manufacturing method of semiconductor integrated circuit device of one embodiment of the present application (mainly FIGS. 8 to 27)
FIG. 8 is an overall top view of the lead frame in the middle of the process (die bonding) during the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present invention. FIG. 9 is an overall top view of the lead frame in the middle of the process (sealing process completion) of the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present invention. FIG. 10 is a plan circuit layout diagram of an example of a semiconductor chip used in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present invention. FIG. 11 is a main process block flow diagram of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 12 is a top view of one element process (sealing step) of the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present invention (in this top view, the upper mold is removed for easy understanding). ) FIG. 13 is a cross-sectional view of a mold and a device corresponding to the cross section AA ′ of FIG. 14 is a cross-sectional view of a mold and a device corresponding to the BB ′ cross section of FIG. 15 is a cross-sectional view of a mold and a device corresponding to the CC ′ cross-section of FIG. FIG. 16 is a partially enlarged top view of a unit device region of the lead frame in the middle of the process (sealing process completion) of the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present invention. FIG. 17 is a lead frame partial front view for explaining the state of processing in one element process (step of removing resin protrusion between leads by laser) of the method for manufacturing a semiconductor integrated circuit device of one embodiment of the present invention. 18 is a cross-sectional view of a device corresponding to the cross section along DD ′ of FIG. FIG. 19 is a front view of a lead frame portion for explaining a process in an elemental process (electrolytic residual resin removing step) of the method for manufacturing a semiconductor integrated circuit device of one embodiment of the present invention. FIG. 20 is a cross-sectional view of a device corresponding to the DD ′ cross-section of FIG. FIG. 21 is another cross-sectional view of the device corresponding to the DD ′ cross-section of FIG. FIG. 22 is a front view of a lead frame portion for explaining a process in an elemental process (water jet residual resin removing step) of the method for manufacturing a semiconductor integrated circuit device of one embodiment of the present invention. FIG. 23 is a partially enlarged top view of the unit device region of the lead frame during the process of the semiconductor integrated circuit device manufacturing method according to one embodiment of the present invention (the completion of the water jet residual resin removing process). FIG. 24 is a partially enlarged top view of the unit device region of the lead frame during the process (before tie bar cutting) of the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention. FIG. 25 is a lead frame partial front view for explaining a process in an elemental process (tie bar cutting step) of the method for manufacturing a semiconductor integrated circuit device of one embodiment of the present invention. FIG. 26 is a partial perspective view of the resin sealing body (semiconductor integrated circuit device package) in one element process (after the resin sealing body separation step) of the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention. FIG. 27 is a partial perspective view of the wiring board and the semiconductor integrated circuit device package showing a state when the resin sealing body of FIG. 26 is mounted on the wiring board. Based on these, the processing flow of the manufacturing method of the semiconductor integrated circuit device of one embodiment of the present application will be described.

  Description will be made in order according to the process flow of FIG. First, in the wafer process, the semiconductor chip 1 is manufactured. As shown in FIG. 10, when the semiconductor chip 1 is, for example, a mixed signal integrated circuit chip, a large number of bonding pads 33 provided on the upper surface 1a of the semiconductor chip 1 and bipolar analogs are used. The circuit block 31 and the MIS (Metal Insulator Semiconductor) type logic memory circuit block 32 are included. Although an example in which one chip is attached to the unit device region 8 will be described here, a plurality of these may be fixed (fixed). Although an example of fixing on the die pad is shown here, when fixing a plurality of chips, they may be fixed directly or indirectly via other chips. The mixed signal integrated circuit chip may be a MIS semiconductor or a BiCMIS (Bipolar Complementary Metal Insulator Semiconductor) type.

  When the chip 1 is completed, the chip 1 is die-bonded for each unit device region 8 of the lead frame 12 as shown in FIG. Thereafter, a bonding wire is connected by, for example, ball and wedge bonding using a gold wire between necessary portions. Next, each sealing region (dotted line in FIG. 5) is resin-sealed with a transfer mold to form individual sealing bodies 2 (resin sealing step 101 in FIG. 11). Specifically, as shown in FIG. 12, the lead frame 12 that has undergone wire bonding is placed between the upper and lower molds 51 (the structure of the lower mold 51b is shown by partially making the lead frame 12 transparent). The mold cavity 53 is set so that the main part of the unit device region 8 matches. Next, the sealing resin 52 is transferred through the runner portion 56 and injected into the cavity 53 from the gate 57. At that time, the resin is filled between the leads beyond the boundary of the original mold cavity 53 and hardened there to form an inter-lead resin protrusion 54. The inter-resin resin protrusion 54 is sufficiently compressed through a pressurization period (sealing pressurization) after filling, and thus has a strong structure. In this respect, the resin is different from a resin burr (so-called flash burr) in which the resin leaking from a slight gap between the lead and the mold 51 is cured without being subjected to sealing pressure.

  Here, the sealing resin 52 used for sealing has a halogen-free configuration as a whole, for example, with the main resin component as a main component of a low molecular weight epoxy resin, about 80% by weight of a silica-based filler, and the like. (In fields where there are no environmental problems, it is possible to add a halogen-based flame retardant).

  The A-A ′ cross section (FIG. 12) at this time is as shown in FIG. 13. As shown in FIG. 13, in the mold cavity 53 formed between the upper mold 51a and the lower mold 51b, the die pad 3, the chip 1, the inner ends of the leads 4, the bonding wires 6, etc. Is sealed with the sealing resin 52 to form the resin sealing body 2.

  Next, the B-B ′ cross section (FIG. 12) is as shown in FIG. 14. As shown in FIG. 14, in this portion, a cavity-like space (sub-cavity) is formed by the inner side surface of the tie bar 11, the upper mold 51a, and the lower mold 51b. Resin pressurization also works. Accordingly, the inter-resin protrusion 54 is formed in the sub-cavity portion.

  Next, looking at the section CC ′ (FIG. 12), as shown in FIG. 15, here, the half-etched suspension lead 9 extends between the lead frame gate portion 25 and the die pad 3. I can see that The left side is an opening 17 for gate break. On the other hand, on the right side, there are a lead 4 on the opposite side, a tie bar 11, a line opening row 13 that divides the tie bar 11 and the lead frame main body, and the like.

  The lead frame 12 taken out from the mold 51 is subjected to gate and runner break processing (separate unnecessary resin in the gate portion and runner portion from the sealing body 2 and the lead frame 12). Thereafter, the resin curing process 102 (FIG. 11) of the resin sealing body 2 is performed.

  In this state, the periphery of the side surface 2d of the sealing body 2 in the unit device region 8 of the lead frame 12 is in a state as shown in FIG. Here, the resin burr 34 is formed thinly on the lead 4 by the sealing resin 52 leaking from the gap between the molds 51 (thin compared to the inter-lead resin protrusion 54).

  Here, as shown in FIG. 17, the inter-resin protrusion 54 is removed by irradiating the inter-lead resin protrusion 54 of the lead frame 12 with a laser beam 61 by a laser irradiation device 62 (see FIG. 11). Removal step 103). At this time, as shown in FIG. 18 (cross-section DD ′ of FIG. 16), the resin burr 34 on the lead 4 is also irradiated with the same laser beam 61, and the resin burr 34 is also removed almost simultaneously. (This may increase the effect of later electrolytic treatment and water jet). The laser used here is, for example, a YAG laser (Nd: YAG or the like), and the laser light 61 has a fundamental wavelength of 1064 nm, for example. This is near-infrared light for thermally removing the resin. Further, even if the near-infrared light is slightly deviated and hits the package body, it does not cause severe damage. The laser output is about 40 W, for example, and a pulse operation of about 20 kHz. The focal point is adjusted to the surface of the resin member to be removed. The laser line width and the laser interval are, for example, about 40 micrometers, and the scan speed is, for example, about 300 mm / second. The number of times of irradiation is, for example, about three times (three rounds around the sealing body 2). The reason for using near-infrared light is that the sealing resin 52 is a composition of a large number of substances, and it is efficient to remove the object as a whole by a thermal action without selectivity. By this laser irradiation, the inter-resin protrusion 54 is considered to be resin burrs. Thus, it is considered that it can be efficiently removed by means effective for resin / burr removal such as subsequent electrolytic treatment or water jet treatment.

  As the wavelength of the laser beam 61, in the case of the same YAG laser, a visible light region of 532 nm or an ultraviolet region of 355 nm can be used. In the case of a carbon dioxide gas laser, a wavelength (mid infrared region) of 10.6 micrometers can be used. In the mid-infrared region, the light itself is disadvantageous in terms of energy, and it is necessary to consider power, processing time, and the like. The visible light region or the ultraviolet region is expensive in terms of power because of harmonics and the like. In addition, since the energy of the light itself is high, the resin removability is good, but there is a possibility of damaging the package body, so it is important to manage the irradiation position accuracy.

  The periphery of the side surface 2d of the sealing body 2 in the unit device region 8 of the lead frame 12 at the time when the laser resin removing step 103 is completed is in a state as shown in FIG. There may be some residual resin 54 a (resin protrusion 54 between the leads that could not be completely removed) on the side surface of the lead 4. On the other hand, the resin burr 34 may be thin but not completely removed. At this time, the process may proceed to the solder plating step 106 (FIG. 11) through deburring or simple water washing (including chemical liquid washing).

  However, in order to ensure higher mounting reliability, it is desirable to perform electrolytic deburring processing 104 (FIG. 11). As shown in FIG. 20 (cross section along DD ′ in FIG. 19), the electrolytic deburring process 104 uses water in an aqueous electrolyte solution in which soda ash (mainly anhydrous sodium carbonate) or the like is dissolved with the lead frame 12 as a cathode. Electrolysis is performed (for example, the solution temperature is about 50 degrees Celsius, the processing time is about 15 minutes, for example, and the current density is about 10 A / dm 2). That is, a hydrogen gas bubble is generated between the lead 4 and the residual resin 54a or the resin burr 34 (in combination with the residual resin piece), and the residual resin piece is lifted by the force as shown in FIG.・ Can be turned off. At this time, the process may be shifted to the solder plating step 106 (FIG. 11) through simple water washing or the like (including chemical cleaning).

  However, in order to ensure higher mounting reliability, it is desirable to perform a hydraulic deburring process 105 (FIG. 11). As shown in FIG. 22, the water pressure deburring process 105 performs high pressure cleaning water or cleaning liquid from the nozzle 64 on the lead frame 12 (at this time, liquid honing processing in which particles are added to the cleaning water or cleaning liquid). Further, instead of or in combination with the hydraulic deburring process, the remaining residual resin piece is finally obtained by supplying a fluid jet 65 such as a chemical process or a blast process. It is a process to remove.

  By the processing so far, the periphery of the side surface 2d of the sealing body 2 in the unit device region 8 of the lead frame 12 is in a clean state as shown in FIG. Here, as shown in FIG. 11, the solder plating process 106 (surface treatment for improving the mountability) is performed by, for example, electroplating in an acidic tin (bismuth) plating solution (an alkaline plating solution is also possible). However, acidic plating solution has the merit of high purity plating). Although electroless plating or solder dip may be used, electroplating is preferable from the viewpoint of economy and reliability. As a material for the solder layer 41, for example, a tin-based lead-free solder made of 2% bismuth and the remaining tin (melting point is 217 degrees Celsius) is suitable (a lead-based solder can also be used if there is no environmental problem). is there). Other lead-free solders include tin / silver solder, tin / bismuth / silver / copper solder, and tin / bismuth / silver / antimony solder.

  Next, as shown in FIGS. 24 and 25, the punching die 21 (FIG. 4) is used to cut the cut surface 21 corresponding to the outer end portion 4 d of the lead 4 from below (L in FIG. 24 is, for example, By cutting the lead frame 12, the sealing body 2 and the tie bar 11 are separated (dam & tie bar cutting step 108 in FIG. 11). ). Subsequently, the sealing body 2 (device) is separated from the lead frame main body 12 by cutting and separating the remaining connecting portions with the punching die 22 (FIG. 4) (detaching step 109 in FIG. 11). The dam & tie bar cutting step 108 and the separation step 109 constitute an element isolation step.

  As described above, by cutting the outer end portion 4d of the lead 4 from below with the punching die 67, the solder layer on the lower surface 4b of the lead 4 moves to the lead tip surface as shown in FIG. A lead tip surface solder region 41c is formed (physically, the lower surface itself flows to become the lower half of the lead tip surface). Since the solder layers (solder regions) 41 (41a, 41b, 41c) are thus formed on the upper surface, lower surface, both side surfaces, and the front end surface of the lead 4, as shown in FIG. When solder reflow mounting is performed on the land 46, the solder fillet 42 is normally formed.

4). Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above-described embodiment, the QFN type plastic package has been specifically described. However, the present invention is not limited to this, and other types of plastic packages having protruding resin portions between the leads are provided. Needless to say, it can be widely applied to packages. In the above-described embodiment, the description has been made mainly on the case where the transfer mold is applied. However, the present invention is not limited thereto, and it is needless to say that the present invention can be applied to other plastic molding methods such as compression molding. Yes.

1 Semiconductor chip (integrated circuit board)
2 Resin sealing body 2b Bottom surface of resin sealing body 2d Side surface of resin sealing body 3 Die pad 3d Side of die pad 4 Lead 4d Outer end of lead 8 Unit device area 11 Tie bar 12 Lead frame 41 Solder layer 51 Mold die 54 Resin protrusion between leads 61 Laser beam

Claims (8)

A die pad having a front surface and a back surface opposite to the front surface;
A plurality of leads disposed around the die pad, each having a front surface, a back surface opposite to the front surface, and a plurality of side surfaces located between the front surface and the back surface;
A semiconductor chip mounted on the surface of the die pad and electrically connected to the plurality of leads;
Front surface, back surface and opposite to the previous SL surface, has a half-etched portion of the back side, one end is connected to the die pad, and the suspension leads supporting the die pad,
The first end of the suspension leads connected to the other end portion on the opposite side to the surface and the surface and a opposite back surface, and bumpers having a flared shape on both sides,
A substantially rectangular shape having an upper surface, a lower surface opposite to the upper surface, and a plurality of side surfaces located between the upper surface and the lower surface; a part of the die pad; and the plurality of leads A part, the semiconductor chip, and a sealing body that seals the half-etched part on the back side of the suspension lead,
A part of the back surface of the plurality of leads is exposed from the lower surface of the sealing body,
Projecting said plurality of respective portions and the plurality of part and said plurality of leads so as to be exposed from the sealing body side of said surface of the lead from the plurality of side surfaces of the sealing body,
The sealing body has a chamfered portion whose corners are chamfered in plan view,
The bumper, front of the plurality of sides of Kifutometai, disposed in the chamfered portion, and protrudes from the side where the chamfered portion is positioned, the back of each of the back and the bumper of the plurality of leads Is a semiconductor device on the same plane . The semiconductor device according to claim 1,
Before Symbol bumper is provided independently for each of the four corners of the sealing body, semi-conductor devices. The semiconductor device according to claim 1 ,
Prior Symbol bumper when mounted on the mounting substrate the semiconductor device is a moiety that is capable of radiating heat generated in the semiconductor device to the outside, a semi-conductor device. The semiconductor device according to claim 1 ,
Some of the back of the front Symbol die pad is exposed from the lower surface of the sealing body, semi-conductor devices. The semiconductor device according to claim 4 ,
In the extending direction of the lower surface as viewed and the suspension leads of the sealing member, between the said rear surface of said and the back surface of the die pad bumper portion of the sealing member is located, semi-conductor devices . The semiconductor device according to claim 4 ,
Periphery of the back surface of the die pad is half-etched, it is covered by the sealing body, the semiconductor device. The semiconductor device according to claim 1,
Wherein each of the inner ends of the plurality of leads are half etched, it is covered by the sealing body, the semiconductor device. The semiconductor device according to claim 1,
Wherein among the respective front Symbol plurality of sides of the plurality of leads, the direction in which the plurality of leads projecting in the side surface facing in a direction substantially orthogonal formed solder layer,
Of each of the plurality of side surfaces of said plurality of leads, said plurality of regions near the front Symbol lower surface of the lead is a side surface facing in a direction protruding solder layer is formed, solder is in a region closer to the top surface layer is not formed, the semiconductor device.

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