JP5516705B2 - Method for driving gate of semiconductor device - Google Patents

Description

  The present invention relates to a gate drive circuit for a power semiconductor element, and more particularly to a gate drive method for a semiconductor element that can reduce noise generated when the semiconductor element is turned off and can reduce switching loss that is in a trade-off relationship with noise. .

In recent years, with the tightening of EMC (Electromagnetic Interference) regulations, noise reduction has become a technical issue in various industrial fields such as inverters. In particular, appropriate measures are required for reducing noise generated by switching of semiconductor elements, which are main components of these devices, and modules on which these are mounted. As countermeasures against noise generation loops, methods such as adding capacitors, ferrite cores, and various filters created by combining these components, and methods for reducing the area of the generation loop for radiation noise, etc. Various measures are taken depending on the application and the situation of the countermeasure device.

In addition, noise countermeasures have been taken by improving the switching waveform that is the source. For example, in an IPM (Intelligence Power Module) that incorporates a gate drive circuit into an IGBT (Insulated Gate Bipolar Transistor) and modularizes it, a countermeasure against noise can be achieved by using a built-in gate drive circuit to reduce noise. Since it is possible to reduce noise with a single module without adding external parts, it is very effective in increasing added value. For this reason, IPM has been put into practical use by taking measures as shown in Non-Patent Document 1, for example.

  In other words, by adding a function to switch the gate drive circuit in two stages depending on the collector current of the IGBT, the rise of the gate voltage is relaxed in the low current region where the turn-off dV / dt of the FWD (flywheel diode) is large. Can be soft-switched. An IPM equipped with a drive circuit designed to reduce noise in this way has already been commercialized.

  On the other hand, for example, methods disclosed in Patent Documents 2 and 3 are disclosed as countermeasures in the gate drive circuit. In other words, aiming at the effect of reducing the turn-off loss of the semiconductor element, a capacitor is provided in parallel with the resistor in the drive circuit, and it is faster than using the gate resistor immediately after the turn-off switching until the capacitor is completely charged. In this method, the gate-emitter capacitance of the semiconductor element is discharged with a constant, thereby shortening the turn-off mirror time and reducing the loss.

Mitsubishi Electric Technical Journal, Vol.77, No.9, 2003, pp.567-570 Japanese Patent No. 3666843 US Pat. No. 6,333,665

  The IPM drive circuit countermeasure described in Non-Patent Document 1 is one of useful means for reducing noise. However, since the gate resistance is set to be large in the low current region where the FWD turn-off voltage change rate dV / dt increases, the switching loss, which is in a trade-off relationship, is greatly sacrificed during the countermeasure period, resulting in low noise. It is a difficult point.

  In addition, since the gate resistance is automatically switched in the module, the user does not know when the current value is switched. In addition, there is a problem that the user himself / herself cannot control the presence or absence of switching and the current value. Specifically, for example, when this IPM is installed in an inverter, switching with various current values is performed during operation, but the gate resistance is automatically switched depending on the current value, so dead time management In addition, module loss management becomes difficult.

  On the other hand, in order to reduce the loss due to the turn-off switching, Patent Documents 2 and 3 take measures to provide a capacitor in parallel with the gate resistance. By increasing the turn-off speed, the switching loss at the turn-off is improved. . However, only with this measure, in which capacitors are connected in parallel, only the switching loss at the time of turn-off is reduced, and the noise that is in a trade-off relationship is rather increased.

  In this way, switching loss and noise are in a trade-off relationship, so in order to reduce both and improve the trade-off characteristics, which part of the switching waveform has a strong correlation with noise, causing it to occur. It is important to speed up the parts that are not the cause of occurrence after grasping whether or not. Therefore, the relationship between the switching waveform during turn-off switching and noise was investigated. FIG. 3 shows the result of the synchronous evaluation of the switching waveform when the DC voltage is turned off by the IGBT and the search coil waveform serving as an index of noise.

3, reference numeral 31 denotes an IGBT collector-emitter voltage Vce, 32 denotes a collector current Ic, 33 denotes a search coil waveform, and 34 denotes a DC voltage level Vdc.
From FIG. 3, in the initial stage of turn-off, almost no vibration of the search coil waveform 33 is observed, and the search coil waveform 33 is abruptly synchronized with the timing of “*” when the collector-emitter voltage Vce31 reaches the DC voltage Vdc34. Can be seen to vibrate.

  Therefore, the behavior of the switching waveform after Vce 31 reaches Vdc 34 is important, and the voltage change rate dV / dt when Vce> Vdc is highly dependent on noise. Conversely, the behavior of the switching waveform before the timing of “*” in FIG. 3 has a low relevance to noise. For this reason, it is desired to reduce the loss of turn-off switching by increasing the speed before “*” and to suppress the noise by delaying as much as possible after “*”.

  In view of the above, an object of the present invention is to improve the trade-off characteristics of noise and loss that occur during turn-off switching.

In order to solve the above-described problem, in the invention of claim 1, in a gate drive method of a semiconductor element that performs on / off control by supplying positive and negative voltages to the gate of the semiconductor element,
When the semiconductor element is turned off, until the collector-emitter voltage of the semiconductor element reaches a DC voltage, the rate of change of the collector-emitter voltage is made larger than usual , and the semiconductor element is turned off. The gate and emitter of this semiconductor element are connected .

  According to the present invention, the turn-off loss can be reduced because the turn-off speed is increased early in the turn-off time. In addition, since a simple circuit is sufficient as a means for increasing the turn-off speed, this is a great advantage. Furthermore, when the present invention is applied as a product including a gate drive circuit such as an IPM, the switching waveform itself that becomes a noise generation source can be improved, so that it is not necessary to add an expensive external component such as a filter. Can do.

Configuration diagram showing an embodiment of the present invention A circuit diagram showing an example in which a reverse bias can be supplied in FIG. Illustration of turn-off operation when a general gate drive circuit is used Turn-off operation explanatory diagram when using the gate drive circuit according to the present invention Circuit diagram showing a general circuit corresponding to FIG. Circuit diagram showing a general circuit corresponding to FIG.

FIG. 1 is a circuit diagram showing a configuration of a gate driving circuit embodying the present invention.
The target semiconductor element is IGBT 1, and its drive circuit is indicated by reference numeral 20. The drive circuit 20 includes a P-channel MOSFET 21 as a first MOSFET, an N-channel MOSFET 22 as a second MOSFET, an N-channel MOSFET 23 as a third MOSFET, an N-channel MOSFET 24 as a fourth MOSFET, and a capacitor connected in series to the MOSFET 23. 25, a control circuit 26 of the MOSFET 24, and the like. The control circuit 26 is a control circuit for maintaining the turn-off of the IGBT 1. Vcc is a DC power supply for applying a gate voltage to the gate terminal of the IGBT 1, and is connected to both ends of the series circuit of the first MOSFET 21 and the second MOSFET 22.

That is, the negative potential side terminal (source terminal) of the first MOSFET 21 and the positive potential side terminal (drain terminal) of the second MOSFET 22 are connected to the gate terminal of the IGBT 1. Further, the negative potential side terminals (source terminals) of the second, third, and fourth MOSFETs 22 to 24 are respectively connected to the emitter terminal of the IGBT 1. A drive signal as illustrated is supplied to each gate of the first to third MOSFETs 21 to 23.

  In the circuit of FIG. 1, when the IGBT 1 is turned on, only the first MOSFET 21 is turned on, and the voltage of the DC power supply Vcc is applied to the gate of the IGBT 1. When the IGBT 1 is turned off, the first MOSFET 21 is turned off and the second and third MOSFETs 22 and 23 are turned on. As a result, the operation at the time of turn-on is not different from the conventional one, but at the beginning of the turn-off, the capacitor 25 rapidly pulls out the charge accumulated between the gate and the emitter of the IGBT 1 to increase the speed and reduce the loss. Can do. In the period when the influence of the noise during the IGBT turn-off operation is large, the charge can be reduced and the noise can be suppressed by extracting the charge accumulated between the gate and the emitter of the IGBT 1 through the second MOSFET 22 having a large on-resistance. it can.

  In other words, the charge accumulated between the gate and emitter of the IGBT 1 may be passed through the capacitor 25 at the initial stage when the IGBT 1 is turned off. For example, the third MOSFET 23 only needs to be turned on earlier than the second MOSFET 22. For this purpose, a delay circuit is provided at the gate of the second MOSFET 22 to delay the drive signal, or the gate resistance of the second MOSFET 22 is increased to turn on the second MOSFET 22. You should lengthen the time. Alternatively, the on-resistance of the second MOSFET 22 may be made larger than that of the third MOSFET 23, and for that purpose, the channel length of the second MOSFET 22 may be made larger than that of the third MOSFET 23. As described above, the on-timing and on-resistance of the second and third MOSFETs (22, 23) can be changed by changing the area of the MOSFET device or miniaturizing it. Thus, in order to suppress both noise and loss, the on-resistance of the second MOSFET 22 is preferably larger than the on-resistances of the third and fourth MOSFETs 23 and 24.

The third MOSFET 23 is used for damping that suppresses LC resonance caused by the wiring inductance L between the gate and the emitter and the capacitance C of the capacitor 25 provided in the circuit of FIG. The fourth MOSFET 24 is turned on when the IGBT 1 is shifted to the off state. The IGBT 1 is turned off by, for example, comparing the gate voltage of the IGBT 1 with the threshold voltage V _IGBT-gth in the control circuit 26 and determining that the IGBT 1 gate voltage is lower than the threshold value. It is good to judge. In addition, the OFF state of the IGBT 1 can be detected by detecting the collector-emitter current of the IGBT 1 and the collector-emitter voltage.

Then, when it is detected that the IGBT 1 has shifted to the off state, the fourth MOSFET 24 is turned on.
When the fourth MOSFET is turned on, the IGBT 1 is kept off and a stable potential is secured. For this reason, the on-resistance of the fourth MOSFET 24 is desirably as small as possible, and is required to be smaller than the on-resistances of the second and third MOSFETs 22 and 23. The fourth MOSFET 24 is intended for short-circuiting, and does not need to be a MOSFET in particular, and may be a bipolar transistor, and a mechanical switch may be used in some cases.

  Further, if the above-described LC resonance is sufficiently suppressed by the on-resistance of the third MOSFET 23 and the potential is stable without causing malfunction even without being kept off, the off-holding fourth MOSFET 24 can be omitted. Although it has been empirically known that the capacitor 25 has a capacitance equal to or greater than the gate-emitter junction capacitance of the IGBT 1, it is known that the effect is high. Therefore, there is no particular need for a numerical definition for capacity.

  FIG. 1 shows a case where Vcc is provided at both ends of the first MOSFET 21 and the second MOSFET 22 connected in series without using a reverse bias in the gate drive circuit. On the other hand, FIG. 2 is a circuit configuration diagram when + Vcc and −Vcc are separately provided so that positive and negative voltages can be supplied when the gate potential of the IGBT 1 is used as a reference. That is, since the basic operation is the same in FIG. 1 and FIG. 2, the present invention can be applied regardless of the presence or absence of a positive / negative power source.

As a comparative example with the present invention, a general gate drive circuit is shown in FIGS.
FIG. 5 shows an example of a case where only the positive power source is used and the reverse bias is not supplied to the gate with the gate potential as a reference. On the other hand, FIG. 6 shows an example in which positive and negative power supplies are provided and the reverse bias can be supplied to the gate when the gate potential is used as a reference. 5 and 6 are the same as FIG. 1 or FIG. 2 except that the capacitor 25 and the third MOSFET 23 shown in FIG.

  FIG. 4 shows an example of an actually measured waveform at the time of turn-off switching when the gate drive circuit of the present invention and the general gate drive circuit shown in FIGS. 5 and 6 are used. Here, a waveform example with reverse bias (± 15 V) is shown. The Vce waveform when the gate drive circuit of the present invention is used is denoted by reference numeral 41, the Ic waveform is denoted by 43, the Vce waveform when a general gate drive circuit is used is denoted by reference numeral 42, and the Ic waveform is denoted by 44. When the gate drive circuit of the present invention is used, the speed before reaching the DC voltage Vdc is increased (the Vce voltage change rate dV / dt is increased) compared to the case of using a general gate drive circuit. However, it can be seen that dV / dt in the region of Vce> Vdc is suppressed to about the same level as the conventional method.

From the above, it can be seen that it is possible to adjust to some extent whether noise is mainly suppressed or loss is controlled by selecting the capacitance of the capacitor 25 and the on-resistances of the second MOSFET 22 and the third MOSFET 23. Table 1 exemplifies actual measurement results when conditions 1 to 3 are selected. The example of FIG. 4 corresponds to condition 3 in Table 1.
That is, by using the gate drive circuit of the present invention, the trade-off characteristics can be improved as compared with the conventional case. In addition, although the operating principle does not change depending on the presence / absence of a positive / negative power supply, it can be said that the effect of improving the trade-off characteristics is slightly higher when there is a negative power supply.

  The gate drive circuit is mainly composed of MOSFETs for the purpose of facilitating integration and reducing the circuit scale (reducing the number of components). As a modification of the circuit of FIG. 1, the source of the MOSFET 22 may be connected to the connection point between the capacitor 25 and the MOSFET 23.

  DESCRIPTION OF SYMBOLS 1 ... IGBT (insulated gate bipolar transistor), 20 ... Gate drive circuit, 21, 22, 23, 24 ... MOSFET (metal oxide film type field effect transistor), 25 ... Capacitor, 26 ... Control circuit for turn-off holding, Vcc, + Vcc, −Vcc… DC power supply.

Claims (1)

In a gate driving method of a semiconductor element for controlling on / off by supplying at least a positive voltage to the gate of the semiconductor element
When the semiconductor element is turned off, the rate of change of the collector-emitter voltage is increased until the collector-emitter voltage of the semiconductor element reaches the DC voltage applied between the collector-emitter. After the emitter voltage reaches a DC voltage, the rate of change of the collector-emitter voltage is reduced , and the gate-emitter of the semiconductor element is connected when the semiconductor element is off. Semiconductor device gate driving method.