JP5507060B2 - Manufacturing method of vertical trench MOSFET - Google Patents

Description

  The present invention relates to a method for manufacturing a vertical trench MOSFET, and more particularly to improvements before and after forming a self-aligned source region.

  As cited below, Non-Patent Document 1 has a description regarding ion channeling.

6.3.3 Ion channeling Channeling begins to occur when incident ions enter the space between atomic columns (Non-Patent Document 3). Once ions enter between the atomic rows, the force of aligning the direction of the ions works due to the potential of the atomic rows, and the ions are collected toward the center of the gap (channel) between the atomic rows. In this case, the ions are stably guided into the trajectory along the channel over a considerable distance. Such ions gradually lose energy due to gentle collisions at shallow angles at the edge of the channel and eventually jump out of the channel by scattering. The penetration depth of channeled ions is several times greater than that in amorphous samples. This is because the energy loss of channeled ions is less than that of non-channeled ions. Channeling effects can be minimized if ions are injected in the direction of high atomic density (for example, <763> direction) to avoid channeling during single-crystal silicon ion implantation. It cannot be removed (see FIG. 12 attached hereto).
As described above, even if ions are implanted into a single crystal by devising to avoid channeling, the resulting distribution has a characteristic atomic distribution tail [carefully measured secondary ion mass spectrometry (SIMS, see Chapter 12). ) And the tail of the carrier distribution (observed by electrical measurement) appear. The tail portion of the distribution by channeling often coincides well with the exponential function exp (−x / λ) of the depth coordinate. A typical value for this λ is ˜0.1 μm. Since ions with a larger critical incident angle causing channeling become larger, the tail of the distribution is more remarkable in the case of phosphorus ion implantation than in boron. The critical angle of this channeling is proportional to Z ₁ ^(1/2) . Regarding the <110> axis, φCrit = 5.9 degrees for 50 keV phosphorus ions, but φCrit = 4.8 degrees for 50 keV boron ions. This critical angle (value in a relatively high energy region) is

It is expressed. Here, d is an interval between atomic rows.
It is considered that the main mechanism of the phenomenon that the tail is generated in the distribution of ions implanted at an incident angle shifted from the main axis to the crystalline target is that ions are channeled in the main axis direction inside the target. (An alternative mechanism has been proposed that is based on interstitial diffusion at the sample temperature during ion implantation.) Experiments related to ion implantation are based on channeling. I have proved that. The fact that phosphorous ions pass through a thinly cut silicon layer indicates that ions with energy that can be measured after passing through the silicon layer are present, and that channeling is clearly occurring. In this experiment, radioisotope P32 is ion-implanted into a silicon crystal sample having a thickness of about 0.5 μm. The ions corresponding to the tail portion of the distribution are collected by being injected into a second target placed behind the thinly cut silicon sample. The experimental results of ion implantation in the incident direction shifted from the principal axis can only occur when the cause of the distribution tail is due to channeling and not due to interstitial diffusion.

  Methods for practical use of channeling ions that penetrate deeply have been studied. However, since very precise control of the sample orientation is necessary, there is a great difficulty in controlling the ion implantation distribution and reproducibility. The figure (see FIG. 13 attached hereto) shows the precision of control of the incident direction required for channeling ion implantation for phosphorus and boron. Here, ions are implanted in various incident directions slightly shifted from the principal axis direction. Then, after annealing at a relatively low temperature (850 ° C.), the carrier concentration distribution was measured by the C-V method. From this figure, it can be seen that the distribution changes remarkably when the incident angle is changed once. (End of Non-Patent Document 1 citation)

As described above, various measures are taken to avoid channeling in the ion implantation process. Regarding the <110> axis, φCrit = 5.9 degrees for 50 keV phosphorus ions, and φCrit = 4.8 for 50 keV boron ions. Degree. For the above reasons, in general, a <100> wafer often employs a method in which phosphorus ions and boron ions are implanted at an angle of 7 to 8 degrees which is slightly larger than these two critical angles. is there.
Patent Documents 1 to 8 are documents in which an invention for preventing channeling of implanted ions is described.

  For example, Patent Document 1 describes a method in which a desired post-injection distribution is obtained by simulation using a tilt angle of 7 degrees, 20 degrees, 40 degrees, and 60 degrees while avoiding channeling as much as possible. Patent Document 4 describes a method for preventing channeling by ion implantation through a cap oxide film.

Patent Documents 5 to 11 describe a method in which oblique ion implantation is applied to a MOSFET trench.
In Patent Document 5, in order to realize the vertical trench MOSFET described in FIG. 1 of the same document, a process of manufacturing a P-type body region (17 in the same document) (FIG. 4 (d) in the same document) In the step of manufacturing the N-type low concentration region (6 in the literature) and the high concentration source region (7 in the literature) (FIG. 5 (b) in the literature), boron and phosphorus are ion-implanted obliquely. Is described.
In Patent Document 6, oblique ion implantation is performed on the sidewall of the trench, but there is no particular mention as to whether oblique ion implantation is performed on the surface of the semiconductor wafer.

  Patent documents 7 and 8 are examples of foreign documents. Patent Document 7 mainly relates to the structure, Patent Document 8 mainly relates to the manufacturing method, and both documents are from the same applicant. It is considered that the features of the inventions described in Patent Documents 7 and 8 are that self-aligned L-shaped source regions are formed by repeating ion implantation at 45 degrees twice (or four times) on the trench sidewalls.

As described above, oblique ion implantation remains an essential technique for forming a self-aligned source region on the trench sidewall. However, as the ratio of the width to the depth of the trench decreases, the shadow angle at the time of implantation can be increased by the trench angle before the incident, so that there is a disadvantage that only the portion close to the semiconductor wafer surface can be implanted, Therefore, the angle has a limit. That is, as the trench becomes narrower and deeper, the oblique angle of ion implantation has to be reduced.
In addition, the ion dose implanted into the surface of the semiconductor wafer has a sine value (sin α) of the inclination angle (as α) of the ion implantation, and there is a problem that the concentration on the surface of the semiconductor wafer cannot be obtained. Furthermore, in order to tilt the semiconductor substrate (wafer), a special mechanism is required. Therefore, there is a problem that it is inevitable that the apparatus becomes more expensive.

On the other hand, Patent Documents 9 and 10 describe an example of a method for forming a self-aligned source region from lateral source diffusion using PSG (phosphosilicate glass) as a source source instead of oblique ion implantation. The
However, as described in Patent Documents 9 and 10, there is a problem in the method of forming a source region by performing diffusion processing using PSG as a source source. In order to form a high-concentration source region, the phosphorus concentration in PSG must be increased. However, there is a limit to this, and there is a fundamental problem with the concentration of phosphorus, which is an N-type impurity diffused in the source region. The problem is that it is dominated by the diffusion temperature (the temperature becomes higher when the concentration is high), and the diffusion coefficient of phosphorus is relatively large, so that it is an unsuitable manufacturing method when fine pattern formation is required. .

By the way, as the unit cell of the trench MOSFET is miniaturized, a region for extracting the source electrode becomes more problematic. A technique for solving such a problem is a technique called “trench contact”, which is disclosed in Patent Documents 12 to 16.
JP, 2003-163173, A Problem, Solution JP, 2004-79953, A Problem, Solution JP, 2004-289154, A Problem, a solution means Drawing 1, Drawing 3, Drawing 4, and Drawing 5 JP, 2004-22723, A Problem, Solution JP, 2001-189456, A Problem, a means for solution Drawing 1, Drawing 4, Drawing 5 Paragraphs 0034,0037,0038 Japanese Patent Laid-Open No. 11-508087 US Pat. No. 6,316,806 FIG. 6A, 6C US Pat. No. 6,583,010 FIG. 6A, 6C Japanese Patent No. 2689606 Japanese Patent Laid-Open No. 5-226661 Japanese Patent Laid-Open No. 3-85765 US Pat. No. 5,623,152 US Pat. No. 5,721,148 US Pat. No. 6,037,628 US Pat. No. 6,110,799 JP 63-224260 A SMSze “VLSI Technology” Toshiba Research Institute Translation P241 6.3.3 Ion Channeling I. Ruge and Graul,, Eds., Second International Conferece on Ion Implantation, Garmish, Springer-Verlag 1972. DVMorgan, Ed., Channeling: Theory, Observation and Applications, Wily, New York, 1973

In developing the vertical trench MOSFET, the present inventors performed boron ion implantation once on the trench and the mesa top surface m around the trench as shown in FIG. At this time, since a shadow that blocks the ion beam is generated on the inner side wall wf in the trench, there is a difference in the number of boron ions that are implanted in the front side wall wn and the inner side wall wf and finally taken in. It will occur.
As a result, when the channel of the MOSFET is completed after such one ion implantation, there is a problem that the channel concentration and the channel length are different between the front side wall wn and the back side wall wf in the trench. It was.
In order not to cause such an imbalance, if ion implantation is performed at a right angle to the surface of the semiconductor wafer, there arises a problem that ion channeling cannot be avoided.

  The present invention has been made in view of the above problems in the prior art, and is ideal for reproducibility and good production efficiency while preventing ion channeling when ion implantation is performed on a semiconductor wafer in which a trench is formed. It is an object of the present invention to provide a method for manufacturing a vertical trench MOSFET in which an impurity introduction region can be formed in a semiconductor around a trench.

The invention according to claim 1 for solving the above problems is a method of manufacturing a vertical trench MOSFET,
Forming the trench from the surface of the semiconductor layer;
Forming gate polysilicon in the trench to a position below the surface;
Forming a cap oxide film on the surface of the semiconductor layer on which the trench and the gate polysilicon are formed, preferably about 200 mm to avoid ion channeling;
First conductivity type impurity ions are implanted at a right angle to the surface of the semiconductor layer on which the cap oxide film is formed or at an angle inclined from the right angle to the longitudinal direction of the surface opening of the trench with a limit of 7 degrees. A first ion implantation step of forming a first conductivity type base layer in a semiconductor portion adjacent to the trench;
The cap oxide film is used as it is and has a tilt angle of 7 degrees in the short direction of the surface opening of the trench with respect to the normal of the surface of the semiconductor layer on which the first conductivity type base layer is formed. A second ion implantation step of implanting conductive impurity ions;
Using the cap oxide film and the tilt angle as they are, the wafer supporting the semiconductor layer is horizontally rotated by 180 degrees, and then third ions for implanting second conductivity type impurity ions into the surface of the semiconductor layer. An injection process,
Through the second ion implantation step and the third ion implantation step, the diffusion depth of the second conductivity type impurity ions from the surface continues from the surface layer portion of the first conductivity type base layer to the sidewall of the trench. A second conductivity type source region having a portion shallower than the upper surface of the gate polysilicon and having a portion formed deeper than the diffusion depth by the second conductivity type impurity ions implanted from the sidewall of the trench. Is formed on both sides of the trench by overlapping the gate polysilicon along the side wall of the trench at the deeply formed portion .

According to the present invention, in ion implantation for forming the base layer, the cap oxide film suppresses ion channeling, and suppresses variations in impurity concentration on both side walls of the trench, thereby improving the reproducibility of the base layer. There is an effect that it can be formed.
Furthermore, according to the present invention, in ion implantation for forming a source region, it is efficient to use a cap oxide film as it is, and a semiconductor supporting a semiconductor layer is simply rotated 180 degrees horizontally. There is an effect that ± 7 degrees of ion implantation is performed once with respect to the perpendicular to the surface of the layer, and the production efficiency can be improved.

  A method for manufacturing a vertical trench MOSFET according to an embodiment of the present invention will be described below. For convenience of explanation, the steps 1 to 12 will be described separately.

[Step 1] First, a silicon laminated substrate (wafer) is obtained by epitaxially growing an N-type semiconductor layer 2 having a desired specification crystal axis <100> on an N-type semiconductor substrate 1 having a desired specification. Then, a part of the oxide film formed by oxidizing the entire surface of the semiconductor layer 2 is opened, and a P-type impurity (boron) is introduced to form a P well 3 and a guard ring 4. A portion of the oxide film that becomes the active region is opened by etching to obtain the configuration shown in FIG. In this configuration, the oxide film 5 has a relatively thick thickness of 5,000 to 7,000 (領域) because it is a field oxide film formed on the breakdown voltage maintaining region.

[Step 2] Next, the surface is oxidized again to form a relatively thin oxide film 6 on the active region (FIG. 1B). The film thickness of the oxide film 6 is only 3,000 (Å). This is because a large electric field strength is not applied to the active region, and if it is unnecessarily thick, processing accuracy is lowered.

[Step 3] Next, a part of the oxide film 6 is opened and etched using the oxide film 6 as an oxide film mask 7 to form a trench 8 (FIG. 1 (c)). As shown in FIG. 6, the trenches 8, 8, 8,... Are formed in a long straight line extending in the same direction.

[Step 4] Next, a sacrificial oxide film 9 having a thickness of about 1,000 (Å) is formed on the inner surface of the trench 8 roughened during the etching in the step 3, and the inner surface of the trench 8 is smoothed by wet etching. (FIG. 2 (a)). By this wet etching, the bottom corner of the trench 8 is also rounded. Subsequently, gate oxidation is performed at a thickness of about 800 (Å) to form a gate oxide film.

[Step 5] Next, polysilicon having a thickness of about 3,000 to 5,000 (Å) is deposited on the entire surface by CVD, and phosphorus is thermally diffused in the deposited polysilicon to obtain a polysilicon layer 10 doped with impurities. At this time, an oxide film 11 is formed on the surface of the polysilicon layer 10 by heat treatment during phosphorus diffusion (FIG. 2B).

[Step 6] Next, the polysilicon layer 10 is etched by leaving a part of the oxide film 11 as the oxide film mask 12 by a known photolithography patterning process. At this time, the polysilicon layer 13 remains on the surface by the oxide film mask 12, and in the trench 8, the polysilicon layer 14 remains after being etched back to a depth of 0.3 (μm) from the surface. At this time, the oxide film in the active region (a part of 7 and 9 in FIG. 2A) exposed by the etching of the polysilicon layer 10 is removed by etching (FIG. 2C). The polysilicon layer 14 becomes a polysilicon gate electrode through the following steps.

[Step 7] Next, after forming a cap oxide film 15 of 200 (Å) by thermal oxidation, boron is ion-implanted at a right angle to the surface to form a P base (P body) layer 16. However, boron may be ion-implanted from an angle perpendicular to the surface at an angle inclined by 7 degrees in the longitudinal direction of the surface opening of the trench 8 (direction perpendicular to the drawing in FIG. 3). As is well known, by ion implantation through the cap oxide film 15, ion channeling can be suppressed even at right-angle ion implantation, and boron is knocked back to the outside by the impact of continuous ion implantation. Can be suppressed. The ion implantation conditions are, for example, 70 keV at 2 × 10 ¹³ dose (1 / (cm) ² ). Following this ion implantation, heat treatment for stretching diffusion is performed. For example, after the processing, the P base layer 16 has a maximum impurity concentration of 2 × 10 ¹⁷ (1 / (cm) ³ ) and a junction depth of 1.4 (μm). FIG. 3 (a)).

Here, the breakdown voltage structure will be described.
In the above structure, the main junction by the P well 3 and the guard ring 4 are deeper in the PN junction than the P base layer 16, so that the withstand voltage when applying a reverse voltage is P well 3 as is well known. Is supported by the main joint and the guard ring 4. That is, in the device region shown in FIG. 3A, most of the portion where the electric field strength becomes high when a reverse voltage is applied is a region where the P well 3 and the guard ring 4 are formed. The electric field strength distribution in the cell region on the inner side thereof is a distribution along the irregularities of the trench 8 and the P base layer 16, but the electric field relaxation is realized because the bottom corner of the trench 8 is rounded. Therefore, it is not necessary to make the P base layer 16 deeper than the trench 8 in order to improve the breakdown voltage.
Of course, it is possible to make the P base layer 16 deeper than the trench 8 as required. In Step 7, since boron is implanted at a right angle to the surface, boron is uniformly implanted into both side walls of the trench 8, so that the heat treatment temperature and time for subsequent stretching diffusion are set larger. A deeper P base layer 16 can be obtained.

[Step 8] Next, an oxide film mask opening for forming the channel stop region 18 is formed by removing the oxide film at the device edge. Subsequently, ion implantation for forming the source region 17 and the channel stop region 18 is performed. At this time, the cap oxide film 15 formed in the step 7 and used at the time of boron implantation is used as it is in this ion implantation, that is, 200 (Å) is used as it is, and arsenic (As) is ionized through the cap oxide film 15. inject. After this ion implantation is performed at a tilt angle of 7 degrees in the short direction of the surface opening of the trench 8 (left-right direction in FIG. 3) with respect to the normal of the surface of the semiconductor substrate 1, the ion implantation is performed once. The ion implantation is performed for the second time by horizontally rotating. Thus, ± 7 degree ion implantation is performed once. Arsenic (As) ion implantation conditions are, for example, 1.0 × 10 ¹⁶ dose (1 / (cm) ² ) and 70 keV. Thus, the source region 17 and the channel stop region 18 which are N-type regions are formed (FIG. 3B).

[Step 9] Next, an interlayer insulating film 19 having a BPSG (phosphorus borosilicate glass / boron phosphosilicate glass) composition is deposited and formed on the entire surface by atmospheric pressure CVD. After annealing, an interlayer insulating film 19 is formed on the interlayer insulating film 19. An opening for forming two trenches is formed (FIG. 4A). When etching this opening, the cap oxide film 15 acts as an etching stopper.

[Step 10] Next, the second trench 20 is formed by etching using an Si etcher, penetrating the source region 17 and reaching the P base layer 16. Subsequently, boron is ion-implanted to form a high-concentration P base layer 21 in a region in the P base layer 16 around the bottom of the second trench 20 (FIG. 4B). The high-concentration P base layer 21 is intended to improve ohmic contact with the P base layer 16 and to reduce the amplification factor of the parasitic npn bipolar transistor. The second trench 20 is shallower than the trench 8.

[Step 11] Next, after forming contact holes, a metal layer 22 is deposited by sputtering (FIG. 5A). Contact holes are provided in the cell region, on the polysilicon layer 13 for routing the gate, the P well 3, the guard ring 4, and the channel stop region 18, respectively. The metal layer 22 is a barrier metal and an electrode metal. Titanium (Ti) is used as the barrier metal, and aluminum (Al) is used as the electrode metal. The barrier metal is preceded by the sputter deposition. Is done. The film thickness of titanium (Ti) is 2.000 (Å), and the film thickness of aluminum (Al) is 5.0 (μm).

[Step 12] Next, the metal layer 22 is patterned by a well-known photolithography / etching technique to form electrode patterns 22a, 22b, 22c, and 22d (FIGS. 5B and 6). Further, the drain electrode 23 is formed on the back surface of the semiconductor substrate 1 (FIG. 5B). In forming the drain electrode 23, first, the back surface of the semiconductor substrate 1 is ground to reduce the thickness of the semiconductor substrate 1 to the required characteristics, and then, for example, a <Ti-Ni-Au> -based composite A drain electrode 23 is formed by sputter deposition on the back surface of the ground semiconductor substrate 1.

  Thereafter, a final protective film (not shown) is formed on the wafer surface, patterning for forming bonding pads is performed, and all wafer processes are completed.

FIG. 6 shows a half plan view of the vertical trench MOSFET of this embodiment. As shown in FIG. 6, each aluminum electrode of the source electrode 22 a, the gate electrode 22 b and its routing line 22 b-1, the guard ring electrode 22 c connected to the guard ring 4, and the equipotential ring electrode 22 d connected to the channel stop region 18. A pattern is formed on the surface.
A black portion shown in FIG. 6 indicates the shape and arrangement of the trench 8, that is, the cell.
According to the vertical trench MOSFET chip of this embodiment, the gate electrode pad 22e is arranged at the upper center of a part of the active region. This gate electrode pad 22e extends in the vertical direction in the center of the chip so as to divide the region into two. The remaining region is mainly a source region including a large number of linear unit cells. Around the periphery of the active region, the gate electrode 22b and its routing line 22b-1, the guard ring electrode 22c, and the equipotential ring electrode 22d are arranged in a clever and complicated manner.

According to the manufacturing method of the vertical trench MOSFET of the present embodiment described above, there are the following actions (1) and (2).
(1) After the cap oxide film 15 is formed to a thickness of about 200 (Å), boron ions are implanted at a right angle to the wafer surface, so that channeling of boron ions is suppressed by the cap oxide film 15; Variations in impurity concentration at both side walls of the trench 8 can be suppressed.
(2) Further, in the ion implantation for forming the N + source region, the cap oxide film 15 is used as it is, and the ion implantation of ± 7 degrees with respect to the perpendicular of the surface of the semiconductor substrate 1 is performed once. By this process, for example, a source region structure having a planar junction depth (B) = 0.18 (μm), a sidewall junction depth (A) = 0.05 (μm), and a B / A ratio = 0.28 is obtained. The plane junction depth (B) = 0.18 (μm) is equal to or less than the depth of the recess of the trench 8, and a sufficient source contact can be obtained even with the trench contact concept. Value. Further, the value of the side wall junction depth (A) = 0.05 (μm) ensures a reliable overlap between the gate and the source and is sufficient for the entire mesa portion between the trenches 8 and 8 exposed from the polysilicon layer 14. A simple source region is formed.

  The present embodiment described above is a novel device for manufacturing a device that sufficiently meets the "strict requirements for low Ron characteristics and high-frequency SW speed" imposed on recent medium voltage (100V) trench gate type MOSFETs. It corresponds to the method. In addition to the actions (1) and (2) above, the trench contact structure is also incorporated in the ion implantation process for forming the P base layer and the ion implantation process for forming the N + source region by this manufacturing method. Therefore, in order to continue mass production of a recent medium-voltage (100V) trench gate type MOSFET having a cell pitch of about 2 (μm) with good reproducibility, the desired device characteristics are stable and the minimum number of processes. There is an effect that the device can be manufactured using a general-purpose specification apparatus without using an apparatus capable of executing special oblique ion implantation (beam inclination angle of 30 to 60 degrees).

Hereinafter, a simulation for finding an accurate condition of the ion implantation in the above step 8 will be disclosed.
1. Simulation conditions The width of the trench 8 was set to 0.5 (μm), the depth of the trench 8 was set to 1.7 (μm), and the film thickness of the cap oxide film 15 was set to four types of 0, 100, 200, and 500 (Å). The depth from the silicon surface to the top of the polysilicon layer 14 was set to 0.3 (μm). For the semiconductor substrate 1, the impurity was phosphorus (N-type) and the resistivity was set to 1.6 (Ω · cm). The maximum impurity concentration of the P base layer 16 is 4 × 10 ¹⁷ (1 / (cm) ³ ), and the junction depth of the P base layer 16 is set to 1.4 (μm). As the implantation conditions, the ion species is arsenic (As), the implantation angle is ± 7 degrees with respect to the surface normal, and the dose is 1.0 × 10 ¹⁶ (1 / (cm) ² ) for both times. The accelerating acceleration energy of arsenic (As) was set to four types of 30, 50, 70, and 120 (keV).
The prediction calculation of how the N + source region 17 is finished under the above conditions was performed.

2. Simulation Result FIG. 7 shows a device cross-sectional image of the simulation result. FIG. 8 shows a table in which simulation conditions and corresponding values of results are described.

As the thickness of the cap oxide film 15 increases, the amount of arsenic (As) ions implanted into the planar (mesa top surface) portion and the trench sidewall portion decreases, so that the planar portion (junction) depth B and sidewall portion ( Bonding) Both depth A drastically decreases. Further, the B / A ratio also decreases drastically as the cap oxide film 15 becomes thicker.
As the acceleration energy increases, the amount of arsenic (As) ions implanted into the flat surface (mesa top surface) and the trench side wall increases, and both the flat surface (junction) depth B and the side wall (junction) depth A increase. The degree of decrease in the B / A ratio tends to decrease.
Based on the values shown in the table of FIG. 8, FIG. 9 shows a change graph of the plane part (joint) depth B, FIG. 10 shows a change graph of the side wall part (joint) depth A, and FIG. 11 shows a change graph of the B / A ratio. Indicated.

  From the above results, the plane part (junction) depth B is less than 0.3 (μm) from the silicon surface to the upper part of the polysilicon layer 14, and the side wall part (junction) depth A is relatively deep. When conditions under which reliable gate-source overlap is guaranteed are selected, the acceleration energy is 70 (keV) and the thickness of the cap oxide film 15 is 200 (Å). Under such conditions, a structure with a flat surface (bonding) depth B = 0.18 (μm), a side wall (bonding) depth A = 0.05 (μm), and a B / A ratio = 0.28 is obtained.

It is process sectional drawing concerning one Embodiment of this invention. It is process sectional drawing concerning one Embodiment of this invention. It is process sectional drawing concerning one Embodiment of this invention. It is process sectional drawing concerning one Embodiment of this invention. It is process sectional drawing concerning one Embodiment of this invention. 1 is a half-body plan view of a vertical trench MOSFET according to an embodiment of the present invention. It is a device cross-sectional image of a simulation result. It is a table | surface which described the simulation conditions and the value of the result corresponding to this. It is a change graph of the plane part (joining) depth B created based on the value shown in the table of FIG. It is a change graph of the side wall part (joining) depth A created based on the value shown in the table of FIG. It is a change graph of B / A ratio created based on the value shown in the table of FIG. It is a schematic diagram of a track of ions incident on a single crystal from a dense <763> direction of atoms. This range shows the part that has not been channeled and the part that has been channeled. (a) Donor carrier distribution in a layer in which 300 keV P31 is implanted in various incident directions slightly shifted from the <111> axis (according to Moline, Reutlinger, Non-Patent Document 2). (b) Distribution of acceptors in a layer into which 150 keV B11 is implanted in various incident directions slightly shifted from the <100> axis (according to Seidel, Non-Patent Document 2). FIG. 4 is a process cross-sectional view of a process in which boron ions are implanted into a trench and a mesa top surface around the trench at an inclination angle of 7 degrees in developing the vertical trench MOSFET.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Semiconductor layer 3 P well 4 Guard ring 8 Trench 10 Polysilicon layer 13 Polysilicon layer 14 Polysilicon layer (gate polysilicon)
15 Cap oxide film 16 P base layer 17 source region 18 channel stop region 19 interlayer insulating film 20 second trench (contact trench)
21 High-concentration P base layer 22a Source electrode 22b Gate electrode 22c Guard ring electrode 22d Equipotential ring electrode 22e Gate electrode pad 22 Metal layer 23 Drain electrode

Claims (1)

A method for manufacturing a vertical trench MOSFET, comprising:
Forming the trench from the surface of the semiconductor layer;
Forming gate polysilicon in the trench to a position below the surface;
Forming a cap oxide film for avoiding ion channeling on the surface of the semiconductor layer in which the trench and the gate polysilicon are formed;
First conductivity type impurity ions are implanted at a right angle to the surface of the semiconductor layer on which the cap oxide film is formed or at an angle inclined from the right angle to the longitudinal direction of the surface opening of the trench with a limit of 7 degrees. A first ion implantation step of forming a first conductivity type base layer in a semiconductor portion adjacent to the trench;
The cap oxide film is used as it is and has a tilt angle of 7 degrees in the short direction of the surface opening of the trench with respect to the normal of the surface of the semiconductor layer on which the first conductivity type base layer is formed. A second ion implantation step of implanting conductive impurity ions;
Using the cap oxide film and the tilt angle as they are, the wafer supporting the semiconductor layer is horizontally rotated by 180 degrees, and then third ions for implanting second conductivity type impurity ions into the surface of the semiconductor layer. An injection process,
Through the second ion implantation step and the third ion implantation step, the diffusion depth of the second conductivity type impurity ions from the surface continues from the surface layer portion of the first conductivity type base layer to the sidewall of the trench. A second conductivity type source region having a portion shallower than the upper surface of the gate polysilicon and having a portion formed deeper than the diffusion depth by the second conductivity type impurity ions implanted from the sidewall of the trench. Is formed on both sides of the trench by overlapping the gate polysilicon along the side wall of the trench at the deeply formed portion .

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