JP5505026B2 - Amplifier circuit and transmission circuit including the amplifier circuit - Google Patents

Description

  An amplifier circuit that can be used to amplify a signal having a high frequency, and a transmission circuit including the amplifier circuit.

  In RF transceivers for wireless communication including power amplifiers, higher carrier signal handling and higher output power are being promoted (see Non-Patent Document 1 and Non-Patent Document 2). When the frequency of the carrier signal to be handled is increased and the output power is increased, a phenomenon occurs in which the frequency band (channel) of the carrier signal (carrier) output from the RF transceiver protrudes into the frequency band of the adjacent carrier signal. Therefore, a technique for reducing the adjacent channel leakage power ratio (ACPR) of the carrier signal output from the RF transceiver is also being developed.

  Here, the phenomenon that protrudes to the frequency band of the adjacent carrier signal is caused by the change of the phase of the output signal output from the power amplifier relative to the input signal by the NMOS transistor that amplifies the input signal included in the power amplifier. It is said that. Specifically, when a large signal is input to the biased NMOS transistor and the gate potential is close to the threshold value, the gate-source capacitance of the NMOS transistor changes greatly, and the phase of the signal output by the NMOS transistor It is said that the above phenomenon is caused by a change from the phase of the signal.

  Therefore, by connecting the gate electrode of the PMOS transistor whose characteristics of the change in the gate-source capacitance with respect to the gate potential of the NMOS transistor are reversed to the gate electrode of the NMOS transistor, the gate-source capacitance with respect to the gate potential of the NMOS transistor. A technique for compensating for the change in the above has been proposed (see Non-Patent Document 3). As a result, it was considered that the gate-source capacitance of the NMOS transistor became substantially constant, the change in the phase of the output signal with respect to the phase of the input signal decreased, and the adjacent channel leakage ratio (ACPR) improved.

  However, the threshold value of the NMOS transistor and the threshold value of the PMOS transistor vary independently, and the change point of the gate-source capacitance is different. Therefore, the change of the gate-source capacitance of the NMOS transistor is not always compensated.

Patrick Reynaert, Michiel S.J.Steyaert, “A 1.75-GHz Polar Modulated CMOS RF Power Amplifier for GSM-EDGE”, IEEE Journal of Solid-state circuit, Vol. 40, No. 12, December 2005 Debopriyo Chowdhury, Christopher D. Hull, Ofir B. Degani, Pankaj Goyal, Yanjie Wang, M. Niknejad, “A Single-Chip Highly Linear 2.4GHz 30dBm Power Amplifier in 90nm CMOS”, ISSCC 2009 / SESSION 22 / PA AND ANTENNA INTERFACE /22.3 Chengzhou Wang, Mani Vaidyanathan, Lawrence E. Larson, “A Capacitance-Compensation Technique for Improved Linearity in CMOS Class-AB Power Amplifiers”, IEEE Journal of Solid-state circuit, Vol. 39, No. 11, November 2004

  An object of the present invention is to provide a power amplifier in which a change in gate-source capacitance of an NMOS transistor for signal amplification included in the power amplifier is suppressed and an adjacent channel leakage ratio (ACPR) is improved.

  According to the first aspect of the present invention, a first amplifier that outputs the second complementary signal obtained by amplifying the first complementary signal and a third complementary signal obtained by amplifying the second complementary signal are obtained. A phase difference between the second amplifier to be output and the first complementary signal and the third complementary signal is detected and added to a signal line on which the second complementary signal propagates according to the voltage of the second complementary signal. There is provided an amplifier circuit comprising: a capacitor correction circuit that controls the voltage dependency of the capacitor so that the phase difference is minimized.

  According to the present invention, an amplifier circuit having an improved adjacent channel leakage ratio (ACPR) can be provided.

FIG. 1 is a view showing an RF transceiver 10, a display 8, and a speaker 9. FIG. 2 is a circuit diagram illustrating the power amplifier 3. 3A and 3B are diagrams for explaining the phase comparator 64 and the filter 63 included in the capacitance correction circuit 60. FIG. FIG. 4 is a diagram showing a change in capacitance of a node where the capacitance correction circuit 60 is connected to the power amplifier 3. FIG. 5 shows a power amplifier 80 according to the second embodiment. FIG. 6 shows a power amplifier 100 according to the third embodiment. FIG. 7 shows the sum of the back gate-gate capacitance of the NMOS transistor 91 and the gate-source capacitance of the NMOS transistor 35 with respect to the potential of the signal line for transmitting the signal Z. FIG. 8 shows a power amplifier 120 of the fourth embodiment. FIG. 9 is a diagram illustrating a power amplifier 200 according to the fifth embodiment.

  The present invention includes the embodiments described below that have been modified by the design that can be conceived by those skilled in the art, and those in which the components shown in the embodiments have been recombined. Further, the present invention includes those in which the constituent elements are replaced with other constituent elements having the same operational effects, and are not limited to the following embodiments.

  FIG. 1 is a view showing an RF transceiver 10, a display 8, and a speaker 9. The RF transceiver 10 includes an antenna 1, a filter 2 (filter), a power amplifier 3 (PA), a voltage controlled oscillator 4 (VCO: Voltage Control Oscillator), and a phase lock loop type frequency tuner 5 (PLL-FS: Phase lock). a loop-frequency synthesizer), a low-pass filter 6 (LPF), and a baseband LSI 7 (Baseband LSI).

The baseband LSI 7 is a semiconductor circuit that converts data signals representing image data, audio data, and the like into wireless signals such as image signals and audio signals and outputs the signals to the low-pass filter 6.
The low-pass filter 6 is a filter that blocks harmonics of the image signal and the audio signal.
The phase lock loop type frequency tuner 5 is a tuner that tunes a carrier wave generated from the voltage controlled oscillator 4 to a clock signal generated from a built-in oscillator.

The voltage controlled oscillator 4 is a circuit that generates a carrier wave and modulates the carrier wave with an image signal and an audio signal received from the low-pass filter 6. That is, the voltage controlled oscillator 4 serves as a mixer that modulates a carrier wave with an image signal or the like.
The power amplifier 3 is an amplifier that amplifies the modulated carrier wave generated from the voltage controlled oscillator 4.
The filter 2 is a filter that removes a noise signal from the amplified carrier wave. The antenna 1 is an antenna that radiates a modulated carrier wave from the filter 2.

  FIG. 2 is a circuit diagram illustrating the power amplifier 3. The power amplifier 3 includes an amplifier 20, an amplifier 30, an amplifier 40, transformers 50 and 58, capacitors 51, 52 and 54, resistors 53, 55, 56, 57 and 59, and capacitance correction circuits 60 and 70.

  The capacitor 51 and the primary coil of the transformer 50 are connected in series between the input terminal and the ground terminal. The amplifier 20 receives the complementary signals X and / X output from the secondary coil of the transformer 50, and outputs the complementary signals Y and / Y.

  The amplifier 20 has a resistor 21 and a resistor 22 connected in series between the first terminal and the second terminal of the amplifier 20, the resistor 21 and the resistor 22 are connected, and a connection node and a ground terminal to which the voltage Vg1 is applied. A resistor 23 connected between the second terminal and the gate electrode of the NMOS transistor 26; an NMOS transistor 26 whose source is connected to the ground line and the back gate; and a first terminal and the NMOS transistor 27 The resistor 24 connected to the gate electrode, the NMOS transistor 27 whose source is connected to the ground line and the back gate, the drain of the NMOS transistor 27 and the drain of the NMOS transistor 26 are connected, and the inductance connected to the power supply line Vdd at the intermediate point 28.

  The capacitor 52 and the resistor 53, and the capacitor 54 and the resistor 55 are connected in series to the signal line through which the complementary signals Y and / Y are transmitted. The amplifier 30 outputs the complementary signals Z and / Z after receiving the complementary signals Y and / Y after passing through the capacitance and the resistance.

  The amplifier 30 has a resistor 31 and a resistor 32 connected in series between the first terminal and the second terminal of the amplifier 30, the resistor 31 and the resistor 32 are connected, and a connection node and a ground terminal to which the voltage Vg2 is applied. The resistor 33, the second terminal and the gate electrode are connected to each other, the NMOS transistor 26 whose source is connected to the ground line and the back gate, and the first terminal and the gate electrode are connected. The NMOS transistor 27 has a source connected to the ground line and the back gate, the drain of the NMOS transistor 27 is connected to the drain of the NMOS transistor 26, and an inductance 28 is connected to the power supply line Vdd at an intermediate point thereof.

  Inductances 56 and 57 are connected in series to the signal lines through which the complementary signals Z and / Z are transmitted. The amplifier 40 receives the complementary signals Z and / Z after passing through the inductance, and then outputs the complementary signals W and / W to the primary coil of the transformer 58. The transformer 58 outputs complementary signals W and / W to an output terminal connected to the ground terminal via the resistor 59. The amplifier 40 includes the same components as the amplifier 30, and the connection between the components is the same. However, the voltage applied to the connection node where the resistor 31 and the resistor 32 are connected is the voltage Vg3.

The capacitance correction circuit 60 receives the signal W of the complementary signals W and / W and the signal Y of the complementary signals Y and / Y, and converts the capacitance according to the phase difference between the signal W and the signal Y into the inductance 57. And a circuit added to the connection node of the amplifier 40.
The capacitance correction circuit 70 receives the signal / W of the complementary signals W and / W and the signal / Y of the complementary signals Y and / Y, and has a capacitance corresponding to the phase difference between the signal / W and the signal / Y. Is added to the connection node between the inductance 56 and the amplifier 40.

  The capacitance correction circuit 60 includes a phase comparator 64, an amplifier 62, a filter 63, and a PMOS transistor 61. The phase comparator 64 receives the signal W and the signal Y, compares the phases, and outputs a complementary signal having a voltage difference proportional to the phase difference. The amplifier 62 amplifies the voltage of the signal output from the phase comparator 64. For example, since the signal W or the signal Y is a clock signal, the phase difference between the signal W and the signal Y is about minus several degrees to plus several degrees when one period is 180 degrees.

  Therefore, in response to the phase difference between the signal W and the signal Y, the phase comparator 64 has a voltage of about minus several tens mV when the signal W is delayed compared to the signal Y, and the signal W is compared with the signal Y. Is advanced, a complementary signal having a voltage of about plus several tens mV is output. Then, the amplifier 62 receives the complementary signal, amplifies the voltage difference between the complementary signals, and adds a signal having a voltage of about 0.5 V to 0.9 V by adding an offset voltage to the back gate of the PMOS transistor 61. Output to.

The PMOS transistor 61 has a threshold value of about minus 0.3 V and is a PMOS transistor whose source, drain, and back gate are short-circuited.
Then, when the signal output from the amplifier 62 changes by about 0.5V to 0.9V, the gate voltage threshold value at which the PMOS transistor 61 is turned on changes from about 0.2V to about 0.6V, and the gate voltage further increases to increase the PMOS. When the transistor 61 starts to turn off, the capacitance between the gate and the source of the PMOS transistor 61 decreases suddenly.

  Here, when the phase of the signal W is delayed as compared with the signal Y, it is estimated that when the voltage applied to the gate of the NMOS transistor 45 of the amplifier 40 increases, the capacitance between the gate and the source changes. The Therefore, if the timing of decreasing the capacitance between the gate and the source of the PMOS transistor 61 is changed in the direction of 0.9 V and delayed, the capacitance between the gate and the source of the NMOS transistor 45 of the amplifier 40 is increased. It will prevent changes.

  On the other hand, when the phase of the signal W is earlier than that of the signal Y, it is estimated that when the voltage applied to the gate of the NMOS transistor 45 of the amplifier 40 increases, the capacitance between the gate and the source changes so as to decrease. The Therefore, if the timing of decreasing the capacitance between the gate and the source of the PMOS transistor 61 is changed in the direction of 0.5 V and advanced, the capacitance between the gate and the source of the NMOS transistor 45 of the amplifier 40 is reduced. It will prevent changes.

  Therefore, the timing at which the NMOS transistor 45 of the amplifier 40 is turned on and the timing at which the PMOS transistor 62 is turned off substantially coincide with each other so that the capacitance between the gate and the source does not change greatly before and after the threshold value of the NMOS transistor 45 of the amplifier 40. In addition, the timing for turning off the PMOS transistor 62 is controlled.

3A and 3B are diagrams for explaining the phase comparator 64 and the filter 63 included in the capacitance correction circuit 60. FIG.
FIG. 3A is a circuit diagram of the phase comparator 64. The phase comparator 64 includes resistors 641 and 642 and NMOS transistors 643, 644, 645, 646, 647, 648, and 649.

The resistor 641 and the NMOS transistor 643 are connected in series between the power supply Vdd and the drain of the NMOS transistor 645, and the first input terminal is connected to the gate electrode of the NMOS transistor 643. The signal Y is input to.
The resistor 642 and the NMOS transistor 644 are connected in series between the power supply Vdd and the drain of the NMOS transistor 645, and the first fixed potential is input to the gate electrode of the NMOS transistor 644.

The source of the NMOS transistor 645 is connected to the drain of the NMOS transistor 649, and the signal W is input to the gate electrode.
The drain of the NMOS transistor 646 is connected to the resistor 641 and the first output terminal, the source of the NMOS transistor 646 is connected to the drain of the NMOS transistor 648, and the gate electrode of the NMOS transistor 646 is the gate of the NMOS transistor 644. The first fixed potential is input while being connected to the electrode.

  The drain of the NMOS transistor 647 is connected to the resistor 642 and the second output terminal, the source of the NMOS transistor 647 is connected to the drain of the NMOS transistor 648, and the gate electrode of the NMOS transistor 647 has a first input terminal. The signal Y is input to the first input terminal.

The source of the NMOS transistor 648 is connected to the drain of the NMOS transistor 649, and the second fixed potential is input to the gate electrode.
A ground power supply is connected to the source of the NMOS transistor 649, and a bias having a third fixed potential is input to the gate electrode.

When the ratio of the current flowing through the first current path consisting of the resistor 641 and the NMOS transistor 646 and the current flowing through the second current path consisting of the resistor 642 and the NMOS transistor 647 does not consider the current flowing through the NMOS transistors 644 and 643, This corresponds to the first fixed potential and the positive signal potential of the complementary signal input to the first input terminal.
Here, the current path by the NMOS transistor 643 is in the first current path, the current path by the NMOS transistor 644 is in the second current path, and the logic “H” period of the signal input to the first input terminal, The connection is made during a period that overlaps the logic "H" period of the signal input to the two input terminals. Further, a current according to the potential of the reverse signal of the complementary signal input to the first input terminal flows through the current path by the NMOS transistor 643, and a current according to the first fixed potential flows through the current path by the NMOS transistor 644. I can run.
Then, in addition to the current to the NMOS transistor 646 and the NMOS transistor 647, the resistor 641 and the resistor 642 are input to the second input terminal during the logic “H” period of the signal input to the first input terminal. In a period that overlaps with the logic “H” period of the signal, current flows to the NMOS transistor 643 and the NMOS transistor 644. As a result, the potential at one end of the resistors 641 and 642 is the level of the signal input to the first input terminal and the signal input to the second input terminal in addition to the potential corresponding to the potential of the complementary signal being input. A potential corresponding to the phase difference is applied.
That is, the potential of the output signal is determined according to the phase difference of the rising edge of the clock signal input to the second input terminal with respect to the rising edge of the clock signal input to the first input terminal.

FIG. 3B is a circuit diagram illustrating an example of the filter 63. The filter 63 includes a resistor 631 and a capacitor 632. One end of the resistor 631 is connected to one of the input terminals, and the other end is connected to one end of the capacitor 632 and the first output terminal. The other end of the capacitor 632 is connected to the second input terminal and the second output terminal.
The filter 63 is a filter circuit that removes a high-frequency component from an input signal input from an input terminal. As a result, the DC component of the signal input to the filter 63 passes as it is, but the noise component is removed.

FIG. 4 is a diagram showing a change in capacitance of a node where the capacitance correction circuit 60 is connected to the power amplifier 3. The node of the power amplifier 3 connected to the capacitance correction circuit 60 is connected to the gate of the PMOS transistor 61 and the gate of the NMOS transistor 45 of the power amplifier 3.
FIG. 4 shows changes in the gate-source capacitance (Cgs) of the NMOS transistor 35 and the gate-source capacitance (Cgs) of the PMOS transistor 61 with respect to the potential of the node where the capacitance correction circuit 60 is connected to the power amplifier 3. It is shown. Further, the sum of the gate-source capacitance (Cgs) of the NMOS transistor 45 and the gate-source capacitance (Cgs) of the PMOS transistor 61 is also shown with respect to the node potential.

  The gate-source capacitance (Cgs) of the NMOS transistor 45 is about 4.0E-13 Farad when the node potential is around 0V, and 2.5E-13 toward the node potential near 0.3V. Decreases to about Farad. After that, when the threshold value of the NMOS transistor 45 near 0.3V is exceeded, it rapidly rises, and when the node potential becomes around 0.4V, it becomes about 4.0E-13 Farad. Thereafter, it gradually rises to about 5.0E-13 Farad as the node potential increases.

  The gate-source capacitance (Cgs) of the PMOS transistor 61 is about 5.0E-13 Farad when the node potential is around 0V, and does not change so much until the node potential is around 2.5V. About 0E-13 Farad. After that, when the potential of the node exceeds 2.5V and exceeds the threshold value of the PMOS transistor 61 near 2.5V, the gate-source capacitance (Cgs) decreases rapidly, and the node potential becomes near 0.3V. It will decrease to 3.5E-13 Farad. As the threshold value of the PMOS transistor 61 shifts, the point at which the capacitance of the PMOS transistor 61 rapidly decreases also shifts.

  The sum of the gate-source capacitance (Cgs) of the PMOS transistor 61 and the gate-source capacitance (Cgs) of the NMOS transistor 45 (substantially equal to the node capacitance) is 1 when the node potential is near 0V. About 5E-12 Farad, and the potential of the node decreases to about 8.5E-13 Farad toward 0.3V. When the node potential rises from 0.3 V to 0.4 V, the gate-source capacitance (Cgs) of the NMOS transistor 45 rises rapidly, and the gate-source capacitance (Cgs) of the PMOS transistor 61 sharply decreases. To do. Therefore, when the potential of the node rises from 0.3 V to 0.4 V, the sum (almost the capacity of the node) does not change abruptly and changes from 8.5E-13 Farad to 8.0E-13 Farad. To do. Furthermore, even if the potential of the node rises from 0.4 V to 0.6 V, their sum (almost the capacity of the node) remains 8.0E-13 Farad. After that, while the potential of the node is from 0.6V to 0.7V, their sum (approximately the capacitance of the node) slightly increases.

  Here, if the threshold value of the PMOS transistor 61 is changed from about 0.25 V to about 0.35 V by the operation of the capacitance correction circuit 60, the PMOS transistor 61 has a node potential in the range from 0.3 V to 0.4 V. The sum of the gate-source capacitance (Cgs) 61 and the gate-source capacitance (Cgs) of the NMOS transistor 45 changes as indicated by the black arrow indicating the oblique direction. As a result of circuit simulation for the power amplifier 3, the gate-source capacitance (Cgs) of the PMOS transistor 61 and the gate-source capacitance of the NMOS transistor 35 are represented by the line indicated by the vertex of the black triangle. It has been found that the phase difference between signal Y and signal W is minimized when the sum of (Cgs) changes. Accordingly, the capacitance correction circuit 60 controls the back gate potential of the PMOS transistor 61 so that the phase difference is minimized.

In the first embodiment, the threshold value of the PMOS transistor 61 is adjusted according to the phase difference between the complementary signal Y and the complementary signal W so as to minimize the phase difference. Then, as the gate potential rises, the capacitance between the gate and the source of the NMOS transistor 45 rapidly increases near the threshold value, but the capacitance between the gate and the source of the PMOS transistor 61 rapidly decreases at a similar potential point. Therefore, the sum of the capacitance between the gate and source of the NMOS transistor 45 and the capacitance between the gate and source of the PMOS transistor 61 is substantially constant. That is, the capacitance of the node connecting the gate of the NMOS transistor 45 and the gate of the PMOS transistor 61 is substantially constant.

  As a result, by comparing the phase of the complementary signal Y and the complementary signal W and adjusting the change point of the source-drain capacitance of the PMOS transistor 61 so as to reduce the phase difference, the gate and source of the NMOS transistor 45 are adjusted. Capacitance changes between are compensated.

  In the above amplifier circuit (power amplifier 3), the gate-source capacitance of the NMOS transistor 45 becomes substantially constant, the phase difference of the output signal with respect to the phase of the input signal of the power amplifier 3 decreases, and the adjacent channel leakage ratio (ACPR) ) Will improve.

  Since the transmission circuit (RF receiver 10) uses the amplification circuit (power amplifier 3), the adjacent channel leakage ratio (ACPR) is improved when a carrier wave is transmitted.

  FIG. 5 shows a power amplifier 80 according to the second embodiment. The power amplifier 80 includes an amplifier 20, an amplifier 30, an amplifier 40, transformers 50 and 58, and capacitance correction circuits 60 and 70. However, it differs from the power amplifier 3 in that the connection point between the capacity correction circuits 60 and 70 is between the amplifier 20 and the amplifier 30. That is, the power amplifier 80 of the second embodiment is a modification of the power amplifier 3 of the first embodiment.

  The operations of the capacitance correction circuits 60 and 70 operate as described in the first embodiment. Then, the nodes whose capacitance is corrected by the capacitance correction circuits 60 and 70 become the gate of the NMOS transistor 35 and the gate of the NMOS transistor 34 of the amplifier 30.

  As a result, the capacitance between the gate and the source of the NMOS transistor 35 of the amplifier 30 becomes a substantially constant value even if the potential of the complementary signal Y varies. Then, the change in the phase of the output signal with respect to the phase of the input signal of the power amplifier 80 is reduced, and the adjacent channel leakage ratio (ACPR) is improved.

FIG. 6 shows a power amplifier 100 according to the third embodiment. The power amplifier 100 includes an amplifier 20, an amplifier 30, an amplifier 40, transformers 50 and 58, and capacitance correction circuits 90 and 95.
Since the amplifier 20, the amplifier 30, the amplifier 40, and the transformers 50 and 58 are similar to the circuit described in the first embodiment, the description thereof is omitted.

  The input terminal of the power amplifier 100 is connected to the transformer 50, and the transformer 50 is connected to the amplifier 20. The amplifier 20 is connected to the amplifier 30 and is connected to the amplifier 40. The amplifier 40 is connected to the transformer 58, and the transformer 58 is connected to the output terminal of the power amplifier 100.

The capacitance correction circuit 90 includes an NMOS transistor 91, a resistor 92, and a resistor 93. The resistor 92 is connected between the back gate and the source of the NMOS transistor 91. The resistor 93 is connected between the back gate and the drain of the NMOS transistor 91.
The gate of the NMOS transistor 91 is connected to a bias power source. The voltage of the bias power supply is twice the threshold voltage of the NMOS transistor 91. The back gate of the NMOS transistor 91 is connected to a signal line that transmits the signal Z of the complementary signal Z output from the amplifier 30 to the amplifier 40. A signal line for transmitting the signal Z is connected to the gate of the NMOS transistor 45 of the amplifier 40.

The capacitance correction circuit 95 includes an NMOS transistor 96, a resistor 97, and a resistor 98. The resistor 96 is connected between the back gate and the source of the NMOS transistor 95. The resistor 97 is connected between the back gate and the drain of the NMOS transistor 95.
The gate of the NMOS transistor 95 is connected to a bias power source. The voltage of the bias power supply is a voltage twice the threshold value of the NMOS transistor 95. The back gate of the NMOS transistor 95 is connected to a signal line that transmits the signal / Z of the complementary signal Z output from the amplifier 30 to the amplifier 40. A signal line for transmitting the signal / Z is connected to the gate of the NMOS transistor 44 of the amplifier 40.

FIG. 7 shows the sum of the back gate-gate capacitance of the NMOS transistor 91 and the gate-source capacitance of the NMOS transistor 35 with respect to the potential of the signal line for transmitting the signal Z.
In FIG. 7, the dotted line shows the change of the sum of the gate-source capacitance of the PMOS transistor 61 and the gate-source capacitance of the NMOS transistor 45 shown in the first embodiment with respect to the potential of the signal line. The solid line shows the change of the sum of the back gate-gate capacitance of the NMOS transistor 91 and the gate-source capacitance of the NMOS transistor 45 with respect to the potential of the signal line.

As can be seen from the comparison between the solid line and the dotted line in FIG. 7, the sum of the capacitance between the gate and the source of the PMOS transistor 61 and the capacitance between the gate and the source of the NMOS transistor 45, and the capacitance between the back gate and the gate of the NMOS transistor 91. The sum of the capacitance between the gate and the source of the NMOS transistor 45 shows the same change. The reason is as follows.
First, when the voltage applied to the back gate of the NMOS transistor 91 is increased, the threshold value of the NMOS transistor 91 is shifted in the direction of increasing. Therefore, when the threshold voltage of the NMOS transistor 91 exceeds the bias voltage applied to the gate of the NMOS transistor 91, the capacitance between the back gate and the gate of the NMOS transistor 91 decreases rapidly. That is, the back gate voltage dependency of the capacitance between the back gate and the gate of the NMOS transistor 91 is the same as the gate voltage dependency of the capacitance between the gate and the source of the PMOS transistor 61. Therefore, the above conclusion is reached.

  By the way, when the resistors 92 and 93 are increased in the capacitance correction circuit 90, when the back gate voltage of the NMOS transistor 91 is increased as shown by the thick arrows in FIG. An increase in the sum of the capacitance and the capacitance between the gate and the source of the NMOS transistor 45 is suppressed. By increasing the resistance values of the resistors 92 and 93, it is presumed that the movement of charges is suppressed in a region where the back gate voltage is high, so that an increase in capacitance is also suppressed.

As described above, also in the power amplifier 100 of the third embodiment, the same effect as that of the power amplifier 3 of the first embodiment is produced.
In the first embodiment, the PMOS transistor 61 is used to correct a sudden capacitance change of the NMOS transistor 45, but in the third embodiment, the NMOS transistor 91 is used. Then, even if the process varies, the threshold value of the NMOS transistor 45 and the threshold value of the NMOS transistor 91 are in the same direction because they are the same NMOS transistor. As a result, even if the bias applied to the gate electrode of the NMOS transistor 91 is a constant value, the difference between the point where the capacitance of the NMOS transistor 45 changes suddenly and the point where the capacitance of the NMOS transistor 91 changes suddenly. Is estimated to be small.

  However, as shown in the fourth embodiment, if the phases of the complementary signal Y and the complementary signal W are compared and the bias is controlled by the phase difference, the capacitance between the back gate and the gate of the NMOS transistor 91 can be further increased. It is possible to prevent an abrupt change from occurring in the sum of the capacitance between the gate and source of the NMOS transistor 45.

FIG. 8 illustrates a power amplifier 120 according to the fourth embodiment. The power amplifier 120 includes an amplifier 20, an amplifier 30, an amplifier 40, transformers 50 and 58, and capacitance correction circuits 105 and 115.
Since the amplifier 20, the amplifier 30, the amplifier 40, and the transformers 50 and 58 are similar to the circuit described in the first embodiment, the description thereof is omitted.
The input terminal of the power amplifier 120 is connected to the transformer 50, and the transformer 50 is connected to the amplifier 20. The amplifier 20 is connected to the amplifier 30 and is connected to the amplifier 40. The amplifier 40 is connected to the transformer 58, and the transformer 58 is connected to the output terminal of the power amplifier 100.

The capacitance correction circuit 105 includes an NMOS transistor 106, a resistor 107, a resistor 108, an amplifier 109, a filter 110, and a phase comparator 111. The resistor 107 is connected between the back gate and the source of the NMOS transistor 106. The resistor 108 is connected between the back gate and the drain of the NMOS transistor 106.
The phase comparator 111 compares the phases of the signal Y in the complementary signal output from the amplifier 20 and the signal W in the complementary signal output from the amplifier 40, and outputs a voltage corresponding to the phase difference. . The filter 110 is a filter that blocks noise of the signal from the phase comparator 111. The amplifier 109 amplifies the output from the filter 110 and outputs a bias voltage to the gate of the NMOS transistor 106. Note that the bias voltage is a voltage value that varies in magnitude around a voltage that is twice the threshold value of the NMOS transistor 106. The gate of the NMOS transistor 106 is connected to the amplifier 109.
The back gate of the NMOS transistor 106 is connected to a signal line for transmitting the signal Z among the complementary signals output from the amplifier 30 to the amplifier 40. A signal line for transmitting the signal Z is connected to the gate of the NMOS transistor 45 of the amplifier 40.

The capacitance correction circuit 115 includes an NMOS transistor 116, a resistor 117, a resistor 118, an amplifier 119, a filter 120, and a phase comparator 121. The resistor 117 is connected between the back gate and the source of the NMOS transistor 116. The resistor 118 is connected between the back gate and the drain of the NMOS transistor 116.
The phase comparator 121 compares the phase of the signal / Y in the complementary signal output from the amplifier 20 with the signal / W in the complementary signal output from the amplifier 40, and outputs a voltage corresponding to the phase difference. Output. The filter 120 is a filter that blocks signal noise from the phase comparator 121. The amplifier 119 amplifies the output from the filter 120 and outputs a bias voltage to the gate of the NMOS transistor 119. Note that the bias voltage is a voltage value that varies in magnitude around a voltage that is twice the threshold value of the NMOS transistor 119. The gate of the NMOS transistor 116 is connected to the amplifier 119.

  The back gate of the NMOS transistor 116 is connected to a signal line for transmitting a signal / Z among complementary signals output from the amplifier 30 to the amplifier 40. A signal line for transmitting the signal / Z is connected to the gate of the NMOS transistor 44 of the amplifier 40.

  According to the power amplifier 120 of the fourth embodiment, a bias voltage that is approximately twice the threshold value is applied to the NMOS transistors 106 and 116, and thus the same effect as that of the power amplifier 100 of the third embodiment is produced. Further, in the power amplifier 120 according to the fourth embodiment, the bias voltage is increased or decreased according to the phase difference between the complementary signal Y and the complementary signal W with a voltage that is twice the threshold value of the NMOS transistors 106 and 116 as the center. Therefore, the point at which the capacitance between the back gate and the gate of the NMOS transistors 106 and 116 changes abruptly can be matched with the point at which the capacitance between the gate and the source of the NMOS transistors 45 and 44 changes abruptly. It is possible to prevent a sudden change in the sum of the back gate-gate capacitances of the NMOS transistors 106 and 116 and the gate-source capacitances of the NMOS transistors 35 and 34 as compared with the third power amplifier 100. .

  FIG. 9 is a diagram illustrating a power amplifier 200 according to the fifth embodiment. The power amplifier 200 includes amplifiers 210, 220 and 230, a capacity corrector 240, an oscillator 201, a transformer 202, a transformer 203, capacitors 204 and 205, an inductance 206, a capacitor 207, a transformer 208, and a resistor 209.

  The oscillator 201 is a circuit that generates a carrier wave. The transformer 202 is a transformer that transmits the carrier wave output from the oscillator 201 to the amplifier 210.

  The amplifier 210 amplifies the carrier wave and outputs it to the amplifier 220. The amplifier 220 amplifies the carrier wave and outputs it to the amplifier 230. The amplifier 230 is an amplifier that outputs the amplified carrier wave to the inductance 206. An inductance 206 is an inductance that transmits a signal to the capacitor 207. The capacitor 207 outputs a signal to the transformer 208.

  The capacitor 204 is a capacitor connected to the node between the amplifier 230 and the inductance 206 and the common line 203. The capacitor 205 is a capacitor connected to the node between the inductance 206 and the capacitor 207 and the common line 203a. The transformer 203b is a transformer that connects the common line 203a and the ground line.

  The capacity corrector 240 receives the signal output from the amplifier 210 and the signal output from the amplifier 230, compares the phase of both signals, and sets the capacity according to the phase difference between the two signals to that of the amplifier 220. Connect to node between amplifier 230. The capacitance corrector 240 includes a phase comparator 244, a filter 243, an amplifier 242, and a PMOS transistor 241, which are the same as the phase comparator 64, the amplifier 62, the filter 63, and the PMOS transistor 61 of the first embodiment. Omit the explanation.

  The amplifier 210 includes a capacitor 211, a resistor 212, an NMOS transistor 213, and an inductance 214. The input terminal of the amplifier 210 is connected to one end of the capacitor 211. The other end of the capacitor 211 is connected to one end of the resistor 212 and the gate of the NMOS transistor 213. The other end of the resistor 212 is connected to a bias. The source of the NMOS transistor 213 is connected to the common line 203a, and the drain is connected to one end of the inductance 214 and the output terminal. The other end of the inductance 214 is connected to the power line. The amplifier 210 amplifies the single layer input signal input from the input terminal by the NMOS transistor 213 and outputs the amplified signal from the output terminal.

The amplifier 220 is an amplifier similar to the amplifier 210. The amplifier 230 is an amplifier similar to the amplifier 230 except that the amplifier 230 does not include the resistor 212 and the capacitor 211 connected to the bias, which are connected to the input terminal.

As described above, the power amplifier 200 according to the fifth embodiment is the power amplifier 200 that amplifies the single layer carrier wave. Since the capacity corrector 240 for correcting the capacity between the amplifier 220 and the amplifier 230 is connected, the potential of the output signal from the amplifier 220 to the amplifier 23 changes as in the power amplifier 3 of the first embodiment. In addition, it is possible to suppress a change in the capacitance of the signal line between the amplifier 220 and the amplifier 230.

  According to the present invention, an amplifier circuit having an improved adjacent channel leakage ratio (ACPR) can be provided.

1 Antenna 2 Filter 3, 80, 100, 120, 200 Power Amplifier 4 VCO
5 PLL-FS
6 LPF
7 Baseband LSI
8 Display 9 Speaker 10 RF transceiver 20, 30, 40, 210, 220, 230 Amplifier 60, 70, 90, 95, 105, 115, 240 Capacity correction circuit

Claims (8)

A first amplifier that outputs a second complementary signal obtained by amplifying the first complementary signal ;
A second amplifier for outputting a third complementary signal obtained by amplifying the second complementary signal;
The first detects a phase difference between the complementary signal and the third complementary signal, the previous SL capacity increase or decrease the second complementary signal is added to the signal lines propagating receives at the gate the second complementary signal, the first And a capacitance correction circuit that reduces the phase difference by controlling timing for canceling the increase / decrease of the gate capacitance of the MOS transistor constituting the two amplifiers according to the voltage of the second complementary signal. Amplification circuit. A first amplifier that outputs a second complementary signal obtained by amplifying the first complementary signal ;
A second amplifier for outputting a third complementary signal obtained by amplifying the second complementary signal;
The first detects a phase difference between the complementary signal and the third complementary signal, the previous SL capacity increase or decrease the first complementary signal is added to the signal lines propagating receives at the gate the first complementary signal, the first And a capacitance correction circuit for reducing the phase difference by controlling timing for canceling the increase / decrease of the gate capacitance of the MOS transistor constituting one amplifier according to the voltage of the first complementary signal. Amplification circuit. A first amplifier that outputs a second complementary signal obtained by amplifying the first complementary signal;
A second amplifier comprising an NMOS transistor that outputs a third complementary signal obtained by amplifying the second complementary signal;
Detecting a phase difference between the first complementary signal and the third complementary signal and receiving the second complementary signal at a gate by increasing or decreasing a capacitance added to a signal line through which the second complementary signal propagates; A capacitance correction circuit that reduces the phase difference by controlling the timing to cancel the increase / decrease according to the voltage of the second complementary signal of the gate capacitance of the NMOS transistor of the amplifier,
The capacitance correction circuit includes:
A phase comparator that outputs a first signal having a voltage corresponding to the detected phase difference;
A filter that removes high-frequency noise from the first signal, a source, a drain, and a back gate are connected to each other, and the first signal after high-frequency noise removal is input to the back gate and the second to the gate. amplification circuit it, comprising a PMOS transistor, the one of the signal is input of the complementary signal. The capacitance correction circuit includes:
An NMOS transistor having a source, a drain, and a back gate connected to each other, and one of the second complementary signals is input to the back gate and a bias voltage is connected to the gate. The amplifier circuit according to claim 1. A first amplifier that outputs a second complementary signal obtained by amplifying the first complementary signal;
A second amplifier comprising an NMOS transistor that outputs a third complementary signal obtained by amplifying the second complementary signal;
Detecting a phase difference between the first complementary signal and the third complementary signal and receiving the second complementary signal at a gate by increasing or decreasing a capacitance added to a signal line through which the second complementary signal propagates; A capacitance correction circuit that reduces the phase difference by controlling the timing to cancel the increase / decrease according to the voltage of the second complementary signal of the gate capacitance of the NMOS transistor of the amplifier ,
The capacitance correction circuit includes:
A phase comparator that outputs a first signal having a voltage corresponding to the detected phase difference;
A filter for removing high frequency noise of the first signal, a source, a drain, and a back gate are connected to each other, and one of the second complementary signals is input to the back gate, and a high frequency is applied to the gate. amplification circuit comprising: the NMOS transistor, the said first signal after the noise removal inputted. A first amplifier for amplifying the first signal and outputting a second signal ;
A second amplifier for outputting a third signal obtained by amplifying the second signal;
Wherein detecting a phase difference between the first signal and the third signal, the previous SL capacity increase or decrease the second signal is added to the signal lines propagating receives at the gate the second signal, configuring the second amplifier And a capacitance correction circuit for reducing the phase difference by controlling timing for canceling the increase / decrease of the gate capacitance of the MOS transistor according to the voltage of the second signal . A first amplifier for amplifying the first signal and outputting a second signal;
A second amplifier comprising an NMOS transistor that outputs the third signal, obtained by amplifying the second signal;
An NMOS transistor of the second amplifier that detects a phase difference between the first signal and the third signal and receives the second signal at a gate by increasing or decreasing a capacitance added to a signal line through which the second signal propagates A capacitance correction circuit that reduces the phase difference by controlling the timing of canceling the increase / decrease of the gate capacitance according to the voltage of the second signal,
The capacitance correction circuit includes:
A phase comparator that outputs a fourth signal having a voltage corresponding to the detected phase difference;
A filter for removing high frequency noise of the fourth signal, the source, drain, and back gate connected to each other, together with the fourth signal after removing high-frequency noise is input to the back gate, the gate second amplification circuit you, comprising a PMOS transistor which signal is input. Baseband for converting data signals to radio signals;
A mixer that generates a first complementary carrier and modulates the first complementary carrier with the wireless signal;
An amplification circuit for amplifying the modulated first complementary carrier wave,
The amplifier is
A first amplifier that outputs a second complementary carrier wave obtained by amplifying the first complementary carrier wave;
A second amplifier for outputting a third complementary carrier wave obtained by amplifying the second complementary carrier wave;
The first complementary carrier is received by the gate by detecting a phase difference between the first complementary carrier and the third complementary carrier and increasing or decreasing the capacitance added to the signal line on which the second complementary carrier propagates. And a capacitance correction circuit for reducing the phase difference by controlling timing for canceling the increase / decrease of the gate capacitance of the MOS transistor constituting the first amplifier according to the voltage of the first complementary carrier wave. A transmission circuit characterized by the above.