FR3101215B1 - ADDITIONAL DATA STREAM FOR NOISE REDUCTION - Google Patents

ADDITIONAL DATA STREAM FOR NOISE REDUCTION Download PDF

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Publication number
FR3101215B1
FR3101215B1 FR1910458A FR1910458A FR3101215B1 FR 3101215 B1 FR3101215 B1 FR 3101215B1 FR 1910458 A FR1910458 A FR 1910458A FR 1910458 A FR1910458 A FR 1910458A FR 3101215 B1 FR3101215 B1 FR 3101215B1
Authority
FR
France
Prior art keywords
lower rate
data stream
data streams
group
rate data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1910458A
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French (fr)
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FR3101215A1 (en
Inventor
Nicolas Alain Paul Nodenot
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MACOM Technology Solutions Holdings Inc
Original Assignee
MACOM Technology Solutions Holdings Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MACOM Technology Solutions Holdings Inc filed Critical MACOM Technology Solutions Holdings Inc
Priority to FR1910458A priority Critical patent/FR3101215B1/en
Priority to EP20869266.5A priority patent/EP4035321A4/en
Priority to US17/008,303 priority patent/US11146340B2/en
Priority to CN202080066795.XA priority patent/CN114731167A/en
Priority to PCT/US2020/048817 priority patent/WO2021061348A1/en
Publication of FR3101215A1 publication Critical patent/FR3101215A1/en
Application granted granted Critical
Publication of FR3101215B1 publication Critical patent/FR3101215B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B15/00—Suppression or limitation of noise or interference
    • H04B15/005—Reducing noise, e.g. humm, from the supply
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving

Abstract

L’invention concerne un procédé et un système pour la réduction du bruit d’alimentation électrique, comprenant la réception d’un flux de données primaire à un certain débit de données, le flux de données primaire comprenant un flux de bits ayant des valeurs logiques égales à zéro ou à un ; puis la division du flux de données primaire pour créer un premier groupe de flux de données à plus bas débit et un deuxième groupe de flux de données à plus bas débit ; le traitement du deuxième groupe de flux de données à plus bas débit pour inverser les valeurs logiques des bits des flux de données à plus bas débit afin de créer des flux de données à plus bas débit traités ; la combinaison du premier groupe de flux de données à plus bas débit avec les flux de données à plus bas débit traités pour créer un flux de données complémentaire ; puis le traitement du flux de données primaire et du flux de données complémentaire simultanément par un système de traitement de données, le traitement simultané réduisant le bruit sur l’alimentation électrique.A method and system for power supply noise reduction includes receiving a primary data stream at a certain data rate, the primary data stream comprising a bit stream having logical values equal to zero or one; then dividing the primary data stream to create a first group of lower rate data streams and a second group of lower rate data streams; processing the second group of lower rate data streams to invert the logical values of the bits of the lower rate data streams to create processed lower rate data streams; combining the first group of lower rate data streams with the processed lower rate data streams to create a complementary data stream; then processing the primary data stream and the complementary data stream simultaneously by a data processing system, the simultaneous processing reducing noise on the power supply.

FR1910458A 2019-09-23 2019-09-23 ADDITIONAL DATA STREAM FOR NOISE REDUCTION Active FR3101215B1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
FR1910458A FR3101215B1 (en) 2019-09-23 2019-09-23 ADDITIONAL DATA STREAM FOR NOISE REDUCTION
EP20869266.5A EP4035321A4 (en) 2019-09-23 2020-08-31 Complementary data flow for noise reduction
US17/008,303 US11146340B2 (en) 2019-09-23 2020-08-31 Complementary data flow for noise reduction
CN202080066795.XA CN114731167A (en) 2019-09-23 2020-08-31 Complementary data streams for noise reduction
PCT/US2020/048817 WO2021061348A1 (en) 2019-09-23 2020-08-31 Complementary data flow for noise reduction

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1910458A FR3101215B1 (en) 2019-09-23 2019-09-23 ADDITIONAL DATA STREAM FOR NOISE REDUCTION
FR1910458 2019-09-23

Publications (2)

Publication Number Publication Date
FR3101215A1 FR3101215A1 (en) 2021-03-26
FR3101215B1 true FR3101215B1 (en) 2022-06-17

Family

ID=69743299

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1910458A Active FR3101215B1 (en) 2019-09-23 2019-09-23 ADDITIONAL DATA STREAM FOR NOISE REDUCTION

Country Status (5)

Country Link
US (1) US11146340B2 (en)
EP (1) EP4035321A4 (en)
CN (1) CN114731167A (en)
FR (1) FR3101215B1 (en)
WO (1) WO2021061348A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11515865B1 (en) * 2021-12-15 2022-11-29 Macom Technology Solutions Holdings, Inc. Serializer clock delay optimization

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6346832B1 (en) * 2000-05-22 2002-02-12 Motorola, Inc. Multi-channel signaling
JP4464189B2 (en) * 2004-04-28 2010-05-19 Ｎｅｃエレクトロニクス株式会社 Noise cancellation circuit
US7548174B2 (en) * 2007-10-04 2009-06-16 Avago Technologies Enterprise IP (Singapore) Pte. Ltd. System and method for equalizing transition density in an integrated circuit
US8225017B1 (en) 2007-10-17 2012-07-17 Marvell International Ltd. Method and apparatus for reducing power supply introduced data dependent jitter in high-speed SerDes transmitters
JP2009188489A (en) * 2008-02-04 2009-08-20 Nec Electronics Corp Transmission circuit and reception circuit for transmitting and receiving signals of plural channels
JP5260193B2 (en) * 2008-09-03 2013-08-14 ルネサスエレクトロニクス株式会社 Semiconductor integrated circuit and switching noise leveling method thereof
JP5505026B2 (en) 2010-03-29 2014-05-28 富士通株式会社 Amplifier circuit and transmission circuit including the amplifier circuit
KR101708822B1 (en) 2010-06-24 2017-02-22 페어차일드코리아반도체 주식회사 Interlock circuit and interlock system including the same
US9549232B1 (en) 2013-07-11 2017-01-17 Inphi Corporation Configurable multi-rate format for communication system for silicon photonics
WO2019003588A1 (en) * 2017-06-29 2019-01-03 パナソニックＩｐマネジメント株式会社 Noise cancel circuit and data transmission circuit

Also Published As

Publication number Publication date
WO2021061348A1 (en) 2021-04-01
US20210091861A1 (en) 2021-03-25
EP4035321A1 (en) 2022-08-03
US11146340B2 (en) 2021-10-12
CN114731167A (en) 2022-07-08
EP4035321A4 (en) 2023-11-29
FR3101215A1 (en) 2021-03-26

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