JPS6333910A - Fet amplifier - Google Patents

Fet amplifier

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Publication number
JPS6333910A
JPS6333910A JP17793586A JP17793586A JPS6333910A JP S6333910 A JPS6333910 A JP S6333910A JP 17793586 A JP17793586 A JP 17793586A JP 17793586 A JP17793586 A JP 17793586A JP S6333910 A JPS6333910 A JP S6333910A
Authority
JP
Japan
Prior art keywords
amplifier
phase
signal
control circuit
fet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17793586A
Other languages
Japanese (ja)
Inventor
Tomohiko Ono
智彦 小野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP17793586A priority Critical patent/JPS6333910A/en
Publication of JPS6333910A publication Critical patent/JPS6333910A/en
Pending legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

PURPOSE: To suppress the passing phase change in the entire FET amplifier by giving a phase signal extracted from two couplers to a control circuit controlling the phase of a 2nd amplifier through a phase detector detecting the phase difference of the coupler side and applying it further to a 2nd amplifier. CONSTITUTION:A coupler 6 is used to extract a little of microwave signal at an input signal terminal 2 and at an output signal terminal 3, the extracted signal is inputted to a phase detector 7 to detect the phase difference among input/output terminals 2-3. Since the phase detection signal does not drive a 2nd amplifier 4 as it is, the, signal is converted into a proper control signal in the control circuit 8 and then fed to the 2nd amplifier 4. That is, the phase change generated in a unit amplifier 1 is extracted by a phase detector 4 and the polarity of the phase change is inverted by the 2nd amplifier 4 through the control of the control circuit 6. Thus, the phase change as the entire FET amplifier is made zero.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、マイクロ波信号の位相補償機能を有するF
ET (を弁効果トランジスタ2増幅器に関するもので
ある。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides an F having a phase compensation function for microwave signals.
ET (is about a valve effect transistor 2 amplifier).

〔従来の技術〕[Conventional technology]

第3図は従来のIF11iT増幅器を示す一実施例であ
り1図中+1)IIi?1!:Tを用いた単位増幅器を
、(2)(3)は入力信号端子及び出力信号端子でおる
FIG. 3 shows an example of a conventional IF11iT amplifier, and +1) IIi? 1! : A unit amplifier using T is connected to (2) and (3) at the input signal terminal and output signal terminal.

従来の11!tTの中で、WK高レベルマイクロ波信号
の増幅を目的としてつくられたlFETFET増幅器 
?1!:T増幅器と対立する立場を有する進行波管増幅
器などに比較して数々の利点を有するため。
Conventional 11! lFETFET amplifier created for the purpose of amplifying WK high-level microwave signals in tT.
? 1! : Because it has many advantages compared to traveling wave tube amplifiers, etc., which are in opposition to T amplifiers.

その利用度が高まりつつある。Its usage is increasing.

利点としては、低位相変化・低飽和特性による低歪の実
現、固体素子を使用することによる信頼性の向上、小形
・軽量などがめげられ、利用分野として、上記利点を十
分に活用することができるマイクロ波による衛星通信回
線が大きな位置を占めている。
Advantages include low distortion due to low phase change and low saturation characteristics, improved reliability due to the use of solid-state elements, small size and light weight, and the above advantages can be fully utilized in the field of application. Satellite communication lines using microwave technology are playing a major role.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記のような従来のFET増幅器において2次のような
問題点があった。すなわち、上述のような高レベルマイ
クロ波信号を扱う増@器は、出力信号の電力レベルに応
じて消費電力が決定される。
The conventional FET amplifier as described above has a secondary problem. That is, the power consumption of the amplifier that handles high-level microwave signals as described above is determined according to the power level of the output signal.

ここでFFXTFET増幅器費電力、すなわち効率の高
い状態で動作させることが望ましいが、一方では効率の
上昇と増幅器の直線性とは相反している。この直線性が
効率に反して低下することを原因としてFET増幅器の
低歪性を損ない0位相特性をも悪化させるという問題点
を有していた。
Here, it is desirable to operate the FFXTFET amplifier at high power consumption, that is, high efficiency, but on the other hand, the increase in efficiency is at odds with the linearity of the amplifier. This reduction in linearity contrary to efficiency has caused a problem in that the low distortion of the FET amplifier is impaired and the 0 phase characteristics are also deteriorated.

第4図は、上述のFET増幅器の相対入力電力レベルに
対する位相特性並びに振@特性の一例である。振幅特性
は相対入力電力が増加するに従い相対出力電力が飽和す
る特性を示しており、ここで特に位相特性に着目すれば
、FET増幅器の直線性悪化に伴なって1位相変化量が
著しく増加していることがわかる。
FIG. 4 is an example of the phase characteristics and amplitude characteristics of the above-mentioned FET amplifier with respect to the relative input power level. The amplitude characteristics show that the relative output power saturates as the relative input power increases, and if we pay particular attention to the phase characteristics, the amount of change in one phase increases significantly as the linearity of the FET amplifier deteriorates. You can see that

この発明はかかる問題点を解決するためになされたもの
で、上記のようなFET増幅器の飽和に伴なう位相特性
の悪化を防ぎ9位相変化を抑えた上で効率の良好なPK
’!”増幅器を得ることを目的とする。
This invention was made in order to solve such problems, and it is possible to prevent the deterioration of the phase characteristics due to the saturation of the FET amplifier as described above, suppress phase changes, and provide a highly efficient PK.
'! ``The purpose is to obtain an amplifier.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係るFET増幅器は、FITを用いた従来の
第1の増幅器入力@に上記第1の増幅器に用いたFET
と異なるデュアルゲー)FETを用いた第2の増幅器を
続続した上、上記第2の増幅器入力端子と第!の増幅器
の出力端予告々にカプラを接続し、上記2台のカプラか
ら抽出した位相信号を9カプラ側の位相差を検出するた
めの位相検波器を通して上記第2の増幅器の位相を制御
する制御回路に接続後、上記第2の増幅器に印加するも
のである。
In the FET amplifier according to the present invention, the FET used in the first amplifier is connected to the conventional first amplifier input @ using FIT.
A second amplifier using a dual-gate FET (different from !) is connected in series, and the input terminal of the second amplifier and the second ! A coupler is connected to the output terminals of the amplifiers, and the phase signals extracted from the two couplers are passed through a phase detector to detect the phase difference on the coupler side, and the phase of the second amplifier is controlled. After connecting to the circuit, it is applied to the second amplifier.

〔作用〕[Effect]

この発明においては、従来の第1の増幅器に直列接続さ
れる第2の増幅器が、PET増幅器飽和時の位相変化に
応じて位相調節を行う。
In this invention, the second amplifier connected in series to the conventional first amplifier performs phase adjustment in accordance with the phase change when the PET amplifier is saturated.

〔実施例〕〔Example〕

W、1図はこの発明の一実施例を示す構成図であり1図
中(1)〜(3)は従来の装置と全(同一のものである
。(4)は従来の第1の増幅器に直列に接続され。
W. Figure 1 is a configuration diagram showing an embodiment of the present invention. In Figure 1, (1) to (3) are all the same as the conventional device. (4) is the conventional first amplifier. connected in series with.

かつ上記第1の増幅器に用いられたFITと異なるデュ
アルゲー)IFETを用いた第2の増幅器。
and a second amplifier using a dual-gate IFET different from the FIT used in the first amplifier.

(5)は上記第1の増幅器の出力端子と第2の増幅器の
入力端子に接続された2台のカプラ、(6)はカプラの
反射端子終端器、(71Fi上記2台のカプラ(5)か
ら取り出される信号を混合し位相差成分を取り出すとこ
ろの位相検波器、(8)は上記位相検波器(7)からの
信号を制御信号に変換し上記デュアルゲートFF1T増
・福器14)に印加するための制御回路である。
(5) are two couplers connected to the output terminal of the first amplifier and the input terminal of the second amplifier, (6) is the reflective terminal terminator of the coupler, (71Fi) the two couplers (5) A phase detector (8) mixes the signals extracted from the phase detector and extracts the phase difference component, and converts the signal from the phase detector (7) into a control signal and applies it to the dual gate FF1T amplifier 14). This is a control circuit for

第2図は上記の実施例で示した第2の増幅器+4)の内
部構成例でろり、 +21+311/i従来の装置と相
当のものを、(9)は直流バイアスが必要部外の回路に
流出する事を防ぐブロックコンデンサ、 C1Gはマイ
クロ波信号がバイアス簡に流出することを防ぐチョーク
コイル、(IυはデュアルゲートPIT、(Ir!Jは
デュγルゲー)PETflllのドレインバイアス端子
Figure 2 shows an example of the internal configuration of the second amplifier +4) shown in the above embodiment, which is equivalent to the conventional device. C1G is a choke coil that prevents the microwave signal from easily leaking out of the bias, (Iυ is a dual gate PIT, (Ir!J is a dual gate) PET flll drain bias terminal.

(1311d第1ゲートバイアス端子、0は制御回路(
5)からの信号をデュアルゲー) F E T Cl1
lの第2ゲートに印加するための制御端子である。
(1311d first gate bias terminal, 0 is the control circuit (
5) Dual game) FET Cl1
This is a control terminal for applying voltage to the second gate of l.

上記のように構成されたF’ET増幅器において。In the F'ET amplifier configured as described above.

@1図で示した単位増幅器(1)は入力信号端子(2)
のマイクロ波信号電力が増加するに従い次第に後段(1
つ から入力段に向かって飽和する。この際。
@1 The unit amplifier (1) shown in the diagram is the input signal terminal (2)
As the microwave signal power of
It saturates from the beginning toward the input stage. On this occasion.

振幅の飽和と共に単位増幅器(1)を通過する信号の位
相が変化することは従来回路で説明した通りである。
As explained in the conventional circuit, the phase of the signal passing through the unit amplifier (1) changes as the amplitude saturates.

カプラ(61は、入力信号端子(2)及び出力信号端子
(3)の部分のマイクロ波信号を少量抽出するためのも
ので、抽出信号は位相検波器())に入力されて入出力
端子(2)〜(3)間の位相差を横用する。位相検出信
号はそのままでは第2の増幅器14)を駆動することが
できないため、制御回路(8)において適当な制御信号
に変換後、第2の増幅器(4)に印加される。
The coupler (61) is for extracting a small amount of the microwave signal at the input signal terminal (2) and output signal terminal (3), and the extracted signal is input to the phase detector ()) and is input to the input/output terminal ( The phase difference between 2) and (3) is used laterally. Since the phase detection signal cannot directly drive the second amplifier 14), it is converted into an appropriate control signal in the control circuit (8) and then applied to the second amplifier (4).

すなわち、単位増幅器+1)で発生した位相の変化とい
うものを位相検波器(4)で取出し、その位相の変化量
の極性を逆にしたものを第2の増幅器(4)で作咬田す
よう制御回路(61で制御するなら、FET増@器全体
としての位相変化量を零にすることが可能となる。ここ
で第2図は、上記の制御回路(8]の信号を受けて動作
する第2の増幅器(4)の内部である。増幅器(4)は
制御端子α4に印加された電圧に応じ、デュアルゲート
FKTQIIのゲートーソース間接合容量を変化させる
事によって、デュアルゲートFITα11を通過するマ
イクロ波信号の位相を調節することが可能であり、デュ
アルゲート?KTαガの増幅機能と相まって、良好な移
相増幅器を構成する。
In other words, the phase change generated in the unit amplifier +1) is extracted by the phase detector (4), and the polarity of the phase change is reversed and detected by the second amplifier (4). If controlled by the control circuit (61), it is possible to make the amount of phase change of the entire FET amplifier zero. Here, FIG. This is the inside of the second amplifier (4).The amplifier (4) changes the gate-source junction capacitance of the dual gate FKTQII according to the voltage applied to the control terminal α4, thereby allowing the microwave to pass through the dual gate FITα11. It is possible to adjust the phase of the signal, and when combined with the amplification function of the dual gate KTα, it constitutes a good phase shift amplifier.

〔発明の効果〕〔Effect of the invention〕

この発明は以上の説明通り、従来の第1の増幅器を通過
するマイクロ波信号の位相を2台のカプラと位相検波器
を用いて検出し、この検出信号を用いて上記従来の増@
器に使用されたと異なるデュアルゲー)FETを用りた
第2の増幅器を駆動する構成によって、FET増幅器全
体の通過位相変化を抑圧するという効果を有する。
As explained above, the present invention detects the phase of the microwave signal passing through the conventional first amplifier using two couplers and a phase detector, and uses this detection signal to detect the phase of the microwave signal passing through the conventional first amplifier.
The configuration of driving the second amplifier using a dual-gate FET (different from that used in the FET amplifier) has the effect of suppressing the change in the passing phase of the entire FET amplifier.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例を示す構成図、@2図は第
1図で示したデュアルゲートFE’!’を用いた第2の
増幅器の内部構成例、第3図、第4図は従来のFET増
幅器を示す構成図とその位相・振幅特注例である。 図において、(1)は準位増幅器、 +21f3Lld
入力信号及び出力信号端子、14)は第2の増幅器、(
5)はカプラ、(6)はv!:端器、(7)は位相検波
器、(8)は制御回路。 (9)はブロックコンデンサ、顛はチョークコイル。 αBはデュアルゲー)FET、α2けドレインバイアス
端子、α9は第1ゲートバイアス端子、(14は制御端
子である。 尚、各図中同一符号は同一または相当部分を示す。 代職人大岩増雄 第1図 1:単位1幅器 7:壮稽旅表籠 第2Ef!J 11:テ)−フルケ―トFE丁 14:制@燗子 @ 3 刃 第 4 図 −20−15−do  −50 相対°入力電力 (dB)
Fig. 1 is a block diagram showing one embodiment of the present invention, and Fig. 2 is a dual gate FE'! shown in Fig. 1. FIG. 3 and FIG. 4 are block diagrams showing a conventional FET amplifier and an example of a custom-made phase and amplitude thereof. In the figure, (1) is a level amplifier, +21f3Lld
The input signal and output signal terminals, 14) are connected to the second amplifier, (
5) is coupler, (6) is v! : Terminal, (7) is a phase detector, (8) is a control circuit. (9) is a block capacitor, and the other is a choke coil. αB is a dual gate) FET, α2 is a drain bias terminal, α9 is a first gate bias terminal, (14 is a control terminal. In addition, the same reference numerals in each figure indicate the same or corresponding parts. Masuo Oiwa, a craftsman No. 1 Figure 1: Unit 1 Width 7: Sougeki Tabi Omote Kago No. 2 Ef!J 11: Te) - Furukate FE Ding 14: Control @ 燗子 @ 3 Blade No. 4 Figure 20-15-do -50 Relative degree input power (dB)

Claims (1)

【特許請求の範囲】[Claims] FET(電界効果トランジスタ)を用いて構成された多
段の第1の増幅器と、上記第1の増幅器の入力側に直列
接続され、かつ上記第1の増幅器に用いられたFETと
異なるデュアルゲートFETを用いた第2の増幅器と、
上記第2の増幅器の入力端子と上記第1の増幅器の出力
端子の各々に接続された2台のカプラと、上記2台のカ
プラに接続されカプラ間の位相差を検出するための位相
検波器と、上記位相検波器と第2の増幅器に接続されか
つ上記第2の増幅器の位相を制御するための制御回路と
を備えたことを特徴とするFET増幅器。
A multistage first amplifier configured using FETs (field effect transistors), and a dual gate FET connected in series to the input side of the first amplifier and different from the FET used in the first amplifier. a second amplifier used;
two couplers connected to each of the input terminal of the second amplifier and the output terminal of the first amplifier; and a phase detector connected to the two couplers for detecting a phase difference between the couplers. and a control circuit connected to the phase detector and the second amplifier and for controlling the phase of the second amplifier.
JP17793586A 1986-07-29 1986-07-29 Fet amplifier Pending JPS6333910A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17793586A JPS6333910A (en) 1986-07-29 1986-07-29 Fet amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17793586A JPS6333910A (en) 1986-07-29 1986-07-29 Fet amplifier

Publications (1)

Publication Number Publication Date
JPS6333910A true JPS6333910A (en) 1988-02-13

Family

ID=16039637

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17793586A Pending JPS6333910A (en) 1986-07-29 1986-07-29 Fet amplifier

Country Status (1)

Country Link
JP (1) JPS6333910A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5424015A (en) * 1992-09-29 1995-06-13 Yamashita Rubber Kabushiki Kaisha Method and device for manufacturing rubber bend pipe
JP2011211410A (en) * 2010-03-29 2011-10-20 Fujitsu Ltd Amplifying circuit and transmission circuit including amplifying circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5424015A (en) * 1992-09-29 1995-06-13 Yamashita Rubber Kabushiki Kaisha Method and device for manufacturing rubber bend pipe
JP2011211410A (en) * 2010-03-29 2011-10-20 Fujitsu Ltd Amplifying circuit and transmission circuit including amplifying circuit

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