JP5496001B2 - Class D amplifier circuit - Google Patents

Description

  The present invention relates to a class D amplifier circuit in which a power supply voltage value of a PWM modulation circuit and a power supply voltage value of an output circuit are different.

  FIG. 2 shows the configuration of a conventional class D amplifier circuit and its peripheral circuits. The entire circuit includes a class D amplifier circuit 10, a speaker 50, a battery B1 such as a lithium ion battery, a regulator 60 that steps down the voltage VDD1 of the battery B1 and outputs a voltage VDD2, and a capacitor that stabilizes the voltage VDD1 of the battery B1. C1, a capacitor C2 for stabilizing the output voltage VDD2 of the regulator 60, and the like. A class D amplifier circuit 10 receives an analog audio signal and converts it into a PWM signal, a PWM conversion circuit 20 that outputs the PWM signal, an output circuit 30 that amplifies the PWM signal, and a PWM signal that is output from the output circuit 30 by filtering the analog signal. The PWM conversion circuit 20 and the output circuit 30 operate using the output voltage VDD2 of the regulator 60 as a power supply voltage.

  By the way, with the spread of portable devices, the class D amplifier circuit 10 is required to realize low power consumption while maintaining high output. As a method for realizing this, as shown in FIG. 3, there is a method in which supply power supply voltages to the PWM modulation circuit 20 and the output circuit 30 of the class D amplifier circuit 10 are made different. Specifically, a method of supplying the output voltage VDD2 (eg, 1.8V) of the regulator 60 as the power supply voltage of the PWM modulation circuit 10 and supplying the voltage VDD1 (eg, 3.7V) of the battery B1 to the output circuit 30. There is. By adopting such a method, PWM modulation is performed by setting the power supply voltage of the PWM modulation circuit 20 as low as 1.8 V while maintaining the high output by generating the amplitude of the output voltage from the power supply of 3.7 V. The power consumption of the circuit 20 can be minimized.

FIG. 4 shows a general circuit configuration of the class D amplifier circuit 10. The PWM modulation circuit 20 includes an integration circuit 21 composed of an OP amplifier 211, a resistor _RIN, and a capacitor _CFB , a comparator 22, an oscillation circuit 23, and a reference voltage generation circuit 24. The output circuit 30 includes a level shifter 31, a pre-driver 32, and a power transistor stage 33. R _FB is a feedback resistor.

The analog audio signal voltage _VIN is integrated by the integrating circuit 21 to become an integrated voltage V1. The integrated voltage V1 is compared with the triangular wave voltage output from the oscillation circuit 23 by the comparator 22, and becomes a PWM modulation signal voltage V2 which is a rectangular wave having two values of VDD2 and VSS. The voltage V2 becomes the voltage V3 level-converted by the level shifter 31 into a rectangular wave composed of two values of VDD1 and VSS. The voltage V3 is buffered by the pre-driver 32 and is output from the power transistor stage 33 as the output voltage Vout. Then, the high-frequency component is cut from the output voltage Vout by the filter circuit 40 to become a demodulated analog signal voltage Vspk, and the speaker 50 is driven. The waveforms of the respective parts of the class D amplifier circuit 10 are shown in FIG. This type of circuit configuration is disclosed in Patent Document 1. Further, a circuit configuration used with two power supplies is described in Patent Document 2.

  Next, operations of the oscillation circuit 23 and the reference voltage generation circuit 24 will be described with reference to FIGS. FIG. 6 is a block diagram of the oscillation circuit 23. The oscillation circuit 23 includes comparators 231 and 232, an RS flip-flop 233, a PMOS transistor MP7, an NMOS transistor MN7, and a capacitor C3. The operation of the oscillation circuit 23 is divided into a charging period and a discharging period of the capacitor C3. Further, a current source that discharges the current Iosc1 is connected to the source of the transistor MP7, and a current source that sucks the current Iosc2 is connected to the source of the transistor MN7.

  During the charging period, the Q output of the RS flip-flop 233 is at a low level. At this time, since the transistor MP7 is in the ON state, the capacitor C3 is charged by the current Iosc1, and the oscillation voltage Vosc rises. When the oscillation voltage Vosc reaches the reference voltage Vref2 of the comparator 232, the output of the comparator 232 changes from low level to high level. This high level voltage is input to the S input of the RS flip-flop 233. As a result, the Q output of the RS flip-flop 233 changes from the low level to the high level. Therefore, the transistor MP7 is turned off, the MN7 is turned on, and the oscillation circuit 23 shifts to the discharge period.

  In the discharge period, since the transistor MN7 is in the on state, the charge of the capacitor C3 is discharged by the current Iosc2, and the oscillation voltage Vosc drops. When the oscillation voltage Vosc reaches the reference voltage Vref1 of the comparator 231, the output of the comparator 232 changes from low level to high level. This high level voltage is input to the R input of the RS flip-flop 233. As a result, the Q output of the RS flip-flop 233 changes from the high level to the low level. Therefore, the transistor MP7 is turned on, the MN7 is turned off, and the oscillation circuit 23 shifts to the charging period.

ここで、Ｉosc１＝Ｉosc２＝Ｉoscであれば、式(１）は式（２）となり、発振周波数ｆoscは電流源電流Ｉoscに比例する。

The oscillation circuit 23 outputs a triangular wave oscillation voltage Vosc as shown in FIG. 7 by repeating the above charging period and discharging period. The oscillation frequency fosc of this triangular wave oscillation voltage Vosc is expressed by equation (1).

Here, if Iosc1 = Iosc2 = Iosc, Equation (1) becomes Equation (2), and the oscillation frequency fosc is proportional to the current source current Iosc.

  FIG. 8 shows a conventional configuration of the reference voltage generation circuit 24 that generates the reference voltages Vref1 and Vref2 input to the comparators 231 and 232 of the oscillation circuit 23. Reference resistors Vref1 and Vref2 are generated by dividing the potential difference between the power supply voltage VDD1 and the ground voltage VSS by the resistors.

US Pat. No. 6,262,632 US Pat. No. 7,262,658

By the way, since the power supply voltage VDD1 is a voltage supplied from the battery B1, as shown in FIG. 9, its value decreases as time passes. On the other hand, since the power supply voltage VDD2 is supplied from the regulator 60, the value is maintained until VDD1 = VDD2. When the power supply voltage VDD1 decreases, the cut-off frequency fc of the PWM modulation circuit 20 decreases. fc is expressed as in Equation (3). A _M is the modulation gain of the comparator 22, and A _LS is the voltage gain of the level shifter 31.

At this time, the modulation gain A _M maintains a constant value, but the voltage gain A _LS decreases with a decrease in the voltage VDD1, so that the cut-off frequency fc decreases from the above equation (3), and the class D amplifier circuit 10 High-frequency playback ability declines. For this reason, there is a problem that the sound quality is deteriorated as the voltage of the battery B1 is lowered.

  FIG. 10 shows the frequency characteristics of the gain of the class D amplifier circuit 10. The cut-off frequency fc, human audible frequency (20 kHz), and oscillation frequency fosc of the oscillation circuit are shown on the frequency axis. As shown in the figure, the cut-off frequency fc needs to be 20 kHz or more and fosc / 2 or less. When the voltage VDD1 of the battery B1 decreases, the cut-off frequency fc decreases, and when it becomes 20 kHz or less, the high frequency component in the audible range of the input signal is attenuated.

  The object of the present invention is to directly connect the output circuit to the battery in order to achieve both high output and low power consumption, and when the power supply voltage of the PWM modulation circuit is connected to the low voltage output from the regulator, the battery voltage decreases. Even in such a case, it is to provide a class D amplifier circuit that solves the above-described problems by maintaining a constant cutoff frequency.

To achieve the above object, the invention according to claim 1 operates at the second power supply voltage, compares the voltage corresponding to the input analog signal voltage with the triangular wave voltage generated by the oscillation circuit, and compares the PWM signal voltage. A PWM modulation circuit that generates a first power supply voltage higher than the second power supply voltage, and the level of the PWM signal voltage output from the PWM modulation circuit is changed from the second power supply voltage to the first power supply voltage. e Bei and an output circuit for amplifying the converted level of the supply voltage, the amplitude of the triangular wave voltage generated by the oscillation circuit, D grade was set to vary in proportion to the value of the first power supply voltage in the amplifier circuit, the oscillator circuit when said triangular wave voltage is lower than the second reference voltage to charge the capacitor with the first current, the said capacitor and the triangular wave voltage is increased to a second reference voltage second When the triangular wave voltage is lowered to a first reference voltage lower than a second reference voltage, the capacitor is charged with the first current, and the operation is repeated thereafter to discharge the voltage with the current. Is the triangular wave voltage, the first and second currents are generated in proportion to the value of the first power supply voltage, an intermediate voltage is generated in proportion to the second power supply voltage, and the first The reference voltage is generated so that a current corresponding to the first current flows through the first resistor to be a voltage lower than the intermediate voltage by a predetermined amount, and the second reference voltage is A current having a value corresponding to the second current flows through a second resistor having the same value as the first resistor, thereby generating a voltage that is higher than the intermediate voltage by the predetermined amount. And

  According to the present invention, since the amplitude of the triangular wave voltage generated by the oscillation circuit changes in proportion to the value of the first power supply voltage, even if the first power supply voltage fluctuates, the cutoff of the class D amplifier circuit The frequency is automatically controlled so as to maintain a constant value. Therefore, in a battery-driven class D amplifier circuit, even when the output circuit is directly connected to the battery in order to achieve both high output and low power consumption, and connected to the low voltage output from the regulator as the power supply voltage of the PWM modulation circuit, Regardless of changes in the output voltage of the battery over time, it is possible to maintain a high frequency reproduction capability. Further, even if the first power supply voltage fluctuates, the oscillation frequency of the oscillation circuit is automatically controlled so as to maintain a constant value.

It is a circuit diagram of the reference voltage generation circuit of the Example of this invention. It is a block diagram which shows the structure of the conventional class D amplifier circuit and its peripheral circuit. It is a block diagram which shows the structure of the conventional class D amplifier circuit aiming at low voltage and high output, and its peripheral circuit. It is a circuit diagram which shows the circuit structure of the conventional class D amplifier circuit. FIG. 5 is a waveform diagram showing operation waveforms of each part of the class D amplifier circuit of FIG. 4. FIG. 5 is a circuit diagram showing a configuration of an oscillation circuit of the class D amplifier circuit of FIG. 4. FIG. 7 is a waveform diagram showing an output waveform of the oscillation circuit of FIG. 6. FIG. 5 is a circuit diagram showing a configuration of a reference voltage generation circuit of the class D amplifier circuit of FIG. 4. It is a figure which shows the time change of the power supply voltage supplied to the class D amplifier circuit of FIG. It is a frequency characteristic figure which shows the stable operation conditions of a class D amplifier circuit.

  FIG. 1 shows a reference voltage generation circuit 24 according to one embodiment of the present invention. The reference voltage generation circuit 24 receives a power supply voltage VDD1 and a voltage VDD2 obtained by stepping down the voltage VDD1 with the regulator 60. 241, 242, 243 are operational amplifiers, MP1, MP2, MP3, MP4, MP5 are PMOS transistors, MN1, MN2, MN3, MN4, MN5 are NMOS transistors, R1, R2, R3, R4, R5, R6, R7 are resistors is there.

となる。この電圧Ｖref０と抵抗Ｒ３によって流れる電流Ｉref０は、

となり、電圧ＶＤＤ１に比例した電流となる。 Hereinafter, the operation of the reference voltage generation path 24 of FIG. 1 will be described. First, the voltage VDD 1 is divided by the resistors R 1 and R 2 and input to the non-inverting input terminal of the operational amplifier 241. When R1 = R2, a voltage of VDD1 / 2 is input to the non-inverting input terminal of the operational amplifier 241. This voltage VDD1 / 2 is negatively fed back by the operational amplifier 241 and the transistor MN1, and appears at the source of the transistor MN1. If this voltage is Vref0,

It becomes. The current Iref0 flowing through the voltage Vref0 and the resistor R3 is

Thus, the current is proportional to the voltage VDD1.

  This current Iref0 is copied by a current mirror made up of transistors MP1, MP2, MN2, and MN3 to generate a current Iref1, and is copied by a current mirror made up of transistors MP1, MP2, and MP3 to generate a current Iref2. . At this time, Iref1 = Iref2 is set. Of these, the current Iref1 flows through the resistor R6, and the current Iref2 flows through the resistor R7.

となる。この中間電圧Ｖcomは、オペアンプ２４２とトランジスタＭＮ４によって負帰還をかけられ、トランジスタＭＮ４のソースに表れる。同じように、中間電圧Ｖcomは、オペアンプ２４３とトランジスタＭＰ４によって負帰還をかけられ、トランジスタＭＰ４のソースに表れる。そして、電流Ｉref１と抵抗Ｒ６によって、中間電圧Ｖcomから「Ｉref１×Ｒ６」だけ電圧降下シフトされた基準電圧Ｖref１が、トランジスタＭＮ３のドレインから出力される。また、電流Ｉref２と抵抗Ｒ７によって、中間電圧Ｖcomから「Ｉref２×Ｒ７」だけ電圧上昇シフトされた基準電圧Ｖref２が、トランジスタＭＰ３のドレインから出力される。これらの基準電圧Ｖref１、Ｖref２は、図６に示した発振回路２３に入力する。 On the other hand, the voltage VDD2 is divided by the resistors R4 and R5, and the intermediate voltage Vcom is generated. If R4 = R5,

It becomes. This intermediate voltage Vcom is negatively fed back by the operational amplifier 242 and the transistor MN4, and appears at the source of the transistor MN4. Similarly, the intermediate voltage Vcom is negatively fed back by the operational amplifier 243 and the transistor MP4, and appears at the source of the transistor MP4. Then, the reference voltage Vref1 that is shifted by “Iref1 × R6” from the intermediate voltage Vcom by the current Iref1 and the resistor R6 is output from the drain of the transistor MN3. In addition, the reference voltage Vref2 that is voltage-shifted by “Iref2 × R7” from the intermediate voltage Vcom by the current Iref2 and the resistor R7 is output from the drain of the transistor MP3. These reference voltages Vref1 and Vref2 are input to the oscillation circuit 23 shown in FIG.

  The current Iref0 is copied by a current mirror composed of transistors MP1, MP2 and MP5, so that a current Iosc1 is output. Likewise, the current Iref0 is copied by a current mirror composed of transistors MP1, MP2, MN2, and MN5, so that a current Iosc2 is output. At this time, Iref0 = Iosc1 = Iosc2 is set. These currents Iosc1 and Iosc2 are input to the oscillation circuit 23 shown in FIG.

Since the currents Iref1 and Iref2 are proportional to the value of the voltage VDD1, the shift amounts of the reference voltages Vref1 and Vref2 from the intermediate voltage Vcom are the same, and are proportional to the value of the voltage VDD1. Therefore, by inputting the reference voltages Vref1 and Vref2 to the oscillation circuit 23, the voltage amplitude of the triangular wave can be made proportional to the value of the voltage VDD1. At this time, the modulation gain _{A M} of the PWM modulation circuit 20 is expressed by the relationship of formula (7). “Vref−Vcom” in Expression (7) is a shift amount. Vref is Vref1 or Vref2.

For example, when the voltage VDD1 is doubled, the voltage gain _{A LS} of the level shifter 31 is doubled, the shift amount (= Vref-Vcom) is doubled, modulation gain of the PWM modulation circuit 20 _{A M} Is automatically controlled to be ½ from the above equation (7). As a result, the cut-off frequency fc shown in Expression (3) can be kept constant regardless of the fluctuation of the voltage VDD1.

  Since Iref0 = Iosc1 = Iosc2, the currents Iosc1 and Iosc2 are proportional to VDD1. Therefore, even if the shift amount (= Vref−Vcom) is doubled by doubling the voltage VDD1, automatic control is performed so that Iosc1 = Iosc2 is doubled. From the relational expression of fosc, the oscillation frequency fosc can be kept constant.

  As a result, in the battery-driven class D amplifier circuit, in order to achieve both high output and low power consumption, the output circuit 30 is directly connected to the battery, and the power supply voltage of the PWM modulation circuit 20 is output from the regulator 60 as the low voltage VDD2. Even when connected to, the cut-off frequency fc can be made constant regardless of the time change of the output voltage VDD1 of the battery, the high frequency reproduction capability can be maintained, and the oscillation frequency of the oscillation circuit can be made constant. Can keep. Also, when VDD1 = VDD2, VDD2 begins to attenuate, so the automatic control of the present invention does not function. However, a decrease in the remaining battery level is detected immediately before reaching VDD1 = VDD2, and the class D amplifier circuit 10 If a mechanism that stops the operation is provided separately, no trouble occurs.

10: Class D amplification circuit 20: PWM modulation circuit, 21: integration circuit, 211: operational amplifier, 22: comparator, 23: oscillation circuit, 231, 232: comparator, 233: RS flip-flop, 24: reference voltage generation circuit, 214 243: operational amplifier 30: output circuit, 31: level shifter, 32: pre-driver, 33: power transistor stage 40: filter circuit 50: speaker 60: regulator

Claims (1)

A PWM modulation circuit that operates at a second power supply voltage and generates a PWM signal voltage by comparing a voltage corresponding to an input analog signal voltage with a triangular wave voltage generated by an oscillation circuit; and higher than the second power supply voltage An output circuit which operates with a first power supply voltage and amplifies the PWM signal voltage output from the PWM modulation circuit after converting the level of the PWM power supply voltage from the second power supply voltage to the level of the first power supply voltage. In the class D amplifier circuit, the amplitude of the triangular wave voltage generated by the oscillation circuit is changed in proportion to the value of the first power supply voltage.
The oscillation circuit charges the capacitor with the first current when the triangular wave voltage is lower than the second reference voltage, and discharges the capacitor with the second current when the triangular wave voltage rises to the second reference voltage. When the triangular wave voltage drops to a first reference voltage lower than a second reference voltage, the capacitor is charged with the first current, and thereafter, this operation is repeated, and the voltage of the capacitor is changed to the triangular wave voltage. age,
The first and second currents are generated in proportion to the value of the first power supply voltage,
An intermediate voltage is generated in proportion to the second power supply voltage;
The first reference voltage is generated so that a current corresponding to the first current flows through the first resistor to be a voltage lower than the intermediate voltage by a predetermined amount,
The second reference voltage is set to a voltage that is higher than the intermediate voltage by the predetermined amount when a current having a value corresponding to the second current flows through a second resistor having the same value as the first resistor. Generated in the
A class D amplifier circuit.

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