JP5495174B2 - Signal generating apparatus, image reading apparatus, image forming apparatus, and signal generating method - Google Patents

Description

  The present invention relates to a signal generator including a phase synchronization circuit, and more specifically, a signal generator capable of setting output characteristics including a multiplication setting, an image reading apparatus including the signal generator, an image forming apparatus, and The present invention relates to a signal generation method executed by the signal generator.

  Phase-locked loops (PLLs) are used for various applications in electronic circuits not only in the communication field but also in a wide range of technical fields. For example, in an image reading device such as a scanner, a PLL circuit is used to generate a timing signal for driving a solid-state imaging device such as a charge coupled device (CCD) (Patent Document 1, Patent Document 2). ).

  FIG. 9 is a block diagram showing signal processing for obtaining a digital image signal from a CCD output in a conventional image reading apparatus. The CCD 512 of the image reading unit 510 reads an image of a document on a contact glass (not shown) and outputs an image signal for each optical separation color (R, G, B) in synchronization with an input drive signal. The image signals for each separation color are AC-coupled by a capacitor 516 and input to an AFE (Analog Front End) 518. The AFE 518 generates a continuous analog signal by sampling the input image signal in synchronization with the sample pulse signal, converts it into a digital image signal, and outputs it. The digital image signal thus obtained is transmitted to the subsequent image processing unit via the interfaces 524 and 530 and subjected to digital processing. The digital processing includes correction of the delay in the sub-scanning direction between the RGB outputs by the interline correction circuit 532, correction of sensitivity variations and light distribution unevenness of the irradiation system by the shading correction circuit 534, and γ correction processing by the γ correction circuit 536. Are exemplified.

  A drive signal necessary for driving the CCD 512 and the AFE 518 is generated by a timing signal generation circuit 520 based on a signal oscillated by a crystal resonator (OSC) 522 and input to each circuit. The timing signal generation circuit 520 receives a clock signal generated by an oscillation circuit (not shown) based on the oscillation of the crystal resonator 522, and multiplies the PLL circuit 550 to a desired frequency. And a fine timing generation unit 552 that generates drive signals for the CCD 512 and the AFE 518 using the clock signal as a reference signal. Setting values such as a multiplication setting in the PLL circuit 550 and a phase setting in the fine timing generation unit 552 are set from the CPU or the SOC via the serial communication unit 556 and stored in the register unit 554. The PLL circuit 550 and the fine timing generation unit 552 operate according to the value of the register unit 554.

  Since the required reference clock frequency is generally device-specific, the conventional timing signal generation circuit 520 sets the register unit 554 via the serial communication unit 556 at the time of start-up, and then sets the value according to the set value of the register unit 554. The PLL circuit 550 and the fine timing generation unit 552 generate a desired drive signal. During the period from when the power is turned on until the initialization of the register 554 is completed, the hard default value of the register operates. During this period, the CCD 512 and the non-required frequency that is not required by the device are used. The AFE 518 is operating.

  As shown in FIG. 9, the input circuit of the AFE 518 normally cuts the offset voltage once by AC coupling and reproduces the DC with reference to about 1.6 V (= 3.3 V / 2) on the AFE 518 side. . In general, the offset voltage of the analog image signal output from the CCD 512 is 5V, whereas the power supply voltage of the AFE 518 is about 3.3V. Therefore, the offset level cannot be adapted unless AC coupling is performed. Because.

  On the other hand, the analog image signal output from the CCD 512 tends to greatly change the offset voltage when the input drive signal is stopped or restarted or the frequency of the drive signal is changed. This is because, within the CCD 512, direct current reproduction by alternating current coupling is performed in order to determine the offset voltage, and the clamp timing in the CCD 512 is shifted due to a change in frequency or a clock stop or restart. This is because the offset level changes transiently.

  The offset fluctuation amount of the analog image signal due to the stop / restart of the drive signal input to the CCD 512 or the change in the frequency thereof may reach several V, but the input circuit of the AFE 518 is AC-coupled as described above. Therefore, the instantaneous offset fluctuation amount of the analog image signal from the CCD 512 is directly transmitted to the input terminal of the AFE 518. Depending on the magnitude of the offset fluctuation amount of the analog image signal, a voltage exceeding the input withstand voltage of the AFE 518 and exceeding the maximum rated voltage may be applied.

  FIG. 10 is a diagram illustrating fluctuations in the offset voltage generated in the CCD output signal and the AFE input signal. FIGS. 10B and 10C show changes over time in the DC component of the signal at both ends I and II of the capacitor 516 in FIG. As shown in FIGS. 10B and 10C, at the timing when the PLL multiplication setting or the like is changed, an offset variation of the variation amount α occurs in the CCD output signal, and the offset variation amount is applied to the input terminal of the AFE. It shows a direct transmission.

  In the conventional PLL circuit, the frequency when the power is turned on and the operating frequency actually used are mostly different, and it is necessary to rewrite the hardware default value to a predetermined setting value by serial communication after the power is turned on. There wasn't. As described above, the offset of the analog image signal output from the CCD varies greatly depending on the amount of change in frequency at the time of rewriting, and there is a problem that an excessive voltage is applied to the AFE. There is also a PLL circuit configuration in which the output of the PLL circuit must be stopped once when the multiplication setting is changed. In that case, since the clock is stopped, the offset of the analog signal output from the CCD fluctuates greatly, and there is a problem that an excessive voltage is applied to the AFE.

  Some PLL circuits have a configuration in which the operating range of an internal voltage controlled oscillator (VCO) is switched according to the output frequency. Even in this case, the VCO operating range at the time of power activation is actually If the operating range is different from the VCO operating range, the clock may not be output normally when the power is turned on. Also in this case, after the initialization is completed normally, a normal clock is output, but the offset of the analog image signal from the CCD fluctuates greatly, and an excessive voltage is applied to the AFE. It can also occur.

  The present invention has been made in view of the above-described problems.In the present invention, the initial value at the time of power-on of a setting value that defines the device operating state such as the multiplication setting and the operation range setting is set to a value unique to the device. Can be set externally, and in this way, it is preferable to avoid problems caused by excessive offset fluctuations caused by fluctuations in the clock frequency caused by the difference between the initial value and the operation value required for the device, or stop or restart. It is an object of the present invention to provide a signal generation apparatus, an image reading apparatus including the signal generation apparatus, an image forming apparatus, and a signal generation method executed by the signal generation apparatus.

  In order to solve the above problems, the present invention provides a signal generator having the following features. The signal generator of the present invention includes a setting storage means for storing a setting value that defines an operation state of the signal generation apparatus such as a multiplication setting and an operation range of the phase synchronization circuit, and an initial setting value stored in the setting storage means. A configuration including a plurality of setting terminals for externally setting a value, and an initialization unit that reflects the logic state represented by the plurality of setting terminals in the setting storage unit in response to power-on of the signal generator. adopt. The phase synchronization circuit of the signal generator according to the present invention is configured such that the frequency of the reference signal input to the phase comparison unit is a multiplication factor by the frequency division unit according to the setting value of the setting storage unit reflected by the initialization unit. Is output from the control oscillation means.

  In the present invention, the setting value that defines the operation state may define one or both of the frequency division value of the frequency dividing means of the phase synchronization circuit and the operation range of the control oscillation means of the phase synchronization circuit. Furthermore, in addition to the frequency dividing means in the feedback loop of the phase synchronization circuit, when the frequency dividing means is provided in the previous stage of the phase comparing means, the operating state is also defined for the frequency division value of the frequency dividing means in the previous stage. A set value can be defined. Furthermore, the present invention can include a plurality of switches connected to each of the plurality of setting terminals for changing the logic state represented by the plurality of setting terminals. The present invention can further include fine timing generation means for receiving an output signal and generating a drive signal for driving an external device such as a CCD or AFE.

  Furthermore, according to the present invention, there are provided an image reading apparatus including a solid-state imaging device driven by a signal output from the signal generating apparatus, and an image forming apparatus including the image reading apparatus.

  Furthermore, according to the present invention, there is provided a signal generation method executed by the signal generation apparatus including the setting storage means, the phase synchronization circuit, and the plurality of setting terminals. In the signal generation method of the present invention, in response to power-on to the signal generation device, the logic state represented by the plurality of setting terminals is reflected in the setting storage means, and the distribution according to the set value of the setting storage means The signal generator is caused to execute the step of multiplying the frequency of the reference signal inputted to the phase comparison means by the multiplication rate by the circumference means and outputting the output signal from the control oscillation means.

  According to the above configuration, by switching the logic state represented by the setting terminal, it is possible to directly obtain the operation state required by the apparatus at the same time as the start-up when the power is turned on. Therefore, after the start-up, the output clock of the phase synchronization circuit, which can be generated due to, for example, changing the setting by serial communication in order to operate the apparatus, is not stopped or restarted, or the frequency is not changed. For this reason, in an external circuit that uses the output signal of this signal generator, an excessive offset was generated due to the difference between the initial value of the set value that defines the operating state and the operating value required for the device. Problems due to fluctuations can be preferably avoided.

1 is a diagram illustrating a mechanism configuration of an image reading apparatus according to an embodiment. FIG. 3 is a block diagram showing signal processing in the image reading apparatus of the present embodiment. FIG. 3 is a circuit block diagram showing one of RGB three systems inside the AFE in the image reading apparatus of the present embodiment. FIG. 3 is a block diagram illustrating a configuration of a timing signal generation circuit in the image reading apparatus according to the embodiment. 1 is a block diagram showing a configuration of a PLL circuit in an image reading apparatus according to an embodiment. The figure which shows the relationship between the logic state which external P1-P3 shows, the dividing value of each frequency divider, and a multiplication factor. The figure which shows the relationship between the logic state which external P1-P3 shows, the VCO output frequency and pixel frequency which are implement | achieved. The figure which shows the relationship between the logic state which external P4 and P5 show, and the operating range of VCO. The block diagram which shows the signal processing until it obtains a digital image signal from CCD output in the conventional image reading apparatus. FIG. 6 is a diagram illustrating fluctuations in offset voltage generated in a CCD output signal and an AFE input signal in a conventional image reading apparatus.

  Hereinafter, although embodiment of this invention is described, embodiment of this invention is not limited to the following embodiment. The embodiments described below will be described using a timing signal generation circuit included in an image reading apparatus as an example of a signal generation apparatus.

  FIG. 1 is a diagram showing a mechanism configuration of the image reading apparatus according to the present embodiment. An image reading apparatus 10 shown in FIG. 1 includes a contact glass 12 on which a document is placed, a white reference plate 16 for correcting distortion caused by an optical system, a document exposure xenon lamp 18, and a first reflection mirror. The first carriage 22 including 20, the second carriage 28 including the second reflecting mirror 24 and the third reflecting mirror 26, and the lens unit 30 are configured. The image reading apparatus 10 further includes a sensor board 34 including a CCD linear image sensor (hereinafter simply referred to as a CCD) 32 and an image processing board 38.

  The first carriage 22 and the second carriage 28 move in the sub-scanning direction A by driving a stepping motor (not shown) during scanning. The light emitted from the xenon lamp 18 is reflected by the original surface on the contact glass 12, and the reflected light passes through the optical system such as the mirrors 20, 24, 26 and the lens unit 30 and is coupled onto the light receiving surface of the CCD 32. Imaged. The image signal output from the CCD 32 is digitized on the sensor board 34 and input to the image processing board 38 via the communication cable 36, and various digital image processing is performed.

  FIG. 2 is a block diagram showing signal processing in the image reading apparatus of the present embodiment. The functional block 100 of the image processing apparatus shown in FIG. 2 includes a sensor block 110 of the sensor board 34 and an image processing block 130 of the image processing board 38. The sensor block 110 includes a CCD 112, an AFE 118, and a timing signal generation circuit 120. The CCD 112 reads an original image on the contact glass 12 and outputs an image signal for each optical separation color (R, G, B) in synchronization with an input drive signal. The image signals for each separation color are AC-coupled by the capacitors 116 and input to the AFE 118.

  The AFE 118 samples the input image signal corresponding to the drive signal to generate a continuous analog signal, converts it into a digital image signal, and outputs it. FIG. 3 exemplifies one circuit block of the RGB three systems inside the AFE in the image reading apparatus of the present embodiment.

  As shown in FIG. 3, inside the AFE 118, a clamp circuit (CLAMP) 140 clamps to a predetermined offset voltage, and a sample hold circuit (SH) 142 samples the image signal including reset noise, feedthrough level, and the like as a sample pulse. By sampling and holding in synchronization with the signal, a continuous analog signal is obtained. The analog signal is amplified to a level of a reference voltage for A / D conversion by a variable gain amplifier 144, and then a digital image of a predetermined bit (for example, 10 bits) by an ADC (Analog to Digital Converter) 146. Converted to a signal. Further, the black offset correction circuit 148 feeds back an analog offset via a DAC (Digital to Analog Converter) so that the CCD output in the dark reaches a predetermined level after A / D conversion.

  Referring to FIG. 2 again, the digital image signal obtained as described above is transmitted to the subsequent image processing block 130 via the interfaces 124 and 132 and subjected to digital processing. As the digital processing, in the example illustrated in FIG. 2, various correction processes by the interline correction circuit 134, the shading correction circuit 136, and the γ correction circuit 138 are illustrated.

  The interline correction circuit 134 corrects the delay in the sub-scanning direction between the RGB outputs. The shading correction circuit 136 obtains a predetermined density level by reading the reflected light from the white reference plate 16 irradiated by the xenon lamp 18 shown in FIG. 1 with the CCD 112, and varies the sensitivity of the CCD 112 and the illumination system. Correct uneven light distribution. The γ correction circuit 138 performs γ correction on the digitized image and corrects an error due to element characteristics.

  A drive signal necessary for driving the CCD 112 and the AFE 118 is generated by the timing signal generation circuit 120 based on a clock signal oscillated by the crystal resonator (OSC) 122 and input to each circuit. The AFE 118 and the timing signal generation circuit 120 have a built-in register for determining an operation state, and are connected to an external CPU or SOC via an interface so that the operation state can be set by serial communication.

  FIG. 4 is a block diagram showing the configuration of the timing signal generation circuit in the image reading apparatus of this embodiment. As shown in FIG. 4, the timing signal generation circuit 120 receives an input clock signal generated by the oscillation circuit based on the oscillation of the crystal resonator 122 and multiplies the signal to a desired frequency. And a fine timing generator 152 that generates drive signals for the CCD 112 and the AFE 118 using the multiplied output clock signal as a reference signal. For example, the fine timing generator 152 generates drive signals for the CCD 112 and the AFE 118 using the output clock signal multiplied by 8 as a reference signal. In this case, the PLL output frequency is eight times the frequency of the drive signal of the CCD 112 or AFE 118.

  Setting values such as the multiplication setting in the PLL circuit 150, the VCO operating range, and the phase setting in the fine timing generation unit 152 can be set from the CPU or the SOC via the serial communication unit 156 and stored in the register unit 154. The register unit 154 constitutes a setting storage unit that defines the operation state of the timing signal generation circuit 120, and the PLL circuit 150 and the fine timing generation unit 152 operate according to the stored value.

  The input circuit of the AFE 118 to which the drive signal from the fine timing generation unit 152 is input is offset by AC coupling using the capacitor 116 as described with reference to FIG. The voltage is temporarily cut and DC regeneration is performed on the AFE 118 side with a predetermined offset potential as a reference. Similarly, in the CCD 112 to which the drive signal from the fine timing generation unit 152 is input, the offset voltage is determined by performing DC reproduction by AC coupling.

  For this reason, when the setting value of the register unit 154 of the timing signal generation circuit 120 is rewritten by the serial communication and the operation state is changed, the following problems may occur. That is, when the frequency of the drive signal input to the CCD 112 is changed, or the clock is stopped or restarted, the clamp timing inside the CCD 112 is shifted, and the offset level changes greatly from the CCD 112. There is a possibility that an instantaneous and excessive offset fluctuation amount of the analog image signal is directly transmitted to the input terminal of the AFE 118.

  Therefore, the register unit 154 of the timing signal generation circuit 120 of this embodiment is further connected to the external setting pins P1 to P5. These external setting pins P1 to P5 designate initial values of register values according to their logical states. The logical state represented by the external setting pins P1 to P5 can be determined by using, for example, the dip switch 160 including the respective contacts 162 drawn to the outside from the respective pins of the external setting pins P1 to P5. By switching each contact 162 of the DIP switch 160, a high (H) or low (L) voltage is applied to each of the external setting pins P1 to P5, and the logic state is determined. In the embodiment to be described, the case of using a dip switch 160 of a slider type or the like that is surface-mounted on a substrate or the like is taken as an example. However, as long as it can be controlled from outside the logical state represented by the external setting pins P1 to P5, The configuration is not particularly limited.

  In the embodiment to be described, the external setting pins P1 to P3 specify the value of a register that defines the frequency division ratio of the PLL circuit 150, and the external setting pins P4 and P5 are registers that define the VCO operating range of the PLL circuit 150. Specify the value of. The logic state represented by the terminals of the external setting pins P1 to P5 is reflected in the register at the timing when the reset is released by the hard reset signal input from the reset IC 158 after power-on. Note that the reset IC 158 constitutes an initialization unit of the present embodiment.

  FIG. 5 is a block diagram showing a configuration of a PLL circuit in the image reading apparatus of the present embodiment. The PLL circuit 150 includes a phase comparator 172, a loop filter 174 such as a low-pass filter, a voltage controlled oscillator (VCO) 176, and a feedback-side frequency divider 178. The VCO 176 operates in an operation range corresponding to the value initially set by the external setting pins P4 and P5 of the register unit 154, and the feedback-side frequency divider 178 also includes the external setting pins P1 to P3 of the register unit 154. The operation is performed with the frequency-divided value corresponding to the value initially set by. The phase comparator 172 can also be configured to operate according to various set values of the register unit 154. The phase comparator 172, the VCO 176, and the feedback-side frequency divider 178 described above constitute the phase comparison unit, the control oscillation unit, and the frequency division unit of this embodiment, respectively.

  In the PLL circuit 150, the frequency fr of the reference clock signal input to the phase comparator 172 matches the frequency fd of the feedback signal fed back through the loop filter 174, VCO 176, and feedback side frequency divider 178 ( (Locked state). Therefore, the output frequency fo of the VCO 176 is higher than the frequency fr of the input reference clock signal.

  If the frequency fr of the reference clock signal and the frequency fd of the feedback signal do not match, an error signal pulse is generated from the phase comparator 172, passed through the loop filter, converted to a DC voltage, and input to the VCO 176. The VCO 176 generates an output clock signal having an output frequency corresponding to the DC voltage, a signal obtained by dividing the output clock signal by the feedback-side divider 178 is fed back, and the frequency fd of the feedback signal is the reference clock signal. Feedback is applied to match the frequency fr. As a result, fr = fd is established, and an output clock signal having an output frequency fo obtained by multiplying the reference clock signal by the divided value of the feedback-side frequency divider 178 is output.

  In the embodiment shown in FIG. 5, an input-side frequency divider 170 is provided before the phase comparator 172, and a signal obtained by dividing the input signal (Ref_clock) from the crystal resonator is supplied to the phase comparator 172. The reference clock signal is input. In this case, a value obtained by dividing the frequency division value of the feedback side frequency divider 178 by the frequency division value of the input side frequency divider 170 is the multiplication factor. The frequency division value of the input side frequency divider 170 also operates at a frequency division value corresponding to a value initially set by the external setting pins P1 to P3 of the register unit 154 described above. The input-side divider 170 is preferably used to generate a reference clock signal in a relatively low frequency band using a high-frequency band crystal resonator that can be manufactured in a small size and high accuracy, but is not necessarily required. Absent. When the input-side frequency divider 170 is not used, the frequency-divided value of the feedback-side frequency divider 178 becomes the multiplication factor as it is.

  The frequency dividing values of the frequency dividers 170 and 178 of the PLL circuit 150 are variable according to the set value of the register unit 154, and after the power is turned on to the timing signal generation circuit 120, the hardware input from the reset IC 158 is turned on. At the timing when the reset is released by the reset signal, the value of the register unit 154 is updated in accordance with the logic state represented by the external setting pins P1 to P3, thereby determining the divided value. That is, in the present embodiment, it is possible to perform frequency division setting without serial communication.

  FIG. 6 shows the relationship between the logic state 200a indicated by the external P1 to P3, the frequency division values 200b and 200c of the frequency dividers 170 and 178, and the multiplication rate 200d. Note that the value of the logical state 200a shown in FIG. 6 is a decimal notation where P1 represents bit 0, P2 represents bit 1, and P3 represents bit 2. As shown in FIG. 6, the logical states indicated by the external P1 to P3 are associated with the divided values of the frequency dividers 170 and 178. By specifying this logical state with the DIP switch 160, for example, an arbitrary multiplication is performed. The rate is realized.

  FIG. 7 exemplifies the output frequency of the VCO 176 and the pixel frequency by the fine timing generation unit 152 realized by switching the logic state indicated by the external P1 to P3 when a crystal resonator having a source oscillation frequency of 12 MHz is used. . As shown in FIG. 7, the output frequency and the pixel frequency of the VCO 176 are determined by the logic state indicated by the external P1 to P3 for a predetermined source oscillation frequency.

  FIG. 8 shows the relationship between the logic state 220a indicated by the external P4 and P5 and the corresponding operating range 220b of the VCO 176. Note that the value of the logical state 200a shown in FIG. 8 is a decimal number representation where P4 represents bit 0 and P5 represents bit 1. As shown in FIG. 8, the logical state indicated by the external P4 and P5 is associated with each operation range of the VCO, and the VCO operation range is determined by specifying this logical state with the DIP switch 160, for example.

  For example, when the pixel frequency is activated to 30 MHz, the dip switch 160 is set so that P1 = "L", P2 = "L", P3 = "H", P4 = "L", P5 = "H". This should be set. That is, by switching the dip switch 160 in advance so as to realize a known operating frequency necessary for the operation of the apparatus, the operation is started at a desired operating frequency immediately after starting. For this reason, in the circuit to which the drive signal from the timing signal generation circuit 120 as described above is input, it is possible to preferably avoid the problem caused by the difference between the startup frequency and the required operating frequency.

  According to the timing signal generation circuit 120 of the above-described embodiment, the operation required by the CCD 112 and the AFE 118 at the same time as the start-up when the power is turned on by switching the dip switch 160 that specifies the logic state represented by the external setting pins P1 to P5. The frequency can be obtained directly. Therefore, since the output clock of the PLL circuit 150 is not stopped and the frequency fluctuation does not occur after that in order to operate the apparatus, it is preferable to prevent the signal level from being disturbed in the circuit that performs DC reproduction inside the CCD or the like. Is done.

  In addition, since a plurality of operating frequencies can be switched externally by a simple operation of switching switches, the same timing signal generation circuit 120 can be applied to various devices. In addition, in the timing signal generation circuit 120 of this embodiment, in addition to setting the initial value of the register unit 154 by the external pins P1 to P5, the change of the setting value by serial communication is also maintained, so that the operation test of the signal generator is performed. Time efficiency is ensured, and it is possible to cope with the necessity of changing the operating frequency after startup. For example, by changing the clock frequency of the apparatus, it is possible to provide additional functions such as providing a plurality of modes such as a high-speed reading mode and a high-quality (low-speed) reading mode for the image reading speed.

  As described above, according to the above-described embodiment, it is possible to externally set the initial value at the time of power-on of the setting value that defines the device operation state such as the multiplication setting and the operation range setting with a value unique to the device. As a result, a signal generator capable of suitably avoiding problems caused by excessive offset fluctuations caused by clock frequency fluctuations, stoppages or restarts caused by a difference between an initial value and an operation value required by the apparatus An image reading apparatus including the signal generation apparatus, an image forming apparatus, and a signal generation method executed by the signal generation apparatus can be provided.

  The signal generation device is not limited to the timing signal generation circuit included in the above-described image reading device, and an image forming apparatus such as a copying machine, a printer, or a printing machine, a digital camera, or the like depending on a specific application. The signal generation device can be configured as a substrate component built into a communication device such as an imaging device, a mobile phone, or a wireless communication LAN device, or as these devices. In another embodiment, the frequency synthesizer can be configured as a single unit.

  Note that the PLL circuit of the above-described embodiment is not limited to the above-described configuration as long as the multiplication rate can be arbitrarily set, and can be configured as an all-digital PLL circuit, for example. When configured as an all-digital PLL circuit, frequency dividing means and phase comparison means can be configured by a counter and TDC (Time to Digital Converter), and control oscillation means can be configured by a DCO (Digitally Controlled Oscillator) circuit.

  Although the embodiments of the present invention have been described so far, the embodiments of the present invention are not limited to the above-described embodiments, and those skilled in the art may conceive other embodiments, additions, modifications, deletions, and the like. It can be changed within the range that can be done, and any embodiment is included in the scope of the present invention as long as the effects of the present invention are exhibited.

DESCRIPTION OF SYMBOLS 10 ... Image reading device, 12 ... Contact glass, 14 ... Pressure plate, 16 ... White reference plate, 18 ... Xenon lamp, 20 ... 1st reflective mirror, 22 ... 1st carriage, 24 ... 2nd reflective mirror, 26 ... 3rd Reflection mirror 28 ... second carriage 30 ... lens unit 32 ... CCD 34 ... sensor board 36 ... communication cable 38 ... image processing board 100 ... functional block 110 ... sensor block 112 ... CCD 116 ... Capacitors 118 ... AFE 120 ... Timing signal generation circuit 122 ... Crystal oscillator 124 ... Interface 130 ... Image processing block 132 ... Interface 134 ... Interline correction circuit 136 ... Shading correction circuit 138 ... γ correction Circuit 140 ... Clamp circuit 142 ... Sample hold circuit 144 ... Possible Gain amplifier, 146 ... ADC, 148 ... black offset correction circuit, 150 ... PLL circuit, 152 ... fine timing generation unit, 154 ... register unit, 156 ... serial communication unit, 158 ... reset IC, 160 ... dip switch, 162 ... contact , 170 ... input side frequency divider, 172 ... phase comparator, 174 ... loop filter, 176 ... VCO, 178 ... feedback side frequency divider, 510 ... image reading unit, 512 ... CCD, 516 ... capacitor, 518 ... AFE, 520: Timing signal generation circuit, 522: Crystal oscillator, 524 ... Interface, 530 ... Interface, 532 ... Interline correction circuit, 534 ... Shading correction circuit, 536 ... γ correction circuit, 550 ... PLL circuit, 552 ... Fine timing generation Part, 554 ... register part, 556 ... serial Le communication unit

JP 2001-31547 A JP 2005-1224028 A

Claims (8)

A signal generator for generating an output signal,
Setting storage means for storing a setting value for defining the operating state of the signal generator;
A phase synchronization circuit including a phase comparison unit, a control oscillation unit, and a frequency division unit, wherein the phase comparison unit has a multiplication factor by the frequency division unit based on a frequency division value corresponding to the set value of the setting storage unit. A phase synchronization circuit that outputs an output signal obtained by multiplying the frequency of the input reference signal from the control oscillation means that operates in an operation range corresponding to the setting value of the setting storage means;
A plurality of setting terminals for externally setting an initial value of the setting value defining the frequency division value and the operation range stored in the setting storage means;
An initialization unit that reflects the logic state represented by the plurality of setting terminals in the setting storage unit at a timing when reset is released after power is turned on to the signal generation device. The setting value whose initial value is externally set by the plurality of setting terminals causes an offset variation of a signal of an external device driven based on the output signal of the phase synchronization circuit in accordance with the change of the setting value. The signal generator according to claim 1, wherein the initial value is an operation value that defines a frequency division value and an operation range for providing an output signal required by the external device.   The signal generator according to claim 1, further comprising a plurality of switches connected to each of the plurality of setting terminals and configured to change a logic state represented by the plurality of setting terminals.   4. The signal generation device according to claim 1, further comprising a fine timing generation unit that receives an input of the output signal and generates a drive signal for driving an external device. 5. Signal generator.   An image reading apparatus comprising the signal generation device according to claim 1, wherein the solid-state imaging device is driven by a signal output from the signal generation device.   An image forming apparatus comprising the image reading apparatus according to claim 5. A setting storage means for storing a setting value for defining an operating state of the signal generator, a phase synchronization circuit including a phase comparison means, a control oscillation means, and a frequency dividing means; and the frequency dividing means stored in the setting storage means. A signal generating method executed by the signal generating device, including a plurality of setting terminals for externally setting a frequency division value and an initial value of a setting value that defines an operating range of the control oscillation means, the signal generating device But,
Reflecting the logic state represented by the plurality of setting terminals in the setting storage means at a timing when reset is released after turning on the power to the signal generator;
An output signal obtained by multiplying the frequency of the reference signal input to the phase comparison unit by the multiplication rate by the frequency division unit based on the frequency division value corresponding to the setting value of the setting storage unit is the setting storage unit. And a step of outputting from the control oscillating means operating in an operating range corresponding to a set value. The setting value whose initial value is externally set by the plurality of setting terminals causes an offset variation of a signal of an external device driven based on the output signal of the phase synchronization circuit in accordance with the change of the setting value. The signal generation method according to claim 7, wherein the initial value is an operation value that defines a frequency division value and an operation range for providing an output signal required by the external device .