JP5494911B2 - Ring oscillator - Google Patents

Description

The present invention relates to a ring oscillator that can control the oscillation frequency, about the Ringuoshire data, particularly can reduce the effects of self-interference wave.

  In recent years, in the flow of integration, there are many cases where a PLL (Phase locked Loop) circuit including an oscillator circuit is incorporated in an LSI (Large Scale Integration). As an oscillator circuit built in an LSI, a ring oscillator that does not require an external loop filter or the like is often used. The advantage of this ring oscillator is that, unlike other oscillators, no coil is required and it can be configured as a circuit equivalent to an amplifier, and therefore it is easy to integrate as an integrated circuit.

  The ring oscillator is configured by coupling a plurality of delay elements having a negative gain as a whole in a ring shape. A typical example is an odd-numbered inverter gate (NOT gate). The output of each inverter gate is input to the next-stage inverter gate in a chain form, and the output of the final-stage inverter gate is input to the first-stage inverter gate, which has a ring structure as a whole. Furthermore, by controlling the power supply bias voltage of the inverter gate constituting the ring oscillator, the delay time of the inverter gate can be controlled and the oscillation frequency of the ring oscillator can be varied (the oscillation frequency becomes higher if the delay time is shortened). ). In this way, it is often used as a frequency variable type VCO (Voltage Controlled Oscillator) in which the power supply bias voltage of the inverter gate is controlled.

  On the other hand, the weak point of the ring oscillator is that the oscillation frequency fluctuates due to the phase shift of the logic inverting circuit (inverter gate) and the inverting amplifier, the fluctuation of the power supply voltage, and the fluctuation of the delay time due to noise. As a countermeasure, compensation is performed by a phase synchronization circuit. As a result, the fluctuation of the power supply voltage can be solved by always following the fluctuation of the oscillation frequency due to the fluctuation of the power supply by the phase synchronization circuit. In general, a PLL circuit includes a ring oscillator and a phase synchronization circuit, and operates stably by stabilizing the oscillation frequency by the phase synchronization circuit.

  There are the following patent documents as prior patent documents related to the ring oscillator. Japanese Patent Laid-Open No. 6-232703 discloses a technique for selecting the number of inverter gates connected by a connection selector in an internal oscillation circuit composed of a plurality of inverter gates. Japanese Patent Laid-Open No. 8-307220 discloses a technique for changing the pumping frequency of a booster circuit by switching the number of inverter gate connection stages of an internal oscillation circuit composed of a plurality of inverter gates. In Patent Document 3 (Japanese Patent Laid-Open No. 2006-261833), a high-speed pass amplifier and a low-speed pass amplifier whose supplied power supply current changes in opposite directions are connected in parallel, and a low-pass signal is further passed to the output stage of this amplifier. A ring oscillator is disclosed in which a filter is provided to suppress variations in a wide area of the oscillation frequency.

Japanese Patent Laid-Open No. 6-232703 JP-A-8-307220 JP 2006-261833 A

  As described above, recent LSIs incorporate a PLL circuit including an oscillator circuit, and a ring oscillator is often used as the oscillator circuit. In addition, IBM announced in 2006 that it was the first to build a complete IC around a single-walled carbon nanotube (CNT) molecule. According to the announcement, a ring oscillator circuit was prototyped and manufactured using normal semiconductor processes and single-molecule carbon nanotubes that serve as the base for all components of the circuit. Since the ring oscillator circuit can be configured with such a simple circuit, it is expected that it will be increasingly used in the future.

  However, the ring oscillator has a weak point in that a multi-frequency harmonic having the number of phases of the oscillation frequency is generated. This noise propagates in the air as electromagnetic noise, or propagates through a conductor through a power source, ground, and the like. Therefore, various electromagnetic noise standards such as FCC Directive (Federal Communication Commission directive: USA), R & TTE Directive (Radio & Telecommunication Terminal Equipment directive: Europe), ARIB (Association of Radio Industries and Businesses: Japan), etc. In addition to causing the wireless device to violate the standards), there is a problem that when the reception frequency overlaps, the received wave of the wireless device and the self-interfering wave interfere with each other and the sensitivity of the wireless device deteriorates.

  For example, recent mobile phones have many functions, are equipped with a plurality of LSIs, and the frequency used in the device is variable. For this reason, if the frequency of harmonic noise from the ring oscillator inside the LSI overlaps with the reception frequency used in the device, the harmonic noise becomes a self-interfering wave, causing interference and degrading the reception sensitivity of the device. To do. This problem is referred to as in-device EMC (self-poisoning), which has been highlighted as a very large problem, and countermeasures are required.

  FIG. 12 shows a configuration diagram of the wireless device 20 that communicates with the transmitting station 11. The wireless device 20 includes an antenna 21, a power amplification unit 22, a frequency conversion unit 23, a baseband unit 24, a control unit 25, and a local oscillator (VCO) 27, and can receive a reception wave from the transmission station 11. However, recent wireless devices have many functions, and further include, for example, a PLL circuit 10 including a ring oscillator 9 as shown in FIG. In this case, when the harmonic noise from the ring oscillator 9 and the transmission / reception frequency of the wireless device overlap, the harmonic noise becomes an interference wave, which deteriorates the transmission / reception sensitivity of the wireless device.

  A configuration example of this ring oscillator is shown in FIG. FIG. 13A is a block diagram of the PLL circuit 10 using a ring oscillator, and FIG. 13B shows the timing and power supply current waveform of each part of the ring oscillator. The PLL circuit 10 includes a phase detector (PD) 1, a charge pump circuit (CP) 2, a low-pass filter (LBP) 3, a frequency divider 4, and a ring oscillator 9. In the ring oscillator 9, the inverter gate 5 is coupled in a seven-stage chain shape. The first-stage inverter gate 5 receives the output G of the final-stage inverter gate 5 and outputs the output to the next-stage inverter gate. The inverter gates sequentially connected in a chain form output B to F to the subsequent stage. The output G of the final stage is input to the first-stage inverter gate in a ring shape, and the first-stage inverter gate inverts and outputs the input signal. In this way, oscillation occurs in a cycle in which the delay time for seven stages of inverter gates is a half cycle.

  From the ring oscillator 9, for example, a clock (Fck) having a frequency of 312 MHz is output, distributed as a clock inside the LSI, and input to the frequency divider 4. The frequency divider 4 outputs a divided clock obtained by dividing the clock (Fck) by 1/12. The phase detector 1 receives the divided clock and the reference clock (Fref = 26 MHz) and compares the phases. The phase comparison result between the divided clock and the reference clock is input to the charge pump circuit 2 to control the output voltage of the charge pump circuit 2. The output voltage of the charge pump circuit 2 is smoothed by the low-pass filter 3 and supplied to the power source of the inverter gate 5 constituting the ring oscillator.

  When the phase of the divided clock is advanced in the phase detector 1, the output voltage of the charge pump circuit 2 is controlled to be low, and the oscillation frequency of the ring oscillator is lowered. Conversely, when the phase of the divided clock is delayed, the output voltage of the charge pump circuit 2 is controlled to be high, and the oscillation frequency of the ring oscillator is increased. Thus, by controlling the output voltage of the charge pump circuit 2 by the control signal from the phase detector 1, the oscillation frequency of the ring oscillator is controlled. By combining with the phase synchronization circuit in this way, the oscillation frequency of the ring oscillator can be compensated and a PLL circuit using the ring oscillator that operates stably can be configured.

  In this PLL circuit, harmonic noise is generated by the power supply current of the inverter gate constituting the ring oscillator. For example, in a ring oscillator using an inverter gate, the output of the inverter gate is inverted one after another. The inverter gate generally has a complementary metal oxide semiconductor (CMOS) configuration, and includes a PMOS (P-channel metal oxide semiconductor) as a load transistor and an NMOS (N-channel metal oxide semiconductor) as a drive transistor.

  When the input changes from high level to low level, the output changes from low level to high level. At this time, the NMOS changes from the conductive state to the non-conductive state, and the PMOS changes from the non-conductive state to the conductive state, and the output is raised to a high level by the power supply current from the power supply voltage. When this output changes from the low level to the high level, the power supply current by the PMOS is the main, the current to the ground is small and can be ignored. The power supply current waveform corresponds to the output high level change, as shown in FIG. 13B, the first output A, then the output C, output E, output G, output B, output D, output F and the respective output level changes. A peak current flows in response to. Harmonic noise is generated by the power supply current flowing at this time, and propagates in the air as electromagnetic noise or through the conductor through the power supply.

  On the other hand, when the input changes from low level to high level, the output changes from high level to low level. At this time, the PMOS changes from the conductive state to the non-conductive state, and the NMOS changes from the non-conductive state to the conductive state, discharging the high-level output charge and pulling it down to the ground voltage. At this time, the ground current by NMOS is the main, and the current from the power source is small and can be ignored. At this time, harmonic noise is generated by the ground current flowing through the ground. In this case, the peak current flows corresponding to the first output B, then the output D, the output F, the output A, the output C, the output E, and the output G and the respective output level changes. In general, since the harmonic noise caused by the power supply current is larger than the harmonic noise caused by the ground current, the following description will be made on the power supply current side.

  The harmonic noise due to the power supply current is the number of phases corresponding to the number of stages of the inverter gate × the frequency of the oscillation frequency, and propagates in the air as electromagnetic noise, or propagates through the conductor through the power supply. As shown as a power supply current waveform in FIG. 13, when the number of phases is 7 and the oscillation frequency is 312 MHz, harmonic noise of 7 × 312 = 2184 MHz is generated. Therefore, when the frequency of 2184 MHz is used in the device, the harmonic noise 2184 MHz becomes a self-interfering wave, interferes with the transmission / reception wave of the 2184 MHz band wireless device, and the transmission / reception sensitivity of the wireless device deteriorates.

  Conventionally, measures have been devised for the propagation of electromagnetic noise in the air, such as shielding the corresponding LSI and circuit section with a metal case. However, this measure has many disadvantages in terms of size and cost. For power supply conductor propagation, cost-effective measures such as providing a power supply with a filter that suppresses the corresponding frequency are taken. Furthermore, in the case of ground propagation noise, there are few effective countermeasures, and countermeasures with great demerits in layout such as separating the ground of the oscillator circuit from the interference circuit have been taken.

  As the use of ring oscillators has increased in this way, the only countermeasures against harmonic noise, which is a self-interference wave, are those that have significant disadvantages in terms of cost, layout, size, and the like. For this reason, there has been a demand for a method for suppressing interference due to the harmonics unique to the ring oscillator without taking measures that have a large disadvantage in terms of cost, layout, size, and the like.

An object of the present invention has been made to solve the problems described above, cost, layout, without a large measure of disadvantage in such size, Ringuoshire data capable of suppressing the interference due to the ring oscillator specific harmonic noise Is to provide.

According to one aspect of the present invention, the detection means for detecting the reception sensitivity of the reception frequency, the detected reception sensitivity is compared with a threshold value to determine whether the reception sensitivity is deteriorated, and the control is performed when the deterioration of the reception sensitivity is determined. A ring oscillator built in a wireless device including a control means for outputting a signal, and comprising an oscillation circuit and a changeover switch for switching the configuration of the oscillation circuit when receiving the control signal , the oscillation circuit comprising a plurality of stages The control means determines that the reception sensitivity has deteriorated due to interference between harmonic noise generated by the oscillation circuit and the reception frequency used by the wireless device, and the control signal is output. that when, phosphorus the switching configuration of the oscillation circuit by switching the switch, it is possible to change the frequency of the harmonic noise which the oscillating circuit is generated Oscillator can be obtained.

According to another aspect of the present invention, the detection means for detecting the reception sensitivity of the reception frequency, the detected reception sensitivity is compared with a threshold value to determine whether the reception sensitivity is deteriorated, and the deterioration of the reception sensitivity is determined. A ring oscillator that is built in a wireless device including a control unit that outputs a control signal, and includes an oscillation circuit and a changeover switch that switches a configuration of the oscillation circuit when receiving the control signal. A first stage inverter gate having a different delay time, and a first delay circuit and a second delay circuit that are switched and connected to the plurality of stages of inverter gates; If the control means determines that the reception sensitivity is deteriorated due to interference with the reception frequency of the signal and the control signal is output, the changeover switch causes the plurality of stages A delay circuit connected to Nbatageto, the ring oscillator is obtained, characterized in that the switch connection to either the other of said first or second delay circuit.

  When the reception frequency of the wireless device interferes with the harmonic noise generated by the ring oscillator, the configuration of the PLL circuit is changed, and the frequency of the harmonic noise generated by the ring oscillator is changed. By changing the frequency of the harmonic noise, the frequency of the harmonic noise and the reception frequency of the wireless device do not overlap, and interference does not occur. Since there is no interference between the frequency of the harmonic noise and the reception frequency of the wireless device, a wireless device with good sensitivity can be obtained.

It is a block block diagram of the radio | wireless apparatus in this invention. It is a table which shows the interference frequency band and threshold value in this invention. FIG. 4 is a configuration block diagram (A) of the PLL circuit in the first embodiment and timing diagrams (B) and (C) of the ring oscillator. It is a spectrum of the interference wave in Example 1. 3 is a flowchart illustrating a control method according to the first embodiment. FIG. 6 is a configuration block diagram (A) of a PLL circuit in a second embodiment and a timing diagram (B) of a ring oscillator. It is a spectrum of the interference wave in Example 2. 6 is a flowchart illustrating a control method in Embodiment 2. FIG. 6 is a configuration block diagram (A) of a PLL circuit according to a third embodiment, and timing diagrams (B) and (C) of a ring oscillator. It is a spectrum of the interference wave in Example 3. 10 is a flowchart illustrating a control method in Embodiment 3. It is a block diagram of a conventional radio apparatus. It is a block diagram of a PLL circuit using a conventional ring oscillator.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, in order to understand the present invention, a radio apparatus including a ring oscillator and a PLL circuit according to the present invention will be described with reference to FIGS. FIG. 1 is a block diagram of a radio apparatus according to the present invention, and FIG. 2 is a table showing interference wave frequency bands and threshold values.

  A radio apparatus 20 illustrated in FIG. 1 includes an antenna 21, a power amplification unit 22, a frequency conversion unit 23, a baseband unit 24, a control unit 25 including a table 26, and a local oscillator (VCO) 27. Transmitting and receiving with the received wave. Further, the wireless device 20 includes a PLL circuit 10 including a ring oscillator 9. The harmonic noise from the ring oscillator 9 becomes a self-interfering wave, which may deteriorate the transmission / reception sensitivity of the wireless device. Therefore, the configuration of the PLL circuit can be changed by the circuit construction control signal from the control unit 25 including the table 26, and the frequency of the harmonic noise generated by the ring oscillator 9 can be changed. By making the frequency band of the harmonic noise of the ring oscillator 9 different from the reception frequency used by the wireless device, interference between the reception frequency and the harmonic noise can be eliminated or suppressed.

  Transmission / reception is performed between the transmission station 11 and the wireless device 20, and the baseband unit 24 detects the reception frequency and its reception sensitivity. The detection item as the reception sensitivity is not particularly limited, but the received radio wave intensity and the bit error rate can be used. For example, received signal strength RSSI, desired wave received power RSCP, energy-to-received power density ratio Ec / NO, bit error rate BER, and the like can be used. Further, it is determined whether or not the detected reception sensitivity is a satisfactory reception sensitivity level. When the frequency received at this time and the frequency of the harmonic noise generated from the ring oscillator 9 overlap and interfere with each other, the reception sensitivity deteriorates. In the case of interference, the harmonic noise generated from the ring oscillator 9 becomes a self-interfering wave and degrades reception sensitivity via the antenna or power supply wiring. As described above, the harmonic noise generated from the ring oscillator 9 interferes and becomes a self-interfering wave when the frequency thereof overlaps the reception frequency used in the radio apparatus. Therefore, since these harmonic noises become interference waves, they can be expressed as interference wave frequencies.

  The frequency band of harmonic noise generated from the ring oscillator 9 is stored as a table 26 in the control unit 25. For example, as shown in FIG. 2, the table 26 includes a lower limit frequency and an upper limit frequency of a frequency band of harmonic noise generated from the ring oscillator 9, and a threshold value at that time. This threshold is a criterion for determination by comparison with the detected reception sensitivity. That is, it is determined whether or not to change the frequency of the harmonic noise generated from the ring oscillator 9 depending on whether the reception sensitivity is better or lower than the threshold value. In FIG. 2, the received signal strength RSSI is shown as a threshold value, but a threshold value can be provided for each item detected and used as a wireless device. In addition, the received signal strength RSSI, desired wave received power RSCP, and the like can be combined instead of one item as the threshold value.

  Next, the control method of the present invention will be described. Initially, the ring oscillator 9 of the PLL circuit 10 oscillates at a frequency initially set by the control unit 25. As an initial setting, a state in which the power consumption of the PLL circuit is minimized is selected. For example, when the ring oscillator 9 is configured by an inverter gate, the initial setting is a state where the number of inverter gates connected in a ring shape with low power consumption is small. When the frequency division ratio is fixed or variable, the initial setting is set to a fixed operation with low power consumption. Next, the reception sensitivity at the reception frequency is detected.

  The control unit 25 of the wireless device 20 confirms whether the reception frequency band being used is included in the interference wave frequency band of the table. When the interference frequency band of the table 26 does not include the reception frequency band of the wireless device 20, the harmonic noise of the ring oscillator 9 does not become an interference wave. Therefore, the reception sensitivity of communication is good, and the ring oscillator 9 continues the oscillation operation with the initial setting state.

  When the interference frequency band of the table 26 includes the reception frequency band of the wireless device 20, the detected reception sensitivity is further compared with the threshold value of the table 26. For example, when the reception frequency of the wireless device 20 is 4360 MHz, it is included in the interference frequency 4354 to 4382 MHz in the second column of the table, the reception sensitivity is affected, and the reception quality is deteriorated. Therefore, the actual reception sensitivity is compared with the threshold value in the table. If the reception sensitivity is better than the threshold, the frequency bands overlap, but the interference is small and the operation is continued in the initial setting state. In the following explanation, the reception frequency band and the interference wave frequency band overlap and interfere, but if the degree of interference is small and the reception sensitivity is good, the reception frequency and the interference wave frequency are Consider no interference. That is, it is assumed that the reception frequency interferes with the interference wave frequency only when the reception frequency deteriorates due to interference between the reception frequency and the interference wave frequency and is not satisfactory.

  The detected reception sensitivity is compared with the threshold value of the table. If the reception sensitivity is inferior, it is determined that the harmonic noise from the ring oscillator interferes and becomes a disturbing wave, and the configuration and frequency division of the PLL oscillator of the PLL circuit Change the ratio. By changing the configuration of the PLL circuit, the harmonic noise frequency from the ring oscillator is changed, the overlapping of the reception frequency and the frequency of the harmonic noise from the ring oscillator is eliminated, and interference is eliminated. Alternatively, the overlapping of the reception frequency and the frequency of the harmonic noise from the ring oscillator is reduced, and the degree of interference is suppressed. Thus, the reception sensitivity of the wireless device can be kept good by changing the harmonic noise frequency from the ring oscillator and suppressing interference.

  As described above, the wireless device of the present invention includes a PLL circuit having a ring oscillator, and the PLL circuit operates in a state where power consumption is minimized as an initial setting. However, when the harmonic noise from the ring oscillator becomes a self-interfering wave and the reception sensitivity of the wireless device decreases, the configuration of the PLL circuit is changed, and the frequency of the harmonic noise from the ring oscillator is changed. By changing the frequency of the harmonic noise from the ring oscillator and making it different from the reception frequency of the wireless device, the overlap of the two frequencies can be eliminated and interference can be suppressed. According to the present invention, a PLL circuit capable of changing the frequency of harmonic noise can be obtained. By making the frequency of the harmonic noise different from the reception frequency, interference can be eliminated, and a radio apparatus having good transmission / reception sensitivity can be obtained.

Example 1
As a first embodiment, a configuration example and a control method example of a first PLL circuit will be described with reference to FIGS. 3A is a block diagram showing the configuration of the PLL circuit 10 of the first embodiment, FIG. 3B is a timing diagram when the ring oscillator has a seven-stage inverter gate configuration, and FIG. 3C shows a timing when the ring oscillator has a five-stage inverter gate configuration. The figure is shown. FIG. 4 shows a spectrum of an interference wave from the ring oscillator, and FIG. 5 shows a flowchart showing a control method of the PLL circuit.

  The PLL circuit 10 includes a phase detector (PD) 1, a charge pump circuit (CP) 2, a low-pass filter (LBP) 3, a frequency divider 4, and a ring oscillator 9A. The ring oscillator includes a plurality of inverter gates 5 that are oscillation circuits and a changeover switch 6, and the changeover switch 6 switches the number of stages of the inverter gates 5 coupled in a ring shape to seven or five. The PLL circuit shown in FIG. 3A is different from the PLL circuit of FIG. 13 only in the configuration of the ring oscillator 9A, and the other components are the same as those in FIG.

  The ring oscillator 9A outputs a clock (Fck) with a frequency of 312 MHz, and the frequency divider 4 divides the clock (Fck) into 1/12 frequency-divided clocks. The phase detector 1 receives the divided clock and the reference clock (Fref) and compares the phases. The phase comparison result between the divided clock and the reference clock is input to the charge pump circuit 2 to control the output voltage of the charge pump circuit 2. The output voltage of the charge pump circuit 2 is smoothed by the low-pass filter 3 and supplied to the power source of the inverter gate 5 of the ring oscillator. When the phase of the divided clock is advanced in the phase detector 1, the output voltage of the charge pump circuit 2 is controlled to be low, and the oscillation frequency of the ring oscillator is lowered. Conversely, when the phase of the divided clock is delayed, the output voltage of the charge pump circuit 2 is controlled to be high, and the oscillation frequency of the ring oscillator is increased. Thus, by controlling the output voltage of the charge pump circuit 2 by the control signal from the phase detector 1, a PLL circuit for controlling the oscillation frequency of the ring oscillator can be configured.

  In the ring oscillator 9A, a changeover switch 6 is provided at the input of the first stage inverter gate 5 as shown in FIG. 3A. The change-over switch 6 switches the output G of the last-stage inverter gate 5 or the output E of the fifth-stage inverter gate according to a switching control signal. FIG. 3B shows the timing and power supply current waveform in the case of a seven-stage configuration in which the output G of the final-stage inverter gate 5 is input by the changeover switch 6. FIG. 3C shows the timing and power supply current waveform in the case of a five-stage configuration in which the output E of the fifth-stage inverter gate 5 is input by the changeover switch 6.

  In the ring oscillator 9A composed of seven stages of inverter gates in FIG. 3B, the output G from the final stage inverter gate is input to the first stage inverter gate 5, and the output A is output to the next stage. The inverter gates sequentially connected in a chain form output B to F to the subsequent stage. The output G of the final stage is again input to the inverter gate of the first stage, and the inverter gate of the first stage is inverted. In this way, oscillation occurs in a cycle in which the delay time for seven stages of inverter gates is a half cycle. Here, the seven inverter gates connected in a ring form an oscillation circuit. At this time, the power supply current waveform corresponds to the timing of the first output A, then the output C, the output E, the output G, the output B, the output D, and the output F in response to the inverter gate output changing from the low level to the high level. Peak current will flow. Harmonic noise is generated by the power supply current flowing at this time, and propagates in the air as electromagnetic noise or through the conductor through the power supply. Therefore, the frequency of the harmonic noise on the power source side generated at this time is the product of the number of inverter gate stages and the oscillation frequency, and is 7 × 312 MHz = 2184 MHz.

  In the ring oscillator 9A composed of five inverter gates in FIG. 3C, the output E from the fifth-stage inverter gate is input to the first-stage inverter gate 5, and the output A is output to the next stage. The inverter gates sequentially connected in a chain form output B to D to the subsequent stage. The fifth-stage output E is input to the first-stage inverter gate, and its output level is inverted. In this way, oscillation occurs in a cycle in which the delay time for five stages of inverter gates is a half cycle. At this time, the inverter gates at the sixth and seventh stages are not related to the oscillation frequency but function as simple inverter gates and transmit the transmission signal to the frequency divider. Here, the five inverter gates connected in a ring form an oscillation circuit. At this time, the waveform of the power source current is such that the peak current is the timing of the first output A and F, then the output C, output E, output B and G, and output D, corresponding to the inverter gate output changing from low level to high level. Will flow. Harmonic noise is generated by the power supply current flowing at this time, and propagates in the air as electromagnetic noise or through the conductor through the power supply. Accordingly, the frequency of the harmonic noise generated at this time is the product of the number of inverter gate stages and the oscillation frequency, and is 5 × 312 MHz = 1560 MHz.

  In the present invention, an inverter gate is adopted as a gate circuit constituting the ring oscillator, but it is not particularly limited. The ring oscillator may be a plurality of delay elements having a negative (-1 or less) gain as a whole. That is, any circuit that can delay the signal and feed back the inverted signal to the first stage may be used. Accordingly, it can be configured by combining a differential amplifier, a logic gate such as a NAND gate and a NOR gate, and basically a circuit that can feed back a signal inverted from the last stage to the logic gate of the first stage. The harmonic noise is 2184 MHz in the case of the seven-stage configuration and 1560 MHz in the case of the five-stage configuration, and the power consumption of the ring oscillator is small in the case of the five-stage configuration that operates at low speed.

  FIG. 4 shows the spectrum of the interference wave from the ring oscillator. In FIG. 4, the solid line A is a spectrum of a five-stage inverter gate configuration, and the dotted line B is a spectrum of a seven-stage inverter gate configuration. The frequency of the harmonic noise differs depending on the number of stages of the inverter gate, and the harmonic noise frequency of the five-stage inverter gate configuration is lower than the harmonic noise frequency of the seven-stage inverter gate configuration. FIG. 4 shows that the frequency band of the harmonic noise varies, but the number of inverter gates can be selected so that it does not overlap with the reception frequency. Thus, by eliminating the overlap between the frequency band of the harmonic noise and the reception frequency, the reception sensitivity of the wireless device can be maintained in a good state.

  Next, a flowchart of a control method of the PLL circuit when the PLL circuit 10 shown in the present embodiment (FIG. 3A) is applied to the radio apparatus 20 of FIG. 1 will be described with reference to FIG. Here, the circuit construction control signal from the control unit 25 is a switching control signal to the changeover switch 6. The number of inverter gates of the ring oscillator is switched to 5 or 7 by the switching control signal. As an initial stage of the PLL circuit, the ring oscillator is set to operate as a five-stage inverter gate with low power consumption by a switching control signal (circuit construction control signal) from the control unit 25 of the wireless device.

  In step S11, the control unit 25 checks whether the number of inverter gate stages of the ring oscillator 9A is five. If it is not a five-stage configuration (NO), it becomes step S15. In the case of a five-stage configuration (YES), in step S12, the control unit 25 refers to the table 1 when the ring oscillator has a five-stage configuration, and whether the interference wave frequency band includes (overlaps) the received wave frequency band. Make a comparison. Step S12 is a step of confirming the frequency of whether or not the harmonic noise (jamming wave) of the ring oscillator and the reception frequency of the wireless device overlap and interfere with each other. When the frequency band of the received wave and the interference wave frequency band do not overlap (NO), the process returns to step S12 with the five-stage inverter gate configuration.

  If the frequency band of the received wave overlaps with the frequency band of the disturbing wave (YES), there is a possibility that the reception sensitivity may deteriorate due to interference. Therefore, the control unit 25 determines the reception sensitivity of the wireless device and the table 26 in step S13. Compare and check the threshold. If the reception sensitivity is better than the threshold of the table 26 (NO), the process returns to step S12 with the five-stage inverter gate configuration. If the reception sensitivity is lower than the threshold of the table 26 (YES), in step 14, the control unit 25 switches the ring oscillator configuration to a seven-stage inverter configuration by a circuit construction control signal. If the reception frequency band and the interference wave frequency band overlap (overlapping), but the degree of interference is small and the reception sensitivity is good, the reception frequency and interference wave frequency should not interfere. Judgment is made as it is. When the reception frequency and the interference wave frequency interfere with each other and the reception sensitivity is deteriorated, it is determined that the reception frequency and the interference wave frequency interfere with each other, and the number of constituent stages of the ring oscillator is switched.

  Next, in step S15, the control unit 25 refers to the table 2 when the ring oscillator has seven stages, and confirms whether or not the received wave frequency band is included in the disturbing wave frequency band. If the received wave frequency band and the interference wave frequency band do not overlap (NO), the ring oscillator is switched to a five-stage configuration by a circuit construction control signal from the control unit 25 in step S17. When the frequency band of the received wave and the interference wave frequency band overlap (YES), the control unit 25 compares and confirms the reception sensitivity of the wireless device and the threshold value of the table 26 in step S16. If the reception sensitivity is better than the threshold of the table 26 (YES), the ring oscillator is switched to a five-stage configuration by a circuit construction control signal from the control unit 25 in step S17. If the reception sensitivity is worse than the threshold of the table 26 (NO), the process returns to step S15 with the ring oscillator having a seven-stage inverter gate configuration.

  As described above, in the PLL circuit, harmonic noise (interference wave) is generated by the power supply current of the inverter gate constituting the ring oscillator. As the initial stage of the PLL circuit, the PLL circuit is set to a state where power consumption is small. In this state, the harmonic noise frequency of the ring oscillator and the reception frequency of the wireless device may overlap, and communication sensitivity may deteriorate due to interference. In this case, the number of stages of the ring oscillator is switched by the changeover switch, the frequency of the harmonic noise is changed, and the harmonic noise frequency and the reception frequency are not overlapped to prevent interference. By changing the frequency of the harmonic noise, the wireless device is not affected by the harmonic noise, and the transmission / reception sensitivity of the wireless device is improved. A radio apparatus including the ring oscillator and the PLL circuit of this embodiment and having good reception characteristics can be configured.

(Example 2)
As a second embodiment, a configuration example and a control method example of the second PLL circuit will be described with reference to FIGS. FIG. 6A is a block diagram showing the configuration of the PLL circuit 10 according to the second embodiment, and FIG. FIG. 7 shows a spectrum of an interference wave from the ring oscillator, and FIG. 8 shows a flowchart showing a control method of the PLL circuit.

  The PLL circuit according to this embodiment includes a ring oscillator 9 in which a phase detector 1, a charge pump circuit 2, a low-pass filter 3, a frequency divider 4, and an inverter gate 5 are coupled in a seven-stage ring shape. Compared with the first embodiment, this embodiment has no changeover switch 6, the ring oscillator has a fixed configuration of seven stages of inverter gates as an oscillation circuit, and the frequency divider 4 is changed to the frequency divider 7. The frequency divider 7 is a frequency divider in which the frequency dividing ratio is not fixed and the frequency dividing ratio is variable from 11 to 13. Here, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  The ring oscillator 9 first outputs a clock (Fck) having a frequency of 312 MHz, and the frequency divider 7 divides the clock (Fck) into variable frequency-divided clocks from 1/11 to 1/13. The phase detector 1 receives the divided clock and the reference clock (Fref) and compares the phases. The phase comparison result between the divided clock and the reference clock is input to the charge pump circuit 2 to control the output voltage of the charge pump circuit 2. The output voltage of the charge pump circuit 2 is smoothed by the low-pass filter 3 and supplied to the power source of the inverter gate 5 of the ring oscillator. When the phase of the divided clock is advanced in the phase detector 1, the output voltage of the charge pump circuit 2 is controlled to be low, and the oscillation frequency of the ring oscillator is lowered. Conversely, when the phase of the divided clock is delayed, the output voltage of the charge pump circuit 2 is controlled to be high, and the oscillation frequency of the ring oscillator is increased. Thus, by controlling the output voltage of the charge pump circuit 2 by the control signal from the phase detector 1, a PLL circuit for controlling the oscillation frequency of the ring oscillator can be configured.

  In this embodiment, the frequency division ratio for dividing the clock generated from the ring oscillator is variable. By changing the frequency dividing ratio, the frequency of the harmonic noise generated by the ring oscillator is changed, and the overlap between the frequency of the harmonic noise and the reception frequency of the wireless device is reduced, thereby increasing the transmission / reception sensitivity.

  The frequency divider 7 can divide and divide within a range of 1/11 to 1/13. The method of changing the frequency division is not particularly limited. For example, the frequency is first divided into 1/12 frequency, the frequency is gradually increased, and the frequency is divided into 1/11 frequency. Thereafter, the frequency division is gradually reduced to 1/12, and further the frequency division is set to 1/13. When the frequency division becomes 1/13, the frequency division is gradually increased again and the frequency division is returned to 1/12. These controls are repeatedly performed based on the diffusion frequency division control signal. Thus, the minimum value of the division ratio is 12, 11, 12, 13, 12, and the average value of the division ratio is the center value of the minimum value and the maximum value of the division ratio. Changing the reciprocation between the maximum values is referred to as diffusion operation. Since the minimum value of the frequency division ratio is 11 and the maximum value is 13, the average value of the frequency division ratio at this time is 12.

  Following the change in the frequency division ratio, the frequency Fck of the oscillation clock from the ring oscillator is 312 MHz (frequency division ratio 12), 286 MHz (frequency division ratio 11), 312 MHz (frequency division ratio 12), 338 MHz (frequency division). Ratio 13) and 312 MHz (frequency division ratio 12). At that time, the harmonic noise generated from the ring oscillator changes between 2002 and 2184 to 2366 MHz. As shown in FIG. 6B, first, the frequency divider 7 outputs 26 MHz by dividing the frequency 312 MHz by 1/12. Thereafter, the frequency divider 7 outputs 26 MHz by dividing the frequency 286 MHz into 1/11. At this time, harmonic noise corresponding to the frequency of the power supply current waveform is generated from the ring oscillator.

  FIG. 7 shows a spectrum of harmonic noise due to the frequency division ratio in the PLL circuit shown in FIG. 6A. The waveform shown by a solid line A in FIG. 7 is a fixed type spectrum with a division ratio of 12, and the waveform shown by a dotted line B is a variable type spectrum example with a division ratio of 11 to 13. According to FIG. 7, the fixed type with the division ratio of 12 has a narrow frequency band but a large peak value. On the other hand, the variable type having a frequency division ratio of 11 to 13 has a broad frequency band and a small peak value. Accordingly, when the frequency of the harmonic noise and the reception frequency do not overlap, the frequency division ratio fixed type is selected, and when the frequency of the harmonic noise and the reception frequency overlap, the frequency division ratio variable type is selected. Even when the frequency of the harmonic noise and the reception frequency overlap, selecting the variable division ratio type will reduce the peak value of the frequency of the harmonic noise and reduce interference between the harmonic noise and the reception frequency. , Deterioration of reception sensitivity can be suppressed. Thus, by reducing the interference between the frequency band of the harmonic noise and the reception frequency, the reception sensitivity of the wireless device can be maintained in a good state.

  Next, a flowchart of a PLL circuit control method when the PLL circuit 10 shown in the present embodiment (FIG. 6A) is applied to the radio apparatus 20 of FIG. 1 will be described with reference to FIG. Here, the circuit construction control signal from the control unit 25 is a diffusion frequency division control signal to the frequency divider 7. The frequency divider is switched to a fixed frequency division operation of 1/12 or a diffusion frequency division operation of 1/11, 1/12, and 1/13 by a diffusion frequency division control signal (circuit construction control signal). As an initial stage of the PLL circuit, the frequency divider is set to a fixed frequency division operation of 1/12 with low power consumption by a diffusion frequency division control signal (circuit construction control signal) from the control unit 25 of the wireless device.

  In step S21, the control unit 25 confirms whether the frequency division ratio of the PLL circuit 10 including the ring oscillator is fixed (12). If it is not fixed (NO), step S25 is performed. If it is fixed (YES), in step S22, the control unit 25 refers to the table in the case where the frequency division ratio is fixed, and compares whether the interference frequency band includes (overlaps) the received wave frequency band. . Step S22 is a step of checking whether or not the harmonic noise (jamming wave) of the ring oscillator and the reception frequency of the wireless device overlap and interfere with each other. If the frequency band of the received wave and the interference wave frequency band do not overlap (NO), the process returns to step S22 with the frequency division ratio fixed.

  If the frequency band of the received wave overlaps with the frequency band of the disturbing wave (YES), there is a possibility that the reception sensitivity may deteriorate due to interference. Compare and check the threshold. If the reception sensitivity is better than the threshold of the table 26 (NO), the process returns to step S22 with the frequency division ratio fixed. If the reception sensitivity is worse than the threshold of the table 26 (YES), in step S24, the control unit 25 switches the division ratio to the diffusion division operation by the diffusion division control signal. If the reception frequency band and the interference wave frequency band overlap (overlapping), but the degree of interference is small and the reception sensitivity is good, the reception frequency and interference wave frequency should not interfere. Judgment is made as it is. When the reception frequency and the interference wave frequency interfere with each other and the reception sensitivity is deteriorated, it is determined that the reception frequency and the interference wave frequency interfere with each other, and the frequency division ratio is switched to the diffusion frequency division operation.

  Next, in step S25, the control unit 25 refers to the table for the frequency division ratio during the diffusion frequency division operation, and confirms whether the received wave frequency band is included in the interference wave frequency band. If the received wave frequency band and the interference wave frequency band do not overlap (NO), the operation is switched to the frequency division ratio fixing operation by the spread frequency division control signal from the control unit 25 in step S27. When the frequency band of the received wave and the interference wave frequency band overlap (YES), the control unit 25 compares and confirms the reception sensitivity of the wireless device and the threshold value of the table 26 in step S26. If the reception sensitivity is better than the threshold of the table 26 (YES), the operation is switched to the frequency division ratio fixing operation by the diffusion frequency division control signal from the control unit 25 in step S27. If the reception sensitivity is worse than the threshold value in the table 26 (NO), the process returns to step S25 with the frequency dividing ratio being the diffusion frequency dividing operation.

  As described above, in the PLL circuit, harmonic noise (interference wave) is generated by the power supply current of the inverter gate constituting the ring oscillator. As the initial stage of the PLL circuit, the PLL circuit is set to a state where power consumption is small. In this state, the harmonic noise frequency of the ring oscillator and the reception frequency of the wireless device may overlap, and communication sensitivity may deteriorate due to interference. In this case, switching from the division ratio fixing operation to the diffusion division operation is performed by the spread division control signal, the frequency of the harmonic noise is changed, and the overlap between the harmonic noise frequency and the reception frequency is reduced. In this way, by performing the diffusion operation of the frequency division ratio, the harmonic noise is diffused in a band that is the number of phases of the clock (Fck). By diffusing harmonic noise to a band larger than the reception frequency bandwidth of the wireless device, it becomes possible to reduce the noise power within the reception frequency band, and to dramatically reduce the amount of interference. .

  In the present embodiment, the noise power in the reception frequency band of the wireless device is reduced by spreading the frequency of the harmonic noise. Therefore, the influence of the harmonic noise from the ring oscillator on the reception frequency of the wireless device can be reduced. A radio receiving circuit having the ring oscillator and the PLL circuit of this embodiment and having good receiving characteristics can be configured.

(Example 3)
As a third embodiment, a configuration example and a control method example of a third PLL circuit will be described with reference to FIGS. FIG. 9A is a block diagram showing the configuration of the PLL circuit 10 according to the third embodiment, and FIGS. 9B and 9C are timing charts thereof. FIG. 10 shows the interference wave spectrum from the PLL circuit. FIG. 11 is a flowchart showing a control method of the PLL circuit in this embodiment.

  The PLL circuit 10 in FIG. 9A includes a phase detector 1, a charge pump circuit 2, a low-pass filter 3, a frequency divider 4, and a ring oscillator 9B. The ring oscillator 9B includes delay circuits 8A and 8B, three stages of inverter gates 5, and a changeover switch 6. Compared with the first embodiment, the present embodiment has a configuration in which a part of the inverter gate 5 of the ring oscillator is changed to the delay circuits 8A and 8B, and the delay circuits 8A and 8B are switched by the changeover switch 6. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  As shown in FIG. 9A, the ring oscillator 9B is provided with a changeover switch 6. The changeover switch 6 switches between the delay circuits 8A and 8B according to a changeover control signal, and the ring oscillator has a delay circuit 8A and a three-stage inverter gate configuration, or a delay circuit 8B and a three-stage inverter gate configuration. Here, the delay times of the delay circuits 8A and 8B are different, and the delay time of the delay circuit 8A is set shorter than the delay time of the delay circuit 8B. For example, the delay circuit 8A is a delay circuit having a delay time corresponding to two stages of inverter gates, and the delay circuit 8B is a delay circuit having a delay time corresponding to four stages of inverter gates. In this case, the circuit configuration corresponds to the configuration of the five-stage inverter gate and the seven-stage inverter gate in the first embodiment. Hereinafter, the case of the delay circuit 8A and the inverter gate three-stage configuration is simply expressed as a delay circuit 8A configuration, and the case of the delay circuit 8B and the inverter gate three-stage configuration is simply expressed as a delay circuit 8B configuration.

  FIG. 9B shows the timing and power supply current waveform in the case of the configuration of the delay circuit 8A by the changeover switch 6. FIG. 9C shows the timing and power supply current waveform in the case of the configuration of the delay circuit 8B by the changeover switch 6. In the case of the configuration of the delay circuit 8A, the output C of the final stage of the inverter gate is input to the delay circuit 8A. The delay circuit 8A delays the input signal for a predetermined time and outputs it to the inverter gate as a signal Td. The first-stage inverter gate receives the signal Td and outputs the output A to the next-stage inverter gate. The next-stage inverter gate outputs the output B, and the final-stage inverter gate outputs the output C to the delay circuit 8A and the frequency divider 4. The ring oscillator 9B oscillates at a period in which a time corresponding to the sum of the delay time of the three stages of the inverter gate and the delay time of the delay circuit 8A is a half cycle. Here, the delay circuit 8A and three stages of inverter gates form an oscillation circuit.

  In the case of the delay circuit 8B configuration, the delay circuit 8B is used instead of the delay circuit 8A, and the same configuration and operation are performed. Since the delay time of the delay circuit 8A is shorter than the delay time of the delay circuit 8B, the operation speed of the inverter gate of the delay circuit 8A configuration is slower than the operation speed of the inverter gate of the delay circuit 8B configuration. Here, the configuration of the delay circuits 8A and 8B is not particularly limited, but can be configured by, for example, an RC delay circuit. Since the RC delay circuit has few rapid changes in the power supply current and the ground current, the generation of harmonic noise is small.

  FIG. 10 shows a spectrum of harmonic noise (jamming wave) from the ring oscillator 9B. The solid line A has a delay circuit 8A configuration (delay circuit 8A and a three-stage inverter gate configuration), and the dotted line B has a delay circuit 8B configuration (delay circuit 8B and a three-stage inverter gate configuration). The delay circuit 8A has a delay amount for two stages of inverter gates, and the delay circuit 8B has a delay amount for four stages of inverter gates. The frequency band of any harmonic noise is broad, but the configuration of the delay circuit 8B is broader. The peak values are all small. As indicated by a solid line A or a dotted line B, the frequency of the harmonic noise differs depending on the delay circuit having a different delay time. Therefore, it can be seen that the configuration of the ring oscillator can be selected so as not to overlap with the reception frequency. Thus, by eliminating the overlap between the frequency band of the harmonic noise and the reception frequency, the reception sensitivity of the wireless device can be maintained in a good state.

  Next, a flowchart of a control method of the PLL circuit when the PLL circuit 10 of the present embodiment is applied to the wireless device 20 of FIG. 1 will be described with reference to FIG. Here, the circuit construction control signal from the control unit 25 is a switching control signal to the changeover switch 6. The delay circuit is switched to 8A or 8B by the switching control signal. As an initial stage of the PLL circuit, the ring oscillator is set to a delay circuit 8A configuration with low power consumption by a switching control signal (circuit construction control signal) from the control unit 25 of the wireless device.

  In step S31, the control unit 25 checks whether the configuration of the ring oscillator 9B is the delay circuit 8A. If the ring oscillator does not have the delay circuit 8A configuration (NO), the process goes to step S35. In the case of the delay circuit 8A configuration (YES), in step S32, the control unit 25 refers to the table A of the delay circuit 8A configuration to compare whether the interference frequency band includes (overlaps) the received wave frequency band. I do. In step S32, the harmonic noise (jamming wave) of the ring oscillator and the reception frequency of the wireless device overlap, and the frequency of whether or not the interference is confirmed. If the frequency band of the received wave and the interference wave frequency band do not overlap (NO), the process returns to step S32 with the delay circuit 8A configuration.

  If the frequency band of the received wave overlaps with the frequency band of the disturbing wave (YES), there is a possibility that the reception sensitivity may deteriorate due to interference. Compare and check the threshold. If the reception sensitivity is better than the threshold of Table A (NO), the process returns to Step S32 with the delay circuit 8A configuration. If the reception sensitivity is lower than the threshold value of Table A (YES), in step S34, the control unit 25 has a delay circuit 8B configuration in which the ring oscillator is configured by a delay circuit 8B and three stages of inverter gates by a circuit construction control signal. Switch as follows. If the reception frequency band and the interference wave frequency band overlap, but the degree of interference is small and the reception sensitivity is good, it is determined that the reception frequency and the interference wave frequency do not interfere with each other. And When the reception frequency and the interference wave frequency interfere with each other and the reception sensitivity is deteriorated, it is determined that the reception frequency and the interference wave frequency interfere with each other, and the delay circuit is switched.

  Next, in step S35, the control unit 25 refers to the type B table B and confirms whether or not the interference wave frequency band includes the reception wave frequency band. If the received wave frequency band and the interference wave frequency band do not overlap (NO), the configuration is switched to the delay circuit 8A configuration by a circuit construction control signal from the control unit 25 in step S37. If the frequency band of the received wave and the interference wave frequency band overlap (YES), the control unit 25 compares and confirms the reception sensitivity of the wireless device and the threshold value of Table B in step S36. If the reception sensitivity is better than the threshold value of Table B (YES), the ring oscillator is switched to the delay circuit 8A configuration by a circuit construction control signal from the control unit 25 in step S37. If the reception sensitivity is worse than the threshold of Table B (NO), the process returns to Step S35 with the ring oscillator configured as the delay circuit 8B.

  In the ring oscillator of the PLL circuit of the present embodiment, a part of the inverter gate is constituted by a delay circuit. Each delay circuit has a different delay time, and different delay circuits are connected by a changeover switch. When the harmonic noise frequency of the ring oscillator and the reception frequency of the wireless device overlap and the communication sensitivity deteriorates due to interference, these delay circuits are switched by the changeover switch. By switching the delay circuit and changing the frequency of the harmonic noise, the harmonic noise frequency and the reception frequency are not overlapped with each other to prevent interference. By changing the frequency of the harmonic noise, the wireless device is not affected by the harmonic noise, and the transmission / reception sensitivity of the wireless device is improved. A radio apparatus including the ring oscillator and the PLL circuit of this embodiment and having good reception characteristics can be configured.

(Example 4)
As a fourth embodiment, a fourth control method example will be described. Embodiments 1 to 3 are control methods of a PLL circuit that measures and controls a reception frequency and its reception sensitivity as a wireless device. However, the PLL circuit control method according to the fourth embodiment is a simple control method using a table in which interference frequencies are recorded without measuring the reception sensitivity of the reception frequency as a wireless device. A fourth embodiment will be described with reference to FIGS.

  The wireless device of FIG. 1 includes a table as shown in FIG. In the first to third embodiments, the table shows the lower limit frequency and upper limit frequency of the frequency band of the harmonic noise (jamming wave) generated from the ring oscillator 9 and the threshold value at that time. This table is, for example, a table for only the interference frequency band. In the table 26 of FIG. 2, the threshold is not adopted only for the interference wave frequency band. For example, in the relationship between the interference frequency shown in the spectrum of FIG. 4 and its intensity (db), if the transmission / reception sensitivity of the wireless device is affected as an interference wave, it is described in the table as the interference frequency. On the other hand, when the intensity (db) is less than a certain value and does not affect the transmission / reception sensitivity of the wireless device, or the influence is small, it is not described in the table as the interference frequency. That is, in the spectrum of FIG. 4, for example, when the intensity is higher than a certain intensity such as 5 dB or higher, or 10 dB or higher, the interference frequency band is stored in the table 26. In the case of an intensity lower than that, even if interference occurs, it is not regarded as an interference wave frequency band because the reception sensitivity is at a satisfactory level.

  The PLL circuit built in the wireless device has several configurations as described in detail in the first to third embodiments, and has respective operation modes. A table 26 in which the interference frequency is described for each configuration and operation mode is created. When the wireless device receives a specific reception frequency, the control unit 25 compares the reception frequency with the interference frequency stored in the table 26. The control unit 25 selects a PLL circuit in an operation mode that does not include a reception frequency as an interference frequency. The configuration of the ring oscillator or the frequency divider is changed by a circuit construction control signal from the control unit 25 to configure a PLL circuit that operates in a desired operation mode. In this way, the PLL circuit is selected such that the frequency of the reception frequency of the wireless device and the interference frequency generated by the PLL circuit do not overlap. Since the reception frequency and the interference frequency of the wireless device do not overlap, a PLL circuit with good reception sensitivity and a wireless device including the PLL circuit can be obtained.

  In this embodiment, a PLL circuit in an operation mode in which the frequency of the reception frequency of the wireless device and the interference frequency do not overlap is selected to configure the PLL circuit. Since the reception frequency and the interference wave frequency of the wireless device do not overlap, a PLL circuit with good reception sensitivity and a wireless device including the PLL circuit can be obtained.

  As described above, in the LL circuit of the present invention, when the harmonic noise generated from the PLL circuit interferes with the transmission / reception frequency of the wireless device and the reception sensitivity is lowered, the configuration of the PLL circuit is changed, and the harmonics of the ring oscillator are changed. Change the frequency of wave noise. The frequency of the harmonic noise is changed so that the harmonic noise frequency and the reception frequency do not overlap to prevent interference. By changing the frequency of the harmonic noise in this way, the wireless device is not affected by the harmonic noise, and the transmission / reception sensitivity of the wireless device is improved. A radio apparatus including the ring oscillator and the PLL circuit of this embodiment and having good reception characteristics can be configured.

  As mentioned above, although this invention was demonstrated as embodiment and an Example, this invention is not limited to said embodiment. Various changes can be made to the configuration and details of the present invention within the scope of the present invention.

1 Phase detector (PD)
2 Charge pump (CP)
3 Low-pass filter (LPF)
4, 7 Frequency divider 5 Inverter gate (logic inversion circuit)
6 switch 8A, 8B delay circuit 9, 9A, 9B ring oscillator 10 PLL circuit 11 transmitting station 20 wireless device 21 antenna 22 power amplification unit 23 frequency conversion unit 24 baseband unit 25 control unit 26 table 27 local oscillator

Claims (2)

A detecting means for detecting the receiving sensitivity of the receiving frequency, and a control means for comparing the detected receiving sensitivity with a threshold value to determine whether or not the receiving sensitivity is deteriorated and outputting a control signal when the receiving sensitivity is determined to be deteriorated. a ring oscillator that will be incorporated in the wireless device, wherein the control means is a plurality of types stored the frequency band of the harmonic noise generated from the ring oscillator as a table, the said table, is generated from the ring oscillator The lower limit frequency and the upper limit frequency of the harmonic noise frequency band and the threshold value of the reception sensitivity at that time are classified for each of the plurality of types, and the control means refers to the table and uses the frequency of the reception frequency being used. Check whether the band is included in the frequency band of the harmonic noise, and if included, the received sensitivity detected for the reception frequency being used and the above When the reception sensitivity and the detected by comparing the value is inferior than the threshold value, which is determined to change the frequency of the harmonic noise generated from the ring oscillator for outputting said control signal,
The ring oscillator, Bei example a changeover switch for switching the configuration of the oscillation circuit and receiving said control signal and the oscillation circuit,
The oscillation circuit is composed of a plurality of inverter gates,
The ring oscillator, the Ru receiving the control signal from the control unit, the switching configuration of the oscillation circuit by the changeover switch, ring and changing the frequency of the harmonic noise which the oscillating circuit is generated Oscillator. A detecting means for detecting the receiving sensitivity of the receiving frequency, and a control means for comparing the detected receiving sensitivity with a threshold value to determine whether or not the receiving sensitivity is deteriorated and outputting a control signal when the receiving sensitivity is determined to be deteriorated. a ring oscillator that will be incorporated in the wireless device, wherein the control means is a plurality of types stored the frequency band of the harmonic noise generated from the ring oscillator as a table, the said table, is generated from the ring oscillator The lower limit frequency and the upper limit frequency of the harmonic noise frequency band and the threshold value of the reception sensitivity at that time are classified for each of the plurality of types, and the control means refers to the table and uses the frequency of the reception frequency being used. Check whether the band is included in the frequency band of the harmonic noise, and if included, the received sensitivity detected for the reception frequency being used and the above When the reception sensitivity and the detected by comparing the value is inferior than the threshold value, which is determined to change the frequency of the harmonic noise generated from the ring oscillator for outputting said control signal,
The ring oscillator, Bei example a changeover switch for switching the configuration of the oscillation circuit and receiving said control signal and the oscillation circuit,
The oscillation circuit includes a plurality of inverter gates and first and second delay circuits having different delay times and switched to the plurality of inverter gates.
The ring oscillator, the Ru receiving the control signal from said control means, a delay circuit connected to an inverter gate of said plurality of stages by the selector switch, to either the other of said first or second delay circuit A ring oscillator , wherein the frequency of harmonic noise generated by the oscillation circuit is changed by switching connection.

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