JP2006303609A - Signal oscillator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a multiband/multimode terminal which can generate signals in two types or more of frequency band simultaneously using one signal oscillator. <P>SOLUTION: The signal oscillator comprises a phase comparator 1 for comparing the phase between a reference signal inputted to one input terminal and a signal inputted to the other input terminal, a loop filter 2 receiving an output signal from the phase comparator 1, a voltage controlled oscillator 3 receiving an output signal from the loop filter 2, a first N frequency divider 4A receiving an output signal from the voltage controlled oscillator 3 and outputting a first frequency division signal, and a second N frequency divider 4B receiving the first frequency division signal and outputting a second frequency division signal to the other input terminal of the phase comparator 1. The voltage controlled oscillator 3 is provided with a first signal output terminal, the first N frequency divider 4A is provided with a second signal output terminal outputting a first frequency division signal, and the second N frequency divider 4B is provided with a third signal output terminal outputting a second frequency division signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a signal oscillator capable of generating a plurality of signals including a plurality of frequency bands.

  Conventionally, mobile phones have used dedicated wireless terminals for each wireless communication system, but in recent years, with the diversification and globalization of mobile phones, there is a demand for multiband and multimode terminals that can support multiple communication systems. It is increasing. In order to realize a multiband multimode terminal, a plurality of signal oscillators having different frequency bands are required. However, if it is intended to mount a plurality of signal oscillators in a multiband multimode terminal, it becomes difficult to reduce the size of the terminal.

  Therefore, a multiband oscillator that can be miniaturized as shown in FIG. 6 has been proposed (see, for example, Patent Document 1). As shown in FIG. 6, the conventional multiband oscillator includes a frequency synthesizer 308, a variable multiplier 306 that receives an output signal from the frequency synthesizer 308, converts the frequency to M times, and outputs the frequency synthesizer 308. The frequency control unit 309 controls the frequency of the first variable multiplier 306.

  The frequency synthesizer 308 converts the reference signal output from the reference oscillator 304 into a P-fold frequency by the second variable multiplier 305 and outputs it to the phase comparator 301. The voltage-controlled oscillator 302 outputs the generated signal to the variable frequency divider 303, and the variable frequency divider 303 converts the frequency of the input signal to 1 / Q, and the first variable multiplier 306 and the phase Each is output to the comparator 301.

As described above, the conventional multiband oscillator includes a frequency multiplier P in the second variable multiplier 305, a frequency divider Q in the variable frequency divider 303, and a frequency multiplier in the first variable multiplier 306, which constitute the frequency synthesizer 308. By setting M for each communication method, signals in a plurality of frequency bands can be generated.
JP 2004-356801 A (FIG. 3)

  However, the conventional multiband oscillator can generate signals of different frequency bands, but cannot simultaneously generate signals of two or more types of frequency bands. As an example, in the UMTS (Universal Mobile Telecommunication System) method among the communication methods, since signals are transmitted and received at the same time, at least two signals in the frequency band for transmission and signals in the frequency band for reception are signals. Is required. For this reason, since two sets of the multiband oscillators described above are required, there is a problem that the miniaturization of the multiband multimode terminal cannot be realized.

  An object of the present invention is to solve the above-mentioned conventional problems and to realize a multiband multimode terminal capable of simultaneously generating signals of two or more frequency bands with one signal oscillator.

  In order to achieve the above object, the present invention has a configuration in which a signal oscillator receives a signal output from a voltage controlled oscillator in series by at least two frequency dividers, and each frequency divider outputs a frequency-divided signal. To do.

  Specifically, the signal oscillator according to the present invention is intended for a signal oscillator that can simultaneously output signals including a plurality of frequency bands, and a reference signal is input to one input terminal and an input is input to the other input terminal. A phase comparator for comparing the phase of the signal, a voltage controlled oscillator for receiving an output signal from the phase comparator, an output signal from the voltage controlled oscillator for outputting a divided signal and the other input terminal of the phase comparator A frequency divider for outputting the second frequency-divided signal, a first signal output terminal for receiving the output signal from the voltage controlled oscillator, and a second signal output terminal for receiving the frequency-divided signal. Features.

  According to the signal oscillator of the present invention, a frequency divider that receives an output signal from the voltage controlled oscillator, outputs a frequency-divided signal, and outputs a frequency-divided signal to the other input terminal of the phase comparator, Since the first signal output terminal for receiving the output signal from the controlled oscillator and the second signal output terminal for receiving the frequency-divided signal are provided, signals having at least two different frequencies can be output simultaneously. . As a result, it is possible to simultaneously generate signals of two or more types of frequency bands with a single signal oscillator, and thus it is possible to reduce the size of a multiband / multimode terminal.

  The signal oscillator of the present invention preferably further includes a multiplier that receives the output signal and the frequency-divided signal from the voltage-controlled oscillator and outputs them to the second signal output terminal. In this way, a signal having a frequency band higher than the oscillation frequency of the signal generated by the voltage controlled oscillator can be obtained.

  In this case, it is preferable that the second frequency divider is a variable frequency divider that can change the frequency division number for the input signal.

  In this case, the multiplier is preferably switchable between a first function for multiplying two input signals and a second function for amplifying and outputting one of the two input signals.

  In this case, the multiplier is preferably composed of a double balance type mixer circuit.

  The double-balanced mixer circuit in this case preferably has an impedance element having frequency selectivity as its load.

  The multiplier preferably outputs the sum of the frequencies of the two input signals.

  The multiplier preferably outputs the difference between the frequencies of the two input signals.

  The multiplier preferably outputs the sum or difference of the frequencies of the two input signals.

  In the signal oscillator of the present invention, it is preferable that the first frequency divider is constituted by a D (Delay) type flip-flop circuit.

  The mobile phone terminal preferably includes the signal oscillator of the present invention.

  The mobile phone base station preferably includes the signal oscillator of the present invention.

  The mobile communication terminal device preferably includes the signal oscillator according to the present invention.

  The mobile communication base station apparatus preferably includes the signal oscillator of the present invention.

  According to the signal oscillator according to the present invention, it is possible to simultaneously generate signals of two or more types of frequency bands with one signal oscillator, and thus it is possible to reduce the size of a multiband multimode terminal.

(First embodiment)
A first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows a block configuration of a signal oscillator according to the first embodiment of the present invention. As shown in FIG. 1, in the signal oscillator according to the first embodiment, one input terminal of two input terminals is connected to a reference signal input terminal 6, and the signal input to the other input terminal is between The phase comparator 1 for comparing the phases at 1, the loop filter 2 as a smoother connected to the output terminal of the phase comparator 1, and the voltage controlled oscillator (VCO) 3 connected to the output terminal of the loop filter 2 A first N frequency divider 4A connected to the output terminal of the voltage controlled oscillator 3 and outputting the input signal as a first frequency divided signal; and an output terminal of the first N frequency divider 4A And a second N divider 4B that divides the inputted first divided signal and outputs the divided first divided signal to the other input terminal of the phase comparator 1 as a second divided signal. Yes. Here, N in the first N frequency divider 4A and the second N frequency divider 4B represents a frequency division number greater than 1, and the frequency of each input signal is output at 1 / N.

  The phase comparator 1, the loop filter 2, the voltage controlled oscillator 3, the first N frequency divider 4A, and the second N frequency divider 4B constitute a frequency synthesizer 7.

  Further, the signal oscillator includes a first signal output terminal 5A that receives an output signal from the voltage controlled oscillator 3, and a second signal output terminal that receives the first divided signal from the first N divider 4A. 5B and a third signal output terminal 5C that receives the second frequency-divided signal from the second N frequency divider 4B are provided.

  Hereinafter, the operation of the signal oscillator configured as described above will be described.

  First, in the phase comparator 1, the phase of the reference signal input from the reference signal input terminal 6 and the phase of the second frequency-divided signal output from the second N frequency divider 4B are compared with each other and compared. The processed signal is smoothed by the loop filter 2 at the subsequent stage.

  Next, the signal smoothed in the loop filter 2 is applied as a control voltage to the voltage controlled oscillator 3, and the voltage controlled oscillator 3 oscillates at a frequency corresponding to the applied control voltage. The output signal from the voltage controlled oscillator 3 is divided by N by the first N divider 4A, further divided by N by the second N divider 4B at the subsequent stage, and input to the phase comparator 1 again. . Here, due to the action of feedback, in the phase comparator 1, the frequency of the output signal of the second N frequency divider 4B matches the frequency of the reference signal. Therefore, if a stable signal source with little fluctuation is used as the reference signal, the output signal of the voltage controlled oscillator 3 obtained from the first signal output terminal 5A and the first N frequency division obtained from the second signal output terminal 5B. The first frequency-divided signal of the frequency divider 4A and the second frequency-divided signal of the second N-frequency divider 4B obtained from the third signal output terminal 5C are stable with little frequency fluctuation.

Hereinafter, the frequencies obtained from the first to third signal output terminals 5A, 5B, 5C will be described. When the oscillation frequency of the voltage controlled oscillator 3 and f _0, a frequency of the signal output from the first signal output terminal 5A is the first divided signal outputted from the f _0, and the second signal output terminal 5B The frequency is f ₀ / N and p, and the frequency of the second divided signal output from the third signal output terminal 5C is f ₀ / N ² .

Here, if the range of the oscillation frequency in the voltage controlled oscillator 3 is f ₀₁ to f ₀₂ , the respective frequency ranges of the signal output terminals 5A, 5B, and 5C are f ₀₁ to f ₀₂ and f ₀₁ / N to f, respectively. ₀₂ / N, and f ₀₂ / N ² changed from f ₀₁ / N ^2, it is possible to obtain a signal at the same time three different frequency bands.

As an example, if the frequency division number N = 2, f ₀₁ = 1710 MHz and f ₀₂ = 1830 MHz, the frequency range of the signal output from the first signal output terminal 5A is 1710 MHz to 1830 MHz, and the second signal output terminal 5B The frequency range of the signal output from is 855 MHz to 915 MHz.

  By the way, the transmission frequency band in the GSM (Global System Mobile communication) system is 880 MHz to 915 MHz. The transmission frequency band in the DCS (Digital Cellular System) system is 1710 MHz to 1785 MHz. Therefore, the frequency range of the signal output from the first signal output terminal 5A includes the DCS transmission frequency band, and the frequency range of the signal output from the second signal output terminal 5B is the GSM transmission frequency. It can be seen that the band is included.

  As described above, in the first embodiment, signals of two or more types of frequency bands can be generated simultaneously. In addition, the multiband oscillator according to the conventional example shown in FIG. 6 requires the first variable multiplier 306 in addition to the synthesizer 308. However, the signal oscillator according to the present embodiment includes only the frequency synthesizer 7. The

  In the first embodiment, two frequency dividers are provided like the first N frequency divider 4A and the second N frequency divider 4B. However, one may be provided, and three or more. It may be provided. In this case, the signal output terminals may be further increased as the number of N frequency dividers increases.

  In the first embodiment, the frequency division numbers of the first N frequency divider 4A and the second N frequency divider 4B are both set to the same value as N, but are set to different values. Also good.

  Further, the first N frequency divider 4A and the second N frequency divider 4B may be configured by a D (Delay) type flip-flop circuit. Since the D-type flip-flop can obtain two sets of signals having a phase difference of 90 ° as output signals, a 90 ° phase shift circuit is not provided outside the signal oscillator according to the present embodiment. , A signal having a phase difference of 90 ° can be obtained.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

  FIG. 2 shows a block configuration of a signal oscillator according to the second embodiment of the present invention. In FIG. 2, the same components as those shown in FIG.

  As shown in FIG. 2, the signal oscillator according to the second embodiment includes a first multiplier circuit 8A, a second multiplier circuit 8B, and a third multiplier circuit 8C in addition to the signal oscillator according to the first embodiment. This is an added configuration.

  Specifically, the first multiplication circuit 8A multiplies the output signal from the voltage controlled oscillator 3 and the first frequency division signal from the first N frequency divider 4A to obtain a first signal output terminal. Output to 51A. The second multiplication circuit 8B multiplies the first divided signal from the first N divider 4A and the second divided signal from the second N divider 4B to obtain the second frequency The signal is output to the signal output terminal 51B. The third multiplication circuit 8C multiplies the second frequency-divided signal from the second N frequency divider 4B and the output signal from the voltage controlled oscillator 3, and outputs the result to the third signal output terminal 51C.

Next, the frequencies obtained from the first to third signal output terminals 5A, 5B, 5C will be described. If the oscillation frequency in the voltage controlled oscillator 3 is f ₀ , the frequency of the signal output from the first signal output terminal 51A is (N + 1) f ₀ / N, and the frequency of the signal output from the second signal output terminal 51B is The frequency is (N + 1) f ₀ / N ² , and the frequency of the signal output from the third signal output terminal 51C is (N ² +1) f ₀ / N ² .

Here, assuming that the range of the oscillation frequency in the voltage controlled oscillator 3 is f ₀₁ to f ₀₂ , the frequency range of the signal output from each signal output terminal 51A, 51B, 51C is from (N + 1) f ₀₁ / N ( N + 1) f ₀₂ / N, (N + 1) f ₀₁ / N ² to (N + 1) f ₀₂ / N ² , and (N ² +1) f ₀₁ / N ² to (N ² +1) f ₀₂ / N ² , simultaneously It is possible to obtain signals of three different frequency bands.

Moreover, the signal oscillator according to the first embodiment cannot obtain a signal in a frequency band higher than the oscillation frequency generated by the voltage-controlled oscillator 3, but in the second embodiment, (N + 1) f ₀₁ / N to (N + 1) f ₀₂ / N, and (N ₂ +1) f ₀₁ / N ₂ to (N ₂ +1) f ₀₂ / N ₂ , higher frequencies than the oscillation frequency generated by the voltage controlled oscillator 3 Band signals can also be obtained.

  As described above, in the second embodiment, it is possible to simultaneously generate signals of two or more types of frequency bands. Furthermore, a signal in a frequency band higher than the oscillation frequency generated by the voltage controlled oscillator 3 can be obtained.

  In the second embodiment, two frequency dividers are provided like the first N frequency divider 4A and the second N frequency divider 4B. However, three or more frequency dividers may be provided. In this case, the signal output terminals may be further increased as the number of N frequency dividers increases.

  In the second embodiment, the frequency division numbers of the first N frequency divider 4A and the second N frequency divider 4B are both set to the same value as N, but are set to different values. Also good.

  In the second embodiment, each of the first to third multiplication circuits 8a, 8b, and 8c is configured to output the sum of the input frequencies. However, the present invention is not limited to this configuration. May be output, and the sum or difference of the input frequencies may be output.

(One Modification of Second Embodiment)
Hereinafter, a modification of the second embodiment of the present invention will be described with reference to the drawings.

  FIG. 3 is an example of each multiplication circuit according to a modification of the second embodiment of the present invention, and shows a circuit configuration of a double balance type mixer circuit as multiplication means capable of switching between a multiplication function and an amplification function. ing.

  As shown in FIG. 3, the double-balanced mixer circuit according to this modification is a general mixer circuit, and includes a first pair of NPN bipolar transistors each receiving a bias current from the first bias circuit 103. The differential transistor pair 105 and 106, the second differential transistor pair 107 and 108, and the bias current received from the second bias circuit 104, one of the pair of NPN bipolar transistors is the first differential transistor pair 105. , 106, and the other is a third differential transistor pair 109, 110 cascode-connected to the second differential transistor pair 107, 108, and a first current source 112 A connected to the emitter of the transistor 109. And a second current source 112B connected to the emitter of the transistor 110, That.

  The first bias circuit 103 is provided with first input terminals 101A and 101B, and the first bias current is applied to the first differential transistor pair 105 and 106 and the second differential transistor pair 107 and 108. The second bias current is output to the bases of the transistors 105 and 108, and the second bias current is output to the bases of the transistors 106 and 107.

  The second bias circuit 104 is provided with second input terminals 102A and 102B, and the first bias current is output to the base of the transistor 110 of the third differential transistor pair 109 and 110, The second bias current is output to the base of the transistor 109.

  A first impedance element 111 is connected to the emitters of the third differential transistor pair 109 and 110. Of the first differential transistor pair 105 and 106 and the second differential transistor pair 107 and 108, the collectors of the transistor 105 and the transistor 107 are both connected to the power supply terminal 115 via the second impedance element 113. The collectors of the transistor 106 and the transistor 108 are both connected to the power supply terminal 115 via the third impedance element 114.

  An output terminal 116A is provided between the second impedance element 113 and the collector of the transistor 105, and an output terminal 116B is provided between the third impedance element 114 and the collector of the transistor 108.

  Hereinafter, the multiplication operation in the double balance type mixer circuit configured as described above will be described.

  First, a signal input to the first input terminals 101A and 101B of the first bias circuit 103 is superimposed with a bias voltage by the first bias circuit 103, and the first differential transistor pair 105 and 106 and The signals are input to the second differential transistor pair 107 and 108, respectively.

  Similarly, a signal input to the second input terminals 102A and 102B of the second bias circuit 104 is superimposed with a bias voltage by the second bias circuit 104, and the third differential transistor pair 109 and 110 is superimposed. Is input. Here, the multiplication result of the two input signals input to the first bias circuit 103 and the second bias circuit 104 is output from the output terminals 116A and 116B.

  On the other hand, by changing the setting for the first bias circuit 103, an amplification operation for amplifying signals input from the second input terminals 102A and 102B can be performed. Specifically, the first bias circuit is configured so that the transistors 106 and 107 connected to the first bias circuit 103 are turned off and the transistors 105 and 108 connected to the first bias circuit 103 are turned on. 103 is set.

  FIG. 4 shows an equivalent circuit during the amplification operation of the double balance type mixer circuit. As shown in FIG. 4, out of the first differential transistor pair 105 and 106 and the second differential transistor pair 107 and 108, the transistors 105 and 108 are cascode-connected to the third differential transistor pair 109 and 110, respectively. Is done. As described above, the signal input from the second input terminals 102A and 102B is amplified by the differential amplifier including the third differential transistor pair 109 and 110 and the impedance elements 111, 113, and 114. Output from output terminals 116A and 116b. Here, the cascode-connected transistors 105 and 108 contribute to the improvement of the high-frequency characteristics of the third differential transistor pair 109 and 110.

  When the double-balanced mixer circuit according to the present modification is used as each multiplication circuit 8A, 8B, 8C of the signal oscillator according to the second embodiment, the frequency band in the signal oscillator according to the first embodiment shown in FIG. And a signal transmitter having both the frequency band in the signal oscillator according to the second embodiment shown in FIG.

That is, when the double-balanced mixer circuit performs an amplification operation, the first to third signal output terminals 51A, 51B, and 51C each have a frequency band (f in the signal oscillator according to the first embodiment). ₀₁ f _02, f ₀₁ / N from f ₀₂ / N, consisting of f ₀₁ / N ₂ to obtain the f ₀₂ / N _2).

On the other hand, when the multiplication operation is performed by the double balance type mixer circuit, the frequency band ((N + 1) f ₀₁ / N to (N + 1) f ₀₂ / N, (N + 1) of the signal oscillator according to the second embodiment is used. ) F ₀₁ / N ² to (N + 1) f ₀₂ / N ² and (N ² +1) f ₀₁ / N ² to (N ² +1) f ₀₂ / N ² ).

  As described above, by applying the double balance type mixer circuit according to this modification to each of the multiplication circuits 8A, 8B, and 8C of the second embodiment, a signal having a larger frequency band can be obtained.

  In this modification, the double balance type mixer circuit is used as the multiplication circuit. However, the present invention is not limited to this, and other circuits such as other mixer circuits can be used as long as they have similar functions.

  Further, in this modification, by using a resonance circuit as each impedance element 111, 113, 114 of the double balance type mixer circuit, the double balance type mixer circuit can be given frequency selectivity. That is, by adjusting the resonance frequency of the resonance circuit constituting each of the impedance elements 111, 113, and 114, it is possible to selectively output either one of the frequencies consisting of the sum or difference of the input frequencies.

(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

  FIG. 5 shows a block configuration of a signal oscillator according to the third embodiment of the present invention. In FIG. 5, the same components as those shown in FIG.

  As shown in FIG. 5, the signal oscillator according to the third embodiment has a configuration in which the second N frequency divider 4 </ b> B constituting the signal oscillator according to the second embodiment is replaced with a variable frequency divider 9. . Therefore, the operation of this embodiment is different from the signal oscillator according to the second embodiment in that the frequency division number Q of the variable frequency divider 9 can be changed. Further, the second signal output terminal 5B is omitted.

The frequency obtained from each of the first and third signal output terminals 5A and 5C will be described. The frequency of the signal output from the first signal output terminal 51A is f _{0 by} the frequency division number Q in the variable frequency divider 9, and the frequency of the signal output from the third signal output terminal 51C is (N · Q + 1). ) F ₀ / N · Q. Therefore, when f ₀₂ the range of the oscillation frequency of the voltage controlled oscillator 3 from f _01, the frequency range of the signal output from the first signal output terminal 51A is next to f ₀₂ from f _01, the third signal output terminal 51C The frequency range of the signal output from is (N · Q + 1) f ₀₁ / N · Q to (N · Q + 1) f ₀₂ / N · Q.

Here, paying attention to the difference in frequency between the first signal output terminal 51A and the third signal output terminal 51C, when the oscillation frequency of the voltage controlled oscillator 3 f _01, the difference in the mutual frequency f ₀₁ / N Q, and when the oscillation frequency in the voltage controlled oscillator 3 is f ₀₂ , the difference between the frequencies is f ₀₂ / N · Q. Therefore, even if the oscillation frequency in the voltage controlled oscillator 3 is changed by adjusting the value of the variable frequency division number Q in the variable frequency divider 9, the first signal output terminal 51A and the third signal output terminal 51C It is possible to keep the frequency difference between the two values constant. This indicates that the transmission frequency band and the reception frequency band of each communication method can be output simultaneously.

  For example, the UMTS (Universal Mobile Telecommunication System) method among the communication methods is a CDMA / FDD (Cord Division Multiple Access / Frequency Division Duplex) method. For this reason, a signal oscillator that simultaneously outputs a transmission frequency band signal and a reception frequency band signal is required.

As an example, if the frequency division number N = 5, Q = 2.021053, and f ₀₁ is 1920 MHz which is the lower limit frequency of the transmission frequency band in UMTS, the frequency of the signal output from the first signal output terminal 51A is 1920 MHz. Thus, the frequency of the signal output from the third signal output terminal 51C is 2110 MHz, which is the lower limit frequency of the reception frequency band in UMTS. Further, when the frequency dividing number N = 5, Q = 2.08421, and f ₀₂ is f ₀₂ = 1980 MHz which is the lower limit frequency of the transmission frequency band in UMTS, the frequency of the signal output from the first signal output terminal 51A Becomes 1980 MHz, and the frequency of the signal output from the third signal output terminal 51C is 2170 MHz which is the upper limit frequency of the reception frequency band in UMTS.

  As described above, it is possible to simultaneously output a UMTS transmission frequency band signal and a reception frequency band signal using only the signal oscillator according to the third embodiment, and therefore, a multiband multimode terminal. Can be reduced in size.

  In the third embodiment, the output signal of the N frequency divider 4A is input to the variable frequency divider 9. However, the N frequency divider 4A and the variable frequency divider 9 are interchanged to change the variable frequency divider. The circuit 9 may receive the output signal from the voltage controlled oscillator 3, and the N frequency divider 4 </ b> A may receive the output signal from the variable frequency divider 9.

  In each of the first to third embodiments, the mobile phone terminal using the signal transmitter according to the present invention has been described. However, the present invention is not limited to this, and mobile communications other than mobile phone base stations and mobile phones. The present invention can also be applied to a terminal device or a mobile communication base station device.

  The signal oscillator according to the present invention is capable of simultaneously generating signals in two or more types of frequency bands with a single signal oscillator, thereby realizing downsizing of a multiband multimode terminal, and a plurality of signals including a plurality of frequency bands. Is useful for a signal oscillator capable of generating the signal generator simultaneously, a mobile phone terminal, a mobile phone base station, a mobile communication terminal device, a mobile communication base station device and the like equipped with the signal oscillator.

1 is a block diagram showing a signal oscillator according to a first embodiment of the present invention. It is a block diagram which shows the signal oscillator which concerns on the 2nd Embodiment of this invention. It is a circuit diagram which shows the double balance type mixer circuit used for the multiplication circuit of the signal oscillator which concerns on the modification of the 2nd Embodiment of this invention. FIG. 4 is an equivalent circuit diagram during an amplification operation of the double balance type mixer circuit shown in FIG. 3. It is a block diagram which shows the signal oscillator which concerns on the 3rd Embodiment of this invention. It is a block diagram which shows the conventional signal oscillator.

Explanation of symbols

1 Phase comparator 2 Loop filter (smoothing device)
3 Voltage controlled oscillator 4A 1st N frequency divider 4B 2nd N frequency divider 5A 1st signal output terminal 5B 2nd signal output terminal 5C 3rd signal output terminal 51A 1st signal output terminal 51B 1st 2nd signal output terminal 51C 3rd signal output terminal 6 Reference signal input terminal 7 Frequency synthesizer 8A 1st multiplication circuit 8B 2nd multiplication circuit 8C 3rd multiplication circuit 101A 1st input terminal 101B 1st input terminal 102A second input terminal 102B second input terminal 103 first bias circuit 104 second bias circuit 105 transistor 106 transistor 107 transistor 108 transistor 109 transistor 110 transistor 111 first impedance element 112A first current source 112B second Second current source 113 Second impedance element 114 Third impedance Dance element 115 Power supply terminal 116A Output terminal 116B Output terminal

Claims (14)

A signal oscillator capable of simultaneously outputting signals including a plurality of frequency bands,
A phase comparator that compares the phase of an input signal that is input to one input terminal and input to the other input terminal;
A voltage controlled oscillator for receiving an output signal from the phase comparator;
A frequency divider that receives an output signal from the voltage controlled oscillator, outputs a divided signal and outputs the divided signal to the other input terminal of the phase comparator;
A first signal output terminal for receiving an output signal from the voltage controlled oscillator;
And a second signal output terminal for receiving the frequency-divided signal.   The signal oscillator according to claim 1, further comprising a multiplier that receives an output signal from the voltage controlled oscillator and the frequency-divided signal and outputs the signal to the second signal output terminal.   The signal oscillator according to claim 2, wherein the frequency divider is a variable frequency divider capable of changing a frequency division number for an input signal.   3. The multiplier can switch between a first function for multiplying two input signals and a second function for amplifying and outputting one of the two input signals. Or the signal oscillator of 3.   The signal oscillator according to claim 2, wherein the multiplier is configured by a double balance type mixer circuit.   6. The signal oscillator according to claim 5, wherein the double balance type mixer circuit includes an impedance element having frequency selectivity as a load.   The signal oscillator according to claim 2, wherein the multiplier outputs a sum of frequencies of two input signals.   The signal oscillator according to claim 2, wherein the multiplier outputs a frequency difference between two input signals.   The signal oscillator according to claim 2, wherein the multiplier outputs a sum or difference of frequencies of two input signals.   The signal oscillator according to claim 1, wherein the frequency divider is configured by a D-type flip-flop circuit.   A mobile phone terminal comprising the signal oscillator according to claim 1.   A mobile phone base station comprising the signal oscillator according to claim 1.   A mobile communication terminal device comprising the signal oscillator according to claim 1.   A mobile communication base station apparatus comprising the signal oscillator according to claim 1.

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