JP5494848B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device having a heterojunction.

  As a prior art as the background of the present invention, there is the following Patent Document 1 filed by the present applicant.

The prior art is formed such that an N-type polycrystalline silicon region is in contact with one main surface of a semiconductor substrate in which an N ⁻ -type epitaxial region is formed on an N ⁺ -type silicon carbide substrate region. And the N-type polycrystalline silicon region are in a heterojunction. A P-type electric field relaxation region is formed so as to be in contact with the end portion of the heterojunction. Further, a back electrode is formed on the back surface of the N ⁺ -type silicon carbide substrate region, and a front electrode is formed on the surface of the polycrystalline silicon region.

  In the conventional technology having the above configuration, when the back electrode is a cathode and the front electrode is an anode, for example, when a positive potential is applied to the anode with the cathode grounded, a conduction characteristic corresponding to the forward characteristic of the diode is obtained. It is done. On the contrary, when a negative potential is applied to the anode, element characteristics corresponding to the reverse characteristics of the diode are obtained, and further, by forming a P-type electric field relaxation region so as to be in contact with the end of the heterojunction, The electric field is relaxed so that the electric field spreading from the epitaxial region does not concentrate at the end of the heterojunction.

  In this prior art, by changing the impurity concentration and conductivity type of the polycrystalline silicon region, for example, a diode having a predetermined reverse characteristic (forward characteristic corresponding thereto) can be arbitrarily adjusted. Compared to the above, there is an advantage that it can be adjusted to an optimum withstand voltage system as required.

JP 2003-318413 A

  In order to bring the reverse characteristics obtained between the polycrystalline silicon region and the epitaxial region, that is, the withstand voltage close to the ideal withstand voltage obtained at the one-dimensional joint surface, it is necessary to suppress the withstand voltage drop due to the multifaceted shape effect as much as possible. It is effective to reduce the impurity concentration of the electric field relaxation region formed at the end of the polycrystalline silicon region.

  However, in the conventional structure, if the impurity concentration in the electric field relaxation region is decreased to increase the breakdown voltage that can be maintained between the epitaxial region and the electric field relaxation region, a depletion layer spreads over the entire electric field relaxation region, and the heterojunction ends. Since the portion is exposed to the electric field spreading in the epitaxial region, the leakage current at the end portion increases. That is, in the conventional structure, the effect of improving the breakdown voltage performance of the epitaxial region by the electric field relaxation region and the effect of preventing the leakage current generated at the end portion of the polycrystalline silicon region have a conflicting relationship.

  The present invention has been made to solve the above-described problems of the prior art, and has an effect of improving the breakdown voltage performance of the first semiconductor region and a first method of forming a heterojunction with the first semiconductor region. An object of the present invention is to provide a semiconductor device capable of achieving both the effects of preventing leakage current generated at the end of the second semiconductor region.

  In order to solve the above-described problem, according to one aspect of the present invention, the first conductive type semiconductor substrate and the semiconductor substrate are made of a semiconductor material having a different band gap and are heterojunctioned with one main surface of the semiconductor substrate. In a semiconductor device having a two-conductivity-type hetero semiconductor region, a second-conductivity-type electric field relaxation region provided in the semiconductor substrate at the outer peripheral portion of the heterojunction surface, and the electric field relaxation region are entirely covered and are hetero A semiconductor having a second conductivity type punch-through prevention region that is in contact with the end of the bonding surface and having a higher concentration than the impurity concentration of the electric field relaxation region, and the hetero semiconductor region and the punch-through prevention region are in ohmic contact An apparatus is provided.

  According to the present invention, both the effect of improving the breakdown voltage performance of the first semiconductor region and the effect of preventing leakage current generated at the end of the second semiconductor region forming a heterojunction with the first semiconductor region are achieved. It is possible to provide a semiconductor device that can be used.

It is sectional drawing which shows the 1st Embodiment of this invention. It is a chip | tip surface view which has the 1st Embodiment of this invention. It is sectional drawing which shows the 1st another embodiment of this invention. It is sectional drawing which shows the 1st further another embodiment of this invention. It is sectional drawing which shows the 1st further another embodiment of this invention. It is sectional drawing which shows the 2nd Embodiment of this invention. It is sectional drawing which shows the 2nd another embodiment of this invention. It is sectional drawing which shows the 3rd Embodiment of this invention. It is sectional drawing which shows the 3rd further another embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings described below, components having the same function are denoted by the same reference numerals, and repeated description thereof is omitted.

(First embodiment)
FIG. 1 shows a cross-sectional structure of a first embodiment of a semiconductor device according to the present invention, and FIG. 2 shows a chip surface thereof. The structure shown in FIG. 1 is formed as a peripheral structure of an outer peripheral end portion of a semiconductor chip of line segment AA ′ in a semiconductor chip as shown in FIG. 2, for example. In this embodiment, a semiconductor device using silicon carbide as a substrate material will be described as an example.

For example, an N ⁻ type epitaxial region 2 is formed on a substrate region 1 of silicon carbide whose polytype is 4H type N ⁺ type. As the substrate region 1, for example, a substrate having a resistivity of several meters to several tens of mΩcm and a thickness of about 200 to 400 μm is used. As the epitaxial region 2, for example, an N-type impurity concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ⁻³ and a thickness of several to several tens of μm are used. In the present embodiment, the semiconductor substrate 100 in which the epitaxial region 2 is formed on the substrate region 1 will be described as an example. However, the semiconductor substrate 100 formed only in the substrate region 1 is used regardless of the resistivity. You can use it.

  A first hetero semiconductor region 3 having a band gap smaller than that of silicon carbide is deposited as an example of the second semiconductor layer so as to be in contact with the main surface of the epitaxial region 2 facing the bonding surface with the substrate region 1. Impurities are introduced into the first hetero semiconductor region 3, which is P-type and doped at a high impurity concentration. The junction between the epitaxial region 2 and the first hetero semiconductor region 3 is formed of a hetero junction made of materials having different band gaps between silicon carbide and polycrystalline silicon, and an energy barrier exists at the junction interface. In FIG. 2, the first hetero semiconductor region 3 and the surface metal electrode 8 stacked on the first hetero semiconductor region 3 are omitted in order to facilitate understanding of the positional relationship between the regions formed in the epitaxial region 2. Show.

In the present embodiment, the P ⁺ -type punch-through prevention region 4 and the punch-through prevention region 4 are in contact with the outer peripheral end of the junction between the epitaxial region 2 and the first hetero semiconductor region 3. Is formed with a P ⁻ type electric field relaxation region 5 having a low impurity concentration. In the present embodiment, the first hetero semiconductor region 3 and the punch-through prevention region 4 are both formed at a high impurity concentration and are ohmically connected to each other. In the present embodiment, as can be seen from FIG. 2, the punch-through region 4 and the electric field relaxation region 5 are formed in an annular shape. 1 illustrates a case where the punch-through prevention region 4 and the epitaxial region 2 are not in contact with each other, but a part of the punch-through prevention region 4 may be in contact with the epitaxial region 2. Further, for example, a P-type guard ring region 6 is formed on the outer periphery of the electric field relaxation region 5. In the present embodiment, the guard ring region 6 is constituted by two floating rings. However, the guard ring region 6 may be constituted by any number or may be omitted. Further, the depth of the guard ring region 6 is also equivalent to that of the electric field relaxation region 5, but may be deeper or shallower than the electric field relaxation region 5. However, when the guard ring region 6 is formed, the manufacturing process can be simplified by forming either the punch-through prevention region 4 and / or the electric field relaxation region 5 at the same time.

  In the present embodiment, a back metal electrode 7 is formed on the back side of the substrate region 1. The back surface metal electrode 7 is ohmically connected to the substrate region 1. As the metal material, for example, Ti (titanium) and Ni (nickel) deposited thereon can be used.

  A surface metal electrode 8 is formed on the surface of the first hetero semiconductor region 3. The surface metal electrode 8 is ohmically connected to the first hetero semiconductor region 3, and as the metal material, for example, Ti (titanium) and Al (aluminum) deposited thereon can be used.

  Further, in FIG. 1, the end of the first hetero semiconductor region 3 is formed so as to run over the interlayer insulating film 9. However, as shown in FIG. 3, for example, the interlayer insulating film 9 is not particularly formed. It doesn't matter.

  As described above, in the present embodiment, a description will be given of a case where a vertical diode having the front surface metal electrode 8 as an anode and the back surface metal electrode 7 as a cathode is configured.

  Next, the operation of the present embodiment will be described.

  First, when the back surface metal electrode 7 is set to the ground potential and a positive potential is applied to the front surface metal electrode 8, the diode exhibits forward characteristics and operates like a Schottky junction diode. That is, the current can flow with a voltage drop determined by the sum of the built-in potentials extending from the heterojunction portion to the epitaxial region 2 and the first hetero semiconductor region 3. For example, in the present embodiment, the sum of the built-in potentials extending from the heterojunction portion to the epitaxial region 2 and the first hetero semiconductor region 3 is about 1.3 V, and a forward current flows with a voltage drop corresponding thereto. At this time, a forward bias is also applied between the electric field relaxation region 5 and the epitaxial region 2, but since the built-in potential of the PN junction made of silicon carbide is about 3V higher than the heterojunction portion, the PN junction operates. do not do. That is, in the present embodiment, it operates as a monopolar diode during forward operation.

  Next, when the front surface metal electrode 8 is set to the ground potential and a positive potential is applied to the back surface metal electrode 7, the diode exhibits reverse characteristics and enters a cut-off state. That is, a depletion layer is formed from the heterojunction between the epitaxial region 2 and the first hetero semiconductor region 3 and the PN junction between the epitaxial region 2 and the electric field relaxation region 5 according to the potential applied to the back surface metal electrode 7. Stretch. At this time, in this embodiment, since the impurity concentration of the electric field relaxation region 5 is reduced, the depletion layer extends not only on the epitaxial region 2 side but also on the electric field relaxation region 5 side. The curvature of the outer peripheral end portion that becomes the maximum electric field at the junction with the epitaxial region 2 is relaxed, and can be made closer to the breakdown voltage at the flat portion.

  At this time, in the conventional structure, when the impurity concentration of the electric field relaxation region 5 is reduced as in the present embodiment, when the entire electric field relaxation region 5 is depleted, the depletion layer reaches the first hetero semiconductor region 3, Leakage current starts flowing at the end of the first hetero semiconductor region 3. In particular, when polycrystalline silicon that is a cluster of crystal grains is used as the first hetero semiconductor region 3 as in the present embodiment, if it is exposed to an electric field at the outer peripheral edge, a single metal shot Compared with key metals and single crystal silicon, the leakage current increases rapidly. However, in this embodiment, since the punch-through prevention region 4 is formed so as to be in contact with the first hetero semiconductor region 3, it is possible to prevent the depletion layer from reaching. That is, in the present embodiment, it is possible to prevent an increase in leakage current at the end portion of the first hetero semiconductor region 3 while improving the breakdown voltage in the epitaxial region 2, so that a higher breakdown voltage ( (Blocking property) can be realized.

  Furthermore, in the present embodiment, when a higher potential is applied to the back surface metal electrode 7 and an avalanche breakdown occurs between the epitaxial region 2 and the electric field relaxation region 5, the generated holes are removed from the punch-through prevention region. The first hetero semiconductor region 3 that is ohmic-connected through 4 is quickly discharged with low resistance. That is, since the avalanche breakdown occurs almost uniformly in the entire outer periphery of the punch-through prevention region 4 formed in an annular shape, the concentration of avalanche breakdown current hardly occurs and the avalanche resistance can be improved.

  As described above, with the structure as in the present embodiment, the forward characteristics have the same effect as the conventional technique, and the breakdown voltage of the reverse characteristics can be improved. In FIG. 1, the case where the hetero diode formed in the central portion of the hetero semiconductor element of FIG. 2 is formed of the first hetero semiconductor region 3 having the same P-type high impurity concentration as the outer peripheral portion has been described. However, as shown in FIG. 4, for example, an N-type second hetero semiconductor region 10 may be formed. That is, the second hetero semiconductor region 10 may be different in conductivity type or impurity concentration from the first hetero semiconductor region 3.

  As described above, in the present embodiment, the case where the punch-through prevention region 4 is used in the outer peripheral portion of the hetero semiconductor element has been described as an example. For example, as shown in FIG. By forming the punch-through prevention region 4 so as to be in contact with the end portion of one hetero semiconductor region 3 or the second hetero semiconductor region (10), the first hetero semiconductor region 3 or the second hetero semiconductor region 3 or the second hetero semiconductor region 3 or the second hetero semiconductor region 3 is formed. It is possible to improve the cutoff performance at the end of the hetero semiconductor region (10).

(Second Embodiment)
FIG. 6 shows a second embodiment of the semiconductor device according to the present invention. FIG. 6 is a cross-sectional view corresponding to FIG. 1 of the first embodiment. In the present embodiment, the description of the same operation as in FIG. 1 is omitted, and different features will be described in detail.

  FIG. 6 shows a so-called transistor in which a gate electrode 12 is formed on a part of the heterojunction interface of the heterojunction diode shown in FIG. As shown in FIG. 6, in this embodiment, a groove is formed in the epitaxial region 2, but a so-called planar type structure in which no groove is formed may be used.

  Next, the operation of the present embodiment will be described.

  In the present embodiment, for example, the front surface metal electrode 8 is grounded, and a positive potential is applied to the back surface metal electrode 7 for use.

  First, when the gate electrode 12 is set to a ground potential or a negative potential, for example, the cutoff state is maintained. That is, energy barriers for conduction electrons are formed at the heterojunction interface between the first hetero semiconductor region 3 and the epitaxial region 2. At this time, in the present embodiment, as described in the first embodiment, the punch-through prevention region 4 is formed so that the leakage current characteristic at the end of the first hetero semiconductor region 3 does not occur. In addition, since the electric field relaxation region 5 is formed with a low impurity concentration so as to approach the breakdown voltage of the flat portion of the epitaxial region 2, it is possible to maintain higher blocking performance.

  Next, when a positive potential is applied to the gate electrode 12 to change from the cutoff state to the conduction state, the gate electric field is applied to the heterojunction interface where the first hetero semiconductor region 3 and the epitaxial region 2 are in contact via the gate insulating film 11. Therefore, an inversion layer of conduction electrons is formed in the first hetero semiconductor region 3 and the epitaxial region 2 in the vicinity of the gate electrode 12. That is, the potential on the first hetero semiconductor region 3 side at the junction interface between the first hetero semiconductor region 3 near the gate electrode 12 and the epitaxial region 2 is pushed down, and the energy barrier on the epitaxial region 2 side becomes steep. Therefore, conduction electrons can be conducted through the energy barrier. In FIG. 6, as an example, the first hetero semiconductor region 3 is formed so as to be in contact with the gate insulating film 11, but as illustrated in FIG. 7, the gate insulating film 11 and the first hetero semiconductor region 3 are separated from each other. The second hetero semiconductor region 10 may be interposed therebetween. The conductivity type and impurity concentration of the second hetero semiconductor region 10 may be any. However, for example, when the N-type high impurity concentration is used, the channel portion through which current is conducted is more easily accumulated and the driving force is improved.

  Next, when the gate electrode 12 is set to the ground potential again to shift from the conductive state to the cut-off state, the inversion state of the conduction electrons formed at the heterojunction interface of the first hetero semiconductor region 3 and the epitaxial region 2 is released. And tunneling in the energy barrier stops. Then, the flow of conduction electrons from the first hetero semiconductor region 3 to the epitaxial region 2 stops, and further, the conduction electrons in the epitaxial region 2 flow to the silicon carbide substrate 1 and when they are depleted, the epitaxial region 2 side becomes heterogeneous. A depletion layer spreads from the junction and enters a cut-off state.

  In the present embodiment, similarly to the conventional structure, for example, reverse conduction (reflux operation) in which the front surface metal electrode 8 is grounded and a negative potential is applied to the rear surface metal electrode 7 is also possible.

  For example, when the front surface metal electrode 8 and the gate electrode 12 are set to the ground potential and a predetermined positive potential is applied to the back surface metal electrode 7, the energy barrier to the conduction electrons disappears, and the first hetero semiconductor region 3 from the epitaxial region 2 side disappears. Conduction electrons flow to the side, and a reverse conduction state is established. At this time, since there is no injection of holes and conduction is made only with conduction electrons, loss due to reverse recovery current when shifting from the reverse conduction state to the cutoff state is small. Note that the above-described gate electrode 12 may be used as a control electrode without being grounded.

(Third embodiment)
FIG. 8 shows a third embodiment of the semiconductor device according to the present invention. FIG. 8 is a cross-sectional view corresponding to FIG. 6 of the second embodiment. In the present embodiment, the description of the same operation as in FIG. 6 is omitted, and different features will be described in detail.

  In the second embodiment, as an example, the case where the configuration for reducing the leakage current described in the second embodiment is used for a part of the switch for driving the gate of the heterojunction has been described. As shown in FIG. 8, the heterojunction may be used as a freewheeling diode built in a part of the switch element. FIG. 8 shows a structure in which a hetero diode is built in a MOSFET made of silicon carbide. That is, the second conductivity type base region 23 and the first conductivity type source region 24 are formed in the semiconductor substrate 100 composed of the first conductivity type substrate region 21 and the epitaxial region 22 made of silicon carbide. A gate electrode 26 is formed through a gate insulating film 25 so as to be in contact with the base 22, the base region 23, and the source region 24. The base region 23 and the source region 24 are connected to the source electrode 27, and the substrate region 21 is connected to the drain electrode 28. Further, the band gap is different from that of the epitaxial region 22, and the first hetero semiconductor region 29 made of, for example, polycrystalline silicon is arranged so as to form a hetero junction with the epitaxial region 22. Note that the first hetero semiconductor region 29 is connected to the source electrode 27. Further, in the present embodiment, the punch-through prevention region 30 and the electric field relaxation region 31 are formed so as to be in contact with the end portion of the first hetero semiconductor region 29. In FIG. 8, the electric field relaxation region 31 and the base region 23 are formed at the same time and a common structure is shown, but another structure may be used. Thus, even when a heterojunction is formed as a built-in free-wheeling diode of a MOSFET, leakage current can be prevented by forming the punch-through prevention region 30. Therefore, as in the second embodiment, since the leakage current at the heterojunction portion in the cut-off state can be reduced, a semiconductor device with high cut-off performance can be provided.

  As described above, in any case, in each part constituting the transistor, at least a part of the first hetero semiconductor region 29 made of, for example, polycrystalline silicon described in the present embodiment is at least partly described. Is included, it is possible to bring about an effect of reducing leakage current.

  In FIG. 8, the hetero diode formed in the central portion of the hetero semiconductor element has been described as being formed by the first hetero semiconductor region 29 having the same P-type high impurity concentration as the outer peripheral portion. As shown in FIG. 9, for example, an N-type second hetero semiconductor region 32 may be formed. That is, the second hetero semiconductor region 32 may be different in conductivity type or impurity concentration from the first hetero semiconductor region 29.

  As described above, in the first to third embodiments, the epitaxial region 2 (or 22) and the first hetero semiconductor region 3 having a different band gap from the epitaxial region 2 (or 22). The epitaxial region 2 (or 22) has a heterojunction made of (or 29) and is in contact with the end of the junction surface between the epitaxial region 2 (or 22) and the first hetero semiconductor region 3 (or 29). It has a second conductivity type electric field relaxation region 5 (or 31) through a second conductivity type punch through prevention region 4 (or 30), and at least the punch through prevention region 4 (or 30) is an electric field relaxation region. The impurity concentration is equal to or higher than 5 (or 31). With such a configuration, there is an effect of improving the breakdown voltage performance of the epitaxial region 2 (or 22) and an effect of preventing leakage current generated at the end of the first hetero semiconductor region 3 (or 29) made of the polycrystalline silicon region. It is possible to achieve both, and the characteristics at the time of interruption can be improved.

  Further, at least an end portion of the first hetero semiconductor region 3 (or 29) in contact with the epitaxial region 2 (or 22) is of the second conductivity type. When an avalanche breakdown occurs in the epitaxial region 2 (or 22) by such a configuration, the generated minority carriers are promptly passed through the punch-through prevention region 4 (or 30) and the first hetero semiconductor region 3 (or 29). Since it can be discharged, the avalanche resistance is improved.

  Further, at least an end portion of the first hetero semiconductor region 3 (or 29) in contact with the epitaxial region 2 (or 22) is in ohmic contact with the punch-through prevention region 4 (or 30). When an avalanche breakdown occurs in the epitaxial region 2 (or 22) by such a configuration, the generated minority carriers are further promptly passed through the punch-through prevention region 4 (or 30) and the first hetero semiconductor region 3 (or 29). Therefore, the avalanche resistance is further improved.

  Also, a semiconductor substrate 100 including the epitaxial region 2 (or 22), and a second hetero semiconductor region 10 (FIG. 4) in contact with one main surface of the semiconductor substrate 100 and having a different band gap from the semiconductor substrate 100 The first hetero semiconductor region 3 (or 29), the punch-through prevention region 4 (or 30) and at least the vicinity of the outermost peripheral portion of the junction end between the semiconductor substrate 100 and the second hetero semiconductor region 10 and Electric field relaxation regions 5 (or 31) are respectively formed. By applying the above-described configuration to the outer peripheral portion of the hetero semiconductor element with such a configuration, the above-described effects can be obtained as a specific structure.

  In the second and third embodiments, a gate is formed at a part of the junction between the first hetero semiconductor region 3 (or 29) (or the second hetero semiconductor region 10 in FIG. 4) and the semiconductor substrate 100. A gate electrode 12 or 26 is formed via the insulating film 11 or 25. By applying the above-described configuration to the outer peripheral portion of the three-terminal hetero semiconductor element with such a configuration, the above-described effects can be obtained as a specific structure.

  In the third embodiment, the semiconductor substrate 100 including the epitaxial region 22, and the second conductivity type base region 23 and the first conductivity type source region 24 are provided in a predetermined region of the semiconductor substrate 100. A gate electrode 26 through a gate insulating film 25 so as to be in contact with at least the semiconductor substrate 100 and the source region 24, and at least an outermost peripheral portion of a junction end portion between the semiconductor substrate 100 and the first hetero semiconductor region 29. In the vicinity, a punch-through prevention region 30 and an electric field relaxation region 31 are formed. By applying the above-described configuration as a built-in diode of a three-terminal semiconductor element with such a configuration, the above-described effects can be obtained as a specific structure.

  In the third embodiment, the semiconductor substrate 100 including the epitaxial region 22, and the second conductivity type base region 23 and the first conductivity type source region 24 are provided in a predetermined region of the semiconductor substrate 100. A second hetero semiconductor having a gate electrode 26 through a gate insulating film 25 so as to be in contact with at least the semiconductor substrate 100 and the source region 24 and having a band gap different from that of the semiconductor substrate 100 The first hetero semiconductor region 29, the punch-through prevention region 30, and the electric field relaxation are provided at least in the vicinity of the outermost peripheral portion of the junction end between the semiconductor substrate 100 and the second hetero semiconductor region 10. Regions 31 are respectively formed. By applying the above-described configuration as a built-in diode of a three-terminal semiconductor element with such a configuration, the above-described effects can be obtained as a specific structure.

  In the first to third embodiments, epitaxial region 2 (or 22) is made of silicon carbide. Such a configuration can be easily realized with a general material.

  Further, the first hetero semiconductor region 3 (or 29) and the second hetero semiconductor region 10 are made of at least one of single crystal silicon, amorphous silicon, and polycrystalline silicon. Such a configuration can be easily realized by a general material and process.

  The epitaxial regions 2 and 22 of the above-described embodiment are the first semiconductor region of the claims, the first hetero semiconductor regions 3 and 29 are the second semiconductor region, and the second hetero semiconductor region 10 is the second semiconductor region 10. It corresponds to a hetero semiconductor region.

  In the first to third embodiments, the semiconductor device using silicon carbide as the substrate material has been described as an example. However, the substrate material may be other semiconductors such as silicon, silicon germane, gallium nitride, and diamond. Materials can be used. In all the embodiments, the 4H type is used as the polytype of silicon carbide, but other polytypes such as 6H and 3C may be used. In all the embodiments, the back surface metal electrode 7 (or the drain electrode 28) and the front surface metal electrode 8 (or the source electrode 27) are arranged to face each other with the epitaxial region 2 (or the epitaxial region 22) interposed therebetween. The so-called vertical structure in which the current between them is passed in the vertical direction has been described. For example, the back surface metal electrode 7 (or drain electrode 28) and the front surface metal electrode 8 (or source electrode 27) are arranged on the same main surface. However, a so-called horizontal structure in which a current between the two flows in the horizontal direction may be used. Moreover, although the example using polycrystalline silicon as the material used for the first hetero semiconductor regions 3 and 29 and the second hetero semiconductor region 10 has been described, a semiconductor material that forms a heterojunction with silicon carbide (for example, a single crystal) As long as it is silicon, germanium, silicon germane, etc., each material may be a separate material. Further, as an example, the description has been given using N-type silicon carbide as the epitaxial regions 2 and 22 and P-type polycrystalline silicon as the first hetero semiconductor regions 3 and 29. However, N-type silicon carbide and N Combinations of type polycrystalline silicon, P type silicon carbide and N type polycrystalline silicon, P type silicon carbide and P type polycrystalline silicon may be used.

  Further, it goes without saying that modifications are included within the scope not departing from the gist of the present invention.

  The embodiment described above is described in order to facilitate understanding of the present invention, and is not described in order to limit the present invention. Therefore, each element disclosed in the above embodiment includes all design changes and equivalents belonging to the technical scope of the present invention.

DESCRIPTION OF SYMBOLS 1 ... Substrate region 2 ... Epitaxial region 3 ... 1st hetero semiconductor region 4 ... Punch through prevention region 5 ... Electric field relaxation region 6 ... Guard ring region 7 ... Back surface metal electrode 8 ... Front surface metal electrode 9 ... Interlayer insulation film 10 ... First Second hetero semiconductor region 11 ... gate insulating film 12 ... gate electrode 21 ... substrate region 22 ... epitaxial region 23 ... base region 24 ... source region 25 ... gate insulating film 26 ... gate electrode 27 ... source electrode 28 ... drain electrode 29 ... th One hetero semiconductor region 30 ... punch-through prevention region 31 ... electric field relaxation region (common with the base region 23)
32 ... Second hetero semiconductor region 100 ... Semiconductor substrate

Claims (5)

A first conductivity type semiconductor substrate;
A semiconductor device comprising a semiconductor material having a band gap different from that of the semiconductor substrate, and having a second conductivity type hetero semiconductor region heterojunction with one main surface of the semiconductor substrate.
An electric field relaxation region of a second conductivity type provided in the semiconductor substrate at the outer peripheral portion of the heterojunction surface;
A punch-through prevention region of a second conductivity type that is entirely covered with the electric field relaxation region, is in contact with an end of the heterojunction surface, and has a higher concentration than the impurity concentration of the electric field relaxation region;
A semiconductor device, wherein the hetero semiconductor region and the punch-through prevention region are in ohmic contact.   2. The hetero semiconductor region according to claim 1, wherein the hetero semiconductor region has a first conductivity type portion and a second conductivity type portion, and at least a portion in contact with the punch-through prevention region is the second conductivity type. Semiconductor device.   3. The semiconductor device according to claim 1, further comprising a second conductivity type guard ring region provided in the semiconductor substrate on an outer periphery of the electric field relaxation region.   4. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of silicon carbide.   5. The semiconductor device according to claim 1, wherein the hetero semiconductor region is made of at least one of single crystal silicon, amorphous silicon, and polycrystalline silicon.

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