JP5491894B2 - Semiconductor relay - Google Patents

Semiconductor relay Download PDF

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JP5491894B2
JP5491894B2 JP2010030387A JP2010030387A JP5491894B2 JP 5491894 B2 JP5491894 B2 JP 5491894B2 JP 2010030387 A JP2010030387 A JP 2010030387A JP 2010030387 A JP2010030387 A JP 2010030387A JP 5491894 B2 JP5491894 B2 JP 5491894B2
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mosfets
light receiving
drive element
receiving drive
conductive plates
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JP2011166077A (en
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就俊 星野
嘉宏 藤原
貴史 芝野
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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Priority to JP2010030387A priority Critical patent/JP5491894B2/en
Priority to CN201080045218.9A priority patent/CN102656803B/en
Priority to PCT/IB2010/002533 priority patent/WO2011042796A1/en
Priority to US13/500,710 priority patent/US8816310B2/en
Priority to KR1020127009016A priority patent/KR101351737B1/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)

Description

本発明は、半導体リレーに関するものである。   The present invention relates to a semiconductor relay.

従来から、MOSFET出力フォトカプラや光MOSFETとも呼ばれる半導体リレーが提供されている(例えば、特許文献1参照)。   Conventionally, a semiconductor relay called a MOSFET output photocoupler or an optical MOSFET has been provided (see, for example, Patent Document 1).

図9〜図12に、半導体リレー1の一例を示す。この半導体リレー1は、入力端子部51と出力端子部61とを2個ずつ有する。さらに、上記の半導体リレー1は、入力端子部51間に接続された発光素子2と、出力端子部61間に互いに直列に接続された2個のMOSFET3a,3bと、発光素子2の光の有無に応じて各MOSFET3a,3bをそれぞれオンオフ駆動する受光駆動素子4とを備える。   An example of the semiconductor relay 1 is shown in FIGS. This semiconductor relay 1 has two input terminal portions 51 and two output terminal portions 61. Further, the semiconductor relay 1 includes a light emitting element 2 connected between the input terminal portions 51, two MOSFETs 3 a and 3 b connected in series between the output terminal portions 61, and the presence or absence of light from the light emitting element 2. The light receiving drive element 4 for driving the MOSFETs 3a and 3b on and off according to the above is provided.

発光素子2は、それぞれ一方ずつの入力端子部51に電気的に接続される一対の端子を有し、この端子間に所定の電力(例えば、所定電圧の直流電力)が入力されることで発光するものである。発光素子2としては例えば発光ダイオードを用いることができる。   The light emitting element 2 has a pair of terminals that are electrically connected to the respective input terminal portions 51, and emits light when predetermined power (for example, DC power of a predetermined voltage) is input between the terminals. To do. For example, a light emitting diode can be used as the light emitting element 2.

受光駆動素子4は、発光素子2の光を受けて電力を発生させる例えばフォトダイオードアレイ(いわゆる太陽電池)からなる受光素子4aと、受光素子4aが電力を発生させている期間には該電力により各MOSFET3a,3bをそれぞれオン駆動するとともに、受光素子4aが電力を発生させていない期間には各MOSFET3a,3bをそれぞれオフ駆動する駆動回路4bとが、1チップに集積化されたものである。上記のような受光駆動素子4は周知技術で実現可能であるので、詳細な説明は省略する。   The light receiving drive element 4 receives light from the light emitting element 2 to generate power, for example, a light receiving element 4a composed of a photodiode array (so-called solar cell), and a period during which the light receiving element 4a generates power. Each MOSFET 3a, 3b is driven on, and a driving circuit 4b that drives each MOSFET 3a, 3b off during a period when the light receiving element 4a does not generate power is integrated on one chip. Since the light receiving drive element 4 as described above can be realized by a well-known technique, a detailed description thereof is omitted.

各MOSFET3a,3bはそれぞれNチャネル型であって、ソース電極31同士が互いに電気的に接続されるとともに、それぞれ、ゲート電極32とソース電極31とが受光駆動素子4の駆動回路4bに電気的に接続され、ドレイン電極33が一方ずつの出力端子部61に電気的に接続されている。すなわち、各MOSFET3a,3bの寄生ダイオードは互いに逆向きとなっているから、2個のMOSFET3a,3bの直列回路の一端ずつに接続された出力端子部61間の電気的接続(導通)のオンオフは、出力端子部61間に入力される電圧の向きに関わらず、各MOSFET3a,3bのオンオフ状態に依存する。   Each of the MOSFETs 3a and 3b is an N-channel type, and the source electrodes 31 are electrically connected to each other, and the gate electrode 32 and the source electrode 31 are electrically connected to the drive circuit 4b of the light receiving drive element 4, respectively. The drain electrode 33 is electrically connected to one of the output terminal portions 61. That is, since the parasitic diodes of the MOSFETs 3a and 3b are opposite to each other, the electrical connection (conduction) between the output terminal portions 61 connected to one end of the series circuit of the two MOSFETs 3a and 3b is turned on / off. Regardless of the direction of the voltage input between the output terminal portions 61, it depends on the on / off states of the MOSFETs 3a and 3b.

上記の半導体リレー1の動作を説明する。入力端子部51間に所定の電力が入力されず発光素子2が消灯されている期間には、各MOSFET3a,3bはそれぞれオフ状態に維持され、従って出力端子部61間の電気的接続はオフされる。   The operation of the semiconductor relay 1 will be described. During a period in which the predetermined power is not inputted between the input terminal portions 51 and the light emitting element 2 is turned off, the MOSFETs 3a and 3b are maintained in the off state, and thus the electrical connection between the output terminal portions 61 is turned off. The

入力端子部51間に所定の電力が入力されることで発光素子2が点灯すると、受光駆動素子4は各MOSFET3a,3bをそれぞれオン駆動し、これによって出力端子部61間の電気的接続がオンされる。   When the light emitting element 2 is turned on by inputting predetermined power between the input terminal portions 51, the light receiving drive element 4 drives each of the MOSFETs 3a and 3b to turn on the electrical connection between the output terminal portions 61. Is done.

また、発光素子2が消灯すると、受光駆動素子4は各MOSFET3a,3bをそれぞれオフ駆動し、これによって出力端子部61間の電気的接続が再度オフされる。   When the light emitting element 2 is turned off, the light receiving drive element 4 drives the MOSFETs 3a and 3b to turn off, whereby the electrical connection between the output terminal portions 61 is turned off again.

ここで、上記の半導体リレー1は、発光素子2と各MOSFET3a,3bと受光駆動素子4とをそれぞれ封止する封止樹脂10を備える。封止樹脂10において少なくとも発光素子2と受光駆動素子4の受光素子4aとに挟まれる部位には、発光素子2の光を通す合成樹脂が用いられる。   Here, the semiconductor relay 1 includes a sealing resin 10 that seals the light emitting element 2, the MOSFETs 3 a and 3 b, and the light receiving drive element 4. A synthetic resin that transmits light from the light emitting element 2 is used at least between the light emitting element 2 and the light receiving element 4 a of the light receiving drive element 4 in the sealing resin 10.

さらに、上記の半導体リレー1は、ぞれぞれ導電材料からなり封止樹脂10内において発光素子2の一方ずつの端子に電気的に接続される接続部52を有する2個の入力導電板5を備える。一方の入力導電板5の接続部52は発光素子2の一方の端子が面実装(表面実装)されるものであり、他方の入力導電板5の接続部52は発光素子2の他方の端子がワイヤボンディングにより電気的に接続されるものである。また、各入力導電板5は、それぞれ封止樹脂10外に突出した入力端子部51を有する。各入力導電板5はそれぞれ例えば金属板に打ち抜き加工と曲げ加工とを施すことにより形成することができる。   Further, the semiconductor relay 1 is composed of two input conductive plates 5 each having a connection portion 52 made of a conductive material and electrically connected to one terminal of the light emitting element 2 in the sealing resin 10. Is provided. The connection portion 52 of one input conductive plate 5 is one in which one terminal of the light emitting element 2 is surface-mounted (surface mounted), and the connection portion 52 of the other input conductive plate 5 is connected to the other terminal of the light emitting element 2. It is electrically connected by wire bonding. Each input conductive plate 5 has an input terminal portion 51 that protrudes outside the sealing resin 10. Each input conductive plate 5 can be formed by punching and bending a metal plate, for example.

また、上記の半導体リレー1は、それぞれ導電材料からなり封止樹脂10内において一方ずつのMOSFET3a,3bのドレイン電極33が面実装された実装部62を有する2個の出力導電板6と、導電材料からなり扁平な形状であって受光駆動素子4が面実装されて封止樹脂10に封止された中央導電板7とを備える。各出力導電板6と中央導電板7とは、それぞれ、入力導電板5と同様に、金属板に打ち抜き加工と曲げ加工とを施すことにより形成することができる。各MOSFET3a,3bは、ソース電極31同士がワイヤボンディングにより互いに電気的に接続されるとともに、ゲート電極32がそれぞれワイヤボンディングにより受光駆動素子4に電気的に接続されている。また、一方のMOSFET3aのソース電極31と受光駆動素子4とがそれぞれワイヤボンディングにより中央導電板7に電気的に接続されることで、各MOSFET3a,3bのソース電極31はそれぞれ中央導電板7を介して受光駆動素子4に電気的に接続されている。また、各出力導電板6は、それぞれ、封止樹脂10外に突出した出力端子部61を有する。   Further, the semiconductor relay 1 includes two output conductive plates 6 each having a mounting portion 62 that is made of a conductive material and surface-mounted with one of the drain electrodes 33 of the MOSFETs 3 a and 3 b in the sealing resin 10. A central conductive plate 7 made of a material and having a flat shape, the light receiving drive element 4 being surface-mounted and sealed with a sealing resin 10 is provided. Each output conductive plate 6 and the central conductive plate 7 can be formed by punching and bending a metal plate, like the input conductive plate 5. In each of the MOSFETs 3a and 3b, the source electrodes 31 are electrically connected to each other by wire bonding, and the gate electrode 32 is electrically connected to the light receiving drive element 4 by wire bonding. Further, the source electrode 31 of one MOSFET 3a and the light receiving drive element 4 are electrically connected to the central conductive plate 7 by wire bonding, respectively, so that the source electrodes 31 of the MOSFETs 3a and 3b are respectively connected via the central conductive plate 7. The light receiving drive element 4 is electrically connected. Each output conductive plate 6 has an output terminal portion 61 that protrudes outside the sealing resin 10.

各入力端子部51及び各出力端子部61は、図11及び図12に示すように、それぞれ共通のプリント配線板Pの実装面(図12での上面)に設けられた導電パターンP1,P2に対して面実装される。   As shown in FIGS. 11 and 12, each input terminal portion 51 and each output terminal portion 61 are formed on conductive patterns P1 and P2 provided on the mounting surface (upper surface in FIG. 12) of the common printed wiring board P, respectively. On the other hand, it is surface-mounted.

従来は、各実装部62や中央導電板7はそれぞれ厚さ方向を上記のプリント配線板Pの厚さ方向に一致させていた。   Conventionally, the thickness direction of each mounting portion 62 and the central conductive plate 7 is matched with the thickness direction of the printed wiring board P.

特開2003−8050号公報JP 2003-8050 A

ところで、出力端子部61間に高周波信号が伝送される場合においては、各MOSFET3a,3bのソース電極31に接続された中央導電板7がいわゆるスタブ回路として作用するので、中央導電板7にも高周波信号が流入する。   By the way, when a high frequency signal is transmitted between the output terminal portions 61, the central conductive plate 7 connected to the source electrode 31 of each of the MOSFETs 3a and 3b functions as a so-called stub circuit. A signal flows in.

さらに、プリント配線板Pにおいては、例えば電磁ノイズを遮蔽する目的で、グランドと同電位とされる導電パターンP3が、非実装面(図12での下面)の全面にわたって設けられる場合がある。この場合、互いに対向する各出力導電板6の実装部62及び中央導電板7とグランドパターンP3との間に寄生容量Cpが発生する。すると、各出力導電板6の実装部62や中央導電板7から上記の寄生容量Cpを介して高周波信号が流出してしまうことで、インサーションロスが増加していた。   Furthermore, in the printed wiring board P, for example, for the purpose of shielding electromagnetic noise, a conductive pattern P3 having the same potential as the ground may be provided over the entire non-mounting surface (the lower surface in FIG. 12). In this case, a parasitic capacitance Cp is generated between the mounting portion 62 and the central conductive plate 7 of each output conductive plate 6 facing each other and the ground pattern P3. Then, a high frequency signal flows out from the mounting portion 62 of each output conductive plate 6 and the central conductive plate 7 through the parasitic capacitance Cp, and thus the insertion loss is increased.

本発明は、上記事由に鑑みて為されたものであり、その目的は、インサーションロスの低減が可能な半導体リレーを提供することにある。   This invention is made | formed in view of the said reason, The objective is to provide the semiconductor relay which can reduce an insertion loss.

第1の発明は、寄生ダイオードの向きを互いに逆向きとするように互いに直列に接続された2個のMOSFETと、一対の端子を有し該端子間に所定の電力が入力されて発光する発光素子と、前記発光素子の発光の有無に応じて前記2個のMOSFETをそれぞれオンオフ駆動する受光駆動素子と、それぞれ導電材料からなり前記2個のMOSFETの直列回路の一端ずつに電気的に接続された2個の出力導電板と、それぞれ導電材料からなり前記発光素子の一方ずつの端子に電気的に接続された2個の入力導電板と、前記2個のMOSFETと前記発光素子と前記受光駆動素子と前記2個の出力導電板と前記2個の入力導電板とをそれぞれ封止した封止樹脂とを備え、前記2個の出力導電板と前記2個の入力導電板とは、それぞれ、前記封止樹脂の外側に突出して互いに共通のプリント配線板に実装される端子部を有し、前記2個の出力導電板は、それぞれ、前記2個のMOSFETのうちの1個ずつが実装された実装部を有し、前記各実装部は、それぞれ、厚さ方向が前記プリント配線板の厚さ方向に対して交差するような向きで前記封止樹脂に封止されていて、前記2個のMOSFETは、前記受光駆動素子と前記プリント配線板とで挟まれる位置に封止されていることを特徴とする。
In the first invention, two MOSFETs connected in series so that the directions of the parasitic diodes are opposite to each other, and a pair of terminals, and light emission that emits light when predetermined power is input between the terminals An element, a light receiving drive element that drives the two MOSFETs on and off according to whether or not the light emitting element emits light, and one end of a series circuit of the two MOSFETs, each made of a conductive material, are electrically connected. Two output conductive plates, two input conductive plates each made of a conductive material and electrically connected to one terminal of the light emitting element, the two MOSFETs, the light emitting element, and the light receiving drive A sealing resin that seals the element, the two output conductive plates, and the two input conductive plates, respectively, the two output conductive plates and the two input conductive plates, Said seal A terminal portion that protrudes outward from the resin and is mounted on a common printed wiring board, and each of the two output conductive plates is a mounting portion on which one of the two MOSFETs is mounted. Each mounting part is sealed with the sealing resin in such a direction that the thickness direction intersects the thickness direction of the printed wiring board, and the two MOSFETs are The light receiving drive element and the printed wiring board are sealed at a position sandwiched between them.

第2の発明は、第1の発明において、前記2個のMOSFETが1チップに集積化されていることを特徴とする。   A second invention is characterized in that, in the first invention, the two MOSFETs are integrated on one chip.

第3の発明は、第1の発明において、前記2個のMOSFETはそれぞれ一方ずつの前記出力導電板に面実装されていることを特徴とする。   A third invention is characterized in that, in the first invention, each of the two MOSFETs is surface-mounted on one of the output conductive plates.

第4の発明は、第1の発明において、前記2個のMOSFETの相互の接続点は前記受光駆動素子に対し直接のワイヤボンディングにより電気的に接続されていることを特徴とする。   According to a fourth invention, in the first invention, a connection point between the two MOSFETs is electrically connected to the light receiving drive element by direct wire bonding.

第5の発明は、第1の発明において、導電材料からなり扁平な形状であって前記受光駆動素子が固定され厚さ方向が前記プリント配線板の厚さ方向に対して交差するような向きで前記封止樹脂に封止された中央導電板を備え、前記2個のMOSFETの相互の接続点と、前記受光駆動素子とは、それぞれ、中央導電板に対してワイヤボンディングにより電気的に接続されていることを特徴とする。   According to a fifth invention, in the first invention, the light receiving drive element is fixed and the thickness direction intersects the thickness direction of the printed wiring board in a flat shape made of a conductive material. A central conductive plate sealed with the sealing resin is provided, and a connection point between the two MOSFETs and the light receiving drive element are electrically connected to the central conductive plate by wire bonding, respectively. It is characterized by.

本発明によれば、各実装部は、それぞれ、各端子部がそれぞれ実装されるプリント配線板の厚さ方向に対して厚さ方向が交差するような向きで封止樹脂に封止されているので、上記のプリント配線板の厚さ方向に対して各実装部がそれぞれ厚さ方向を平行とされる場合に比べ、上記のプリント配線板の導電パターンと各実装部との間に発生し得る寄生容量が低下することにより、インサーションロスの低減が可能である。   According to the present invention, each mounting portion is sealed with the sealing resin in such a direction that the thickness direction intersects the thickness direction of the printed wiring board on which each terminal portion is mounted. Therefore, compared with the case where each mounting part is parallel to the thickness direction of the printed wiring board, it may occur between the conductive pattern of the printed wiring board and each mounting part. By reducing the parasitic capacitance, the insertion loss can be reduced.

本発明の実施形態を示す正面図である。It is a front view which shows embodiment of this invention. (a)(b)はそれぞれ異なる視点から見た同上を示す斜視図である。(A) and (b) are perspective views showing the same as seen from different viewpoints. 同上の要部を示す左側面図である。It is a left view which shows the principal part same as the above. 同上(曲線B)と従来例(曲線A)とのそれぞれについて、周波数特性を示す説明図である。It is explanatory drawing which shows a frequency characteristic about each of a same as the above (curve B) and a prior art example (curve A). 同上の変更例を示す斜視図である。It is a perspective view which shows the example of a change same as the above. 図5の例の要部を示す左側面図である。It is a left view which shows the principal part of the example of FIG. 同上の別の変更例を示す斜視図である。It is a perspective view which shows another example of a change same as the above. 図7の例の要部を示す左側面図である。It is a left view which shows the principal part of the example of FIG. 半導体リレーを示す回路ブロック図である。It is a circuit block diagram which shows a semiconductor relay. 従来例を示す斜視図である。It is a perspective view which shows a prior art example. 同上を示す一部破断した平面図である。It is a partially broken plan view showing the same. 同上を示す正面図である。It is a front view showing the same.

以下、本発明を実施するための最良の形態について、図面を参照しながら説明する。   The best mode for carrying out the present invention will be described below with reference to the drawings.

本実施形態の基本構成は図9〜図12で説明した従来例と共通であるので、共通する部分についての説明は省略する。   Since the basic configuration of this embodiment is the same as that of the conventional example described with reference to FIGS. 9 to 12, the description of the common parts is omitted.

本実施形態では、図1に示すように、各端子部51,61がそれぞれ面実装されるプリント配線板Pの厚さ方向に対し、中央導電板7と各実装部62とがそれぞれ厚さ方向を直交させる向きとされている。   In the present embodiment, as shown in FIG. 1, the central conductive plate 7 and each mounting portion 62 are each in the thickness direction with respect to the thickness direction of the printed wiring board P on which the terminal portions 51 and 61 are surface-mounted. The directions are orthogonal to each other.

具体的に説明すると、各入力導電板5と各出力導電板6とは、それぞれ、厚さ方向に一回だけ略直角に曲げられたL字形状とされており、曲げられた部位の一方側にそれぞれ端子部である入力端子部51又は出力端子部61が形成され、他方側に接続部52又は実装部62が形成されている。   Specifically, each of the input conductive plates 5 and each of the output conductive plates 6 is formed in an L shape that is bent substantially at a right angle once in the thickness direction, and one side of the bent portion. The input terminal part 51 or the output terminal part 61 which is a terminal part is formed respectively, and the connection part 52 or the mounting part 62 is formed on the other side.

また、受光駆動素子4に対するMOSFET3aのソース電極31の電気的接続は、従来例のように中央導電板7を介してではなく、図3に示すような直接のワイヤボンディングにより達成されている。これにより、MOSFET3aのソース電極31を受光駆動素子4に対し従来例のように中央導電板7を介して接続する場合に比べて必要なワイヤボンディングの回数が減少している。   Further, the electrical connection of the source electrode 31 of the MOSFET 3a to the light receiving drive element 4 is achieved not by the central conductive plate 7 as in the conventional example but by direct wire bonding as shown in FIG. As a result, the number of wire bondings required is reduced compared to the case where the source electrode 31 of the MOSFET 3a is connected to the light receiving drive element 4 via the central conductive plate 7 as in the conventional example.

さらに、各MOSFET3a,3bはそれぞれドレイン電極33(図9参照)が出力導電板6の実装部62に対して面実装されている。これにより、各MOSFET3a,3bのドレイン電極33と実装部62との電気的接続をワイヤボンディングで達成する場合に比べ、電流容量の増加が可能となっており、本発明者の実験によれば電流容量を2倍以上とすることができた。   Further, the drain electrodes 33 (see FIG. 9) of each MOSFET 3 a and 3 b are surface-mounted on the mounting portion 62 of the output conductive plate 6. As a result, the current capacity can be increased as compared with the case where the electrical connection between the drain electrode 33 and the mounting portion 62 of each MOSFET 3a, 3b is achieved by wire bonding. The capacity could be doubled or more.

また、封止樹脂10は全体として直方体形状とされており、半導体リレー1は封止樹脂10の一面(図1での下面)をプリント配線板Pに向けてプリント配線板Pに面実装される。   Further, the sealing resin 10 has a rectangular parallelepiped shape as a whole, and the semiconductor relay 1 is surface-mounted on the printed wiring board P with one surface (the lower surface in FIG. 1) facing the printed wiring board P. .

以下、上下左右は図1を基準とし、図1の紙面に直交する方向のうち手前方向(図2(a)の左下方向)を前方向と呼ぶ。なお、上記の方向は説明の便宜のために定義するものであって、実際の使用状態での方向とは必ずしも一致しない。   Hereinafter, the top, bottom, left, and right are based on FIG. 1, and the front direction (the lower left direction in FIG. 2A) of the directions orthogonal to the paper surface of FIG. Note that the above direction is defined for convenience of explanation, and does not necessarily match the direction in the actual use state.

中央導電板7は、厚さ方向を左右方向に向けた扁平な形状であって、上端部から前後両側に突設された腕部71を有する。製造時、封止樹脂10による封止の際には、中央導電板7及び受光駆動素子4はそれぞれ腕部71において支持される。   The central conductive plate 7 has a flat shape with the thickness direction directed in the left-right direction, and has arm portions 71 projecting from the upper end to both the front and rear sides. At the time of manufacturing, when sealing with the sealing resin 10, the central conductive plate 7 and the light receiving drive element 4 are each supported by the arm portion 71.

また、各入力端子部51と各出力端子部61とはそれぞれ厚さ方向の両面のうち接続部52や実装部62が突出していない側の面を封止樹脂10の下面に略面一としている。さらに、各入力端子部51はそれぞれ封止樹脂10の左面の下端部において前後に並んで左方に突出し、各出力端子部61はそれぞれ封止樹脂10の右面の下端部において前後に並んで右方に突出している。   In addition, each input terminal portion 51 and each output terminal portion 61 are substantially flush with the lower surface of the sealing resin 10 on the surface of the both sides in the thickness direction where the connection portion 52 and the mounting portion 62 do not protrude. . Furthermore, the input terminal portions 51 are arranged side by side at the lower end portion of the left surface of the sealing resin 10 and protrude leftward, and the output terminal portions 61 are arranged at the lower end portion of the right surface of the sealing resin 10 and are aligned to the right. It protrudes toward.

さらに、中央導電板7と各実装部62とは、それぞれ表裏両面を封止樹脂10の面のうち上記一面に直交する面である左右の面に対して平行とする向きで封止されている。すなわち、中央導電板7と各実装部62とは、それぞれ厚さ方向がプリント配線板Pの厚さ方向に直交する向きとされている。   Further, the central conductive plate 7 and each mounting portion 62 are sealed in a direction in which both front and back surfaces are parallel to the left and right surfaces that are orthogonal to the one surface of the surface of the sealing resin 10. . That is, the thickness direction of the central conductive plate 7 and each mounting portion 62 is set to be orthogonal to the thickness direction of the printed wiring board P.

上記構成によれば、各端子部51,61がそれぞれ実装されるプリント配線板Pの厚さ方向に対し、各実装部62が厚さ方向を平行とされる場合に比べ、上記のプリント配線板Pの導電パターンP3と各実装部62との間に発生し得る寄生容量が低下することにより、インサーションロスが抑えられる。図4に、図10〜図12で説明した従来例でのインサーションロスの解析結果を曲線Aで示し、本実施形態でのインサーションロスの解析結果を曲線Bで示す。図4からもわかるように、本実施形態では従来例よりもインサーションロスが抑えられている。   According to the said structure, compared with the case where each mounting part 62 makes the thickness direction parallel with respect to the thickness direction of the printed wiring board P in which each terminal part 51 and 61 is each mounted, said printed wiring board Insertion loss is suppressed by reducing the parasitic capacitance that may occur between the P conductive pattern P3 and each mounting portion 62. In FIG. 4, the analysis result of the insertion loss in the conventional example described in FIGS. 10 to 12 is shown by a curve A, and the analysis result of the insertion loss in this embodiment is shown by a curve B. As can be seen from FIG. 4, in this embodiment, the insertion loss is suppressed as compared with the conventional example.

なお、図5及び図6に示すように、MOSFET3aのソース電極31を受光駆動素子4に対し従来例と同様に中央導電板7を介して電気的に接続してもよい。すなわち、MOSFET3aのソース電極31(すなわち、2個のMOSFET3a,3bの相互の接続点)と受光駆動素子4とをそれぞれ中央導電板7に対してワイヤボンディングにより電気的に接続する。この場合、中央導電板7も、各MOSFET3a,3bのソース電極31がワイヤボンディングにより実装されていることになるから、出力端子部61間を伝送される高周波信号は中央導電板7に流入する。しかしながら、中央導電板7の厚さ方向もやはりプリント配線板Pの厚さ方向に対して直交しているので、上記のような高周波信号の流入に関わらずインサーションロスの増加は抑えられる。上記構成を採用すると、図1〜図3の例に比べ、製造時に必要なワイヤボンディングの回数は増加するものの、各MOSFET3a,3bのゲート−ソース間電圧の低下速度を速くすることができ、従って半導体リレー1のターンオフ時間の短縮が可能である。本発明者の実験によれば、図5及び図6の例では、図1〜図3の例に比べ、ターンオフ時間を2分の1以下にすることができた。   As shown in FIGS. 5 and 6, the source electrode 31 of the MOSFET 3a may be electrically connected to the light receiving drive element 4 through the central conductive plate 7 as in the conventional example. That is, the source electrode 31 of the MOSFET 3a (that is, the connection point between the two MOSFETs 3a and 3b) and the light receiving drive element 4 are electrically connected to the central conductive plate 7 by wire bonding. In this case, since the source electrode 31 of each of the MOSFETs 3 a and 3 b is also mounted on the central conductive plate 7 by wire bonding, a high frequency signal transmitted between the output terminal portions 61 flows into the central conductive plate 7. However, since the thickness direction of the central conductive plate 7 is also orthogonal to the thickness direction of the printed wiring board P, an increase in insertion loss can be suppressed regardless of the inflow of the high-frequency signal as described above. When the above configuration is adopted, the number of times of wire bonding required at the time of manufacture increases as compared with the examples of FIGS. 1 to 3, but the rate of decrease in the gate-source voltage of each MOSFET 3a, 3b can be increased. The turn-off time of the semiconductor relay 1 can be shortened. According to the experiment by the present inventor, the turn-off time in the example of FIGS. 5 and 6 can be reduced to half or less as compared with the example of FIGS.

また、図7及び図8に示すように、2個のMOSFET3a,3bが1チップに集積化されたスイッチング素子3を用いてもよい。このようなスイッチング素子3は周知技術で実現可能であるので、詳細な図示並びに説明は省略する。図7及び図8の例では、スイッチング素子3は中央導電板7において受光駆動素子4と同じ側の面に固定されている。また、スイッチング素子3に含まれる各MOSFET3a,3bは、それぞれ、ソース電極31(すなわち、2個のMOSFET3a,3bの相互の接続点)が中央導電板7に対してワイヤボンディングにより実装され、ゲート電極32が受光駆動素子4に対して直接のワイヤボンディングにより電気的に接続され、ドレイン電極33が一方ずつの出力導電板6の実装部62に対してワイヤボンディングにより実装されている。上記のように適宜の集積化を行えば、部品点数の削減が可能となる。   Further, as shown in FIGS. 7 and 8, a switching element 3 in which two MOSFETs 3a and 3b are integrated on one chip may be used. Since such a switching element 3 can be realized by a well-known technique, detailed illustration and description thereof are omitted. In the example of FIGS. 7 and 8, the switching element 3 is fixed to the surface on the same side as the light receiving drive element 4 in the central conductive plate 7. Each of the MOSFETs 3a and 3b included in the switching element 3 has a source electrode 31 (that is, a connection point between the two MOSFETs 3a and 3b) mounted on the central conductive plate 7 by wire bonding. 32 is electrically connected to the light receiving drive element 4 by direct wire bonding, and the drain electrode 33 is mounted to the mounting portion 62 of each output conductive plate 6 by wire bonding. If appropriate integration is performed as described above, the number of parts can be reduced.

さらに、各端子部51,61がそれぞれ厚さ方向の一面において面実装される構成とする代わりに、各端子部51,61がそれぞれ厚さ方向を左右方向に向けて下端面において面実装される構成としてもよい。この場合、各入力導電板5と各出力導電板6とは、それぞれ、曲げられた部位を有さない扁平な形状とすることができる。   Furthermore, instead of adopting a configuration in which each terminal portion 51, 61 is surface-mounted on one surface in the thickness direction, each terminal portion 51, 61 is surface-mounted on the lower end surface with the thickness direction facing in the left-right direction. It is good also as a structure. In this case, each of the input conductive plates 5 and each of the output conductive plates 6 can have a flat shape that does not have a bent portion.

1 半導体リレー
2 発光素子
3a,3b MOSFET
4 受光駆動素子
5 入力導電板
6 出力導電板
7 中央導電板
31 ソース電極(2個のMOSFETの相互の接続点)
51 入力端子部
61 出力端子部
62 実装部
P プリント配線板
DESCRIPTION OF SYMBOLS 1 Semiconductor relay 2 Light emitting element 3a, 3b MOSFET
4 Light receiving drive element 5 Input conductive plate 6 Output conductive plate 7 Center conductive plate 31 Source electrode (connection point of two MOSFETs)
51 Input terminal portion 61 Output terminal portion 62 Mounting portion P Printed wiring board

Claims (5)

寄生ダイオードの向きを互いに逆向きとするように互いに直列に接続された2個のMOSFETと、
一対の端子を有し該端子間に所定の電力が入力されて発光する発光素子と、
前記発光素子の発光の有無に応じて前記2個のMOSFETをそれぞれオンオフ駆動する受光駆動素子と、
それぞれ導電材料からなり前記2個のMOSFETの直列回路の一端ずつに電気的に接続された2個の出力導電板と、
それぞれ導電材料からなり前記発光素子の一方ずつの端子に電気的に接続された2個の入力導電板と、
前記2個のMOSFETと前記発光素子と前記受光駆動素子と前記2個の出力導電板と前記2個の入力導電板とをそれぞれ封止した封止樹脂とを備え、
前記2個の出力導電板と前記2個の入力導電板とは、それぞれ、前記封止樹脂の外側に突出して互いに共通のプリント配線板に実装される端子部を有し、
前記2個の出力導電板は、それぞれ、前記2個のMOSFETのうちの1個ずつが実装された実装部を有し、
前記各実装部は、それぞれ、厚さ方向が前記プリント配線板の厚さ方向に対して交差するような向きで前記封止樹脂に封止されていて、
前記2個のMOSFETは、前記受光駆動素子と前記プリント配線板とで挟まれる位置に封止されていることを特徴とする半導体リレー。
Two MOSFETs connected in series so that the directions of the parasitic diodes are opposite to each other;
A light emitting element that has a pair of terminals and emits light when a predetermined power is input between the terminals;
A light receiving drive element for turning on and off the two MOSFETs according to whether the light emitting element emits light;
Two output conductive plates each made of a conductive material and electrically connected to one end of the series circuit of the two MOSFETs;
Two input conductive plates each made of a conductive material and electrically connected to one terminal of the light emitting element;
A sealing resin for sealing the two MOSFETs, the light emitting element, the light receiving drive element, the two output conductive plates, and the two input conductive plates;
The two output conductive plates and the two input conductive plates each have a terminal portion that protrudes outside the sealing resin and is mounted on a common printed wiring board.
Each of the two output conductive plates has a mounting portion on which one of the two MOSFETs is mounted,
Each of the mounting parts is sealed in the sealing resin in such a direction that the thickness direction intersects the thickness direction of the printed wiring board ,
The two MOSFETs are sealed at a position sandwiched between the light receiving drive element and the printed wiring board .
前記2個のMOSFETが1チップに集積化されていることを特徴とする請求項1記載の半導体リレー。   2. The semiconductor relay according to claim 1, wherein the two MOSFETs are integrated on one chip. 前記2個のMOSFETはそれぞれ一方ずつの前記出力導電板に面実装されていることを特徴とする請求項1記載の半導体リレー。   The semiconductor relay according to claim 1, wherein each of the two MOSFETs is surface-mounted on one of the output conductive plates. 前記2個のMOSFETの相互の接続点は前記受光駆動素子に対し直接のワイヤボンディングにより電気的に接続されていることを特徴とする請求項1記載の半導体リレー。   2. The semiconductor relay according to claim 1, wherein a connection point between the two MOSFETs is electrically connected to the light receiving drive element by direct wire bonding. 導電材料からなり扁平な形状であって前記受光駆動素子が固定され厚さ方向が前記プリント配線板の厚さ方向に対して交差するような向きで前記封止樹脂に封止された中央導電板を備え、
前記2個のMOSFETの相互の接続点と、前記受光駆動素子とは、それぞれ、中央導電板に対してワイヤボンディングにより電気的に接続されていることを特徴とする請求項1記載の半導体リレー。
A central conductive plate made of a conductive material and having a flat shape and sealed with the sealing resin in such a direction that the light receiving drive element is fixed and the thickness direction intersects the thickness direction of the printed wiring board With
2. The semiconductor relay according to claim 1, wherein a connection point between the two MOSFETs and the light receiving drive element are electrically connected to a central conductive plate by wire bonding, respectively.
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