JP5489529B2 - Information processing apparatus and information processing apparatus control method - Google Patents

Description

  The present invention relates to information processing for printed circuit board design support.

  A semiconductor integrated circuit (Integrated Circuit: IC) or a large-scale semiconductor integrated circuit (Large-Scale Integration: LSI) is mounted on a printed circuit board constituting the electric circuit. Hereinafter, the semiconductor integrated circuit and the large-scale semiconductor integrated circuit are referred to as IC. In order for this electric circuit to operate normally, the distortion (hereinafter referred to as noise) of the waveform of the electric signal transmitted between the ICs is reduced to a certain range, and the waveform with low noise at the destination IC (hereinafter referred to as the receiver IC). Is preferably input. For this purpose, various devices are required for component arrangement and wiring. For example, when a digital signal is transmitted from a transmission source IC (hereinafter referred to as a driver IC) to a plurality of receiver ICs, it is ideal to input the waveform of FIG. However, actually, noise called overshoot, undershoot, ringing, or stepping occurs as shown in FIG. For example, consider the connection relationship shown in FIG. In this case, when the wiring length from the branch point A to the receiver IC 181 or the receiver IC 182 is short as shown in FIG. 13A, the input waveform of the receiver IC 180 is not stepped. On the other hand, when the wiring length from the branch point A to the receiver IC 181 or the receiver IC 182 is long as shown in FIG. This is because the difference in arrival time of the electrical signal output from the driver IC (hereinafter referred to as signal 1) and the electrical signal reflected by the receiver IC 181 or the receiver IC 182 (hereinafter referred to as signal 2) to the branch point A is signal 1. This is because the transition time is longer. That is, the waveforms of the signal 1 and the signal 2 are synthesized at the branch point A to be an input waveform of the receiver IC 180, and the synthesized waveform is a waveform having a step as shown in FIG. Therefore, as shown in FIG. 13A, a device for shortening the wiring length from the branch point A to the receiver IC 181 and the receiver IC 182, that is, the branch length is taken.

  On the other hand, with the recent increase in circuit scale, the increase in density and complexity of signal wiring on a printed circuit board is accelerating. For this reason, it becomes difficult for circuit designers to manually devise the above-described component arrangement and wiring while predicting the timing of waveform and signal synchronization. Currently, signal waveform analysis software for electric circuits is used. It became so. As a result, circuit designers can examine component placement and wiring while performing operation verification, that is, while looking at an assumed signal waveform. On the other hand, in the simulation necessary for signal waveform analysis, it may be difficult to obtain or create a model, and it takes a long time to set analysis conditions. For this reason, an enormous design time is required to analyze signals on all wirings that require waveform analysis.

  In order to solve these problems, Patent Document 1 discloses a driver in which the reflection time when the electric signal is reflected and returned at the impedance mismatched portion is within the transition time of the electric signal. A technique for checking the wiring length of an IC and a reflection portion is disclosed. Similarly, a technique for checking the wiring length between the receiver IC and the parallel termination component so that the time for the electrical signal to reciprocate between the receiver IC and the parallel termination component for the receiver IC is within the transition time of the electrical signal is disclosed. ing.

  Patent Document 2 discloses a technique for displaying a wiring length between an electronic component and a branching point, or a wiring length between branching points on a screen, and performing a comparison check with a predetermined line length.

JP 2002-63225 A Japanese Patent Laid-Open No. 2002-230074

  However, Patent Document 1 does not consider the branch length in the branch wiring path to which a plurality of receiver ICs are connected as described above.

  In the said patent document 2, the reflective location of an electric signal is not specified. Further, the round trip time of the electric signal is not taken into consideration.

  For this reason, the circuit designer has to check whether the wiring between the electronic component and the branch point or the branch point and the branch point determined to have a long wiring length should be corrected. If a wiring that does not need to be corrected is mistakenly corrected, the surrounding parts and wiring may be rearranged to unnecessarily extend the circuit design period.

  In order to solve the above problem, it is necessary to determine whether or not the path of the electric signal on the signal branch wiring is appropriate.

In order to solve the above-described problem, an information processing apparatus according to claim 1, input means for inputting layout information on a printed circuit board and electrical characteristic information of a driver semiconductor integrated circuit on the printed circuit board, and the driver semiconductor A path connecting a selection means for selecting an integrated circuit and a plurality of receiver semiconductor integrated circuits connected to the selected driver semiconductor integrated circuit on the printed circuit board and the selected driver semiconductor integrated circuit based on the layout information Path information acquisition means for acquiring path information indicating, a setting means for setting a synthesis point at a branch position on the path, and a distance between the synthesis point and each of the receiver semiconductor integrated circuits based on the path information. A distance acquisition means for acquiring and an electrical signal output from the selected driver integrated circuit based on the electrical characteristic information; A transition time acquisition means for acquiring a transition time of the signal, and determining whether or not the route is appropriate based on a distance that maximizes a distance between the synthesis point and the receiver semiconductor integrated circuit among the distances and the transition time Determining means, and the setting means sets the composite point at a branch position with the shortest wiring distance from the driver integrated circuit or a branch position with the longest wiring distance from the receiver semiconductor integrated circuit .

  According to the present invention, it is possible to automatically determine whether or not an electrical signal path on a signal branch wiring is appropriate.

1 is a system configuration diagram for realizing design support of a printed circuit board according to an embodiment. It is a functional block diagram for implement | achieving the design support of the printed circuit board which concerns on embodiment. It is a flowchart of the printed circuit board design support program which concerns on embodiment. It is a flowchart of the printed circuit board design support program which concerns on embodiment. It is a figure which shows an example of the termination | terminus method of receiver IC. It is a figure which shows an example of the wiring connection condition of driver IC and receiver IC. It is a figure which shows an example of the electrical property information which concerns on embodiment. It is a figure which shows an example of the input screen for a user to input check conditions in the printed circuit board design assistance program which concerns on Example 1. FIG. It is a figure which shows an example of the check result by the table format output with the printed circuit board design assistance program which concerns on embodiment. It is a figure which shows an example of the wiring connection condition after correcting a wiring branch condition corresponding to the check result output with the printed circuit board design support program which concerns on embodiment. 10 is a flowchart of a printed circuit board design support program according to the second embodiment. It is a figure which shows an example of an ideal electrical signal waveform and an electrical signal waveform with noise. It is a figure which shows an example of each wiring connection condition which transmits the electric signal waveform of FIG.

  Hereinafter, a preferred example of an embodiment of an information processing apparatus according to the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description and examples, and can be appropriately modified and combined within the scope of the gist of the present invention. The same components in the drawings will be described using the same reference numerals as appropriate.

  FIG. 1 is an apparatus configuration diagram for explaining a schematic configuration of a computer apparatus including a printed circuit board design support program according to the present embodiment. In FIG. 1, a central processing unit (CPU) 10 controls the entire apparatus. The main storage device 11 includes a read-only storage device (ROM) and a storage device (RAM) on which the CPU 10 temporarily reads and writes during calculation processing. The display device 12 is a cathode ray tube or a liquid crystal display. The input device 13 is a mouse, a keyboard, or the like. The external storage device 14 is used for reading / writing data from / to a recording medium such as a hard disk, a floppy (registered trademark) disk, a CD, a DVD, or an MD. The output device 15 is a printer for printing calculation results and the like output to the display device 12. The bus 16 transmits information such as an address bus, a data bus, and a control bus. The printed circuit board design support program 14a is a processing program installed in the computer device. The layout information 14b relates to the printed circuit board, and details will be described later. The electrical characteristic information 14c relates to an electronic component, and details will be described later. A central processing unit (CPU) 10, a main storage device 11, a display device 12, an input device 13, an external storage device 14 and an output device 15 are connected to each other via a bus 16. And, it is configured such that necessary information such as control information and data information can be exchanged between the devices via the bus 16 under the control of the CPU 10. The processing program 14a, layout information 14b, and electrical characteristic information 14c according to the present embodiment are stored in advance in the external storage device 15.

  Here, the layout information includes information regarding the layer configuration of the printed circuit board and the characteristics of the material. Furthermore, the layout information includes component information such as the position coordinates of components mounted on the printed circuit board and the shape and size of the conductor portion to which the terminals are connected, the wiring names of the wiring between components, and the points constituting the wiring figures. Includes wiring information such as position coordinates.

  The electrical characteristics information is the electrical characteristics information of each component such as the output rise time, fall time, threshold voltage, input capacitance, input resistance, output resistance and resistance value of the capacitor, capacitor capacitance, resistance value, etc. including.

  FIG. 2 is a functional configuration diagram for schematically explaining a preferred example of the functional relationship of the printed circuit board design support program according to the present invention. In FIG. 2, an input unit 20 inputs instruction information such as reading of layout information 14b and electrical characteristic information 14c input by the user using the input device 12 and execution of the processing program 14a into the computer device. Further, information relating to conditions (hereinafter referred to as check conditions) used for execution of the processing program 14a and the like is input into the computer apparatus. Furthermore, the input information is processed or controlled as necessary under the control of the CPU 10 and stored in the main storage device 11.

  When the execution of the processing program is input from the input unit 20, the external storage information extraction unit 21 extracts the processing program 14 a stored in the external storage device 14 by a control command from the CPU 10 according to the input, and the main storage device 11 is stored. When an instruction to read layout information or electrical characteristic information is issued from the input unit 20, the layout information 14 b or electrical characteristic information 14 c in the external storage device 14 is extracted and stored in the main storage device 11 under the control of the CPU 10. To do.

  The branch status check unit 22 includes a branch wiring path search unit 22a, a signal reflection point / combination point setting unit 22b, and a determination unit 22c, which are three functional parts.

  The branch wiring path search unit 22a specifies the output terminal of the driver IC from the electrical characteristic information 14c extracted by the external storage information extraction unit 21 under the control of the CPU 10. Then, based on the layout information 14 b extracted by the external storage information extraction unit 21, a wiring branch path from the output terminal of the driver IC is searched and stored in the main storage device 11.

  The signal reflection point / composite point setting unit 22b specifies the input terminal of the unterminated receiver IC from each wiring branch path under the control of the CPU 10, and sets it as a signal reflection point that is a reflection point of the electric signal. Then, the branch position with the shortest wiring distance from the output terminal of the driver IC is identified from among the branch positions that continue to other receiver ICs on the wiring branch path including the signal reflection point, and the signal is synthesized on the wiring branch path. Set to the signal synthesis point. Here, it is equivalent even if the branch position having the longest wiring distance from the signal reflection point is set as the signal synthesis point. In that case, the determination unit 22c described later may specify the shortest combination of wiring distances between the signal reflection point and the signal synthesis point. The combination of the signal reflection point and the signal synthesis point is specified for each wiring branch path.

  The determination unit 22c specifies the longest combination of the wiring distances between the signal reflection point and the signal combination point from the combination specified by the signal reflection point / combination point setting unit 22b under the control of the CPU 10, and the signal specified as the longest combination The wiring length between the synthesis point and the signal reflection point is calculated. Then, under the control of the CPU 10, a time for reciprocating between the signal reflection point specified for the combination having the longest electrical signal and the signal synthesis point (hereinafter referred to as a reciprocation time) is calculated. Further, the signal transition time of the driver IC on the signal reflection path (smaller time between the rise time and the fall time) is obtained from the electrical characteristic information 14c in the main memory device 11, and compared with the round trip time. When the round trip time is longer than the signal transition time, it is determined as “NG”, and when the round trip time is equal to or shorter than the signal transition time, it is determined as “OK”, and the determination information is stored in the main storage device 11. To do.

  The check result output unit 23 displays the determination information in the main storage device 11 by a method such as display on the display device 12, recording in the external storage device 14, or output using the output device 15 under the control of the CPU 10. Output and notify the user as a warning.

  Hereinafter, the operation of the printed circuit board design support program according to the present embodiment will be described in detail with reference to the flowcharts of FIGS. 3 and 4 and the drawings of FIGS.

  The flowcharts of FIGS. 3 and 4 will be described. Unless otherwise specified, each step in each flowchart is processed and controlled by the CPU 10. Note that steps A to E shown in FIGS. 3 and 4 are steps provided to prevent the progress arrow in the flowchart from obscuring the drawing, and the steps before and after the step with the same reference numerals are connected. .

  In step S300, when an instruction to start the program is received via the input unit 20, the external storage information extraction unit 21 transfers the processing program 14a from the external storage device 14 to the main storage device 11, reads it, and starts the processing program 14a. To do.

  In step S <b> 301, the external storage information extraction unit 21 transfers the layout information 14 b and the electrical characteristic information 14 c in the external storage device 14 to the main storage device 11.

  In step S302, a check condition from the user is accepted via the input unit 20. Here, it is assumed that the check condition is a refdes of the driver IC (information such as a number assigned to identify a component on the printed circuit board). The following method is conceivable as a method for inputting the driver IC's Lefdes. In the first method, information (such as Lefdes) that can identify all ICs mounted on the printed circuit board to be checked is read from the layout information 14b and displayed on the input screen by the display device 12, and the user selects by the user. This is a method for acquiring the refde of the indicated IC. The second method is a method in which an IC is directly selected by a user on a circuit diagram or a printed circuit board design drawing, and a reflex of the selected IC is obtained. In the third method, a file in which information that allows the user to specify the driver IC is previously stored in a file is stored in the external storage device 14, and the CPU 10 stores the information in the external storage information extraction unit 21 from the external storage device 14. In this method, the data is transferred to the main storage device 11 and read. The above three methods are some examples of the method for acquiring the driver IC's reflex, and other methods may be adopted as long as the driver IC's reflex can be acquired.

  In step S303, after acquiring the check conditions in step S302, it is determined whether there is an unchecked driver IC to be checked. If it is determined in step S303 that there is an unchecked target driver IC, the process proceeds to step S304. If it is determined that there is no unchecked target driver IC, the processing program 14a is terminated.

  Steps S304 to S308 are processes executed by the branch wiring route search unit 22a. In step S304, if it is determined in step S303 that there is an unchecked driver IC to be checked, one of the unchecked driver ICs to be checked (hereinafter referred to as IC-A) is selected.

  In step S305, the output terminal of IC-A is specified from the electrical characteristic information 14c in the main storage device 11.

  In step S306, it is determined whether there is an unchecked IC-A output terminal. If it is determined in step S306 that there is an unchecked IC-A output terminal, the process proceeds to step S307. If it is determined that there is no unchecked driver IC output terminal, the process returns to step S303.

  In step S307, if it is determined in step S306 that there is an unchecked IC-A output terminal, one (hereinafter, output terminal B) is selected from the IC-A output terminals.

  In step S308, route information indicating all wiring branch routes starting from the output terminal B is acquired while referring to the layout information 14b in the main storage device 11. However, the wiring branch path to be acquired is only the path related to the signal wiring, and the path connected to the power source or the ground may not be the acquisition target.

  The next steps S309 to S315 are processes executed by the signal reflection point / composite point setting unit 22b. In step S309, when all the routing information of the wiring branch path starting from the output terminal B is acquired, it is determined whether or not termination processing has been performed on the input terminal of the receiver IC on each wiring branch path. 11 stores termination processing determination information of the input terminal of each receiver IC. As a method for specifying the receiver IC here, a method is adopted in which an IC different from the driver IC on the wiring branch path is used as the receiver IC. On the other hand, it is good also as a process which specifies receiver IC by determining whether the terminal of IC on a wiring branch path | route is an input terminal from the electrical property information 14c in the main memory device 11. FIG. The presence / absence of termination processing for the input terminal of each receiver IC is determined, for example, by the wiring distance between the terminal of the termination component shown in FIGS. 5A and 5B and the input terminal of the receiver IC being a predetermined value. It is possible to determine whether it is too short. FIG. 5 is merely an example of termination processing on the receiver side, and in the case of other termination processing methods, since termination components are generally used, determination can be made by the same method as described above. Further, when the wiring method is one-stroke writing or the like and the input terminal of the receiver IC is not branched from the wiring, it is not necessary to determine whether or not to perform termination processing.

  In step S310, when it is determined in step S309 whether the input terminal of the receiver IC on each wiring branch path is terminated, the input terminal of the unterminated receiver IC is set as a signal reflection point.

  In step S311, it is determined whether there is a set signal reflection point. If it is determined in step S311 that there is a signal reflection point, the process proceeds to step S312. If it is determined that there is no signal reflection point, the process proceeds to step S322.

  In step S312, if it is determined in step S311 that there is a signal reflection point, it is determined whether there is a signal reflection point for which a combination with a signal synthesis point is not set. If it is determined in step S312 that there is a signal reflection point, the process proceeds to step S313. If it is determined that there is no signal reflection point, the process proceeds to step S316.

  In step S313, when it is determined in step S312 that there is a signal reflection point, one signal reflection point (hereinafter, signal reflection point C) is selected.

  In step S314, the branch position connected to the input terminal of the receiver IC different from the input terminal of the receiver IC set at the signal reflection point C on the wiring branch path including the signal reflection point C (hereinafter referred to as branch position D). Is identified.

  In step S315, among the branch positions D, the branch position with the shortest wiring distance from the output terminal B is set as the signal synthesis point. When the signal synthesis point is set in step S315, the process returns to step S312. The loop processing from step S312 to step S315 is executed until there is no signal reflection point for which no signal synthesis point is set in step S312. If it is determined in step S312 that there is no signal synthesis point for which no signal synthesis point is set, the process proceeds to step S316.

  Hereinafter, the processing from step S316 to step S322 is processing executed by the determination unit 22c. In step S316, the combination having the longest wiring distance between two points is specified from the combinations of the signal reflection point and the signal synthesis point.

  In step S317, the wiring distance (d) from the signal reflection point of the specified combination to the signal synthesis point is acquired.

In step S318, the round-trip propagation delay time (when the signal reciprocates between the signal reflection point and the signal synthesis point) (from the layout information 14b in the main storage device 11 and the wiring distance d between the signal reflection point and the signal synthesis point). t _p ) is calculated.

In step S319, the shorter one (t _c ) of the rise time and fall time of the signal output from the electrical characteristic information 14c in the main storage device 11 to the output terminal B is acquired.

In step S320, it compares the transition time _{t c} of the propagation delay time _{t p} and the signal. If t _p > t _c in step S320, the process proceeds to step S321. If t _p ≦ t _c , the process proceeds to step S322.

  In step S321, NG (indicating inappropriateness) information is output as a warning via the check result output unit 23.

  In step S322, OK (indicating appropriate) information is output via the check result output unit 23. However, in consideration of the case where the number of wirings to be checked is very large, it is possible not to execute the process of step S322. When the process of step S321 or step S322 is executed, the process returns to step S306.

Here, the propagation delay time t _plh [ns / m] per unit length of the signal required in the calculation in step S318 can be calculated by the following equation.

Ε _r in the above formula is the relative dielectric constant of the insulating layer and is included in the layout information 14b. Equation 1 is an example of a method for calculating the propagation delay time, and even if the propagation delay time is calculated by other calculation methods, the substantial execution process is the same.

  The above is the detailed description of an example of the flowchart of the printed circuit board design support program according to the present embodiment. Next, the operation of the printed circuit board design support program will be described in detail with reference to FIGS.

  FIG. 6 is a schematic diagram illustrating an example of a wiring connection state from the driver IC to the receiver IC on the printed circuit board. In general, a printed circuit board has a multilayer structure in which a plurality of conductive layers are stacked via an insulating layer, and components such as integrated circuits and passive components are placed on the outermost two layers (hereinafter referred to as surface layers) of the stacked layers. Implemented. FIG. 6 shows an example in which component mounting and wiring are performed only on one surface layer for the sake of brevity.

  First, the wiring connection status of FIG. 6 will be described. The driver IC 800 has a reference of IC1. The output terminal 810 is an output terminal of the driver IC 800, and the terminal number is 6. Reflexes of the receiver ICs 801 to 804 are IC2 to IC5, respectively. The input terminals 821 to 824 are each one of the input terminals of the receiver ICs 801, 802, 803, and 804, and the terminal numbers are all three. The reflex of the resistor 805 is R1, the terminal closer to the 6th terminal of IC1 of R1 is the 1st terminal, and the terminal far from the 6th terminal of IC1 is the 2nd terminal. The wirings 830 to 837 are wirings (hereinafter referred to as lines) connecting between the terminal of the component and the branch point on the wiring or between the branch points of the wiring. Here, it is assumed that the wiring length of each line is 50 mm for 830, 150 mm for 831, 50 mm for 832, 50 mm for 833, 60 mm for 834, 10 mm for 835, 10 mm for 836, and 10 mm for 837. Branch points 840, 841, and 842 are wiring branch points.

  Hereinafter, the processing operation when the program of this embodiment is applied to the wiring in the connection state shown in FIG. 6 will be described in detail.

  When the program is started in step S300, layout information 14b and electrical characteristic information 14c are acquired in step S301. FIG. 7 shows an example of the electrical characteristic information 14c. In the example of FIG. 7, FIG. 7A shows the relationship between Lefdes, the manufacturer, and the model number, FIG. 7B shows the manufacturer, the model number, and the terminal name and type of the component, and FIG. 7C shows the manufacturer, model number, and power supply voltage. Information on electrical characteristics such as rise time and fall time is shown. Here, only a part of the electrical characteristic information is taken as an example, but more information is actually shown as the electrical characteristic information. Further, the method for storing the electrical property information data is not limited to this, and various other storage methods may be used.

  In step S302, a check condition is acquired. Here, as described above, it is assumed that the reflex of the driver IC is acquired. For example, the format may be such that the user selects the IC reflex on the screen as shown in FIG. 8 and the result is received by the input unit 20. The user selects an IC reflex that needs to be registered as a driver IC to be checked from the IC selection list 1010, and presses an add button 1020. At that time, the refdes of the IC selected by the user are deleted from the IC selection list 1010, and the refdes of the selected IC are added to the driver IC registration list 1011. In addition, the user selects the IC ref to be released from the driver IC to be checked from the driver IC registration list 1011 and presses the delete button 1021. At that time, the refdes of the IC selected by the user are deleted from the driver IC registration list 1011, and the refdes of the IC are added to the IC selection list 1010. The user repeats this, registers the refdes of all ICs to be checked as driver ICs in the driver IC registration list, and presses the output button 1022. At that time, the refdes of the IC registered in the driver IC registration list are stored in the main storage device 11. The above is the method for inputting check conditions when the driver IC selection screen of FIG. 8 is used. This input method is merely an example, and other input methods can be used as described above. Here, consider a case where the user inputs only IC1 as the ref des of the driver IC to be checked in step S302.

  In step S303, it is determined that IC1 is an unchecked driver IC to be checked. In step S304, IC1 is selected as a driver IC to be checked.

  In step S305, the sixth terminal is specified as the output terminal of IC1 with reference to FIGS. 7A and 7B. In step S306, it is determined that there is a sixth terminal of IC1 as an output terminal of the driver IC, and in step S307, the sixth terminal of IC1 is selected.

  In step S308, all the route information of the wiring branch route connected from the sixth terminal of IC1 is acquired. All the wiring branch paths acquired in step S308 are the four paths 111 to 114. For example, the path 111 starts from the 6th terminal of the IC1, and passes through the line 830, the 1st terminal of the resistor R1, the 2nd terminal of the resistor R1, the line 831, the branch point 840, and the line 835 in this order. To No. 3 terminal.

  In step S309, it is determined whether the terminal of the receiver IC on each wiring branch path is terminated. For example, in the case of the path 111, an IC terminal (hereinafter referred to as an input terminal of the receiver IC) different from IC1 that is a driver IC on the path is the third terminal of IC2. And it is determined that the terminal 3 of this IC2 is not terminated. This traces the path in the reverse direction from the third terminal of IC2, which is the end point of the path 111, and there is no termination component on the path 111 and at the branch destination of the branch point 840 and within a certain distance from the third terminal of IC2. It is possible to judge from this. Here, the constant distance may be a format that the user inputs with the input unit 20. Similarly, it is determined that there are no termination components at the third terminal of IC3, the third terminal of IC4, and the third terminal of IC5 on the paths 112, 113, and 114, respectively.

  In step S310, the third terminal of IC2, the third terminal of IC3, the third terminal of IC4, and the third terminal of IC5 are set as signal reflection points.

  In step S311 and step S312, it is determined that the signal reflection point includes the third terminal of IC2, the third terminal of IC3, the third terminal of IC4, and the third terminal of IC5, and in step S313, of the above four terminals. One is selected. For example, the third terminal of IC2 is selected.

  In step S314, the path including the third terminal of IC2, that is, the branch point 840 on the path 111 is acquired, and whether or not the branch terminal of the branch point 840 has an input terminal of the receiver IC different from the third terminal of IC2. Determined. Specifically, the route 112 is searched in order, and the branch point 840 is acquired. Then, a route is further searched in order from the branch point 840 on the route 112, and the third terminal of IC3 is acquired. Since the third terminal of IC3 is determined as the input terminal of the receiver IC in step S309, it is determined that the branch point 840 on the path 111 is a branch position to another receiver IC. In step S314, since only the branch point 840 is acquired as the branch position, the branch point 840 is set as the signal synthesis point for the third terminal of IC2. Then, the process returns to step S312, and it is determined that there are the third terminal of IC3, the third terminal of IC4, and the third terminal of IC5 as signal reflection points for which no signal combining point is set again. In step S313, one of the three terminals is selected. For example, the third terminal of IC5 is selected. In step S314, a branch point 840, a branch point 841, and a branch point 842 are acquired as branch positions connected to the input terminal of the receiver IC different from the third terminal of IC5 on the path 114 by the same method as described above. The

  In step S315, first, wiring distances from the sixth terminal of IC1 to each branch point 840, branch point 841, and branch point 842 are calculated. For example, since the wiring length from the sixth terminal of IC1 to the branch point 840 is equal to the sum of the wiring lengths of the line 830 and the line 831, it is calculated as 200 mm. Since the wiring distance from the sixth terminal of IC1 to the branch point 841 is equal to the sum of the wiring lengths of the line 830, the line 831 and the line 832, it is calculated as 250 mm. Similarly, the wiring distance from the sixth terminal of IC1 to the branch point 842 is calculated as 300 mm. A branch point 840 having the shortest wiring distance from the sixth terminal of IC1 is set as a signal synthesis point for the third terminal of IC5. Then, the process returns to step S312. Thereafter, similarly, the processing from step S312 to step S315 is sequentially repeated until there is no signal reflection point for which no signal combining point is set in step S312. In this embodiment, a branch point 840 is set as a signal synthesis point for the third terminal of IC3 and the third terminal of IC4. Then, when there is no signal reflection point for which no signal combining point is set in step S312, the process proceeds to step 316.

  In step S316, first, each wiring distance between the signal reflection point and the signal synthesis point set in steps S312 to 315 is calculated. First, since the wiring distance from the third terminal of IC2 to the branch point 840 is equal to the wiring length of the line 835 from the path 111, it is 10 mm. Next, the wiring distance from the third terminal of IC5 to the branch point 840 is 160 mm because it is equal to the sum of the wiring lengths of line 834, line 833, and line 832 from path 114. Similarly, the wiring distance from the third terminal of IC4 to the branch point 840 is calculated as 110 mm, and the wiring distance from the third terminal of IC3 to the branch point 840 is calculated as 60 mm. The wiring distance between the signal reflection point and the signal combining point is the longest in the wiring distance between the third terminal of IC5 and the branching point 840 since it is determined that the third terminal of IC5 is at the branching point 840. Identified as a long combination.

  In step S317, the wiring distance d (= 160 mm) between the third terminal of IC5 and the branch point 840, which is the signal reflection point and signal combining point specified as the combination having the longest wiring distance in step S316, is acquired.

In step S318, the round-trip propagation delay time t _p [ns] (= t _plh × 2d × 10 ⁻³ ) is calculated from t _plh [ns / m] calculated in _Equation 1 and the wiring distance d [mm]. . For example, if the relative dielectric constant of the insulating layer of the printed circuit board is 4.4, t _plh = 5.48 [ns / m] from _Equation 1. Therefore, the round-trip propagation delay time between the third terminal of IC5 and the branch point 840 is t _p = 5.48 × 2 × 160 × 10 ⁻³ = 1.75 [ns].

In step S319, referring to FIGS. 7A and 7C, the output rise time (1.5 [ns]) and fall time (1.5 [ns]) of the output of IC1 are acquired, and the transition time is obtained. t _c = 1.5 [ns] is acquired.

In step S320, it is determined that t _p > t _c and the process proceeds to step S321.

  In step S321, NG information is output assuming that the wiring distance between the third terminal of IC5 and the branch point 840 is redundant. Here, an example regarding the output method of NG information is given. However, since there are various methods for outputting NG information, the method is not limited to the example given here. FIG. 9 shows an example of output contents when NG information is output as a file. The output file shows the output terminal of the driver IC, the signal synthesis point, the signal reflection point, the determination result, the branch wiring length, and the allowable wiring length. Here, the coordinates of the branch point 840 are used as the signal synthesis point. However, for example, the input terminal of the receiver IC at the branch destination can also be described. The allowable wiring length is a maximum allowable value of the wiring distance of the branch wiring determined by the transition time of the output signal of the driver IC. Here, output is performed in a table format, but it is also possible to output in a text format delimited using specific symbols such as commas. Further, each column of the table can be color-coded or shaded according to the determination result of the table. FIG. 9B is an example when NG information is output on the design data. In FIG. 9B, the wiring between the third terminal of the IC 5 that is the signal reflection point and the branch point 840 that is the signal synthesis point is indicated by a one-dot chain line. In this way, it is only necessary to display so that the portion determined to be NG because the branch wiring is redundant can be recognized by the user. Further, the entire wiring including NG regarding the length of the branch wiring may be displayed so as to be recognized by the user on the assumption that correction is necessary. Here, the display is made with a one-dot chain line, but it may be displayed with a color different from that of the normal wiring or with another type of line such as a dotted line. Various display methods are conceivable, such as highlighting the branch position determined to be NG and the position of the input terminal of the receiver IC, and further connecting them with a straight line.

  The above is the processing operation of the printed circuit board design support program in the present embodiment. By confirming the output result shown in FIG. 9A or 9B, the user can easily recognize the wiring that needs to be corrected. Then, the component arrangement or wiring is changed so that the wiring length of the branch wiring is reduced. For example, as shown in FIG. 10, it is preferable to reduce the wiring length of the branch wiring by changing the wiring structure and branching from the branch point 1440 if possible. This is an example of the wiring change, and the wiring changing method is not limited to this because the wiring needs to be changed depending on the state of the wiring around the branch wiring to be checked.

  In the present embodiment, an example is given in which the calculation of the propagation delay time per unit length of the signal is executed in step S318. On the other hand, the layout information 14b necessary for the calculation has already been acquired in step S301. That is, the above calculation may be executed anywhere between step S301 and step S318. Similarly, an example is given in which the transition time of the output signal of the driver IC is acquired in step S319. On the other hand, the electrical characteristic information 14c necessary for the acquisition has already been acquired in step S301. That is, the acquisition may be executed anywhere from step S301 to step S319. That is, the case where the calculation of the propagation delay time per unit length of the signal and the acquisition of the transition time of the output signal of the driver IC are different are also within the scope of the present embodiment.

  In the first embodiment, the case where the driver IC is specified is described as an example in which the user inputs the check condition. On the other hand, considering the recent increase in the number of IC terminals, the user may check only the desired wiring. This is to prevent the user from having to search for a result that needs to be checked from the output result when a lot of results that the user determines that the check is not necessary are output. In general, since designers often reflect the characteristics and roles of electrical signals in the wiring names, it is desirable that the user specify the wiring names of the signal wirings. Therefore, in this embodiment, an example is shown in which the user designates a wiring name as a check condition.

  FIG. 11 is a part of a flowchart for explaining a preferred example of the processing procedure in the printed circuit board design support method and program according to this embodiment. Even when the user designates a wiring name, it is preferable that the output terminal of the driver IC is acquired in order to acquire the routing information of the wiring branch path in step S308. Accordingly, the flowchart of FIG. 11 replaces the processing from step S303 to step S305 in the flowchart of FIG. 3 with step S1500 to step S1505. The processing operations before step S301 and after step S307 are the same as those in the first embodiment. Accordingly, the processing operation from step S302 to step S306 will be described below.

  First, the flowchart of FIG. 11 will be described. In step S302, when the CPU 10 transfers the layout information 14b and the electrical characteristic information 14c to the main storage device 11 in the external storage information extraction unit 21 in step S301, the input unit 20 receives the check condition. The check condition here is a wiring name of a signal wiring to be checked. As a method for designating the wiring name of the signal wiring by the user, for example, a list of wiring names is displayed on a window displayed on the display device 12 and the wiring name selected by the user using the input device 13 is displayed. A method of storing in the main storage device 11 is conceivable. In addition, referring to the layout information 14 b in the main storage device 11, the wiring name of the signal wiring selected by the user using the input device 13 on the circuit diagram or printed circuit board design drawing displayed on the display device 12 is referred to. A method of acquiring and storing in the main storage device 11 is conceivable. Further, a method of reading information such as a text file stored in advance in an external storage device and storing it in the main storage device 11 can be considered.

  Hereinafter, steps S1500 to S1505 are all executed by the branch wiring route acquisition unit 22a. In step S1500, upon receiving the check condition in step S302, the CPU 10 determines whether there is a wiring name to be checked for which no component terminal has been acquired. If there is a check target wiring name for which the component terminal has not been acquired in step S1500, the process proceeds to step S1501, and if there is no check target wiring name for which the component terminal has not been acquired, the process proceeds to step S306.

  In step S1501, if there is a check target wiring name for which no component terminal has been acquired in step S1500, the CPU 10 selects one of the check target wiring names (hereinafter referred to as a wiring name E).

  In step S1502, the CPU 10 refers to the netlist included in the layout information 14b in the main storage device 11, and acquires a component terminal directly connected to the signal wiring belonging to the wiring name E. Here, the net list is a list in which a component terminal connected to a wiring belonging to each wiring name on the circuit and a terminal name are described for each wiring. Here, the net list is used, but it is also possible to substitute the list information obtained from the layout information 14b and the circuit diagram corresponding to the printed circuit board for the reflexes and terminal names of each component terminal and the wiring names to which they belong.

  In step S1503, when the component terminal is acquired in step S1502, the CPU 10 refers to the electrical characteristic information 14c, determines whether there is an IC output terminal in the acquired component terminal, and if so, outputs the driver IC output terminal. As specified.

  In step S1504, the CPU 10 determines whether or not the component acquired in step S1503 has a terminal for a component for countermeasures against noise (hereinafter, countermeasure component). Here, the countermeasure component is a component serving as a noise filter such as a resistor (including a resistor array) or a coil, for example, called a damping resistor. Information that can identify these parts as countermeasure parts may be included in the part information and the electrical characteristic information 14c. However, in reality, resistances, coils, noise filters, and the like may be countermeasure parts regardless of countermeasure parts, and all of these parts may be temporarily determined as countermeasure parts. If there is a countermeasure component terminal in step S1504, the process proceeds to step S1505. If there is no countermeasure component terminal, the process returns to step S1500.

  In step S1505, if there is a countermeasure component terminal in step S1504, the CPU 10 acquires and checks the wiring name to which the opposite terminal of the countermeasure component terminal belongs based on the layout information 14b, the electrical characteristic information 14c, or the component information. Add to the target wiring name. However, if it is the same as the wiring name of the power source or ground and other wiring names to be checked, it is not acquired. Then, the process returns to step S1500. Similarly, the loop processing from step S1500 to step S1505 is executed until it is determined in step S1500 that there is no check target wiring name for which no component terminal has been acquired.

  In step S306, if it is determined in step S1500 that there is no name of a wiring to be checked for which no component terminal has been acquired, it is determined whether there is an output terminal for an unchecked driver IC. If it is determined in step S306 that there is an unchecked driver IC output terminal, the process proceeds to step S307. If it is determined that there is no unchecked driver IC output terminal, the program is terminated. The processes after step S307 are the same as those in the first embodiment. With the above processing, even when the user designates a wiring name, the output terminal of the driver IC connected to the signal wiring can be acquired and the same check as in the first embodiment can be performed.

  Next, the processing operation from step S302 to step S306 in the flowchart of FIG. 11 will be described in detail using the schematic diagram of the wiring connection situation shown in FIG. In general, the wiring names of the respective lines are the same as long as the lines are directly connected. That is, the name of the wiring to which each line belongs does not differ unless a part such as an IC or a series part is used. For example, in the case of FIG. 6, the wiring names of the line 830 and the line 831 are different, but the lines 831, 832, 833, 834, 835, 836, and 837 have the same wiring name. Here, the line name of the line 830 is LINE_AAA, and the line name of the line 831 is LINE_BBB. In this case, there are two netlists, LINE_AAA and LINE_BBB, only in the portion of FIG.

  First, check conditions are accepted in step S302. Here, it is assumed that the user designates only LINE_BBB.

  In step S1500, it is determined that there is LINE_BBB as a check target wiring name for which no component terminal has been acquired, and in step S1501, a wiring name LINE_BBB is selected.

  In step S1502, a component terminal directly connected to the wiring name LINE_BBB is acquired from the net list. That is, the third terminal of IC2, the third terminal of IC3, the third terminal of IC4, the third terminal of IC5, and the second terminal of resistor R1 are acquired.

  In step S1503, since the third terminal of IC2, the third terminal of IC3, the third terminal of IC4, and the third terminal of IC5 are not output terminals of the IC from the electrical characteristic information 14c, the process proceeds to step S1504.

  In step S1504, since the resistance R1 can be temporarily determined as a countermeasure component, it is determined that there is a countermeasure component, and the process proceeds to step S1505.

  In step S1505, the first terminal which is the opposite terminal of the second terminal of the resistor R1 is acquired, and the wiring name LINE_AAA to which the first terminal of the resistor R1 belongs is added as a wiring name to be checked from the net list. In step S1500, it is determined that there is a wiring name LINE_AAA as a check target wiring that has not been acquired, and a wiring name LINE_AAA is selected in step S1501. In step S1502, a component terminal connected to the wiring name LINE_AAA is acquired from the net list. That is, the sixth terminal of IC1 and the first terminal of resistor R1 are acquired. In step S1503, the electrical characteristic information 14c is referred to, and the sixth terminal of IC1 is specified as the output terminal of the driver IC. In step S1504, it is temporarily determined that the first terminal of the resistor R1 is a countermeasure component terminal. In step S1505, LINE_BBB, which is the wiring name to which the second terminal of the resistor R1 belongs, is acquired. However, since LINE_BBB is already registered as the wiring name to be checked, it is not added. Returning to step S1500, since it is determined that there is no wiring name to be checked for which no component terminal has been acquired, the process proceeds to step S306.

  In step S306, the 6th terminal of IC1 is acquired as the output terminal of the unchecked driver IC.

  After step S307, the same processing as in the first embodiment is executed. Then, when the check of the length of the branch wiring is completed in the wiring path connected to the sixth terminal of IC1, that is, when step S320 or step S321 is completed, the process returns to step S306. Finally, it is determined in step S306 that there is no unchecked driver IC output terminal, and the program is terminated.

  The above is the processing operation of the printed circuit board design support program in the present embodiment. As in the first embodiment, the user can check the output result of the printed circuit board design support program in the present embodiment and easily recognize the branch wiring that needs to be corrected. Then, the component arrangement or wiring is changed so that the branch wiring is shortened.

  In the above embodiment, the transition time and the round trip propagation delay time are compared. However, a distance with respect to the transition time may be calculated and compared with the wiring distance.

  The present invention can also be realized by supplying a storage medium storing software program codes for realizing the functions of the above-described embodiments (for example, the functions shown in the above flowchart) to a system or apparatus. In this case, the function of the above-described embodiment is realized by the computer (or CPU or MPU) of the system or apparatus reading and executing the program code stored in the storage medium so that the computer can read it.

Claims (9)

Input means for inputting layout information on the printed circuit board and electrical characteristic information of the driver semiconductor integrated circuit on the printed circuit board;
Selecting means for selecting the driver semiconductor integrated circuit;
Based on the layout information, path information for acquiring path information indicating a path connecting a plurality of receiver semiconductor integrated circuits connected to the selected driver semiconductor integrated circuit on the printed circuit board and the selected driver semiconductor integrated circuit. Acquisition means;
Setting means for setting a composite point at a branch position on the route;
Based on the path information, distance acquisition means for acquiring a distance between the synthesis point and each of the receiver semiconductor integrated circuits;
Transition time acquisition means for acquiring a transition time of an electrical signal output from the selected driver integrated circuit based on the electrical characteristic information;
Determination means for determining whether or not the route is appropriate based on a distance between the combined point and the receiver semiconductor integrated circuit, and the transition time, among the distances ,
The information processing apparatus , wherein the setting means sets the synthesis point at a branch position where the wiring distance from the driver integrated circuit is shortest or a branch position where the wiring distance from the receiver semiconductor integrated circuit is longest .   The information processing apparatus according to claim 1, further comprising a notification unit that notifies a warning when the route is inappropriate as a result of the determination by the determination unit. The determination means includes a calculation means for calculating a round trip time required for a round trip of the electrical signal at the distance,
The information processing apparatus according to claim 1 , wherein the information processing apparatus determines whether the route is appropriate by comparing the transition time and the round-trip time. The information processing apparatus according to claim 3 , wherein the determination unit determines that the route is inappropriate when the round trip time is greater than the transition time. The route information obtaining means, according to any one of claims 1 to 4, characterized in that it comprises a specifying means for specifying said plurality of receiver semiconductor integrated circuit which has not been terminated with the layout information Information processing device. It said selection means, the information processing apparatus according to any one of claims 1 to 5, characterized in that selecting the driver semiconductor integrated circuit by a user instruction. A method for controlling an information processing apparatus,
An input means, an input step of inputting an electrical characteristic information of the driver semiconductor integrated circuit layout information and on the printed circuit board on the printed board,
A selection step in which the selection means selects the driver semiconductor integrated circuit; and
A path indicating a path connecting a plurality of receiver semiconductor integrated circuits connected to the selected driver semiconductor integrated circuit on the printed circuit board and the selected driver semiconductor integrated circuit based on the layout information. A route information acquisition process for acquiring information;
A setting step in which a setting means sets a composite point at a branch position on the route;
A distance acquisition unit that acquires a distance between the synthesis point and each of the receiver semiconductor integrated circuits based on the path information;
A transition time acquiring unit acquires a transition time of the selected driver integrated circuit based on the electrical characteristic information; and
Determining means, among the distance, the distance between said combining point the receiver semiconductor integrated circuit is closed and a determination step of determining whether the route is appropriately based on the distance which maximizes the transition time,
The information processing apparatus control is characterized in that the setting step sets the composite point at a branch position where the wiring distance from the driver integrated circuit is shortest or a branch position where the wiring distance from the receiver semiconductor integrated circuit is longest. Method. For realizing each means according to the computer in any one of claims 1 to 6, computer-executable program. A computer-readable recording medium on which the program according to claim 8 is recorded.