JP5487082B2 - High frequency circuit - Google Patents

Description

  Embodiments described herein relate generally to a high frequency circuit having an oscillation suppression circuit.

  In recent high frequency transistors, a large number of cells are connected in parallel to increase the output. Since distributed synthesis is performed for a large number of cells, a large number of loops having different lengths are formed. As a result, a plurality of loops may oscillate at frequencies unique to the loop.

  In order to suppress such loop oscillation, it is necessary to connect the lines constituting the loop in which the oscillation occurs with a resistor having a specific resistance value at a specific position.

Japanese Patent No. 3289464 Japanese Patent Application Laid-Open No. 07-307626

  When there are multiple loops with different lengths that oscillate, even if a resistor having the optimum resistance value is connected to each loop, the resistance to each loop is in a parallel connection relationship. The resistance is affected and the resistance value becomes lower than the optimum resistance value, and the oscillation suppression effect is weakened.

  In addition, for a loop that oscillates relatively small and is close enough to allow the lines constituting the loop to be directly connected by a resistor, oscillation can be suppressed only by forming a resistor between the lines. However, the lines constituting the loop are separated from each other, and an inductance is generated between the resistance and the line for the loop in which the resistor and the line must be connected by a line or a wire, and the oscillation suppressing effect by the resistance is weakened.

  The high-frequency circuit according to the present embodiment includes a plurality of transistors, a plurality of input matching circuits, and an input-side oscillation suppression circuit. The plurality of transistors are arranged in parallel on the semiconductor substrate. The plurality of input matching circuits are disposed on the first insulating substrate and connected to the gate terminal electrodes of the plurality of transistors, respectively. The input-side oscillation suppression circuit includes an input-side fourth oscillation suppression resistor, an input-side first capacitor, and an input-side first inductor. The input-side fourth oscillation suppression resistor is disposed on the first insulating substrate and is disposed adjacent to the input matching circuit. The input-side first capacitor is connected in series to the input-side fourth oscillation suppression resistor. The input-side first inductor is connected between a point on the transmission line connecting adjacent input matching circuits and the input-side first capacitor.

When the inductance value of the input-side first inductor is L1, and the capacitance value of the input-side first capacitor is C1, the input-side first inductor represented by 1 / {2π (L1 × C1) ^1/2 } and the input-side first inductor The resonance frequency of one capacitor is equal to the oscillation frequency focs2 of the two-cell loop.

The typical circuit block diagram of the high frequency circuit which concerns on embodiment. The typical circuit block diagram of the input side oscillation suppression circuit used for the high frequency circuit which concerns on embodiment. The typical circuit block diagram of the output side oscillation suppression circuit used for the high frequency circuit which concerns on embodiment. FIG. 4 is a schematic circuit configuration diagram for explaining a minimum loop LP1, a two-cell loop LP2, and a four-cell loop LP3 in the high-frequency circuit according to the embodiment. The typical circuit block diagram explaining the loop LP4 containing an oscillation suppression circuit in the high frequency circuit which concerns on embodiment. (A) The enlarged view of the typical plane pattern structure of the semiconductor device mounted in the high frequency circuit which concerns on embodiment, (b) The enlarged view of J part of Fig.6 (a). FIG. 7 is a schematic cross-sectional structure diagram taken along the line II of FIG. 6B, which is a configuration example 1 of the semiconductor device mounted on the high-frequency circuit according to the embodiment. FIG. 7 is a schematic cross-sectional structure diagram taken along line II of FIG. 6B, which is a configuration example 2 of the semiconductor device mounted on the high-frequency circuit according to the embodiment. FIG. 7 is a schematic cross-sectional structure diagram taken along the line II of FIG. 6B, which is a configuration example 3 of the semiconductor device mounted on the high-frequency circuit according to the embodiment. FIG. 7 is a schematic cross-sectional structure diagram taken along the line II of FIG. 6B, which is a configuration example 4 of the semiconductor device mounted on the high-frequency circuit according to the embodiment.

  Next, embodiments will be described with reference to the drawings. In the following, the same elements are denoted by the same reference numerals to avoid duplication of explanation and to simplify the explanation. It should be noted that the drawings are schematic and different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  The embodiment described below exemplifies an apparatus and a method for embodying the technical idea, and the embodiment does not specify the arrangement of each component as described below. This embodiment can be modified in various ways within the scope of the claims.

  A schematic circuit configuration of the high-frequency circuit 1 according to the embodiment is expressed as shown in FIG.

  As shown in FIG. 1, the high-frequency circuit 1 according to the embodiment includes a plurality of transistors Q1 to Q8 arranged in parallel on a semiconductor substrate 10 and a plurality of transistors Q1 to Q1 arranged on a first insulating substrate 12. A plurality of input matching circuits 16 respectively connected to the gate terminal electrodes G1 to G8 of Q8, and input-side first oscillation suppression resistors R11a, which are arranged on the first insulating substrate 12 and arranged between the input matching circuits 16. An input-side second oscillation suppression resistor R11b, an input-side third oscillation suppression resistor R11c, and a tree-shaped transmission line 17 which is arranged on the first insulating substrate 12 and connects between the plurality of input matching circuits 16 and the input terminal Pi. 18, 19 and the input side fourth oscillation suppression resistor R12, which is disposed on the first insulating substrate 12 and disposed between the transmission lines 18, and is connected to one terminal TAi of the input side fourth oscillation suppression resistor R12. The An input side composed of a first power-side capacitor C12, an input-side first inductor L12, an input-side first capacitor C12 connected to the other terminal TBi of the input-side fourth oscillation suppression resistor R12, and an input-side first inductor L12. The oscillation suppression circuit 2, the plurality of output matching circuits 26 disposed on the second insulating substrate 14 and connected to the drain terminal electrodes D1 to D8 of the plurality of transistors Q1 to Q8, respectively, and the second insulating substrate 14 The output side first oscillation suppression resistor R21a, the output side second oscillation suppression resistor R21b, the output side third oscillation suppression resistor R21c, and the second insulation substrate 14 disposed between the output matching circuits 26. Arranged on the second insulating substrate 14 between the plurality of output matching circuits 26 and the output terminal Po, and disposed on the second insulating substrate 14. Output-side fourth oscillation suppression resistor R22, output-side first capacitor C22 and output-side first inductor L22 connected to one terminal TAo of output-side fourth oscillation suppression resistor R22, and output-side fourth oscillation suppression resistor R22. The output-side oscillation suppression circuit 4 including the output-side first capacitor C22 and the output-side first inductor L22 connected to the other terminal TBo.

(Input side)
A schematic circuit configuration of the input-side oscillation suppression circuit 2 used in the high-frequency circuit according to the embodiment is represented as shown in FIG. 2, and a schematic circuit configuration of the output-side oscillation suppression circuit 4 is as shown in FIG. A schematic circuit configuration expressed and explaining the minimum loop LP1, the 2-cell loop LP2, and the 4-cell loop LP3 is expressed as shown in FIG.

  As shown in FIG. 1, a plurality of input matching circuits 16 and input terminals Pi are connected by tree-shaped transmission lines 17, 18, and 19. The adjacent input matching circuit 16 and the transmission line 17 connecting them form a minimum loop LP1 (see FIGS. 2 and 4). The point on the transmission line 17 that connects the adjacent input matching circuits 16 and is equidistant from the adjacent input matching circuit 16 is represented by the nodes S1i, S2i, S3i, and S4i of the loop.

  A two-cell loop LP2 is formed by the adjacent minimum loop LP1 and the transmission line 18 connecting them (see FIGS. 2 and 4). The transmission line 18 connecting the minimum loop LP1 is connected at the nodes S1i, S2i, S3i, and S4i of the minimum loop. In the oscillation of the minimum loop LP1, since the node is equivalent to the ground point, the transmission line 18 connected to the node and the resistance connected to the transmission line 18 do not affect the oscillation of the minimum loop. A point on the transmission line 18 connecting the adjacent minimum loop LP1 and equidistant from the adjacent minimum loop LP1 is represented by loop nodes S5i and S6i.

  A 4-cell loop LP3 is formed by the 2-cell loop LP2 and the transmission line 19 connecting them (see FIG. 4). The transmission line 19 connecting the two-cell loop LP2 is connected at the nodes S5i and S6i of the two-cell loop. In the oscillation of the two-cell loop LP2, since the node of the loop is equivalent to the ground point, the transmission line 19 connected to the node and the resistance connected to the transmission line 19 do not affect the oscillation of the two-cell loop LP2. A point on the transmission line 19 connecting the adjacent two-cell loops LP2 and equidistant from the adjacent two-cell loops LP2 is represented by a loop node S7i.

  In addition, as shown in FIG. 1, the high-frequency circuit 1 according to the embodiment is arranged on the first insulating substrate 12 and is arranged between the input matching circuit 16 and the input side first oscillation suppression resistor R11a / input. Side second oscillation suppression resistor R11b and input side third oscillation suppression resistor R11c.

  Here, the input side first oscillation suppression resistor R11a is arranged on the minimum loop LP1 to be suppressed as shown in FIG. 4 from the minimum loop nodes S1i, S2i, S3i, S4i to the minimum loop oscillation frequency fosc1. The position is about 1/4 of the wavelength at.

  Further, the high-frequency circuit 1 according to the embodiment includes an input-side oscillation suppression circuit 2 connected between two points on the transmission line 17 as shown in FIG. The input-side oscillation suppression circuit 2 includes an input-side fourth oscillation suppression resistor R12, an input-side first capacitor C12 connected to one terminal TAi of the input-side fourth oscillation suppression resistor R12, and an input-side first inductor L12. And a second series resonance circuit composed of an input-side first capacitor C12 connected to the other terminal TBi of the input-side fourth oscillation suppression resistor R12 and an input-side first inductor L12. Consists of connections.

Here, when the capacitance value of the input-side first capacitor C12 is C1, and the inductance value of the input-side first inductor L12 is L1, the resonance frequency of the series circuit including the input-side first capacitor C12 and the input-side first inductor L12 is 1 / {2π (L1 × C1) ^1/2 }, and an inductance value L1 and a capacitance value C1 are determined so as to be equal to the oscillation frequency fosc2 of the 2-cell loop. As shown in FIG. 4, the input-side fourth oscillation suppression resistor R12 is arranged at about 1/4 of the wavelength at the two-cell loop oscillation frequency fosc2 from the two-cell loop nodes S5i and S6i on the two-cell loop LP2 to be suppressed. It becomes the position.

  Since the input-side oscillation suppression circuit 2 is provided, a 4-cell loop LP3 having a different length from the 2-cell loop LP2 is formed. Since the input-side fourth oscillation suppression resistor R12 of the input-side oscillation suppression circuit 2 becomes a node in the 4-cell loop LP3, there is no oscillation suppression effect with respect to the oscillation frequency fosc4 of the 4-cell loop LP3. An input-side second oscillation suppression resistor R11b is provided to suppress oscillation that occurs in the 4-cell loop LP3. As shown in FIG. 4, the input-side second oscillation suppression resistor R11b is disposed on the 4-cell loop LP3 to be suppressed from the input-side fourth oscillation suppression resistor R12, which is a node of the 4-cell loop LP3, to the 4-cell loop LP3. The position is about 1/4 of the wavelength at the oscillation frequency fosc4.

  In the 2-cell loop LP2, the input-side second oscillation suppression resistor R11b and the input-side oscillation suppression circuit 2 are arranged in parallel. At this time, the length from the input-side second oscillation suppression resistor R11b to the input-side fourth oscillation suppression resistor R12 of the input-side oscillation suppression circuit 2 forms the path LPi as shown in FIG. The path LPi is provided by a part of the input matching circuit 16, the transmission line 17, a part of the transmission line 18, the first inductor L12, and the first capacitor C12, and is about the wavelength at the two-cell loop oscillation frequency fosc2. It is determined to be (2n-1) / 4 (n is an integer).

(Output side)
As shown in FIG. 1, a plurality of output matching circuits 26 and output terminals Po are connected by tree-shaped transmission lines 27, 28, and 29. The adjacent output matching circuit 26 and the transmission line 27 connecting them form a minimum loop LP1 (see FIGS. 3 and 4). A point on the transmission line 27 that connects the adjacent output matching circuits 26 and is equidistant from the adjacent output matching circuit 26 is represented by a loop node S1o, S2o, S3o, and S4o.

  A two-cell loop LP2 is formed by the adjacent minimum loop LP1 and the transmission line 26 connecting them (see FIGS. 3 and 4). The transmission line 28 connecting the minimum loop LP1 is connected at the nodes S1o, S2o, S3o, and S4o of the minimum loop. In the oscillation of the minimum loop LP1, since the node is equivalent to the ground point, the transmission line 28 connected to the node and the resistance connected to the transmission line 28 do not affect the oscillation of the minimum loop LP1. A point on the transmission line 28 connecting the adjacent minimum loop LP1 and equidistant from the adjacent minimum loop LP1 is represented by a loop node S5o / S6o.

  A 4-cell loop LP3 is formed by the 2-cell loop and the transmission line 29 connecting them (see FIG. 4). The transmission line 29 connecting the two-cell loop LP2 is connected at the nodes S5o and S6o of the two-cell loop. In the oscillation of the two-cell loop LP2, since the node is equivalent to the ground point, the transmission line 29 connected to the node and the resistance connected to the transmission line 29 do not affect the oscillation of the two-cell loop LP2. A point on the transmission line 29 connecting the adjacent two-cell loops LP2 and equidistant from the adjacent two-cell loops LP2 is represented by a loop node S7o.

  Further, as shown in FIG. 1, the high-frequency circuit 1 according to the embodiment is disposed on the second insulating substrate 14 and is arranged between the output matching circuit 26 and the output-side first oscillation suppression resistor R21a / output. Side second oscillation suppression resistor R21b and output side third oscillation suppression resistor R21c.

  Here, the position where the output-side first oscillation suppression resistor R21a is arranged is the minimum loop oscillation frequency fosc1 from the minimum loop nodes S1o, S2o, S3o, S4o on the minimum loop LP1 to be suppressed as shown in FIG. The position is about 1/4 of the wavelength at.

  The high-frequency circuit 1 according to the embodiment includes an output-side oscillation suppression circuit 4 connected between two points on the transmission line 27 as shown in FIG. The output-side oscillation suppression circuit 4 includes an output-side fourth oscillation suppression resistor R22, an output-side first capacitor C22 connected to one terminal TAo of the output-side fourth oscillation suppression resistor R22, and an output-side first inductor L22. And a second series resonance circuit composed of an output-side first capacitor C22 connected to the other terminal TBo of the output-side fourth oscillation suppression resistor R22 and an output-side first inductor L22. Consists of.

Here, when the capacitance value of the output-side first capacitor C22 is C2, and the inductance value of the output-side first inductor L22 is L2, the resonance frequency of the series circuit including the output-side first capacitor C22 and the output-side first inductor L22 is The inductance value L2 and the capacitance value C2 are determined so as to be equal to the oscillation frequency fosc2 of the 2-cell loop LP2, which is expressed by 1 / {2π (L2 × C2) ^1/2 }. As shown in FIG. 4, the position where the output-side fourth oscillation suppression resistor R22 is arranged is about 1 / of the wavelength at the 2-cell loop oscillation frequency fosc2 from the nodes S5o and S6o of the 2-cell loop on the 2-cell loop LP2 to be suppressed. 4 position.

  In the high-frequency circuit according to the embodiment, a schematic circuit configuration for explaining the loop LP4 including the oscillation suppression circuit is expressed as shown in FIG. Since the output-side oscillation suppression circuit 4 is provided here, a loop LP4 including an oscillation suppression circuit having a length different from that of the 2-cell loop LP2 is formed. Since the output-side fourth oscillation suppression resistor R22 of the output-side oscillation suppression circuit 4 becomes a node in the loop LP4 including the oscillation suppression circuit, there is no oscillation suppression effect on the oscillation frequency fosc4 of the loop LP4 including the oscillation suppression circuit. In order to suppress oscillation generated in the loop LP4 including the oscillation suppression circuit, an output-side second oscillation suppression resistor R21b is provided. The output side second oscillation suppression resistor R21b is arranged on the output side serving as a node of the loop LP4 including the oscillation suppression circuit on the loop LP4 including the oscillation suppression circuit to be suppressed as shown in FIGS. From the fourth oscillation suppression resistor R22, the position is about 1/4 of the wavelength at the oscillation frequency fosc4 of the loop LP4 including the oscillation suppression circuit.

  In the 2-cell loop, the output-side second oscillation suppression resistor R21b and the output-side oscillation suppression circuit 4 are arranged in parallel. At this time, the length from the output-side second oscillation suppression resistor R21b to the output-side fourth oscillation suppression resistor R22 of the output-side oscillation suppression circuit 4 constitutes the path LPo as shown in FIG. The path LPo is provided by a part of the output matching circuit 26, a transmission line 27, a part of the transmission line 28, the output-side first capacitor C22, and the output-side first inductor L22, and the two-cell loop oscillation frequency fosc2. It is determined to be about (2n-1) / 4 of the wavelength at (n is an integer).

  The input matching circuit 16 is connected to the input side of the plurality of transistors Q1 to Q8, that is, to the gate terminal electrodes G1 to G8 side. The input matching circuit 16 is divided for each of the transistors Q <b> 1 to Q <b> 8 and is disposed on the first insulating substrate 12.

  Each of the plurality of divided input matching circuits 16 is electrically connected to the respective gate terminal electrodes G1 to G8 of the plurality of transistors Q1 to Q8 by a conductor such as a bonding wire.

  An output matching circuit 26 is connected to the output side of the plurality of transistors Q1 to Q8, that is, the drain terminal electrodes D1 to D8 side. The output matching circuit 26 is divided for each of the transistors Q <b> 1 to Q <b> 8 and is disposed on the second insulating substrate 14.

  Each of the divided output matching circuits 26 is electrically connected to the respective drain terminal electrodes D1 to D8 of the plurality of transistors Q1 to Q8 by a conductor such as a bonding wire.

  Between the respective input matching circuits 16 on the first insulating substrate 12, for example, the input side first oscillation suppression resistor R11a, the input side second oscillation suppression resistor R11b, and the input side third oscillation suppression are filled so as to fill them. A resistor R11c is disposed. Similarly, between the output matching circuits 26 on the second insulating substrate 14, for example, the output side first oscillation suppression resistor R21a, the output side second oscillation suppression resistor R21b, Three oscillation suppression resistors R21c are arranged. For example, the input side first oscillation suppression resistor R11a, the input side second oscillation suppression resistor R11b, the input side third oscillation suppression resistor R11c, the output side first oscillation suppression resistor R21a, the output side second oscillation suppression resistor R21b, and the output side second The triple oscillation suppression resistor R21c is made of tantalum nitride (TaN) or an alloy centered on nickel (Ni) and chromium (Cr).

(loop)
In the high-frequency circuit 1 according to the present embodiment, the minimum loop LP1, the 2-cell loop LP2, and the 4-cell loop LP3 will be described with reference to FIG. In FIG. 4, the input side oscillation suppression circuit 2 including L12, C12, R12, C12, and L12 and the output side oscillation suppression circuit 4 including L22, C22, R22, C22, and L22 are not shown.

  The minimum loop oscillation having the minimum loop oscillation frequency fosc1 is an odd mode oscillation that occurs between a pair of cells (minimum loop). As shown in FIG. 4, the minimum loop LP1 is composed of adjacent transistors Q1 and Q2, Q3 and Q4, Q5 and Q6, Q7 and Q8, and a transmission line connecting them.

  The 2-cell loop oscillation having the 2-cell loop oscillation frequency fosc2 is an odd mode oscillation that occurs between a pair of two cells (2-cell loop). As shown in FIG. 4, the two-cell loop LP2 is composed of adjacent adjacent minimum loop pairs and a transmission line connecting them.

  The 4-cell loop oscillation having the 4-cell loop oscillation frequency fosc3 is an odd mode oscillation generated between a pair of 4 cells (4 cell loop). As shown in FIG. 4, the 4-cell loop LP3 is composed of adjacent two-cell loop pairs adjacent to each other and a transmission line connecting them.

(Oscillation suppression)
This is suppressed by connecting the points (antinodes) where the voltage amplitude of the standing wave of the loop oscillation becomes large with an oscillation suppression resistor having a value near the characteristic impedance of the transmission line.

  The plurality of input matching circuits 16 are connected by an input-side first oscillation suppression resistor R11a disposed between them. The plurality of output matching circuits 26 are connected by an output-side first oscillation suppression resistor R21a disposed between them. Therefore, for example, high-frequency oscillation in the GHz band passing through the minimum loop LP1 is attenuated by the input-side first oscillation suppression resistor R11a and the output-side first oscillation suppression resistor R21a. Thereby, high frequency oscillation can be suppressed. In the high-frequency circuit 1 according to the present embodiment, the signal component of the minimum loop oscillation frequency fosc1 based on the minimum loop LP1 is the input side first oscillation suppression resistor R11a disposed between the adjacent input matching circuits 16 and the adjacent output matching. The output side first oscillation suppression resistor R21a disposed between the circuits 26 can be attenuated.

  The point (antinode) where the voltage amplitude of the standing wave of the 2-cell loop oscillation becomes large is generally separated, and the point (antinode) where the voltage amplitude of the standing wave of the 2-cell loop oscillation becomes large and the fourth oscillation on the input side. The bonding wires RW12 and the point (antinode) where the voltage amplitude of the standing wave of the two-cell loop oscillation becomes large and the output side fourth oscillation suppression resistor R22 are connected by bonding wires BW1 and BW2, respectively. BW1 and BW2 generate an input-side first inductor L12 and an output-side first inductor L22. Since these inductance components weaken the oscillation suppressing effect, they are not preferable.

  The point (antinode) where the voltage amplitude of the standing wave of 2-cell loop oscillation becomes large and the input side fourth oscillation suppression resistor R12, and the point (antinode) where the voltage amplitude of the standing wave of 2-cell loop oscillation becomes large and the output side first The four oscillation suppression resistors R22 are preferably connected by aerial wiring using bonding wires BW1 and BW2. This is because by using the aerial wiring with the bonding wires BW1 and BW2, it is possible to connect with a smaller inductance than the pattern wiring.

  By connecting the input-side first capacitor C12 in series to the input-side first inductor L12, the input-side first inductor is generated at a specific frequency due to series resonance including the input-side first capacitor C12 and the input-side first inductor L12. L12 can be canceled. The capacitance value C1 of the input-side first capacitor C12 is determined so that the specific frequency becomes the frequency of loop oscillation.

  Similarly, by connecting the output-side first capacitor C22 in series with the output-side first inductor L22, the output-side first capacitor C22 and the output-side first inductor L22 are connected to the output-side first capacitor C22 by a series resonance. One inductor L22 can be canceled. The capacitance value C2 of the output-side first capacitor C22 is determined so that the specific frequency becomes the frequency of the loop oscillation.

  Since the input-side second oscillation suppression resistor R11b and the input-side oscillation suppression circuit 2 are arranged in parallel in the 2-cell loop LP2, the substantial resistance value that suppresses the 2-cell loop oscillation is the input side of the input-side oscillation suppression circuit 2. It becomes smaller than the fourth oscillation suppression resistor R12. At this time, the length from the input-side second oscillation suppression resistor R11b to the input-side fourth oscillation suppression resistor R12 of the input-side oscillation suppression circuit 2 forms the path LPi as shown in FIG. The path LPi is provided by a part of the input matching circuit 16, the transmission line 17, a part of the transmission line 18, the input-side first inductor L12, and the input-side first capacitor C12. The two-cell loop oscillation frequency fosc2 Is determined so as to be approximately (2n-1) / 4 (n is an integer) of the wavelength of the input side second oscillation suppression resistor R11b viewed from the input side fourth oscillation suppression resistor R12, and impedance conversion is performed. At the oscillation frequency of the cell loop, the resistance value of the input-side second oscillation suppression resistor R11b becomes infinite, and only the input-side fourth oscillation suppression resistor R12 works effectively.

  Similarly, since the output-side second oscillation suppression resistor R21b and the output-side oscillation suppression circuit 4 are arranged in parallel in the 2-cell loop, the substantial resistance value that suppresses the 2-cell loop oscillation is that of the output-side oscillation suppression circuit 4. It becomes smaller than the output-side fourth oscillation suppression resistor R22. At this time, the length from the output-side second oscillation suppression resistor R21b to the output-side fourth oscillation suppression resistor R22 of the output-side oscillation suppression circuit 4 forms the path LPo as shown in FIG. The path LPo is provided by a part of the output matching circuit 26, the transmission line 27, a part of the transmission line 28, the output-side first inductor L22, and the output-side first capacitor C22, and at the 2-cell loop oscillation frequency fosc2. By determining the wavelength to be about (2n-1) / 4 (n is an integer), the output-side second oscillation suppression resistor R21b viewed from the output-side fourth oscillation suppression resistor R22 is impedance-converted, and a two-cell loop At the oscillation frequency, the resistance value of the output-side second oscillation suppression resistor R21b becomes infinite, and only the output-side fourth oscillation suppression resistor R22 works effectively.

(Semiconductor element structure)
An enlarged view of a schematic planar pattern configuration of the semiconductor device 24 mounted on the high-frequency circuit according to the embodiment is represented as shown in FIG. 6A, and an enlarged view of a portion J in FIG. It is expressed as shown in FIG. Moreover, it is the structural examples 1-4 of the semiconductor device 24 mounted in the high frequency circuit which concerns on embodiment, Comprising: The typical cross-section structural examples 1-4 along the II line | wire of FIG.6 (b) are respectively figures. 7 to 10 as shown in FIG.

  In the semiconductor device 24 mounted on the high-frequency circuit according to the embodiment, the plurality of FET cells FET1 to FET8 corresponding to the transistors Q1 to Q8 in FIG. 1 include a semi-insulating substrate 110 as shown in FIGS. And a gate finger electrode 124, a source finger electrode 120 and a drain finger electrode 122, each having a plurality of fingers, disposed on the first surface of the semi-insulating substrate 110, and disposed on the first surface of the semi-insulating substrate 110, A plurality of gate terminal electrodes G1, G2,..., G8 formed by bundling a plurality of fingers for each of the gate finger electrode 124, the source finger electrode 120 and the drain finger electrode 122, and a plurality of source terminal electrodes S11, S12, S21, S22. ,..., S81, S82 and drain terminal electrodes D1, D ,..., D8, VIA holes SC11, SC12, SC21, SC22,..., SC81, SC82 disposed below the source terminal electrodes S11, S12, S21, S22,. Are arranged on the second surface opposite to the first surface, and VIA holes SC11, SC12, SC21, SC22,..., SC81, SC82 are provided to the source terminal electrodes S11, S12, S21, S22,. And a ground electrode (not shown) connected to each other.

  A bonding wire is connected between the gate terminal electrodes G1, G2,..., G8 and the input matching circuit 16, and a bonding wire is connected between the drain terminal electrodes D1, D2,. Is connected. A barrier metal layer (not shown) formed on the inner walls of the VIA holes SC11, SC12, SC21, SC22,..., SC81, SC82, and a filled metal layer (not shown) formed on the barrier metal layer and filling the VIA holes. The source terminal electrodes S11, S12, S21, S22,..., S81, S82 are connected to a ground electrode (not shown).

  The semi-insulating substrate 110 is a GaAs substrate, a SiC substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on a SiC substrate, a substrate in which a heterojunction epitaxial layer made of GaN / AlGaN is formed on a SiC substrate, a sapphire substrate, or One of the diamond substrates.

(Structural example 1)
As shown in FIG. 7, the configuration example 1 of the FET cell of the semiconductor device 24 mounted on the package according to the embodiment includes a semi-insulating substrate 110 and a nitride compound disposed on the semi-insulating substrate 110. Semiconductor layer 112, aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118 disposed on nitride compound semiconductor layer 112, and aluminum gallium nitride layer (Al _x Ga) _1-x N) (0.1 ≦ x ≦ 1) 118, a source finger electrode (S) 120, a gate finger electrode (G) 124, and a drain finger electrode (D) 122. A two-dimensional electron gas (2DEG) layer is formed at the interface between the nitride-based compound semiconductor layer 112 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. 116 is formed. In the configuration example 1 illustrated in FIG. 7, the HEMT is illustrated.

(Structural example 2)
A configuration example 2 of the FET cell of the semiconductor device 24 mounted on the package according to the embodiment includes a semi-insulating substrate 110 and a nitride compound disposed on the semi-insulating substrate 110 as shown in FIG. On semiconductor layer 112, source region 126 and drain region 128 disposed on nitride compound semiconductor layer 112, source finger electrode (S) 120 disposed on source region 126, on nitride compound semiconductor layer 112 A gate finger electrode (G) 124 disposed on the drain region 128 and a drain finger electrode (D) 122 disposed on the drain region 128. A Schottky contact is formed at the interface between the nitride-based compound semiconductor layer 112 and the gate finger electrode (G) 124. In the configuration example 2 shown in FIG. 8, a metal-semiconductor field effect transistor (MESFET) is shown.

(Structural example 3)
A configuration example 3 of the FET cell of the semiconductor device 24 mounted on the package according to the embodiment includes a semi-insulating substrate 110 and a nitride-based compound disposed on the semi-insulating substrate 110 as shown in FIG. Semiconductor layer 112, aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118 disposed on nitride compound semiconductor layer 112, and aluminum gallium nitride layer (Al _x Ga) _1-x N) (0.1 ≦ x ≦ 1) 118 source finger electrode (S) 120 and drain finger electrode (D) 122, and aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118 and a gate finger electrode (G) 124 disposed in a recess portion. A 2DEG layer 116 is formed at the interface between the nitride-based compound semiconductor layer 112 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. In the configuration example 3 illustrated in FIG. 9, the HEMT is illustrated.

(Structural example 4)
As shown in FIG. 10, the configuration example 4 of the FET cell of the semiconductor device 24 mounted on the package according to the embodiment includes a semi-insulating substrate 110 and a nitride compound disposed on the semi-insulating substrate 110. Semiconductor layer 112, aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118 disposed on nitride compound semiconductor layer 112, and aluminum gallium nitride layer (Al _x Ga) _1-x N) (0.1 ≦ x ≦ 1) 118 source finger electrode (S) 120 and drain finger electrode (D) 122, and aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118 and a gate finger electrode 124 disposed in a two-stage recess portion. A 2DEG layer 116 is formed at the interface between the nitride-based compound semiconductor layer 112 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. In the configuration example 4 illustrated in FIG. 10, the HEMT is illustrated.

  Moreover, in the above configuration examples 1 to 4, the nitride-based compound semiconductor layer 112 other than the active region is used as an electrically inactive element isolation region. Here, the active region refers to the 2DEG layer 116 immediately below the source finger electrode 120, the gate finger electrode 124, and the drain finger electrode 122, between the source finger electrode 120 and the gate finger electrode 124, and between the drain finger electrode 122 and the gate finger electrode 124. 2 DEG layer 116.

As another method for forming the element isolation region, the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 and a part of the nitride-based compound semiconductor layer 112 in the depth direction are used. It can also be formed by ion implantation. As the ion species, for example, nitrogen (N), argon (Ar), or the like can be applied. The dose accompanying ion implantation is, for example, about 1 × 10 ¹⁴ (ions / cm ² ), and the acceleration energy is, for example, about 100 keV to 200 keV.

A passivation insulating layer (not shown) is formed on the element isolation region and the device surface. As this insulating layer, for example, a nitride film, an alumina (Al ₂ O ₃ ) film, an oxide film (SiO ₂ ), an oxynitride film (SiON) or the like deposited by PECVD (Plasma Enhanced Chemical Vapor Deposition) method is formed. be able to.

  The source finger electrode 120 and the drain finger electrode 122 are made of, for example, Ti / Al. The gate finger electrode 124 can be formed of, for example, Ni / Au.

  In the semiconductor device 24 mounted on the package according to the embodiment, the longitudinal pattern lengths of the gate finger electrode 124, the source finger electrode 120, and the drain finger electrode 122 are microwave / millimeter wave / submillimeter wave and the operating frequency. As the value increases, it is set shorter. For example, in the millimeter wave band, the pattern length is about 25 μm to 50 μm.

  Further, the width of the source finger electrode 120 is, for example, about 40 μm, and the width of the source terminal electrodes S11, S12, S21, S22,..., S101, S102 is, for example, about 100 μm. Further, the formation width of the VIA holes SC11, SC12, SC21, SC22,..., SC101, SC102 is, for example, about 10 μm to 40 μm.

  According to the high frequency circuit according to the embodiment, the distance between the oscillation suppression resistors is set to ¼ of the wavelength that oscillates in the large loop, so that the small loop with respect to the large loop resistance at the oscillation frequency. This resistance is not affected, and the expected oscillation suppression effect is obtained.

  In addition, according to the high frequency circuit according to the embodiment, the oscillation suppression resistor of the large loop is not connected to the line constituting the small loop, but connected to the line outside the loop, so that the oscillation occurring in the small loop is prevented. Is not affected by the oscillation suppression resistance of the large loop outside the loop, and the expected oscillation suppression effect is obtained.

  Further, according to the high-frequency circuit according to the embodiment, when an oscillation suppression resistor is connected to a larger loop, a capacitor is connected in series with the inductance of the line or wire, and the inductance and capacitance are included. By selecting the capacitance value of the capacitor so that the resonance frequency of the series resonance circuit is equal to the oscillation frequency, the oscillation suppression resistor and the line appear to be short-circuited at the oscillation frequency, so the expected oscillation suppression effect is obtained. It is done.

  According to the above embodiment, it is possible to provide a high frequency circuit capable of suppressing both of the three odd mode oscillations of the minimum loop oscillation frequency fosc, the 2-cell loop oscillation frequency fosc2, and the 4-cell loop oscillation frequency fosc3.

[Other embodiments]
Although several embodiments have been described, these embodiments have been presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  The discrete transistors applied to the high-frequency circuit according to the embodiment are not limited to FETs and HEMTs, but are LDMOS (Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistors) and heterojunction bipolar transistors (HBTs). An amplifying device such as a MEMS (Micro Electro Mechanical Systems) device can also be applied.

  As described above, various embodiments that are not described herein are included.

DESCRIPTION OF SYMBOLS 1 ... High frequency circuit 2 ... Input side oscillation suppression circuit 4 ... Output side oscillation suppression circuit 10 ... Semiconductor substrate 12 ... 1st insulating substrate 14 ... 2nd insulating substrate 16 ... Input matching circuit (MN-IN)
17, 18, 19, 28, 29 ... transmission line 24 ... semiconductor device 26 ... output matching circuit (MN-OUT)
110 ... Semi-insulating substrate 112 ... Nitride compound semiconductor layer (GaN epitaxial growth layer)
116: Two-dimensional electron gas (2DEG) layer 118: Aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1)
120 ... Source finger electrode 122 ... Drain finger electrode 124 ... Gate finger electrode 126 ... Source region 128 ... Drain region G, G1, G2, ..., G8 ... Gate terminal electrodes S, S11, S12, ..., S81, S82 ... Source terminals Electrodes D, D1, D2, ..., D8 ... Drain terminal electrodes SC11, SC12, ..., SC81, SC82 ... VIA holes Q1, Q2, ..., Q8 ... Transistor L12 ... Input side first inductor L13 ... Input side second inductor L22 ... output-side first inductor L23 ... output-side second inductor C12 ... input-side first capacitor C13 ... input-side second capacitor C22 ... output-side first capacitor C23 ... output-side second capacitor R11a ... input-side first oscillation suppression resistor R11b: input-side second oscillation suppression resistor R11c: input-side third oscillation suppression Anti-R21a ... Output side first oscillation suppression resistor R21b ... Output side second oscillation suppression resistor R21c ... Output side third oscillation suppression resistor R12 ... Input side fourth oscillation suppression resistor R22 ... Output side fourth oscillation suppression resistor R13 ... Input side Fifth oscillation suppression resistor R23... Output-side fifth oscillation suppression resistors LPi, LPo... Path LP1... Minimum loop LP2... 2 cell loop LP3 4 loop loop LP4 Loop including an oscillation suppression circuit L1 Inductance value of input first inductor L12 L2 ... Inductance value C1 of output side first inductor L22 ... Capacitance value C2 of input side first capacitor C12 ... Capacitance values S1i to S7i of output side first capacitor C22, S1o to S7o ... Node of loop
fosc1 ... Minimum loop oscillation frequency
fosc2 ... 2 cell loop oscillation frequency
fosc3: 4-cell loop oscillation frequency

Claims (12)

A plurality of transistors arranged in parallel on a semiconductor substrate;
A plurality of input matching circuits disposed on a first insulating substrate and respectively connected to gate terminal electrodes of the plurality of transistors;
An input-side fourth oscillation suppression resistor disposed on the first insulating substrate and adjacent to the input matching circuit; and an input-side first capacitor connected in series to the input-side fourth oscillation suppression resistor; And an input-side oscillation suppression circuit having a point on a transmission line connecting between the adjacent input matching circuits and an input-side first inductor connected between the input-side first capacitors, and the input-side first inductor And L1 and the capacitance value of the first input capacitor is C1, the first input inductor and the first input capacitor represented by 1 / {2π (L1 × C1) ^1/2 }. The high-frequency circuit is characterized in that the resonance frequency is equal to the oscillation frequency fosc2 of the two-cell loop. An input-side first oscillation suppression resistor disposed on the first insulating substrate and disposed between the adjacent input matching circuits;
An input-side second oscillation suppression resistor disposed between two cell loops constituted by a transmission line connecting between the adjacent input matching circuit and the adjacent input matching circuit;
2. The high frequency device according to claim 1, further comprising: an input-side third oscillation suppression resistor disposed between four cell loops configured by a transmission line that connects between the two adjacent cell loops and between the two adjacent cell loops. circuit.   3. The length from the input-side second oscillation suppression resistor to the input-side fourth oscillation suppression resistor is approximately equal to an odd multiple of 1/4 of the wavelength of the oscillation frequency fosc2 of the two-cell loop. The high-frequency circuit described. The high frequency circuit according to claim 1, wherein the first inductor on the input side is formed of a bonding wire. Wherein the input-side second oscillation suppressing resistor to the input-side fourth oscillation suppression resistor, according to claim 2, characterized in that formed in the first transmission line and a bonding wire which is disposed on an insulating substrate High frequency circuit. A plurality of output matching circuits disposed on a second insulating substrate and respectively connected to drain terminal electrodes of the plurality of transistors;
An output-side fourth oscillation suppression resistor disposed on the second insulating substrate and adjacent to the output matching circuit; an output-side first capacitor connected in series to the output-side fourth oscillation suppression resistor; An output-side oscillation suppression circuit having a point on a transmission line connecting the adjacent output matching circuits and an output-side first inductor connected between the output-side first capacitors, and the output-side first inductor The output side first inductor and the output side first capacitor represented by 1 / {2π (L2 × C2) ^1/2 }, where L2 is the inductance value of the output capacitor and C2 is the capacitance value of the output side first capacitor The high-frequency circuit according to claim 1, wherein the resonance frequency is equal to the oscillation frequency fosc2 of the two-cell loop. An output-side first oscillation suppression resistor disposed on the second insulating substrate and disposed between the adjacent output matching circuits;
An output-side second oscillation suppression resistor disposed between two cell loops constituted by a transmission line connecting between the adjacent output matching circuit and the adjacent output matching circuit;
The high frequency according to claim 6, further comprising: an output-side third oscillation suppression resistor disposed between the adjacent two cell loops and a four-cell loop formed by a transmission line connecting the adjacent two-cell loops. circuit.   8. The length from the output-side second oscillation suppression resistor to the output-side fourth oscillation suppression resistor is substantially equal to an odd multiple of 1/4 of the wavelength of the oscillation frequency fosc2 of the two-cell loop. The high-frequency circuit described. The high-frequency circuit according to claim 6, wherein the first inductor on the output side is formed of a bonding wire. Wherein the output-side second oscillation suppressing resistor to said output-side fourth oscillation suppression resistor, according to claim 7, characterized in that it is formed by the second transmission line and a bonding wire which is disposed on an insulating substrate High frequency circuit. The plurality of transistors are:
A semi-insulating substrate;
A gate finger electrode, a source finger electrode and a drain finger electrode disposed on the first surface of the semi-insulating substrate, each having a plurality of fingers;
A plurality of gate terminal electrodes arranged on the first surface of the semi-insulating substrate and formed by bundling a plurality of fingers for each of the gate finger electrode, the source finger electrode and the drain finger electrode; A drain terminal electrode;
A VIA hole disposed under the source terminal electrode;
2. A ground electrode disposed on a second surface opposite to the first surface of the semi-insulating substrate and connected to the source terminal electrode via the VIA hole. 11. The high frequency circuit according to any one of 10 above.   The semi-insulating substrate is a GaAs substrate, a SiC substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on a SiC substrate, a substrate in which a heterojunction epitaxial layer made of GaN / AlGaN is formed on a SiC substrate, a sapphire substrate, or The high-frequency circuit according to claim 11, wherein the high-frequency circuit is any one of a diamond substrate.