JP5547048B2 - Power amplifier bias circuit - Google Patents

Description

  Embodiments described herein relate generally to a power amplifier bias circuit.

  The bias circuit of the power amplifier is connected so that the bias circuit appears to be open at the connection point of the bias circuit, that is, the RF signal does not leak into the bias circuit so that the bias circuit does not affect the RF characteristics. .

  Specifically, they are connected via a microstrip line having a high impedance and a length of λ / 4 with respect to the RF frequency. By showing one of λ / 4 as a short circuit with respect to the ground, the other can be shown as open. In order to show a short circuit with respect to the ground, an open stub of λ / 4 length is arranged, or a capacitor of about 1 pF is arranged.

  In the bias circuit of the power amplifier, a plurality of capacitors are arranged in parallel to supply a stable voltage to the power amplifier at all frequencies. An actual capacitor has an inductance component in series with the capacitance component, and has a self-resonant frequency due to the capacitance component and the inductance component. When the frequency is lower than the self-resonance frequency, it is C-type (behaves as a capacitance), and at high frequency, it is L-type (behaves as an inductance). Appears. In order to avoid this, the capacitors in parallel with the 1 pF capacitor are connected via a microstrip line having a high impedance and a length of λ / 4 with respect to the RF frequency, and are composed of a series connection of 1000 pF and 50Ω. The circuit is arranged in parallel.

http://www.excelics.com/MFET%20APP%20NOTE.pdf: “Recommendations for the Handling, Mounting and Biasing of High Power GaAs FETs” Steven Sea Clips, “RF Power Amplifiers for Wireless Communications”, 11.3, Bias Supply Modulation Effects, Steven C. Cripps, “RF Power Amplifiers for Wireless Communications”, 11.3 Bias Supply Modulation Effects. ARTECH HOUSE

  If any impedance exists between the bias supply source and the output terminal of the amplifier, the voltage appearing at the output terminal of the amplifier is modulated, which adversely affects the characteristics of the amplifier. For example, reactance exists between the bias supply source and the output terminal of the amplifier according to the distance. For the RF signal, the bias circuit appears to be open at the connection point of the bias circuit, that is, since the RF signal is configured not to leak into the bias circuit, voltage modulation does not occur, but other frequency components (f) When this occurs, voltage modulation occurs. Specifically, when the distance between the bias supply source and the output terminal of the amplifier is about 50 mm, there is a reactance of about 50 nH, and when the alternating current of the frequency component (f) is I, the modulated voltage amplitude (ripple) Voltage) is 2πf × I.

  In the measurement of the third-order intermodulation distortion IM3 used as a method for evaluating the linearity of the amplifier, two signals having slightly different frequencies are input, but a frequency component of a difference between these frequencies is generated and flows into the bias circuit. Voltage modulation with that differential frequency occurs. Since high signal quality is required in the terrestrial communication network, the output power is measured when the third-order intermodulation distortion IM3 as an evaluation index is about −40 dBc, but the signal quality such as VSAT (Very Small Aperture Terminal) is used. In an application where the demand for is moderate, the output power is measured when the third-order intermodulation distortion IM3 which is the evaluation index is about −25 dBc. In the measurement at −25 dBc, since the output level is higher than that at −40 dBc, the current flowing between the bias supply source and the output terminal of the amplifier is also large, and the ripple voltage is large.

  In general, a power amplifier having a larger maximum output has a larger current, resulting in a larger ripple voltage.

  In order to suppress the ripple voltage, a bypass reservoir capacitor is connected in parallel to the output terminal of the power amplifier.

For example, when the difference frequency Δf is 5 MHz, in the case of a 6 GHz band 80 W class GaAs MESFET (for example, TIM 5964-80SL), the value of the current amplitude I _PK at the time of −25 dBc operation is about 3 A, and this charge amount is within a period of 5 MHz. , And the value of the bypass reservoir capacitor C _BR required to make the ripple voltage ΔV within 0.1V can be expressed as C _BR = Q / ΔV. Here, Q = I _PK ∫ (0 to T / 2) sin ωtdt = I _PK ∫ (0 to π / ω) sin ωtdt. Therefore, the value of Q is about 3 × (1 / 2πf) = 1 × 10 ⁻⁷ (C), and C _BR = 1 μF from the ripple voltage ΔV = 0.1 V.

In the configuration of the conventional example, a capacitor of 1 μF can be arranged in a capacitor outside the housing via a feed thru capacitor, but from the capacitor outside the housing to the output terminal of the power amplifier The distance between them is about 50 mm, there is a reactance of about 50 nH, and the voltage amplitude (ripple voltage) is ΔV = 2πf × L × I = 2π × 5 × 10 ⁶ × 50 × 10 ⁻⁹ × 3 , ΔV is about 4.7V. That is, there is a problem that the voltage actually appearing at the output terminal of the power amplifier has a ripple of about 4.7 V even though a voltage of 10 V is supplied.

  A chip capacitor of 1 μF has a series resistance (ESR) inside, and there is a problem that a ripple voltage is generated due to a voltage drop in the series resistance. This is because if the ESR is large, a short circuit cannot be made with respect to the ground.

  In order to make the microstrip line have a high impedance, for example, Zo = 120Ω, the line width is 0.15 mm on a substrate having a relative dielectric constant of 2.2 and a thickness of 0.254 mm. The current that can flow here is about 2 A. If the line width is 0.5 mm in order to flow about 6 A, the current drops to Zo = 66Ω, the RF signal easily leaks to the bias circuit, and the bias circuit adversely affects the RF characteristics. The problem arises. That is, Zo and allowable current are not compatible. For example, if the bias current is configured with Zo = 66Ω giving priority to the allowable current> 6 A, the RF characteristics are adversely affected.

The bias circuit for a power amplifier according to the present embodiment includes a first bonding wire connected to a bias circuit connection point of the output-side matching transmission line of the power amplifier, and a second bonding wire connected to the terminal end of the first bonding wire. An open stub transmission line connected to the end of the first bonding wire, and a bypass reservoir capacitor connected between a line connecting the end of the second bonding wire and the drain bias voltage supply terminal and the ground potential. The bypass reservoir capacitor is constituted by a parallel connection of a plurality of capacitors equal to or less than the value of the bypass reservoir capacitor .

The typical circuit block diagram of the bias circuit for power amplifiers which concerns on a comparative example. The typical circuit block diagram of the bias circuit for power amplifiers which concerns on embodiment. The plane block diagram of (lambda) / 4 length open stub. The Smith chart explaining operation | movement of (lambda) / 4 length open stub. The typical circuit block diagram of the bias circuit for power amplifiers which concerns on embodiment provided with the ideal capacitor Cid instead of (lambda) / 4 length open stub. An example of frequency characteristics of impedance ESR (Ω) of equivalent series resistance ESR. The frequency characteristic example of the insertion loss (dB) of a chip capacitor. (A) Equivalent circuit configuration of chip capacitor, (b) Frequency characteristic of insertion loss (dB) when considering the effect of equivalent series inductance ESL, (c) Insertion loss when considering the effect of equivalent series resistance ESR ( (dB) frequency characteristics, (d) frequency characteristics of insertion loss (dB) in consideration of the effects of equivalent series inductance ESL and equivalent series resistance ESR. (A) Parallel circuit of capacitor Ci1 and capacitor Ci2, (b) Parallel circuit of capacitor Ci1 and inductor Lr. In power amplifier for applying a bias circuit for a power amplifier according to the embodiment (FET), the simulation results showing the relationship between the ripple voltage ΔV and the bypass reservoir capacitor C _BR to parameters a current amplitude I _PK. In power amplifier for applying a bias circuit for a power amplifier according to the embodiment (FET), the simulation results showing the relationship between the ripple voltage ΔV and the bypass reservoir capacitor C _BR of the difference frequency f as a parameter. (A) The enlarged view of the typical plane pattern structure of the high frequency semiconductor chip to which the bias circuit for power amplifiers which concerns on embodiment is applied, (b) The enlarged view of J part of Fig.12 (a). FIG. 13 is a structural example 1 of the high-frequency semiconductor chip to which the power amplifier bias circuit according to the embodiment is applied, and is a schematic cross-sectional structure diagram taken along the line II of FIG. FIG. 13 is a structural example 2 of a high-frequency semiconductor chip to which the power amplifier bias circuit according to the embodiment is applied, and is a schematic cross-sectional structure diagram taken along the line II of FIG. FIG. 13 is a structural example 3 of a high-frequency semiconductor chip to which the power amplifier bias circuit according to the embodiment is applied, and is a schematic cross-sectional structure diagram taken along line II in FIG. FIG. 13 is a structural example 4 of a high-frequency semiconductor chip to which the power amplifier bias circuit according to the embodiment is applied, and is a schematic cross-sectional structure diagram taken along line II in FIG.

  Next, embodiments will be described with reference to the drawings. In the following, the same elements are denoted by the same reference numerals to avoid duplication of explanation and to simplify the explanation. It should be noted that the drawings are schematic and different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  The embodiment described below exemplifies an apparatus and a method for embodying the technical idea, and the embodiment does not specify the arrangement of each component as described below. This embodiment can be modified in various ways within the scope of the claims.

(Comparative example)
As shown in FIG. 1, the power amplifier bias circuit according to the comparative example is arranged on the input side of the power amplifier (FET) 10 and on the output side of the power amplifier (FET) 10. And a drain bias circuit 14a.

  A 50Ω transmission line Zo and a DC blocking chip capacitor C11 are connected between the gate input of the power amplifier (FET) 10 and the RF input terminal Pi, and between the drain output of the power amplifier (FET) 10 and the RF output terminal Po. Is connected to a 50Ω transmission line Zo and a DC blocking chip capacitor C12. Here, the value of the chip capacitors C11 and C12 is, for example, 10 / f (GHz) pF.

  Further, as shown in FIG. 1, the gate bias circuit 12a includes a high impedance λ / 4 long transmission line ZH connected to a bias circuit connection point Ni on the 50Ω transmission line Zo, and a high impedance λ / 4 long transmission line ZH. And a low impedance λ / 4 long open stub transmission line ZL connected to the terminal TN1.

  Further, as shown in FIG. 1, the gate bias circuit 12a includes a 50Ω chip resistor R1, an inductor L1, a 50Ω chip resistor R11, and chip capacitors C2, C32, R11 connected in series between the terminal TN1 and the gate bias voltage Vgs supply terminal. C31, a feedthrough capacitor C41, and a capacitor C51. Here, the chip capacitors C2, C32, and C31 are about 1000 pF, 1.0 pF, and 1.0 pF, respectively, and the feedthrough capacitor C41 and the capacitor C51 are about 1000 pF and 33 μF, respectively.

  Further, as shown in FIG. 1, the drain bias circuit 14a includes a high impedance λ / 4 long transmission line ZH connected to a bias circuit connection point No on the 50Ω transmission line Zo, and a high impedance λ / 4 long transmission line ZH. A low impedance λ / 4 long open stub transmission line ZL connected to the terminal TN1 and a high impedance λ / 4 long transmission line ZH connected to the terminal TN1.

  Further, as shown in FIG. 1, the drain bias circuit 14a includes a series circuit of a chip capacitor C22 and a 50Ω chip resistor R22 connected between the line connecting the terminal TN2 and the drain bias voltage Vds supply terminal and the ground potential. A chip capacitor C33, a feedthrough capacitor C42, and a series circuit of a capacitor C52 and a 50Ω chip resistor R12. Here, the chip capacitors C22 and C33 are about 1000 pF and 1.0 pF, respectively, and the feedthrough capacitor C42 and the capacitor C52 are about 1000 pF and 33 μF, respectively.

  The bias circuit of the power amplifier is connected so that the bias circuit appears to be open at the bias circuit connection points Ni and No so that the bias circuit does not affect the RF characteristics, that is, the RF signal does not leak into the bias circuit. ing.

  Specifically, they are connected via a microstrip line having a high impedance and a length of λ / 4 with respect to the RF frequency, that is, a high impedance λ / 4 long transmission line ZH. By showing one of the high-impedance λ / 4 long transmission lines ZH as a short circuit with respect to the ground, the other can be shown open. In order to show a short circuit with respect to the ground, a λ / 4 long open stub, that is, a low impedance λ / 4 long open stub transmission line ZL is provided.

  In the bias circuit of the power amplifier, a plurality of capacitors are arranged in parallel to supply a stable voltage to the power amplifier at all frequencies. An actual capacitor has an inductance component in series with the capacitance component, and has a self-resonant frequency due to the capacitance component and the inductance component. When the frequency is lower than the self-resonance frequency, it is C-type (behaves as a capacitance), and at high frequency, it is L-type (behaves as an inductance). Appears. In order to avoid this, a microstrip line having a high impedance and a length of λ / 4 with respect to the RF frequency between the capacitors parallel to the 1 pF chip capacitor C33, that is, a high impedance λ / 4 long transmission line ZH is used. A circuit comprising a series connection of a 1000 pF chip capacitor C22 and a 50Ω chip resistor R22 is arranged in parallel.

[First embodiment]
A schematic circuit configuration of the power amplifier bias circuit according to the embodiment is expressed as shown in FIG.

  As shown in FIG. 2, the power amplifier bias circuit according to the embodiment is arranged on the input side of the power amplifier (FET) 10 and on the output side of the power amplifier (FET) 10. And a drain bias circuit 14.

The power amplifier bias circuit according to the embodiment includes a first bonding wire BW2 connected to a bias circuit connection point No of the output-side matching transmission line Zo of the power amplifier (FET) 10, and a terminal 41 of the first bonding wire BW2. The second bonding wire BW1 connected to the terminal, the open stub transmission line ZL connected to the terminal 41 of the first bonding wire BW2, and the terminal 40 of the second bonding wire BW1 and the drain bias voltage Vds supply terminal are connected. And a bypass reservoir capacitor C _BR connected between the line and the ground potential.

Further, in the power amplifier bias circuit according to the embodiment, when the bypass reservoir capacitor value is C _BR , the current amplitude value is I _PK , the allowable ripple voltage value is ΔV, and the differential frequency value is Δf, the bypass The reservoir capacitor has a value of C _BR = I _PK × (1 / 2πΔf) / ΔV or more.

  Here, both the first bonding wire BW2 and the second bonding wire BW1 have a length of λ / 4.

  The open stub transmission line ZL has a length of λ / 4.

Further, the bypass reservoir capacitor C _BR is configured by a parallel connection of a plurality of capacitors equal to or less than the value of the bypass reservoir capacitor C _BR .

Further, the value of the bypass reservoir capacitor C _BR may be 1 μF or more, and the bypass reservoir capacitor C _BR may be configured by a parallel connection of a plurality of capacitors having a value of 1 μF or less.

  In the power amplifier bias circuit according to the embodiment, the ripple voltage ΔV is 0.1 V or less when the output power is measured when the third-order intermodulation distortion IM3 is about −25 dBc.

In the bias circuit for a power amplifier according to the embodiment, the bypass reservoir capacitor C _BR is configured by a parallel connection of a plurality of capacitors equal to or less than the value of the bypass reservoir capacitor C _BR , thereby effectively reducing the equivalent series resistance. ESR is reduced.

  A 50Ω transmission line Zo and a DC blocking chip capacitor C11 are connected between the gate input of the power amplifier (FET) 10 and the RF input terminal Pi, and between the drain output of the power amplifier (FET) 10 and the RF output terminal Po. Is connected to a 50Ω transmission line Zo and a DC blocking chip capacitor C12. Here, the value of the chip capacitors C11 and C12 is, for example, 10 / f (GHz) pF. For example, when using at 4 GHz, it becomes 2.5 pF. Here, the impedance Z = | 1 / ωC | is about 16Ω and does not become 50Ω.

  Further, as shown in FIG. 2, the gate bias circuit 12 includes a high impedance λ / 4 long transmission line ZH connected to a bias circuit connection point Ni on the 50Ω transmission line Zo and a high impedance λ / 4 long transmission line ZH. And a low impedance λ / 4 long open stub transmission line ZL connected to the terminal TN1. Here, the high impedance λ / 4 long transmission line ZH is a transmission line having a sufficiently high impedance with respect to the 50Ω transmission line Zo. The low impedance λ / 4 long open stub transmission line ZL is a transmission line having a sufficiently low impedance with respect to the 50Ω transmission line Zo.

  Further, as shown in FIG. 2, the gate bias circuit 12 includes a 50Ω chip resistor R1, an inductor L1, a 50Ω chip resistor R11, and chip capacitors C2, C32, R11 connected in series between the terminal TN1 and the gate bias voltage Vgs supply terminal. C31, a feedthrough capacitor C41, and a capacitor C51. Here, the chip capacitors C2, C32, and C31 are about 1000 pF, 1.0 pF, and 1.0 pF, respectively, and the feedthrough capacitor C41 and the capacitor C51 are about 1000 pF and 33 μF, respectively.

  Further, as shown in FIG. 2, the drain bias circuit 14 is connected to the λ / 4 long bonding wire BW2 connected to the bias circuit connection point No on the 50Ω transmission line Zo and the terminal 41 of the λ / 4 long bonding wire BW2. A low impedance λ / 4 long open stub transmission line ZL and a λ / 4 long bonding wire BW1 connected to the terminal end 41 are provided.

Further, as shown in FIG. 2, the drain bias circuit 14 includes a bypass reservoir capacitor C connected between a line connecting the terminal 40 of the λ / 4 long bonding wire BW1 and the drain bias voltage Vds supply terminal and the ground potential. _BR , a series circuit of a chip capacitor C22 and a 50Ω chip resistor R22, a chip capacitor C33, a feedthrough capacitor C42, and a series circuit of a capacitor C52 and a 50Ω chip resistor R12. Here, as shown in FIG. 2, the bypass reservoir capacitor C _BR is configured by, for example, four capacitors C6 having a capacitance value similar to that of C _BR connected in parallel. Further, the chip capacitors C22 and C33 are about 1000 pF and 1.0 pF, respectively, and the feedthrough capacitor C42 and the capacitor C52 are about 1000 pF and 33 μF, respectively.

  The bias circuit of the power amplifier is connected so that the bias circuit appears to be open at the bias circuit connection points Ni and No so that the bias circuit does not affect the RF characteristics, that is, the RF signal does not leak into the bias circuit. ing.

  Specifically, they are connected via a microstrip line having a high impedance and a length of λ / 4 with respect to the RF frequency, that is, a high impedance λ / 4 long transmission line ZH. By showing one of the high-impedance λ / 4 long transmission lines ZH as a short circuit with respect to the ground, the other can be shown open. In order to show a short circuit with respect to the ground, a λ / 4 long open stub, that is, a low impedance λ / 4 long open stub transmission line ZL is provided.

  The planar configuration of the λ / 4 long open stub is schematically represented as shown in FIG. 3, and the operation of the λ / 4 long open stub is represented on the Smith chart as shown in FIG. At the connection point IS on the signal line SL, a λ / 4 long open stub is connected and the terminal IO is opened, so that the position λ / 4 long from the terminal IO that is open (connection point IS). Is equivalent to short. Since the open end of the λ / 4 length stub is open, the connection point IS on the signal line becomes short as shown in FIG. 4 due to the phase rotation of λ / 4 length.

  In the bias circuit for a power amplifier according to the present embodiment, as shown in FIG. 2, a connection point 41 between the λ / 4 long open stub ZL and the λ / 4 long bonding wire BW2 and the λ / 4 long bonding wire BW1 is provided. Shows short to ground.

  Here, the inductance of the λ / 4 long bonding wire BW2 and the λ / 4 long bonding wire BW1 used in the power amplifier bias circuit according to the present embodiment is, for example, about 1 nH / mm. The length λ / 4 is the length in the air, and is, for example, about 12.5 mm at a frequency of 6 GHz. The diameter is, for example, about 1 mmφ. Moreover, a tin plating copper wire can be applied as a material, for example. The current value that can be conducted is, for example, about 5 A.

  A schematic circuit configuration of the bias circuit for a power amplifier according to the embodiment including an ideal capacitor Cid instead of the λ / 4 long open stub is expressed as shown in FIG.

As shown in FIG. 5, the power amplifier bias circuit according to the embodiment includes a first bonding wire BW2 connected to a bias circuit connection point No of the output-side matching transmission line Zo of the power amplifier (FET) 10, and a first bonding wire BW2. A second bonding wire BW1 connected to the terminal 41 of the first bonding wire BW2, an ideal capacitor Cid connected between the terminal 41 of the first bonding wire BW2 and the ground potential, and a terminal 40 of the second bonding wire BW1. and a drain bias voltage bypass reservoir and line which connects the inter-Vds supply terminals connected between the ground potential capacitor C _BR. Here, the ideal capacitor Cid is a pure capacitor having no equivalent series resistance ESR and equivalent series inductance ESL.

  In order to make a short circuit with respect to the ground, an ideal capacitor Cid is disposed instead of the λ / 4 long open stub ZL. Here, an ideal value of the capacitor Cid is, for example, about 1 pF. This is because by arranging an ideal capacitor Cid instead of the λ / 4 long open stub ZL, the connection point 41 of the capacitor Cid becomes short-circuited with respect to the ground potential in terms of high frequency. Other configurations are the same as those of the embodiment shown in FIG.

  In the bias circuit of the power amplifier, a plurality of capacitors are arranged in parallel to supply a stable voltage to the power amplifier at all frequencies. An actual capacitor has an inductance component in series with the capacitance component, and has a self-resonant frequency due to the capacitance component and the inductance component.

  An example of frequency characteristics of impedance / equivalent series resistance ESR (Ω) of a capacitor having capacitance values of 1000 pF, 100 pF, 10 pF, and 1 pF is expressed as shown in FIG. As shown in FIG. 6, the frequency characteristics of impedance / ESR (Ω) vary greatly depending on the capacitance value of the capacitor. This is because each capacitor has a different self-resonant frequency. For this reason, in order to obtain a low impedance in a wide frequency range, it is necessary to arrange a plurality of capacitors having different capacitance values in parallel.

  An example of frequency characteristics of the insertion loss (dB) of the chip capacitor is expressed as shown in FIG. In FIG. 7, an ideal capacitor having a capacitance value of 1000 pF has a frequency characteristic of a curve indicated by Ci, whereas an actual capacitor having a capacitance value of 1000 pF has a frequency characteristic of a curve indicated by Cr. The curve indicated by Cr has a C property that behaves as a capacitance at a frequency lower than the self-resonance frequency, but has an L property that behaves as an inductance at a frequency higher than the self-resonance frequency.

  The equivalent circuit configuration of the chip capacitor is expressed as shown in FIG. 8A, and the frequency characteristic of the insertion loss (dB) when the influence of the equivalent series inductance ESL is taken into consideration is as shown in FIG. 8B. The frequency characteristics of the insertion loss (dB) in the case where the influence of the equivalent series resistance ESR is taken into consideration is expressed as shown in FIG. 8C, and the influence of the equivalent series inductance ESL and the equivalent series resistance ESR is taken into consideration. In this case, the frequency characteristic of the insertion loss (dB) is expressed as shown in FIG.

  Since it has C characteristics at a frequency lower than the self-resonant frequency and L characteristics at a high frequency, when capacitors having different capacitance values are arranged in parallel, a frequency that appears to be open due to resonance occurs between the self-resonant frequencies. . Here, the state where the impedance decreases as the frequency increases is expressed as C-type, and the state where the impedance increases as the frequency increases is expressed as L-type.

  The parallel circuit of the capacitor Ci1 and the capacitor Ci2 in the ideal state is expressed as shown in FIG. Here, the capacitance value of the capacitor Ci1 is 1 pF, for example, and the capacitance value of the capacitor Ci2 is 1000 pF, for example. A parallel circuit of the capacitor Ci1 and the inductor Lr in the actual state is expressed as shown in FIG.

  When a 1 pF capacitor Ci1 and a 1000 pF capacitor Ci2 are to be arranged in parallel, the 1 pF capacitor Ci1 has a C property in the actual state, but the 1000 pF capacitor Ci2 has an L property, that is, an inductor Lr. For example, parallel resonance of the inductor Lr and the capacitor Ci1 occurs near f = 4 GHz in the vicinity of the region surrounded by A in FIG. 6, and the capacitor is substantially open, that is, no capacitor is present.

To avoid this, in the bias circuit for a power amplifier according to the present embodiment, as shown in FIG. 2, the bypass reservoir capacitor C _BR inter has RF frequency length at a high impedance in parallel with the chip capacitor C33 of 1pF Λ / 4 long bonding wire BW1 and λ / 4 long bonding wire BW2 having a length of λ / 4 are connected to each other, and a λ / 4 long open stub ZL is connected to the connection point 41 and connected. Point 41 is shown shorted to ground. Further, a circuit composed of a series connection of a 1000 pF chip capacitor C22 and a 50Ω chip resistor R22 is arranged in parallel at the connection point 40.

  In the power amplifier bias circuit according to the present embodiment, as shown in FIG. 2, instead of the two-stage λ / 4 long microstrip lines ZH and ZH, λ / 4 long bonding wires BW1 and λ / 4 long bonding are used. By configuring with the wire BW2, high impedance and high current capacity can be obtained. When the allowable current> 6A is constituted by a microstrip line, Zo = 66Ω, whereas Zo = 220Ω, which is constituted by the λ / 4 long bonding wire BW1 and the λ / 4 long bonding wire BW2, is obtained.

  In measuring the third-order intermodulation distortion IM3, when two frequencies are input to one power amplifier (FET) 10, a differential frequency component is generated. Here, the third-order intermodulation distortion IM3 is caused by the nonlinearity of the device when two input signals (frequency f1, f2; f1-f2 = several tens MHz) having substantially the same frequency are supplied to the power amplifier (FET) 10. Signals having frequencies (2f2-f1) and (2f1-f2) are output, and the signal level is expressed as a ratio to the signal level of the fundamental wave (f1 or f2).

  In the basic third-order intermodulation distortion IM3 measurement method, two fundamental wave signals are mixed and used as an input signal to the power amplifier (FET) 10. Third-order intermodulation distortion IM3 caused by the power amplifier (FET) 10 is measured by a spectrum analyzer.

In the power amplifier (FET) to which the bias circuit for the power amplifier according to the embodiment is applied, the simulation result showing the relationship between the ripple voltage ΔV having the current amplitude I _PK as a parameter and the bypass reservoir capacitor (smoothing capacitor) C _BR is , As shown in FIG. FIG. 10 is an example of the difference frequency Δf = 5 MHz.

As shown in FIG. 10, for example, in order to suppress the ripple voltage ΔV to 0.1 V or less, when the difference frequency Δf = 50 MHz and the current amplitude I _PK = 0.3 A, the bypass reservoir capacitor C _BR = 0.1 μF or more When the difference frequency Δf = 50 MHz and the current amplitude I _PK = 1.0 A, the bypass reservoir capacitor C _BR = 0.3 μF or more, and when the difference frequency Δf = 50 MHz and the current amplitude I _PK = 3.0 A, the bypass reservoir capacitor C A value of _BR = 1.0 μF or more is required.

Further, in the power amplifier (FET) to which the power amplifier bias circuit according to the embodiment is applied, a simulation result showing a relationship between the ripple voltage ΔV using the difference frequency Δf as a parameter and the bypass reservoir capacitor (smoothing capacitor) C _BR Is expressed as shown in FIG.

As shown in FIG. 11, for example, in order to suppress the ripple voltage ΔV to 0.1 V or less, when the current amplitude I _PK = 3 A and the difference frequency Δf = 1 MHz, the bypass reservoir capacitor C _BR = 5 μF or more and the current amplitude I _{When PK} = 3A · differential frequency Δf = 5 MHz, bypass reservoir capacitor C _BR = 1 μF or more When current amplitude I _PK = 3A · differential frequency Δf = 50 MHz, bypass reservoir capacitor C _BR = 0.1 μF or more is required It becomes.

(Configuration of high-frequency semiconductor chip)
An enlarged view of a schematic planar pattern configuration of the high-frequency semiconductor chip 24 of the power amplifier to which the power amplifier bias circuit according to the embodiment is applied is expressed as shown in FIG. An enlarged view of the portion is expressed as shown in FIG. Further, structural examples 1 to 4 of the high-frequency semiconductor chip 24 to which the power amplifier bias circuit according to the embodiment is applied, and schematic cross-sectional structural examples 1 to 4 taken along the line I-I in FIG. These are expressed as shown in FIGS.

  In the high-frequency semiconductor chip 24 of the power amplifier to which the power amplifier bias circuit according to the embodiment is applied, the plurality of FET cells FET1 to FET10 are semi-insulated with the semi-insulating substrate 110 as shown in FIGS. A gate finger electrode 124, a source finger electrode 120 and a drain finger electrode 122, each of which is disposed on the first surface of the conductive substrate 110 and having a plurality of fingers, and a gate finger electrode 124 disposed on the first surface of the semi-insulating substrate 110. , G10, a plurality of source terminal electrodes S11, S12, S21, S22,..., S101 formed by bundling a plurality of fingers for each of the source finger electrode 120 and the drain finger electrode 122. , S102 and the drain terminal electrode D1 , D10, VIA holes SC11, SC12, SC21, SC22,..., SC101, SC102 disposed below the source terminal electrodes S11, S12, S21, S22,. 110 is disposed on the second surface opposite to the first surface, and VIA holes SC11, SC12, SC21, SC22,..., SC101, SC102 with respect to the source terminal electrodes S11, S12, S21, S22,. And a ground electrode (not shown) connected to each other.

  A bonding wire is connected to the gate terminal electrodes G1, G2,..., G10, and a bonding wire is connected to the drain terminal electrodes D1, D2,.

  Barrier metal layers (not shown) formed on the inner walls of the VIA holes SC11, SC12, SC21, SC22,..., SC101, SC102, and a filled metal layer (not shown) formed on the barrier metal layers and filling the VIA holes. The source terminal electrodes S11, S12, S21, S22,..., S101, S102 are connected to the ground electrode.

  The semi-insulating substrate 110 is a GaAs substrate, a SiC substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on a SiC substrate, a substrate in which a heterojunction epitaxial layer made of GaN / AlGaN is formed on a SiC substrate, a sapphire substrate, or One of the diamond substrates.

―Structure Example 1―
As a schematic cross-sectional configuration along the line II in FIG. 12B, the structure example 1 of the FET cell of the high-frequency semiconductor chip 24 of the power amplifier to which the power amplifier bias circuit according to the embodiment is applied is shown in FIG. As shown, a semi-insulating substrate 110, a nitride compound semiconductor layer 112 disposed on the semi-insulating substrate 110, and an aluminum gallium nitride layer (Al _x Ga) disposed on the nitride compound semiconductor layer 112. _1-x N) (0.1 ≦ x ≦ 1) 118 and a source finger electrode 120 disposed on the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118, A gate finger electrode 124 and a drain finger electrode 122 are provided. A two-dimensional electron gas (2DEG) layer is formed at the interface between the nitride-based compound semiconductor layer 112 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. 116 is formed. In Structural Example 1 shown in FIG. 13, a heterojunction field effect transistor (HFET) or a high electron mobility transistor (HEMT) is shown.

-Structural example 2-
As a schematic cross-sectional configuration along the line II in FIG. 12B, a structure example 2 of the FET cell of the high-frequency semiconductor chip 24 of the power amplifier to which the power amplifier bias circuit according to the embodiment is applied is shown in FIG. As shown, a semi-insulating substrate 110, a nitride compound semiconductor layer 112 disposed on the semi-insulating substrate 110, a source region 126 and a drain region 128 disposed on the nitride compound semiconductor layer 112, A source finger electrode 120 disposed on the source region 126, a gate finger electrode 124 disposed on the nitride-based compound semiconductor layer 112, and a drain finger electrode 122 disposed on the drain region 128. A Schottky contact is formed at the interface between the nitride-based compound semiconductor layer 112 and the gate finger electrode 124. In Structural Example 2 shown in FIG. 14, a metal-semiconductor field effect transistor (MESFET) is shown.

―Structure Example 3―
As a schematic cross-sectional configuration taken along line II in FIG. 12B, the structure example 3 of the FET cell of the high-frequency semiconductor chip 24 to which the power amplifier bias circuit according to the embodiment is applied is as shown in FIG. A semi-insulating substrate 110, a nitride compound semiconductor layer 112 disposed on the semi-insulating substrate 110, and an aluminum gallium nitride layer (Al _x Ga _1-x disposed on the nitride compound semiconductor layer 112) N) (0.1 ≦ x ≦ 1) 118 and source finger electrode 120 and drain finger electrode disposed on aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118 122 and a gate finger electrode 124 disposed in a recess portion on an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. A 2DEG layer 116 is formed at the interface between the nitride-based compound semiconductor layer 112 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. In Structural Example 3 shown in FIG. 15, an HFET or HEMT is shown.

-Structural example 4-
As a schematic cross-sectional configuration along the line II in FIG. 12B, the structure example 4 of the FET cell of the high-frequency semiconductor chip 24 to which the bias circuit for a power amplifier according to the embodiment is applied is as shown in FIG. A semi-insulating substrate 110, a nitride compound semiconductor layer 112 disposed on the semi-insulating substrate 110, and an aluminum gallium nitride layer (Al _x Ga _1-x disposed on the nitride compound semiconductor layer 112) N) (0.1 ≦ x ≦ 1) 118 and source finger electrode 120 and drain finger electrode disposed on aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118 122 and a gate finger electrode 124 disposed in a two-stage recess portion on an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. A 2DEG layer 116 is formed at the interface between the nitride-based compound semiconductor layer 112 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. In Structural Example 4 shown in FIG. 16, an HFET or HEMT is shown.

  In Structural Examples 1 to 4, the nitride-based compound semiconductor layer 112 other than the active region is used as an electrically inactive element isolation region. Here, the active region refers to the 2DEG layer 116 immediately below the source finger electrode 120, the gate finger electrode 124, and the drain finger electrode 122, between the source finger electrode 120 and the gate finger electrode 124, and between the drain finger electrode 122 and the gate finger electrode 124. 2 DEG layer 116. In the structural examples 1 to 4, the nitride compound semiconductor layer 112 other than the active region is used as an electrically inactive element isolation region.

As another method for forming the element isolation region, the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 and a part of the nitride-based compound semiconductor layer 112 in the depth direction are used. It can also be formed by ion implantation. As the ion species, for example, nitrogen (N), argon (Ar), or the like can be applied. The dose accompanying ion implantation is, for example, about 1 × 10 ¹⁴ (ions / cm ² ), and the acceleration energy is, for example, about 100 keV to 200 keV.

A passivation insulating layer (not shown) is formed on the element isolation region and the device surface. As this insulating layer, for example, a nitride film, an alumina (Al ₂ O ₃ ) film, an oxide film (SiO ₂ ), an oxynitride film (SiON) or the like deposited by PECVD (Plasma Enhanced Chemical Vapor Deposition) method is formed. be able to.

  The source finger electrode 120 and the drain finger electrode 122 are made of, for example, Ti / Al. The gate finger electrode 124 can be formed of, for example, Ni / Au.

  In the high-frequency semiconductor chip 24 to which the power amplifier bias circuit according to the embodiment is applied, the longitudinal pattern lengths of the gate finger electrode 124, the source finger electrode 120, and the drain finger electrode 122 are microwave / millimeter wave / submillimeter. As the wave and operating frequency increase, it is set shorter. For example, in the millimeter wave band, the pattern length is about 25 μm to 50 μm.

  Further, the width of the source finger electrode 120 is, for example, about 40 μm, and the width of the source terminal electrodes S11, S12, S21, S22,..., S101, S102 is, for example, about 100 μm. Further, the formation width of the VIA holes SC11, SC12, SC21, SC22,..., SC101, SC102 is, for example, about 10 μm to 40 μm.

  According to the present embodiment, it is possible to provide a power amplifier bias circuit having a small ripple voltage even when measuring output power with a third-order intermodulation distortion IM3 of about −25 dBc in a power amplifier having a large maximum output. .

  A high impedance and a high current capacity can be obtained by using a bondy wire instead of the two-stage λ / 4 long microstrip line.

Connect the bias circuit and the RF signal line lambda / 4 length bonding wires BW1 and BW2 of the second stage, arranged 1μF approximately bypass reservoir capacitor C _BR to the bias circuit side, the bypass reservoir capacitor C _BR of 1μF about A plurality of capacitors of about 1 μF or less are connected in parallel. Since the distance from the 1μF approximately bypass reservoir capacitor C _BR to the drain output terminal of the power amplifier is connected by two-stage lambda / 4 length bonding wires BW1 and BW2, its length becomes approximately 12 mm, the reactance component It is reduced to about 12 nH.

According to the power amplifier bias circuit according to the present embodiment, reduce the 1μF approximately bypass reservoir capacitor C _BR, by constituting a parallel connection of 1μF following plurality of capacitors, effectively series resistance (ESR) Is done.

  According to the present embodiment, it is possible to provide a power amplifier bias circuit applicable to a high-output power amplifier.

  According to the present embodiment, even when the differential frequency Δf is several hundreds of MHz, the ripple voltage ΔV of the power amplifier bias circuit is suppressed and the bias circuit voltage is smoothed, and the microwave / millimeter wave / submillimeter wave band has a high frequency. An applicable power amplifier bias circuit can be provided.

[Other embodiments]
Although the embodiment has been described, this embodiment is presented as an example and is not intended to limit the scope of the invention. The novel embodiment can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. This embodiment and its modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  Note that the high-frequency semiconductor chip mounted on the semiconductor device according to the embodiment is not limited to the FET and the HEMT, but is also an LDMOS (Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistor) or a heterojunction bipolar transistor (HBT). Needless to say, amplifying elements such as bipolar transistors and MEMS (Micro Electro Mechanical Systems) elements are also applicable.

  As described above, various embodiments that are not described herein are included.

10 ... Power amplifier (FET)
DESCRIPTION OF SYMBOLS 12, 12a ... Gate bias circuit 14, 14a ... Drain bias circuit 24 ... High frequency semiconductor chip 40, 41, TN1, TN2 ... Termination 110 ... Semi-insulating substrate 112 ... Nitride compound semiconductor layer (GaN epitaxial growth layer)
116: Two-dimensional electron gas (2DEG) layer 118: Aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1)
DESCRIPTION OF SYMBOLS 120 ... Source finger electrode 122 ... Drain finger electrode 124 ... Gate finger electrode 126 ... Source region 128 ... Drain region G, G1, G2, ..., G10 ... Gate terminal electrode S, S11, S12, ..., S101, S102 ... Source terminal electrode D, D1, D2, ..., D10 ... drain terminal electrode SC11, SC12, ..., SC91, SC92, SC101, SC102 ... VIA holes C _BR ... bypass reservoir capacitor Cid ... ideal capacitor I _PK ... current amplitude [Delta] V ... ripple Voltage Δf ... Differential frequency BW1, BW2 ... Bonding wire Pi ... RF input terminal Po ... RF output terminal Zo ... 50Ω transmission line ZH ... High impedance λ / 4 long transmission line ZL ... Low impedance λ / 4 long open stub transmission line C11, C12 ... 10 / f (GHz) p Chip capacitors C2, C22, C31, C32, C33 ... Chip capacitors C41, C42 ... Feed-through capacitors C51, C52 ... Capacitor L1 ... Inductors R1, R11, R12, R22 ... Chip resistors Vgs ... Gate bias voltage Vds ... Drain bias voltage N1 , N2: Bias circuit connection point

Claims (4)

A first bonding wire connected to a bias circuit connection point of the output-side matching transmission line of the power amplifier;
A second bonding wire connected to the end of the first bonding wire;
An open stub transmission line connected to an end of the first bonding wire;
A bypass reservoir capacitor connected between a line connecting the end of the second bonding wire and the drain bias voltage supply terminal and a ground potential;
The bias circuit for a power amplifier, wherein the bypass reservoir capacitor is configured by parallel connection of a plurality of capacitors equal to or less than the value of the bypass reservoir capacitor. A first bonding wire connected to a bias circuit connection point of the output-side matching transmission line of the power amplifier;
A second bonding wire connected to the end of the first bonding wire;
An ideal capacitor connected between the end of the first bonding wire and a ground potential;
A bias circuit for a power amplifier, comprising: a line connecting a terminal of the second bonding wire and a drain bias voltage supply terminal; and a bypass reservoir capacitor connected between a ground potential. When the bypass reservoir capacitor value is C _BR , the current amplitude value is I _PK , the allowable ripple voltage value is ΔV, and the differential frequency value is Δf, the bypass reservoir capacitor has C _BR = I _PK × (1 The bias circuit for a power amplifier according to claim 1, wherein the bias circuit has a value equal to or greater than / 2πΔf) / ΔV.   4. The power amplifier bias circuit according to claim 1, wherein each of the first bonding wire and the second bonding wire has a length of λ / 4. 5.