JP5484388B2 - Network equipment - Google Patents

Description

  The present invention relates to a network device, and more particularly to a network device used in a network synchronization network and having a 1000BASE-T interface port.

  In recent years, in the field of wide area networks, the application of packet-based technology such as Ethernet (registered trademark) with low cost and high accommodation efficiency has become mainstream from line-based technology such as SDH. Among them, there is an increasing need for legacy carriers to accommodate existing SDH synchronization lines in the Ethernet network. At that time, it is important to construct a synchronous distribution system for synchronization on Ethernet. It has become.

  As for synchronous delivery of a packet network, there is a method of Synchronous Ethernet (registered trademark) that performs clock delivery via an Ethernet port, and is defined in Non-Patent Document 1. The clock on the network side device is extracted by the device on the user side and subjected to slave synchronization, and further developed to a downstream device. At this time, there is an ESMC (Ethernet Synchronization Messaging Channel) as an interface for transmitting the quality of the distribution clock, and packet data storing an SSM (Synchronization Status Message) code indicating the quality of the clock is transmitted from the network side device via the main signal port. Send to user side device. This protocol is defined in Non-Patent Document 2.

  In addition, there is a time synchronization protocol defined by IEEE 1588, Precise Timing Protocol (hereinafter referred to as PTP). The device synchronized with the master clock transmits packet data called PTP Message to the subordinate device via the main signal port, and the subordinate side corrects the time difference by using the packet data as a trigger.

  As described above, in both cases of Synchronous Ethernet and PTP, the user-side device is usually configured to be subordinately synchronized with the clock of the network-side device, and the master-slave relationship is established by the protocol for packet transmission.

  Incidentally, Non-Patent Document 3 defines the operation of a 1000BASE-T physical layer device (hereinafter referred to as PHY), which is one of Ethernet interfaces. When connecting between devices with an electrical Ethernet port, devices that support Gigabit Ethernet typically have a link speed, half-duplex / full-duplex through an auto-negotiation process between each other's PHYs when linking. To decide. Further, when linking up with 1000BASE-T, the role of MASTER / SLAVE of both PHYs is also determined during auto-negotiation. The PHY of one device becomes MASTER and uses the local clock of the device as the data transmission timing, and the PHY of the other device becomes SLAVE and recovers the clock from the received data and uses it as the transmission timing. It is defined that both downstream communications are synchronized. Which device becomes MASTER / SLAVE is determined by comparing the port settings stored in the internal memory (register) by each PHY in the auto-negotiation process. The correspondence between the register setting and the MASTER / SLAVE relationship follows FIG.

From the above, when the connection with the 1000BASE-T interface is on the synchronous Ethernet network, it is necessary to match the MASTER / SLAVE relationship of both PHYs with the sending / receiving side of synchronous delivery. That is, unless the network-side device PHY is “MASTER” and the user-side device PHY is “SLAVE”, the clock cannot be transferred from the network side to the user side. Therefore, it is necessary to set the PHY port so that the desired master-slave relationship is obtained.
Paragraph No. 0036 of Patent Document 1 discloses an example of the concept regarding PHY MASTER / SLAVE setting at the time of clock distribution.

ITU-T G.8261 ITU-T G.8264 IEEE 802.3, paragraph 40

Japanese translation of PCT publication 2010-52481

  In the 1000BASE-T interface on synchronous Ethernet, in order to determine the clock distribution route, it is possible to store the manual_MASTER in the upstream PHY register and the manual_SLAVE setting in the downstream PHY register, and perform auto-negotiation. In addition, a desired MASTER / SLAVE relationship can be realized.

  However, if this device is used in common on a network that is not synchronous Ethernet, it is uncertain how the PHY setting of the connection destination device is, so if the manual setting is stored in the register from the beginning. If this happens, it will not be possible to link up if it is necessary to connect to a device with the same manual setting (manual MASTER and manual MASTER).

  Also, as disclosed in Patent Document 1, when the clock distribution is dynamically determined and the PHY master / slave relationship is assigned, even if the synchronous master / slave relationship originally matches the PHY master / slave relationship, Reassigning the PHY master / slave relationship again causes unnecessary link disconnection.

  When starting up the device, the 1000BASE-T port PHY is set to multiport device, and it is set to an initial setting that can be linked up regardless of the PHY setting of the connection destination device, and then ESMC or PTP Message is sent from the connection destination device. Only when it receives the message, it recognizes that the network to which it belongs is synchronous Ethernet. The received ESMC or PTP Message is analyzed, and the received port having the highest clock quality is determined. In order to extract a clock from this port and send it to another port, a setting is made to 1000BASE-T PHY. If the MASTER MASTER / SLAVE state has already been adapted, the state is maintained without changing the setting, and the PHY register is set to “manual_SLAVE” on the receiving side and “manual_MASTER” on the sending side only when the state does not match. Change the setting and restart the auto-negotiation to determine the clock distribution route.

  When using a 1000BASE-T interface in a synchronous Ethernet network, it is possible to reliably determine a clock transmission path without causing unnecessary link disconnection, and even when used in a network other than a synchronous Ethernet, a connection destination device You can link up reliably regardless of the setting.

It is a block diagram explaining the structure of a network. It is a figure explaining the SSM code stored in ESMC. It is a block diagram explaining the clock transmission of 1000BASE-T. It is a figure explaining the correspondence of the PHY device setting of a LOCAL / REMOTE apparatus and MASTER / SLAVE. It is a block diagram of a network device. It is the 1st part of the flowchart explaining operation | movement of a network apparatus and PHY. It is the 2nd part of the flowchart explaining operation | movement of a network apparatus and PHY. It is a 3rd part of the flowchart explaining operation | movement of a network apparatus and PHY. It is a figure explaining how the state of both PHYs changes with respect to each case of REMOTE apparatus PHY setting, when a LOCAL apparatus should become a clock receiving port. When a LOCAL apparatus should become a clock transmission port, it is a figure explaining how the state of both PHY changes with respect to each case of REMOTE apparatus PHY setting. It is a block diagram of a network device. It is the 1st part of the flowchart explaining operation | movement of a network apparatus and PHY. It is the 2nd part of the flowchart explaining operation | movement of a network apparatus and PHY. It is a 3rd part of the flowchart explaining operation | movement of a network apparatus and PHY. It is the 4th part of the flowchart explaining operation | movement of a network apparatus and PHY. It is a block diagram explaining the structure of a network. It is a block diagram explaining a network synchronization malfunction. It is a block diagram explaining the structure of a network. It is a block diagram explaining a network failure.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings using examples. The same reference numerals are assigned to substantially the same parts, and the description will not be repeated.

  The configuration of the network configuration will be described with reference to FIG. In FIG. 1, an access network system 100 includes an OLT 25, an optical splitter 27, an ONT 28, a T1-Ether converter 30, and a PRC (Primary Reference Clock) 26. The OLT 25 is connected to the WAN 24. The OLT 25 and the splitter 27 are connected by a trunk fiber. The splitter 27 and the ONT 28 are connected by a branch line fiber. The ONT 28 and the T1-Ether converter 30 are electrically connected. The ONT 28 transmits an ESMC frame 29 to the T1-Ether converter 30.

  The T1-Ether converter 30 accommodates the T1 line in the Ethernet and performs communication with the opposite T1 device via the WAN. In order to perform communication using a line of a synchronous format such as T1, it is necessary to perform a synchronous operation between opposite terminals, so synchronous Ethernet is applied. In FIG. 1, the OLT 25 receives the clock from the PRC 26. The OLT 25 distributes the received clock to the ONT 28 and the T1-Ether converter 30 via the communication port using synchronous Ethernet. Even if it is placed in the opposite device, the synchronous operation is performed by receiving the clock from the same source PRC via the synchronous Ethernet, so that the synchronous operation is possible between the opposite terminals. In normal clock distribution, distribution is performed in a downstream direction from the host network apparatus that receives the PRC toward the user side apparatus.

  ESMC is defined as an interface for notifying the quality of a clock to be distributed when a clock is distributed from an upstream device to a downstream device. ESMC is packet data transmitted from the upstream device toward the downstream device through the main signal port. The ESMC stores an SSM code indicating the clock quality. By receiving the ESMC, the device recognizes that it is in the synchronous Ethernet network and that the received port is connected to the upstream device. The receiving apparatus further recognizes the quality of the reception clock by analyzing the SSM code, and determines whether or not it can be transmitted downstream in synchronization with this clock.

  The SSM code will be described with reference to FIG. FIG. 781 5.5.2. 2, PRC has the highest quality level, SSU (Synchronization Supply Unit) _A, SSU_B, SEC (Synchronous Equipment Clock), and finally DNU (Do Not Use) having the lowest quality.

  PRC is a primary reference clock equivalent level, SSU is a synchronization supply unit level, SEC is a device clock level, and DNU is a level that cannot be used for synchronization.

  The quality level is expressed by a 4-bit field in the ESMC, where 0010 is the PRC level and 1111 is the DNU level.

  Although FIG. 2 shows the case of Option I of the clock quality discussed in ITU-T G.781, Option II or III is also used as appropriate depending on the type of device to be applied.

  When there are a plurality of ports that receive ESMC, the SSM codes of both are compared, and the clock is extracted from the port with the higher clock quality and synchronized. If there are a plurality of ports that have received the highest quality SSM, an arbitrary port may be selected from among them in order of port numbers.

  As a type similar to this ESMC, there is a time synchronization protocol PTP defined by IEEE 1588. IEEE 1588 discusses a method for exchanging packet data called PTP Message in order to distribute time from an upstream device synchronized with a reference clock to a downstream device. Similar to ESMC, by receiving a PTP Message from an upstream device, it can be determined that the device itself should operate in synchronization with the upstream device. In the embodiment described below, the case where the ESMC is mainly received and operated will be described, but the case where the PTP Message is received is also included in the embodiment.

  With reference to FIG. 3, clock transmission in the 1000BASE-T interface will be described. FIG. 3 shows details of a portion of FIG. In FIG. 3, ONT 28 and T1-Ether converter 30 are linked by 1000BASE-T.

  The ONT 28 includes a PLL 2801, a PHY 2802, and a port 2803. The PHY 2802 includes a register 2804. The T1-Ether converter 30 includes 3001, 3002, 3003, 3004, 3005, and 3006. The PHY 3002 includes a register 3007.

  The PLL 2801 receives the network extraction clock. The PLL 2801 generates a reference clock (REF CLK) and a gigabit transmission clock (GTXCLK) and supplies them to the PHY 2802. PHY 2802 is a MASTER. PHY3002 is SLAVE. Therefore, the PHY 3002 extracts the reception clock (RX CLK) from the reception data, and provides it to the PLLs 3001 and 3006. The PLL 3001 generates a reference clock (REF CLK) and a gigabit transmission clock (GTXCLK) and supplies them to the PHYs 3002 and 3004. The PLL 3006 generates a transmission clock (TXCLK) and supplies it to the PHY 3005. The PHY 3004 uses a gigabit transmission clock (GTXCLK) as a transmission timing and transmits the clock downstream.

In the PHY at both ends of the 1000BASE-T link, which is MASTER and which is SLAVE, the device settings stored in the registers 2804 and 3007 of each PHY are compared in the auto-negotiation process. To decide. As described in Table 40-3 of IEEE 802.3 40.5.1.1, the PHY holds the device setting in 3 bits (Reg 9.12: 10) in the register. Device settings are
・ Manual MASTER (Reg 9.12: 10 = 11X)
・ Manual SLAVE (Reg 9.12: 10 = 10X)
・ Multiport device (Reg 9.12: 10 = 0X1)
Single-port device (Reg 9.12: 10 = 0X0)
One of the four levels is set. Here, X is 0 or 1.

  With reference to FIG. 4, the combination of the device settings of LOCAL PHY and REMOTE PHY and MASTER / SLAVE will be described. Here, LOCAL is a local device, and REMORTE is a counter device. In FIG. 4, when LOCAL and REMOTE have different device settings, the master is the first in the order of the master MASTER, the multiport device, the single-port device, and the manual SLAVE, and the later is the SLAVE.

  If the same device setting is used for LOCAL and REMOTE, the link is disconnected between the manual settings. In multiports and single-ports, a seed value (SEED value), which is a random value stored in the PHY register, is compared, and the higher one becomes MASTER and the other becomes SLAVE. If the seed values are also equal, it is determined that the link has failed and the auto-negotiation process is performed again after reissuing the seed value.

  The configuration of the network device will be described with reference to FIG. In FIG. 5, the network device 31 has two electrical ports 3108 and 3109 on the left WAN side and two electrical ports 3110 and 3111 on the LAN side. All ports can be linked by 1000BASE-T, and are converted into GMII (Gigabit Media Independent Interface) by each PHY device 3101, 3102, 3103, 3104 and processed. In the network device 31, the WAN port and the LAN port are distinguished in advance, and when placed in the synchronous Ethernet, a clock is extracted from one of the WAN ports and expanded to all the LAN ports. As part of the internal processing of the main signal in the network device 31, an SSM determination block 3105 is provided. The SSM determination block 3105 extracts and analyzes an ESMC frame from data received at the WAN port. Based on the result, the SSM decision block 3105 selects which PHY is used to synchronize with the received clock. The SSM determination block 3105 sets a value in the device setting register of each PHY. The SSM determination block 3105 instructs the selector 3106.

  In FIG. 5, ESMC 2901 storing SSM = 1111 is received by the WAN port 3108, and ESMC 2903 storing SSM = 0010 is received by the WAN port 3109. The SSM determination block 3105 determines that it is synchronized with the reception clock (RX CLK) extracted from the port 3109 because SSM = 0010 has higher clock quality, and instructs the selector 3105. This clock is distributed in the apparatus as a reference clock via the PLL 3107. The PHYs 3102 and 3104 arranged in the two LAN ports use this reference clock for transmission timing. In order to transmit the clock quality to the downstream apparatus, ESMCs 2902 and 2904 generated inside the apparatus are transmitted from the LAN port.

  The essence of the present embodiment is the clock receiving port recognition and PHY device setting procedure. A specific procedure will be described with reference to the flowcharts of FIGS. Now, let us consider an operation flow for PHY of one specific port among the ports of the network device 31.

  In FIG. 6, after the apparatus is activated, the PHY determines whether it is a 1000BASE-T link during auto-negotiation of the target port (S1). If NO, it is out of process and ends. If the target port is a 1000BASE-T link in step 1, the PHY sets a multiport device as an initial setting (S2). As a result, it is possible to link up regardless of the device setting of the connection destination PHY.

  Thereafter, the network device waits for reception of ESMC from one or more WAN ports (S3). If received (YES), the SSM decision block 3105 analyzes the SSM code and determines the WAN port from which the synchronous clock is extracted (S4). ESMC is transmitted in 1s cycle. However, when receiving from multiple ports, it is possible that the determination operation is affected by the order of reception. Therefore, the ESMC is received several times or received several times. It is desirable to provide a protection condition such as comparing with the SSM of another port after it disappears.

The SSM determination rule is described below.
-If ESMC is not received from WAN port, all ports are not changed because synchronous Ethernet is not supported.
-Even if ESMC is received from the LAN port, it is invalid. All ports are unchanged.
-When ESMC is received from one WAN port, it is synchronized with the clock of this port regardless of SSM. The remaining WAN ports remain unchanged. All LAN ports are clocked.
• When receiving ESMC from multiple WAN ports, compare SSM and synchronize to the clock of the highest quality port. The remaining WAN ports remain unchanged. All LAN ports are clocked.
-If there are multiple ports with the highest quality level, any WAN port may be selected. The rest of the WAN port is unchanged. All LAN ports are clocked.

  Returning to FIG. 6, when it is determined that the target port is a port that receives the synchronous clock (S5: YES), the process jumps to FIG. If it is a LAN port (S6: YES), the process jumps to FIG. If none of them (such as the WAN port that does not synchronize with the clock), the PHY device setting is not particularly changed, and the standby state is set until the ESMC reception state is changed (S7). In either case, after changing the PHY setting described later, the function of this embodiment enters a standby state. However, in the ESMC that is continuously receiving, when the reception status changes, such as when the SSM code changes (S7). : YES), it is assumed that the setting is made again by returning to the SSM comparison in step 4 again.

  A case where the target port is a port that receives a synchronous clock will be described with reference to FIG. In order to receive the clock, the PHY must be SLAVE. It is determined whether PHY is SLAVE (S8). If the target PHY is already SLAVE (YES), it is suitable for the clock reception operation, so the PHY setting is not changed and the standby state is set (S9: NO). If a change occurs in the ESMC reception status in the entire apparatus during standby (S9: YES), the PHY returns to step 4 in FIG. 6 and resumes from the SSM determination. If the target PHY is MASTER (S8: NO), the PHY is set to manual SLAVE and forcibly restarts auto-negotiation (S11). Thereafter, the PHY determines whether the link is successful (S12). If the link is successful again (YES), the PHY enters the SLAVE state, so that it conforms to the clock reception and enters the standby state. If the link is not successful in step 12 (NO), the PHY is set to multiport device in order to prioritize linking first. This allows relinking. The reason why the link could not be established is that the network device 31 requests the REMOTE device to change the PHY setting because the REMOTE device at the connection destination is considered to be caused by an unmatch such as a manual SLAVE being set in the PHY. A notification to be transmitted is transmitted (S13). This may be a method of transmitting packet data through the target WAN port. After this, it is unavoidable to enter a standby state (S14: NO, S15: NO). If the REMOTE device changes the PHY setting in response to the request, the link breaks once, the target PHY becomes SLAVE, relinks, enters a desired state (S15: YES), and enters a standby state. If a change in the ESMC reception state occurs during standby (S14: YES), the process returns to step 4 in FIG. 6 to perform setting again.

  A case where the target port is a LAN port will be described with reference to FIG. In order to distribute clocks to downstream devices, the PHY of the LAN port must be MASTER. The PHY determines whether the status is MASTER (S16). If it is SLAVE (NO), PHY is forcibly changed to manual MASTER and restarts auto-negotiation (S19). If the target PHY has already been set to MASTER (S16: YES), it is suitable for the clock transmission operation, so there is no PHY setting change and a standby state is set (S17: NO, S18: NO). If a change occurs in the ESMC reception state in the entire apparatus during standby (S17: YES), the process returns to step 4 in FIG. 6 to perform setting again. In addition, when a link disconnection occurs due to an external factor such as unplugging the cable during standby (S18: YES), the PHY is set to the manual master at the link disconnection timing so that the link can always be performed in the MASTER state at the next link. Set (S19). After setting to manual master in step 19, the PHY determines whether the link is successful (S20). If the link can be successful again (YES), PHY becomes MASTER, so that it conforms to the operation of clock transmission and enters a standby state (S17: NO, S18: NO). When the link up cannot be performed due to the change to the manual master (S20: NO), an unmatch such as the PHY setting of the REMOTE device being the manual master is considered. The LOCAL side PHY is set again to the multiport device, and a notification requesting the PHY setting change is transmitted to the REMOTE device after the link up (S21). The standby state remains incompatible with the clock transmission operation (S22: NO, S23: NO). If the REMOTE device changes the PHY setting in response to the request, the link is broken once, and after re-linking, the target PHY becomes the MASTER and becomes a desired state (S23: YES). If a change in the ESMC reception state occurs during standby (S17 or S22: YES), the process returns to step 4 in FIG.

  With reference to FIG. 9, description will be made of how the state transition occurs between the PHY (LOCAL) of the port that receives the clock and the PHY of the connection destination REMOTE. As described in Step 2 of FIG. 6, the initial setting of the LOCAL side (own device) PHY is set to the multiport device setting. There are four types of settings on the REMOTE side (opposite device) PHY, but there are two types of multiport device settings: when LOCAL is set to MASTER and when it is set to SLAVE. Therefore, cases 1 to 5 can exist as initial states.

  In response to the determination result of the SSM determination block 3105, when the LOCAL side is determined as the clock reception port, the LOCAL is already SLAVE in the cases 1 and 2, so that it is suitable for the clock reception operation.

  In case 3 and case 4, LOCAL is MASTER, so the setting is changed to manual SLAVE and auto-negotiation is restarted. As a result, relinking and LOCAL becomes SLAVE, which is suitable for clock reception operation.

  Even in case 5, since LOCAL is MASTER, the setting is changed to manual SLAVE. However, since the REMOTE side is also manual SLAVE, the link is down. Therefore, the LOCAL side is returned to the multiport device setting, re-linked, and a setting change request is transmitted to REMOTE. If there is nothing, the standby state is entered without conforming to the clock reception operation. However, if the REMOTE side is changed to the manual master as requested, LOCAL becomes SLAVE after re-linking up, and enters the standby state in the conformity state of the clock reception operation.

  With reference to FIG. 10, description will be made of how state transition is made between the PHY (LOCAL) of the LAN port and the PHY of the connection destination REMOTE. As described in step 2 of FIG. 6, the initial setting of the LOCAL side PHY is set to the multiport device setting. The four types of settings on the REMOTE side include the initial states from case 1 to case 5, including the case where LOCAL becomes MASTER and SLAVE when multiport devices are set.

  In case 3, case 4, and case 5, LOCAL is MASTER and is already adapted to the clock transmission operation, so there is no change in setting. However, when a link disconnection due to an external factor such as a cable disconnection occurs, the setting is changed to the manual master using this timing so that the master is surely set even after re-linking up.

In case 2, since LOCAL is SLAVE, the setting is changed to manual MASTER, and after re-linking, MASTER is adapted to the transmission operation.
Even in case 1, since LOCAL is SLAVE, the setting is changed to manual MASTER. However, the link is down between the manual masters. Return to multiport device setting in LOCAL, and send a setting change request to the REMOTE device. If there is nothing, it enters the standby state with incompatibility of the clock transmission operation. However, if the REMOTE side changes the setting to manual SLAVE upon request, LOCAL becomes MASTER after re-linking up, and enters the standby state with the conformity of the clock transmission operation. . If a link breakage due to an external factor occurs, the setting is changed to the LOCAL side manual master so that the master is surely set after re-linking.

  In the present embodiment, application to the network apparatus shown in FIG. 11 will be described in which there is no WAN / LAN distinction between ports and each port can be used regardless of whether it is connected to either the upstream apparatus or the downstream apparatus.

  In FIG. 11, the network device 54 has ports 5401, 5402, 5403, and 5404, and each can be connected with 1000 BASE-T. In addition, each port develops communication data inside the apparatus by GMII using PHYs 5405, 5406, 5407, and 5408. When the ESMC 29 is received from the connected device, the SSM determination block 5409 recognizes from which port the ESMC has been received and compares the ESMC SSM code to determine which port to synchronize with the received clock. To do. The SSM determination block 5409 performs device setting of each PHY according to the determination result, and instructs the selector 5410 which RXCLK from which PHY is to be adopted. The selected clock is distributed as a reference clock to the entire apparatus via the PLL 5411.

  With reference to FIGS. 12-15, the PHY device setting procedure in Example 2 is demonstrated. After starting the network device, the PHY determines whether the target port can be connected by 1000BASE-T (S55). If YES in step 55, the PHY sets the initial setting to multiport device (S56). Thereafter, the network device 54 waits for reception of ESMCNO by one or more ports in the entire device (S57: NO). When YES in step 57, the SSM determination block 5409 grasps from which port the ESMC has been received. Further, the SSM determination block 5409 compares the SSM codes of the respective ports, and determines the port having the highest clock quality as the clock extraction port (S58). As a result, it is determined whether the target port is a PHY clock receiving port (S59). If YES, jump to FIG. If NO in step 59, the PHY determines whether the target port has received ESMC (S60). If YES, jump to FIG. If NO in step 60, the process jumps to FIG.

The SSM determination rule is shown below.
-If all ports and ESMC are not received, PHY settings are not changed because synchronous Ethernet is not supported.
-When ESMC is received by one port, it synchronizes with the reception clock of that port regardless of SSM and recognizes all other ports as clock transmission ports.
When ESMC is received by a plurality of ports, the received port is recognized as a WAN port, and the port not receiving is recognized as a LAN port, and the port having the highest quality level indicated in the SSM is set as a clock synchronization port. Other ESMC receiving ports do not change settings. All ESMC non-reception ports are clock transmission ports.
When there are a plurality of ports having the highest SSM level, any port among them may be determined as a clock synchronization port. Other ESMC receiving ports do not change settings. All ports not receiving ESMC are clock transmission ports.

  A case where the target port is a clock reception port will be described with reference to FIG. To receive the clock, PHY must be SLAVE. The PHY determines whether the status is SLAVE (S61). If the PHY status is originally SLAVE (YES), the setting is not particularly changed (S62: NO). When there is a change in the ESMC reception status (S62: YES), the network device 54 returns to step 58 in FIG. 12 and restarts from the SSM comparison.

  In step 61, if the status is MASTER, the PHY is set to manual SLAVE and restarts the auto negotiation (S64). The PHY determines whether the link is successful (S65). If YES, the PHY enters the SLAVE state and can receive a clock, and the process proceeds to step 62. If the link fails in step 65, it is considered that the PHY setting on the REMOTE side is also set to manual SLAVE. Prioritizing link up, the PHY returns the LOCAL side PHY setting to the multiport device and restarts auto-negotiation. If the link up can be performed again, a setting change request is notified to the REMOTE device (S66). The PHY enters a standby state (S67: NO, S68: NO). When the REMOTE device receives the change request and changes the setting to the manual master, the LOCAL side is once linked again and then relinked to enter the SLAVE state (S68: YES). If there is a change in the ESMC reception status (S67: YES), the network device 54 returns to step 58 in FIG. 12 and restarts from the SSM comparison.

  With reference to FIG. 14, the PHY setting procedure when the target port is not a clock reception port but receives an ESMC will be described. Although this port does not perform clock extraction but receives ESMC, it can be determined that it is connected to a device located on the upstream side of the network. Therefore, if a failure occurs in the port currently selected as the clock source, this port may be set as the clock source. Therefore, it is not necessary to forcibly change the setting until the link is disconnected, but it is desirable to change to SLAVE if there is an opportunity.

  The network device 54 determines whether there is a change in the ESMC reception status (S69). When YES, the network device 54 returns to step 58 in FIG. 12 and restarts from the SSM comparison. If NO in step 69, the PHY determines whether or not a link break has occurred (S70. If NO, the process returns to step 69. If a link break due to an external factor such as a cable disconnection occurs in step 70, PHY. Using this opportunity, the setting is changed to manual SLAVE (S71) PHY determines whether the link is successful (S72) If the link is successful (YES), it becomes SLAVE, and the process proceeds to step 69. If the link fails in step 72 (NO), it is expected that the REMOTE device is also in the manual SLAVE, so the PHY returns the setting to the multiport device, links up again, and then returns to the REMOTE device. On the other hand, a setting change request is notified (S73).

  The network device 54 determines whether there is a change in the ESMC reception status (S74). When YES, the network device 54 returns to step 58 in FIG. 12 and restarts from the SSM comparison. When NO in step 74, the PHY determines whether or not the link has been re-linked by SLAVE after the link break has occurred (S75). If NO, the processing makes a transition to Step 74. When the REMOTE device changes its own PHY setting to manual MASTER in response to the request, the link is temporarily disconnected and then linked up again. When the LOCAL side becomes SLAVE (S75: YES), the process proceeds to step 69.

  Finally, a case where the target port does not receive ESMC will be described with reference to FIG. This port determines that it is connected to a device located on the downstream side of the network, and sets PHY to MASTER to distribute the clock. The PHY determines whether the status is MASTER (S76). If the PHY status is SLAVE, it is forcibly set to manual MASTER, and auto-negotiation is restarted (S79). If the PHY status is already MASTER, there is no setting change. The network device 54 determines whether there is a change in the ESMC reception status (S77). When YES, the network device 54 returns to step 58 in FIG. 12 and restarts from the SSM comparison. If NO in step 77, the PHY determines whether a link break has occurred (S78). If NO, the process returns to step 77. If YES in step 78, the PHY uses the opportunity to set the manual MASTER and starts auto-negotiation (S79). After setting the manual master, the PHY determines whether the link is successful (S80). If the link is successful (YES), PHY becomes MASTER, clock distribution operation becomes possible, and the process proceeds to step 77. If the link fails in step 80, it is considered that the REMOTE apparatus is also set to the manual master. The PHY returns to the multiport device, and when it is able to link up again, notifies the REMOTE device of a setting change request (S81). The network device 54 determines whether there is a change in the ESMC reception status (S82). When YES, the network device 54 returns to step 58 in FIG. 12 and restarts from the SSM comparison. When NO at step 82, the PHY determines whether re-up is performed with MASTER after a link break has occurred (S83). If YES, the processing makes a transition to Step 77. When NO at step 83, the process proceeds to step 82.

  The network configuration of the network device according to the second embodiment will be described with reference to FIGS.

  In FIG. 16 and FIG. 17, two ONTs 28 are connected to the OLT 25 via the optical splitter 27. Further, the two ONTs 28 are connected to ports 5401 and 5402 of the network device 54. The port 5403 of the network device 54 is connected to the ATM-Ether converter 86, and the port 5404 is connected to the T1-Ether converter 29. A WAN 24 is connected to the OLT 25.

  The PRC 26 supplies a clock to the OLT 25. This clock is also distributed to the two ONTs 28. The two ONTs 28 transmit ESMC toward the downstream side to convey the clock quality. In FIG. 16, both the ONT 28-1 and the ONT 28-2 receive a PRC quality clock from the OLT 25, and both ONTs 28 transmit an ESMC of SSM = 0010. In the network device 54, both are the same SSM, but the clock is extracted from the port 5401, and the PHY setting is changed according to the above-described flow. As a result, the PHY of the port 5401 is SLAVE, and the ports 5403 and 5404 are MASTER. The port 5402 receives the ESMC, but has not been set as a clock reception port. Therefore, the port 5402 is in either the MASTER or SLAVE state with the default multiport device setting.

  FIG. 17 shows a case in which a synchronization failure has occurred in the ONT 28-1 from this state. In FIG. 17, since the synchronous clock cannot be extracted from the OLT 25, the ONT 28-1 transmits an ESMC storing SSM = 1111 toward the device 54. In response to the change in the ESMC reception state, the device 54 compares the SSM again and determines to receive the clock from the port 5402. As a result of changing the PHY setting according to the operation of the second embodiment, the port 5402 becomes SLAVE, and a clock is extracted from this port.

  With reference to FIGS. 18 and 19, another network configuration using a network device will be described. In FIG. 18, the WAN 24 is connected to the network device 54 via two media converters 87 (hereinafter referred to as MC). The PRC 26 is supplied with reference clocks to MC 87-1 and 87-3 and is distributed to MC 87-2 and 87-4 by synchronous Ethernet. The MCs 87-2 and 87-4 transmit the ESMC of SSM = 0010 to the downstream network device 54. In accordance with the operation of the second embodiment, the network device 54 compares the SSM for the ports 5401 and 5402 that have received the ESMC. In the case of FIG. 16, the SSM is the same value, but it is determined that the clock is received from the port 5401, and the PHY and clock selection setting procedure is performed. As a result, the PHY of the port 5401 becomes the SLAVE mode. It becomes. On the other hand, the port 5402 takes either the MASTER or SLAVE state with the default multiport device setting. Further, since the ports 5403 and 5404 have not received the ESMC, they are regarded as clock transmission ports and become MASTER by the PHY setting change procedure, and the clock and the ESMC generated in the device are further down-converted into the ATM-Ether converter 86. , And the T1-Ether converter 29.

Here, FIG. 19 shows the situation when a failure occurs in the connection between the MC 87-2 and the network device 54 and communication is interrupted. In FIG. 19, in response to the fact that ESMC is no longer sent from MC 87-2, the network device 54 performs SSM determination again and extracts the clock from the port 5402 receiving SSM = 0010. Change the PHY settings. As a result, port 5402 links in the SLAVE state and receives a clock from this port. Ports 5401, 5403, and 5404 are regarded as clock transmission ports because they have not received ESMC. The PHY of port 5401 is set to manual MASTER, but is not linked up due to a failure.
[Appendix]
The present invention can also take the following forms.
(1) When the link cannot be established as a result of restarting auto-negotiation after changing the PHY register to manual MASTER or manual SLAVE,
2. The network device according to claim 1, wherein the auto negotiation is restarted by returning the PHY register to the multiport device setting.
(2) The network device according to (1), wherein the PHY register setting is returned to the multiport device setting, a link is established, and then a request for changing the PHY register setting is notified to the REMOTE device.
(3) When reception of ESMC or PTP Message is stopped at one or more ports,
If you start receiving ESMC or PTP Message on a port that has not been received before,
If the value of the SSM code changes,
When at least one of
Re-determine whether each port is either clock receiving or clock transmitting,
2. The network device according to claim 1, wherein the PHY is set accordingly.
(4) Recognize that the ESMC packet is received by periodically receiving more than a certain number of ESMC packets having the same SSM code,
The network device according to claim 1, wherein the ESMC is recognized as having stopped due to failure to receive the ESMC reception cycle for a predetermined number of times.
(5) When the SSM code is at the DNS (Do Not Use) level in all the ports that received ESMC,
2. The network device according to claim 1, wherein PHY register change and auto-negotiation are not restarted at all.

  24 ... WAN, 25 ... OLT, 26 ... PRC (primary reference clock), 27 ... optical splitter, 28 ... ONT, 29 ... ESMC packet data, 30 ... T1-Ether converter, 31 ... network device, 54 ... network device 86 ... ATM-Ether converter, 87 ... Media converter, 100 ... Access network system.

Claims (10)

In a network device having a plurality of electrical ports compliant with the 1000BASE-T standard,
At startup, the multiport device setting is stored in the PHY registers of all the electrical ports,
When the first electrical port starts to receive ESMC or PTP Message, it is determined whether the plurality of electrical ports is a clock reception port, a clock transmission port, or neither port.
The clock receiving port changes the first register to manual SLAVE so that its first PHY becomes SLAVE,
The network device characterized in that the clock transmission port restarts auto-negotiation by changing the second register to manual MASTER so that the second PHY becomes MASTER. When the first PHY is already SLAVE, or when the second PHY is already MASTER,
The network device according to claim 1, wherein restart of auto-negotiation is omitted. When a link break occurs,
3. The network device according to claim 2, wherein the first register of the first PHY is set to manual SLAVE, and the second register of the second PHY is set to manual MASTER.   The network device according to claim 1, wherein when the number of the electrical port that has received the ESMC or PTP Message is one, the electrical port is used as the clock reception port. When the ESMC is received from a plurality of the electrical ports, the electrical port having the highest clock quality indicated by the SSM is set as the clock reception port,
2. The network device according to claim 1, wherein when there are a plurality of electrical ports having the highest clock quality, an arbitrary electrical port is selected as the clock reception port.   2. The network device according to claim 1, wherein when the PTP Message is received from a plurality of the electrical ports, an arbitrary electrical port is set as the clock reception port.   The network device according to claim 1, wherein the electric port that has not received the ESMC and the PTP Message is determined as a clock transmission port. The network device according to claim 1, wherein a WAN port or a LAN port is designated in advance for each electrical port,
A network device characterized in that when an ESMC or PTP Message is received from one or more WAN ports, a WAN port that is not determined as the clock reception port omits register change and auto-negotiation restart. The network device according to claim 1, wherein a WAN port or a LAN port is designated in advance for each electrical port,
A network device characterized in that even if the ESMC or the PTP Message is received, if the electrical port is designated as the LAN port in advance, it is determined as the clock transmission port.   The network device according to claim 1, wherein the clock transmission port transmits an ESMC in which the quality of a clock being synchronized is stored in an SSM.

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