JP5481728B2 - Equalizer - Google Patents

Description

  The present invention relates to an equalizer that performs equalization processing and an equalization processing method, and more particularly to an equalizer and equalization that achieve good convergence in equalization processing even when the number of symbols in a synchronization word is small. It relates to the processing method.

For example, in the case of introducing a decision feedback equalizer DFE (Decision Feedback Equalizer) that compensates for distortion of a received signal due to the influence of a delayed wave in a digital wireless terminal device for land mobile communication, especially when moving at high speed, etc. Since propagation path fluctuations become faster, a sequential least squares (RLS) algorithm is desired that has a high tap gain pull-in speed and can sufficiently converge the tap gain coefficient with about 10 symbols. ing.
However, in the RLS algorithm, the number of multiplications increases in proportion to the square of the number of taps of the adaptive filter, and a complicated determinant is used for the calculation. Since a problem arises, it is difficult to realize processing by a fixed-point DSP (Digital Signal Processor) with low cost and low power consumption, and it is difficult to mount it on a portable terminal radio.

On the other hand, as a tap gain update algorithm for a linear equalizer and a non-linear equalizer, a least square (LMS: Least) that exhibits a relatively good convergence characteristic for a small amount of computation that is proportional to the number of taps of an adaptive filter.
(Mean Square) algorithm is known.
In the LMS algorithm, the tap gain is controlled so as to gradually approach the optimum tap gain that minimizes the mean square value of the error. Therefore, at least about 30 to 50 symbols are required to converge the coefficients. However, it is recognized as a typical adaptive algorithm from the viewpoint of high stability and a small amount of calculation. Desirable implementations in the signal processing apparatus include reducing the amount of calculation, shortening the convergence time of the tap gain coefficient during the training operation, and reducing the number of symbols required for the training operation.
For example, in a fixed-system communication system such as a municipal digital broadcast communication system, a transmission-side antenna and a reception-side antenna are fixedly installed, and fluctuations in the propagation path are small. Equalization processing from the front of the buffer, that is, equalization processing performed along the time axis (hereinafter referred to as forward equalization), and equalization processing from the rear, that is, equalization processing performed retrospectively along the time axis (hereinafter referred to as “equalization processing”) The method of performing reverse equalization) can compensate for propagation path distortion. For example, a communication system that establishes a base station at a city hall, etc., and establishes an outdoor child station at a school or public hall to report disasters, etc., is used for wireless communication. There is a problem that radio waves (delayed waves) reflected and delayed by a mountain or the like are combined with radio waves (direct waves) that arrive directly and received by the outdoor slave station.

JP 2004-180109 A

ARIB STD-T86, “Municipal Digital Broadcasting System”, The Japan Radio Industry Association

  However, in the conventional technology as described above, for example, in the case where the known symbol that can be used for training such as ARIB STD-T86 (Non-patent Document 1) is only the synchronization word at the center of the frame, it is inevitably necessary. Therefore, the data before the sync word must be equalized in the reverse direction, and the data after the sync word must be equalized in the forward direction.

Here, such a problem will be specifically described.
FIG. 3 is a diagram showing a frame format used for general wireless communication, and is a signal format of one frame. Since the synchronization word SW, which is a known symbol, is arranged at the center of the frame, and data such as a traffic channel is arranged on both sides of the frame, the data before the synchronization word is equalized in the reverse direction and synchronized. For the data after the word, forward equalization is performed.
FIG. 3 is a diagram to be referred to in an embodiment described later. Here, FIG. 3 is referred to for convenience of explanation, but there is no intention to limit the present invention.

  FIG. 4 is a diagram showing a delay profile indicating that a delayed wave is combined with a received signal received by an outdoor slave station in the prior art. Here, FIG. 4 (a) is a delay profile when the outdoor slave station is installed in a place where the master station can be seen from, and FIG. 4 (b) is a case where the outdoor slave station is installed in a place where the master station cannot be seen. The delay profile is shown. In the case of FIG. 4 (a), there is a power difference between the direct wave and the delayed wave, and the power of the direct wave is dominant, but in the case of FIG. 4 (b), the direct wave is blocked and only the delayed wave is present. Therefore, the power difference between the delayed wave 401 and the delayed wave 402 is small, and the delayed waves interfere with each other.

FIG. 5 is a diagram showing a delay profile when equalization processing is performed on a conventional received signal.
FIG. 5 shows a delay profile in the case where equalization is performed on a signal received by the outdoor slave station when the outdoor slave station is installed in a location that cannot be seen from the master station. FIG. 5A is a diagram illustrating a case where forward equalization is performed on a received signal, and FIG. 5B is a diagram illustrating a case where reverse equalization is performed on a received signal.
When the forward equalization of FIG. 5A is performed, the delay profile is the same as that of FIG. 4B. However, when the reverse equalization is performed as shown in FIG. Since the process is performed in the reverse direction, the time relationship of the delay profile is opposite to that in FIG.
In the equalizer, the preceding wave in FIG. 5 becomes a direct wave, and the following wave becomes a delayed wave. A case where the direct wave is larger than the delayed wave is called a minimum phase condition, and a case where the delayed wave is larger than the direct wave is called a non-minimum phase condition. Normally, since the input signal has a minimum phase condition in which the direct wave is larger than the delayed wave as shown in FIG. 4A, the forward equalization in FIG. The reverse equalization of b) is a non-minimum phase condition.
Here, the decision feedback type equalizer requires a larger number of taps in the non-minimum phase condition than in the minimum phase condition, and the convergence characteristic is inferior under the same tap number condition.

FIG. 6 is a diagram showing a computer simulation result of conventional equalization errors of forward equalization and reverse equalization.
In FIG. 6, the forward direction when the difference in intensity between the delayed wave 501 and the delayed wave 502 in FIG. 5 is 3 dB and the time difference is T / 2 (T: symbol period, T = 1 / 11.25 kHz = 88.9 μs). The equalization error of equalization and reverse direction equalization is obtained by computer simulation. According to FIG. 6, since the data before the sync word is subjected to the reverse equalization process, the non-minimum phase condition is set and the equalization error is large.

  FIG. 11 is a diagram showing a constellation of the equalizer output under the condition in FIG. 6 in the prior art. FIG. 11A shows a constellation of the first half of the frame subjected to the reverse equalization, and FIG. ) Shows the constellation of the second half of the frame after forward equalization. In FIG. 11B, the equalization error is small and the constellation is converged, but the constellation diverges in the first half of the frame in which the reverse equalization in FIG. 11A is performed.

  Further, when the magnitude relationship between the delayed waves 401 and 402 in FIG. 4B is reversed, the forward equalization is a non-minimum phase condition and the reverse equalization is a minimum phase condition. Depending on the magnitude relationship of the waves, either the first half or the second half of the frame data has a non-minimum condition, and the equalization characteristics deteriorate.

The present invention has been made in view of such a conventional situation, and an object of the present invention is to provide an equalizer that can perform an effective equalization process in a frame configuration as shown in FIG. And
It is another object of the present invention to provide an equalizer that can perform an effective equalization process when a phase change occurs due to a frequency deviation that occurs during wireless communication.

(Configuration example corresponding to the first embodiment)
In order to achieve the above object, in the present invention, an equalizer for equalizing a received signal including a frame including a known symbol portion has the following configuration.
That is, backward forward equalization processing means performs equalization processing in the forward direction on a signal behind the known symbol portion included in the frame. A forward forward equalization processing means performs an equalization process in a forward direction on a signal ahead of the known symbol portion included in the frame. A forward reverse equalization processing means performs an equalization process in a reverse direction on a signal ahead of the known symbol portion included in the frame. A backward backward equalization processing unit performs an equalization process in a backward direction on a signal behind the known symbol portion included in the frame. The forward acquisition means compares the error in the equalization processing by the forward forward equalization processing means with the error in the equalization processing by the forward reverse equalization processing means, and determines the better equalization processing result. get. The backward acquisition means compares the error in the equalization processing by the backward forward equalization processing means with the error in the equalization processing by the backward backward equalization processing means, and determines the better equalization processing result. get. And the result of the equalization process acquired by the said front acquisition means and the result of the equalization process acquired by the said back acquisition means are employ | adopted.

Therefore, equalization processing is performed in each of the forward direction and the reverse direction with respect to the signal ahead of the known symbol part included in the frame, and the better (smaller error) equalization processing result is adopted. Since equalization processing is performed in each of the forward direction and the reverse direction with respect to the signal behind the known symbol part included in the frame, and the equalization processing result of the better (smaller error) is adopted, As a whole, equalization processing with high accuracy can be realized. Thus, for example, effective equalization processing can be performed in the frame configuration as shown in FIG.
In addition, as shown in a first embodiment to be described later, it is possible to realize an equalizer that can perform an effective equalization process when a phase change due to a frequency deviation that occurs during wireless communication occurs. .

Here, frames having various configurations may be used.
Various known symbol portions may be used. For example, a synchronization word (SW) can be used.
Further, when processing is performed on a signal ahead or behind a known symbol part included in a frame, for example, when a known symbol part is necessary or may be present, the known symbol part is For example, when the known symbol portion is unnecessary or may not be included, the processing may be performed without including the known symbol portion.

Further, as an error in the equalization process, for example, an average of equalization errors in a case where the equalization process is performed a plurality of times may be used.
Further, the equalization processing result adopted for the signal ahead of the known symbol part included in the frame and the equalization processing result adopted for the signal behind the known symbol part included in the frame are, for example, as they are. The next process or storage in the memory may be performed. Alternatively, the next process or storage in the memory may be performed after the two equalization processing results are combined. Here, when these two equalization processing results are combined, if there is an overlapping part, only one of the overlapping parts is adopted or the two are averaged and adopted. May be.

(Configuration example corresponding to the second embodiment)
In order to achieve the above object, in the present invention, an equalizer for equalizing a received signal including a frame including a known symbol portion has the following configuration.
That is, the symbol forward equalization processing means performs equalization processing in the forward direction using all or part of the known symbol portion included in the frame as an equalization target. The symbol reverse direction equalization processing means performs equalization processing in the reverse direction using all or part of the known symbol portion included in the frame as an equalization target. The direction selection means compares the error in the equalization process by the symbol forward direction equalization processing means with the error in the equalization process by the symbol reverse direction equalization processing means, and the direction selection means Select the direction. The signal equalization processing means performs equalization processing on the received signal composed of the frame in the direction selected by the direction selection means.

Accordingly, equalization processing is performed in each of the forward direction and the reverse direction using a known symbol portion included in the frame, and a better direction (smaller error) direction (forward direction or reverse direction) is selected. Since the received signal composed of the frame is equalized in the selected direction, it is possible to realize an equalization process with high accuracy, and to the received signal composed of the frame in one direction (forward direction or It is sufficient if the equalization process is performed only in the reverse direction). Thus, for example, effective equalization processing can be performed in the frame configuration as shown in FIG.
Further, as shown in a second embodiment to be described later, it is possible to realize an equalizer that can perform an effective equalization process when a phase change occurs due to a frequency deviation that occurs during wireless communication. .

Here, frames having various configurations may be used.
Various known symbol portions may be used. For example, a synchronization word (SW) can be used.
Further, in the equalization process using the known symbol part, for example, all of the known symbol part may be used as an equalization process target, or a part of the known symbol part is used as an equalization process target. May be.
In addition, as the equalization process in the forward direction or the reverse direction using the known symbol portion, for example, equalization processes may be performed a plurality of times.
Further, as an error in the equalization process, for example, an average of equalization errors in a case where the equalization process is performed a plurality of times may be used.

  In addition, when equalization processing is performed in the forward direction or the reverse direction on a reception signal composed of a frame, for example, a signal ahead of a known symbol part included in the frame and a known symbol part included in the frame Processing is performed separately for the rear signals. At this time, when processing is performed on a signal ahead or behind the known symbol part included in the frame, for example, when the known symbol part is necessary or may be present, the known symbol part For example, when a known symbol portion is unnecessary or may not be included, the processing may be performed without including a known symbol portion.

  The equalization processing result obtained for the signal ahead of the known symbol part included in the frame and the equalization processing result obtained for the signal behind the known symbol part included in the frame are, for example, as they are. The next process or storage in the memory may be performed. Alternatively, the next process or storage in the memory may be performed after the two equalization processing results are combined. Here, when these two equalization processing results are combined, if there is an overlapping part, only one of the overlapping parts is adopted or the two are averaged and adopted. May be.

As described above, according to the equalizer of the present invention, for example, effective equalization processing can be performed in the frame configuration as shown in FIG.
Further, as shown in a first embodiment and a second embodiment, which will be described later, for example, an equalization that can perform an effective equalization process when a phase change due to a frequency deviation that occurs during wireless communication occurs. It is also possible to implement a vessel.

It is a book figure which shows the structural example of the adaptive equalizer which concerns on 1st Example of this invention. It is a block diagram which shows the structural example of the equalization process part which concerns on one Example of this invention. It is a figure which shows an example of the frame format used for general radio | wireless communication. (A) And (b) is a figure which shows an example of the delay profile showing that a delayed wave was synthesize | combined with the received signal which the outdoor sub_station | mobile_unit received in the prior art. (A) And (b) is a figure which shows an example of the delay profile in the case of performing the equalization process with respect to the received signal in a prior art. It is a figure which shows an example of the result of having calculated | required the equalization error of the forward equalization in a prior art, and a reverse equalization by computer simulation. It is a figure which shows an example of the accumulation | storage to the forward buffer and reverse buffer which concern on one Example of this invention. It is a figure for demonstrating the processing operation of the equalization process part which concerns on one Example of this invention. It is a block diagram which shows the detailed structural example of the decision feedback equalizer which concerns on one Example of this invention. It is a block diagram which shows the detailed structural example of the non-judgment output feedback process part which concerns on one Example of this invention. (A) And (b) is a figure which shows an example of the constellation of the equalizer output in a prior art. It is a figure which shows an example of the computer simulation result of the equalization error based on one Example of this invention. (A) And (b) is a figure which shows an example of the computer simulation result of the equalization output constellation which concerns on one Example of this invention. It is a figure which shows the structural example of the receiver using the equalization processing method which concerns on one Example of this invention. It is a book figure which shows the structural example of the adaptive equalizer which concerns on 2nd Example of this invention. It is a block diagram which shows the structural example of the equalization process part which concerns on one Example of this invention. It is a figure for demonstrating the processing operation of the equalization process part which concerns on one Example of this invention. It is a figure which shows an example of the computer simulation result of the equalization error based on one Example of this invention.

  Embodiments according to the present invention will be described with reference to the drawings.

A first embodiment of the present invention will be described.
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 14 is a diagram showing an embodiment of the configuration of a receiver using the equalization processing method in an embodiment of the present invention.
The receiver of this example includes a demodulation unit 1 and a demodulation processing unit 2 between an input terminal Z1 and an output terminal Z2.
The demodulation unit 1 includes an RF (radio frequency) unit 11, an A / D (Analog to Digital) converter 12, an orthogonal demodulation unit 13, and a reception filter unit 14.
The demodulation processing unit 2 includes an adaptive equalizer 15.

Further, in the wireless communication of this example, description will be made assuming that communication is performed using the frame configuration shown in FIG.
Specifically, a burst transient response ramp time (R) symbol 301, an information (DATA) symbol 302 composed of various data, a pilot symbol (P) symbol 303, and information following the pilot symbol 303 (DATA) ) Symbol 304, followed by synchronization word sequence (SW) symbol 305, following information (DATA) symbol 306, pilot symbol (P) symbol 307, following information (DATA) symbol 308, and guard time. (G) symbol 309.
In this example, an information (DATA) symbol is shown, but various frame configurations may be used.

An example of the operation performed in the receiver of this example is shown.
A received signal wirelessly received by the antenna is input from the input terminal Z1 to the RF unit 11 in the demodulator 1, and the RF unit 11 performs power amplitude amplification by a buffer amplifier and frequency conversion by a mixer. Thereafter, the received signal is converted from an analog signal to a digital signal by the A / D converter 12. The received signal converted into the digital signal is orthogonally demodulated by the orthogonal demodulator 13 and separated into an I component and a Q component of the baseband signal. The I and Q components of the baseband signal are filtered by the reception filter unit 14 and input to the adaptive equalizer 15 in the demodulation processing unit 2.
The signal input to the adaptive equalizer 15 is equalized by the adaptive equalizer, and the equalized signal is output from the output terminal Z2.

FIG. 1 is a block diagram showing an adaptive equalizer according to an embodiment of the present invention. The adaptive equalizer 15 performs equalization processing for one frame, the accumulation processing unit 101, forward buffers 102 and 103, backward buffers 104 and 105, equalization processing units 106 and 107, and forward output buffers 108 and 109. , Reverse output buffers 110 and 111, and an output coupling unit 112.
The accumulation processing unit 101 controls accumulation in the forward buffers 102 and 103 and the backward buffers 104 and 105.
The equalization processing unit 106 receives the data of the forward buffers 102 and 103, performs forward equalization processing, inputs the forward equalization output of the second half of the frame to the forward output buffer 108, and forwards the first half of the frame. The equalized output is input to the forward output buffer 109. The equalization processing unit 107 inputs the data of the reverse buffers 104 and 105, performs reverse equalization processing, inputs the reverse equalization output of the first half of the frame to the reverse output buffer 110, and reverses the second half of the frame The equalized output is input to the backward output buffer 111.

  FIG. 7 is a diagram for explaining accumulation in the forward buffer and the backward buffer according to an embodiment of the present invention. In the forward buffer 103, data of frames 701 to 703, that is, symbols 301 and 302 are stored. , 303, 304, and 305 (hereinafter referred to as the first frame data) is accumulated in the forward direction as the data of the symbol 301 as the head address, and the forward buffer 102 stores the data from the frames 702 to 704, that is, , 305, 306, 307, 308, and 309 (hereinafter referred to as frame second half data) are stored in the forward direction as the data of the symbol 305, respectively. The backward buffer 104 stores the first half data of the frame in the reverse direction and the data of the symbol 305 as the head address, and the backward buffer 105 stores the second half of the data in the backward direction and the data of the symbol 309 as the head address. accumulate.

FIG. 2 is a block diagram showing a configuration example of the equalization processing unit in one embodiment of the present invention.
The equalization processing unit 106 is a decision feedback equalizer (hereinafter referred to as DFE) 203-1, 203-2, a non-judgment output feedback processing unit 204, a tap gain coefficient buffer 205, a buffer 206, and amplitude and phase correction coefficient calculation. A unit 207, an amplitude and phase correction unit 208, a coefficient correction unit 209, and an output coupling unit 210. Since the equalization processing unit 107 has the same configuration as the equalization processing unit 106, the description thereof will be omitted or will be described together with the equalization processing unit 106.
2, the data content stored in the forward buffer 102 or the backward buffer 104 described in FIG. 7 is input to the DFE 203-1 through the terminal 201, and similarly to the forward buffer 103 or the backward buffer 105. The accumulated data content is input to the DFE 203-2 and the non-judgment output feedback processing unit 204 via the terminal 202.

FIG. 9 is a block diagram showing details of the decision feedback equalizer in one embodiment of the present invention.
In FIG. 9, the decision feedback equalizer DFE 203-1 is a delay circuit that gives a delay of 1/2 symbol, a number obtained by subtracting one from the NFF that is the number of feedforward taps, that is, NFF-1 delay. Circuits 904-1 to 904- (NFF-1) NFB delay circuits 905-1 to 905-NFB, which are the number of feedback taps giving a delay of one symbol, NFF + NFB complex multipliers 906-0 to 906 -(NFF-1), 907-1 to 907-NFB, complex adders 908-1 and 908-2, complex subtractor 909, error power calculation unit 910, symbol determination unit 911, switch 912, synchronous word symbol storage memory 913 and a tap gain coefficient updating unit 914. Note that the DFE 203-2 has the same configuration as the DFE 203-1, and therefore description thereof will be omitted unless otherwise specified.
Here, the update algorithm of the tap gain coefficient updating unit 914 is, for example, the least mean square LMS. A signal from the terminal 201 or 202 is input from the terminal 901. Here, the DFE 203-1 outputs the final value of the tap gain coefficient to the tap gain coefficient buffer 205 via the terminal 902. In the case of DFE 203-2, the tap gain coefficient from the coefficient correction unit 209 is input as an initial value via the terminal 903.
When performing the training operation using the synchronization word symbol stored in the synchronization word symbol storage memory 913 as a reference signal, the terminals 912- (a) and 912- (c) of the switch 912 are connected, and the synchronization word symbol storage memory is connected. The synchronization word symbol is input from 913 to the delay circuit 905-1 of the feedback tap. When performing a tracking operation using the symbol determination result as a reference signal, the terminals 912- (a) and 912- (b) of the switch 912 are connected, and the output of the symbol determination unit 911 is sent to the delay circuit 905-1 of the feedback tap. input.

FIG. 10 is a block diagram showing a detailed configuration example of the non-judgment output feedback processing unit in one embodiment of the present invention. The non-deterministic output feedback processing unit 204 includes NFF-1 delay circuits 1003-1 to 1003- (NFF-1) that give a 1/2 symbol delay, and NFB delay circuits 1004-1 that give a 1 symbol delay. ˜1004-NFB, NFF + NFB complex multipliers 1005-0 to 1005- (NFF-1), 1006-1 to 1006-NFB, complex adders 1007-1 and 1007-2, and at the equalizer output An output y of 1007-1 is directly fed back to the feedback taps u _{-1 to} u _-NFB to obtain an equalizer output y.

FIG. 8 is a diagram for explaining the processing operation of the equalization processing unit in one embodiment of the present invention.
The equalization processing unit 106 or 107 performs forward equalization and backward equalization for each of the first half frame data and the second half frame data.
When the forward equalization is performed on the first half frame data and the second half frame data, first, the synchronization word (SW) for the data of the first half data of the frame 801 to 803, that is, the data of the symbols 305, 306, 307, and 308 ) The signal portion of the symbol 305 is repeated, for example, an arbitrary number of times (for example, 16 times) according to the coefficient update algorithm, and after training is performed, tracking is performed on input signals 802 to 803. These training and tracking processes are processed by the DFE 203-1.
Here, the training is a process of converging the tap gain coefficient using a known symbol such as a synchronization word (SW) as a reference signal, and terminals 912-(a) and 912-(c) of the switch 912. Connect and implement. In addition, the tracking is a process in which the equalizer output is subjected to symbol determination, and the determination result is used as a reference signal to converge the tap gain coefficient. The terminals 912- (a) and 912- (b) of the switch 912 are used. Connect and implement.

Next, an equalization process when a frequency deviation occurs between the transmitting and receiving station oscillators when performing wireless communication using an embodiment of the present invention will be described with reference to FIG.
Normally, when a frequency deviation occurs in the local oscillator on the transmission side and the reception side when performing wireless communication, a signal at the time of data 803 and a signal at the time of 804 cause a phase difference corresponding to the frequency deviation. The tap gain coefficient at the time of 803 cannot be used for the equalization processing from the data 804 as it is. Therefore, non-determination output feedback processing is performed up to the pilot signal 303 by the non-determination output feedback processing unit 204 for the input signals from data 804 to 805, that is, the symbols 301, 302, and 303, and the output is stored in the buffer 206. To do. When the tap gain coefficient at the time of data 803 is set as an initial value and the non-deterministic output feedback processing unit 204 calculates the output by returning to the feedback tap without determining the equalizer output, the pilot output of the data 805 is Since the output has a phase rotated by the amount of the frequency deviation, the rotated phase is obtained from this, and the phase of the tap gain coefficient is corrected and used.

The amplitude and phase correction coefficient calculation unit 207 sets a symbol at the time of pilot symbol transmission as p, and calculates p ′ = p / | p | ² complex conjugate (p ′) ^* obtained by dividing p by the square of the magnitude of p. , multiplies the output y _p of the pilot P portion of the stored output values in the buffer 206, calculates the the multiplication result k (equation 1).

(Equation 1)
k = y _p · (p ′) ^*
However, p ′ = p / | p | ²
・ ・ (Formula 1)

Subsequently, g obtained by dividing k by the square of | k | ² of the magnitude of k is calculated by (Expression 2), and is input to the amplitude and phase correction unit 208 and the coefficient correction unit 209.

(Equation 2)
g = k / | k | ²
.. (Formula 2)

The amplitude and phase correction unit 208 corrects the phase rotation due to the frequency deviation by multiplying the output value stored in the buffer 206 by the complex conjugate g ^* of g, and inputs the result to the output coupling unit 210. .
The coefficient correction unit 209 multiplies the tap gain coefficients h ₀ , h ₁ ,..., H _NFF-1 of the feedforward tap by the above g, and tap gain coefficients h _−NFB , h _{−NFB + 1 of} the feedback tap _,.・ H- ₁ is input as it is and input to the DFE 203-2 as an initial value of the tap gain coefficient.
The DFE 203-2 uses the tap gain coefficient input from the coefficient correction unit 209 as an initial value, and data 805 to 806, that is, symbols 304 and 305 in the case of forward equalization, and symbol 306 in the case of reverse equalization. , 305 are tracked, and the equalized output is input to the output combining unit 210. In output coupling section 210, the output up to the pilot by amplitude and phase correction section 208 and the output after the pilot by DFE 203-2 are combined and output to terminal 212.

FIG. 12 is a diagram showing a computer simulation result of the equalization error in one embodiment of the present invention.
In FIG. 12, the latter half of the frame when the intensity difference between the delay wave 501 and the delay wave 502 in FIG. 5 is 3 dB and the time difference is T / 2 (T: symbol period, T = 1 / 11.25 kHz = 88.9 μs). Forward equalization of data (hereinafter referred to as forward equalization (1)), forward equalization of data in the first half of the frame (hereinafter referred to as forward equalization (2)), backward direction of the first half of the data, etc. FIG. 4 shows the computer-simulated error of equalization (hereinafter referred to as reverse equalization (1)) and reverse equalization of the latter half of the frame data (hereinafter referred to as reverse equalization (2)). is there.
For example, in the case of the condition of FIG. 12, when comparing the average of equalization errors of the forward equalization (2) and the reverse equalization (1) in the first half of the frame, the forward equalization (2) is the reverse direction. The equalization error is smaller than that of equalization (1). In the latter half of the frame data, the forward equalization error (1) is compared with the average of the equalization errors of the backward equalization (2) as in the first half of the frame data. Since equalization (1) has less equalization error than reverse equalization (2), equalization output by forward equalization is selected for both the first half frame data and the second half frame data.

FIG. 13 is a diagram showing a computer simulation result of the equalized output constellation in one embodiment of the present invention.
In FIG. 13, when the constellation for the selected output of the first frame data and the second frame data selected in FIG. 12 is confirmed, it can be confirmed that the constellation has converged in both the first frame data and the second frame data. .

  From the above, the forward equalization output of the second half frame data is accumulated in the forward output buffer 108 of FIG. 1, and the forward equalization output of the first half frame data is accumulated in the forward output buffer 109. Further, the reverse output buffer 110 stores the reverse equalization output of the first half frame data, and the reverse output buffer 111 stores the reverse output of the second frame data. After that, the output combining unit 112 compares the average of the equalization error in the forward equalization of the first half frame data with the average of the equalization error in the reverse equalization, and the equalization error in the forward equalization is more If it is smaller, the information stored in the forward output buffer 109 is selected as the equalized output of the first half of the frame data. If the equalization error in the backward equalization is smaller, the information is stored in the backward output buffer 110. Select stored information. Also, in the case of the latter half of the frame data, as in the case of the first half of the frame data, the average of the equalization error in the forward equalization is compared with the average of the equalization error in the backward equalization to equalize the forward equalization. When the error is small, information stored in the forward output buffer 108 is selected as the equalized output of the latter half of the frame data. When the equalization error of the backward equalization is smaller, the information is stored in the backward output buffer 111. Select stored information.

Then, the output combining unit 112 combines the selected first frame data and the selected second frame data to obtain a signal for one frame. When the SW 305 overlaps between the first half frame data and the second half frame data, for example, either one of the SW 305s can be used, or the average value of both SW 305s can be used.
Further, in the output combining unit 112, for example, only data (DATA) 302, 304, 306, and 308 portions can be combined.

  From the above, according to the embodiment of the present invention, it is possible to perform equalization processing in both directions for all data sections in the frame, so that the equalization error is smaller for all data sections. The output in the equalization direction can be selected, and the best equalization performance can be obtained.

  In addition, according to the embodiment of the present invention, for example, any frame can be implemented as long as it is a frame having data that becomes a known symbol and a pilot symbol in the frame. It is possible to provide an equalization processing method.

  Also, according to the embodiment of the present invention, a communication that is a signal format in which a synchronization word that is a known symbol is arranged at the center of a frame, there is a data section on both sides thereof, and a pilot symbol is arranged in each data section. In an equalizer mounted on a receiver used in the system, the equalizer performs forward equalization for processing all signals in a frame in the direction in which the time advances and reverse processing in the direction in which the time goes back. Two-way decision feedback equalization characterized by performing both direction equalization and selecting an equalization output with a smaller average equalization error from the forward equalization and the reverse equalization outputs The bidirectional decision feedback equalizer includes a forward equalization process for processing from the synchronization word toward the end of the frame, and a forward equalization process for processing from the beginning of the frame toward the synchronization word. Synchronous word Perform forward equalization processing from the beginning of the frame toward the beginning of the frame, and reverse equalization processing from the end of the frame toward the synchronization word, and forward processing from the beginning of the frame toward the synchronization word. The tap gain coefficient converged by the forward equalization processing that is processed from the synchronization word toward the end of the frame is converted into a pilot symbol (a pilot symbol ahead of the two pilot symbols in the frame). Correcting according to the equalization output, using this as the initial value of the tap gain coefficient, performing a forward equalization process, and processing from the end of the frame toward the sync word, The tap gain coefficient converged by the reverse equalization processing from the first to the beginning of the frame is changed to the pilot symbol (two pilots in the frame). Correction is performed according to the equalization output of the rear pilot symbols), and this is used as the initial value of the tap gain coefficient to perform reverse equalization processing, and equalization output for the data section ahead of the synchronization word Compares the average equalization error between the forward equalization processing processed from the head of the frame toward the synchronization word and the reverse equalization processing processed from the synchronization word toward the head of the frame. The output with the smaller error is selected, and the equalized output for the data section after the sync word is processed in the forward equalization process from the sync word toward the end of the frame, and from the end of the frame toward the sync word. By comparing the average equalization error of the reverse equalization processing to be processed and selecting the output having the smaller average equalization error, good equalization processing performance can be obtained.

  Further, according to the embodiment of the present invention, the forward equalization processing processed from the head of the frame toward the synchronization word is the tap gain converged by the forward equalization processing processed from the synchronization word toward the end of the frame. Using the coefficient, the equalizer output is obtained by directly feeding back the equalizer output to the feedback tap from the head of the frame toward the pilot symbol (the pilot symbol in the front of the two pilot symbols). , A value k obtained by multiplying the output value for the pilot symbol by the complex conjugate of the value p ′ obtained by dividing the output value for the pilot symbol by the square of the size of the symbol p at the time of transmission of the pilot symbol is obtained. Find the value g divided by the square of the magnitude, multiply the equalized output from the beginning of the frame to the pilot symbol by the complex conjugate of the value g, The tap gain coefficient obtained by multiplying the tap gain coefficient of the feedforward tap among the tap gain coefficients converged by the forward equalization processing that is processed from the synchronization word toward the end of the frame as the equalized output up to the pilot symbol is multiplied by the value g. As an initial value, forward equalization processing is performed from the symbol next to the pilot symbol toward the synchronization word, and backward equalization processing from the end of the frame toward the synchronization word is performed from the synchronization word toward the beginning of the frame. Using the tap gain coefficient after performing the reverse equalization process, the equalized output is output from the end of the frame toward the pilot symbol (the pilot symbol behind the two pilot symbols in the frame). In the equalized output, the output value for the pilot symbol is added to the output value for the pilot symbol. A value k obtained by multiplying a complex value obtained by dividing the Bol value p by the square of the magnitude of p is obtained, and g obtained by dividing the k by the square of the magnitude of k is obtained to equalize from the frame end to the pilot symbol. The output is multiplied by the complex conjugate of the value g to obtain an equalized output from the end of the frame to the pilot symbol, and is fed from the tap gain coefficients converged by the reverse equalization processing that is processed from the synchronization word toward the beginning of the frame. It is possible to perform a reverse equalization process from the symbol before the pilot symbol toward the synchronization word with the tap gain coefficient obtained by multiplying the tap gain coefficient of the forward tap by the value g as an initial value.

Here, an example of the connection relationship of each terminal shown in FIG. 2, FIG. 9, and FIG. 10 is shown.
2 is applied to the equalization processing unit 106, the signal from the forward buffer 102 is input to the terminal 201, the signal from the forward buffer 203 is input to the terminal 202, and the signal from the terminal 211 is input. The signal is output to the forward output buffer 108, and the signal from the terminal 212 is output to the forward output buffer 109.
2 is applied to the equalization processing unit 107, the signal from the backward buffer 104 is input to the terminal 201, the signal from the backward buffer 105 is input to the terminal 202, and the signal from the terminal 211 is The signal is output to the backward output buffer 110, and the signal from the terminal 212 is output to the backward output buffer 111.

When the configuration of FIG. 9 is applied to the DFE 203-1, a signal from the terminal 201 is input to the terminal 901, a signal from the terminal 902 is output to the tap gain coefficient buffer 205, and a signal from the terminal 916 (etc. Output) is output to the terminal 211, and a signal (information on error power) from the terminal 915 is output to the output coupling unit 112, for example. For example, an initial value of a predetermined tap gain coefficient may be input to the terminal 903.
When the configuration of FIG. 9 is applied to the DFE 203-2, a signal from the terminal 202 is input to the terminal 901, a signal (initial value of the tap gain coefficient) from the coefficient correction unit 209 is input to the terminal 903, A signal (equalized output) from the terminal 916 is output to the output coupling unit 210, and a signal (error power information) from the terminal 915 is output to the output coupling unit 112, for example. Note that the signal (tap gain coefficient) from the terminal 902 does not have to be input to other processing units.

  The configuration of FIG. 10 is applied to the non-judgment output feedback processing unit 204, a signal from the terminal 202 is input to the terminal 1001, a predetermined tap gain coefficient is input to the terminal 1002, and a signal from the terminal 1008 (equalized output) Is output to the buffer 206.

Configuration examples (1-1) to (1-4) in the present embodiment are shown.
(1-1) In an equalizer 15 for equalizing a received signal including a frame including a known symbol part (SW),
The equalizer 15 performs equalization processing based on a signal to be equalized and obtains an equalization processing result signal; and
A first storage function unit 103 that stores the known symbol (SW) included in the frame constituting the reception signal and the reception signal in front of the known symbol (SW) in a forward direction;
A second storage function unit 102 for storing, in the forward direction, the known symbol (SW) included in the frame constituting the reception signal and the reception signal behind the known symbol (SW);
A third storage function unit 104 for storing the known symbol (SW) included in the frame constituting the received signal and the received signal in front of the known symbol (SW) in reverse order;
A fourth storage function unit 105 for storing the known symbol (SW) included in the frame constituting the reception signal and the reception signal behind the symbol in reverse order;
Information stored in the first storage function unit 103 and the second storage function unit 102 is individually input, and all or a part of the known symbol part (SW) included therein is equalized. A first control function unit (for example, a control unit (not shown)) that performs forward equalization processing on each of the information input by the equalization function unit 106 as a target;
Information stored in the second storage function unit 104 and the fourth storage function unit 105 is individually input, and all or a part of the known symbol part (SW) included therein is equalized. And a second control function unit (for example, a control unit (not shown)) that performs reverse equalization processing on each of the information input by the equalization function unit 107 as a target. And an equalizer 15.

(1-2) In the equalizer 15 described in (1-1) above,
The equalizer 15 is configured such that the equalization processing result obtained by performing the forward equalization processing by the first control function unit and the equalization processing result obtained by performing the reverse equalization processing by the second control function unit. A comparison function unit 112 for comparing the error averages;
An equalizer 15 comprising: a combining function unit 112 that combines the equalization processing results compared by the comparison function unit 112.

(1-3) In the equalizer 15 described in (1-1) or (1-2) above,
The first control function unit inputs the stored contents stored in the forward direction by the first storage function unit 103 and the second storage function unit 102, and the known symbol part (SW ) Is repeated a plurality of times as a target for equalization processing, and forward equalization processing is performed by the equalization.
The second control function unit inputs the storage contents stored in reverse order by the third storage function unit 104 and the fourth storage function unit 105, and the known symbol part (SW) included in the stored contents The equalizer 15 is characterized in that a reverse equalization process is performed by the equalization using all or a part of the above as a target for the equalization process.

(1-4) In an equalizer 15 for equalizing a received signal including a frame including a known symbol part (SW),
The equalizer 15 performs an equalization process based on a signal to be equalized and obtains an equalization process result signal; and
A first storage step of storing the known symbol (SW) included in the frame constituting the received signal and the received signal in front of the known symbol (SW) in a forward direction;
A second storage step of storing the known symbol (SW) included in the frame constituting the received signal and the received signal behind the second symbol in a forward direction;
A third storage step of storing the known symbol (SW) included in the frame constituting the received signal and the received signal in front of the known symbol (SW) in reverse order;
A fourth storage step of storing the known symbol (SW) included in the frame constituting the reception signal and the reception signal behind the symbol in reverse order;
The information stored in the first storage step and the second storage step is individually input, and all or a part of the known symbol part (SW) included therein is used as an equalization processing target. A first control step of performing forward equalization processing on each of the information input by the equalization step;
The information stored in the third storage step and the fourth storage step is individually input, and all or a part of the known symbol part (SW) included therein is used as an equalization processing target. And a second control step for performing a backward equalization process on each of the information input in the equalization step.

  As described above, according to this embodiment, for example, when a known symbol part is included inside a frame, such as a frame in which an information part, a known symbol part, and an information part are arranged side by side, Effective equalization processing can be performed by effectively using forward equalization and reverse equalization for frame data. In addition, the frame constituting the received signal is divided into the first half portion and the second half portion of the frame including known symbols, and is subjected to equalization processing, for example, the number of symbols in the known symbol portion is small, and unidirectional equalization processing is performed. Even in the case where the equalization error becomes large, good equalization performance can be realized.

As described above, an equalizer capable of performing effective equalization processing in a frame configuration including a known symbol portion can be provided.
Specifically, the best equalization is performed by performing equalization in both directions for all data sections in the frame and selecting an output in the equalization direction with a smaller equalization error for all data sections. Performance can be obtained.

  Note that in the equalizer 15 of this example, the forward buffer 102 and the equalization processing unit 106 perform the equalization process in the forward direction on the signal (frame second half data) behind the known symbol portion (SW). The forward forward equalization processing means is configured by the forward buffer 103 and the equalization processing unit 106 to perform equalization processing in the forward direction with respect to the signal (first frame data) ahead of the known symbol portion (SW). The forward-forward equalization processing means is configured by the function of performing, and the reverse buffer 104 and the equalization processing unit 107 perform the reverse direction with respect to the signal (first frame data) ahead of the known symbol portion (SW). The forward reverse equalization processing means is configured by the function of performing the equalization processing, and the backward buffer 105 and the equalization processing unit 107 are behind the known symbol portion (SW). The backward reverse equalization processing means is configured by the function of performing the equalization process in the reverse direction on the signal (second half frame data), and the output combining unit 112 has a signal (frame) ahead of the known symbol part (SW). The forward acquisition means is configured by the function of acquiring the better equalization error among the equalization processing results stored in the forward output buffer 109 and the backward output buffer 110 for the first half data), and the output coupling unit The signal with the better equalization error is acquired from the equalization processing results stored in the forward output buffer 108 and the backward output buffer 111 for the signal 112 (second half frame data) behind the known symbol portion (SW). The backward acquisition means is constituted by the function to perform.

A second embodiment of the present invention will be described.
In the present embodiment, the description of the same configuration and operation as those of the first embodiment will be omitted or simplified, and mainly the configuration and operation different from those of the first embodiment will be described in detail.
For convenience of explanation, in the present embodiment, the same components as those in the first embodiment will be described with the same reference numerals.

Embodiments of the present invention will be described below with reference to the drawings.
The configuration of the receiver of FIG. 14 is the same as that of the first embodiment described above.
The frame configuration shown in FIG. 3 is the same as that of the first embodiment described above.

FIG. 15 is a block diagram showing the adaptive equalizer 15 in one embodiment of the present invention. The adaptive equalizer 15 performs equalization processing for one frame, and accumulates processing unit 101, forward buffers 102 and 103, reverse buffers 104 and 105, equalization processing unit 106, output buffers 116 and 117, and output combining unit. 112, training / forward / reverse direction determination unit 113, and switches 114 and 115.
The accumulation processing unit 101 controls accumulation in the forward buffers 102 and 103 and the backward buffers 104 and 105.
The training / forward / reverse determination unit 113 performs forward training of the synchronization word part (SW) signal of the forward buffer 102 and backward training of the synchronization word part (SW) of the backward buffer 104, and each direction. The equalization errors of the training results are compared, the tap gain coefficient trained in the direction in which the equalization error is small is selected and input to the equalization processing unit 106, and the selection result (“forward” or “reverse”) is selected. ) Is input to the switches 114 and 115 and the output coupling unit 112.

The switches 114 and 115 are switched in conjunction with selection information of “forward / reverse direction” input from the training / forward / reverse direction determination unit 113. When “forward” is selected, the terminals (a) and (c) are connected to both the switches 114 and 115, and the accumulation results of the forward buffer 102 and the forward buffer 103 are input to the equalization processing unit 106. When “reverse direction” is selected, both the switches 114 and 115 are connected to the terminals (b) and (c), and the accumulation results of the reverse buffer 104 and the reverse buffer 105 are input to the equalization processing unit 106.
The equalization processing unit 106 receives the data of the forward buffer 102 or the backward buffer 104 via the switch 114 and receives the data of the forward buffer 103 or the backward buffer 105 via the switch 115. The forward equalization process or the reverse equalization process is performed, the forward equalization output of the second half of the frame or the reverse equalization output of the first half of the frame is input to the output buffer 116, and the forward equalization output or the frame of the first half of the frame is input. The backward equalization output in the latter half is input to the output buffer 117.
When the training / forward / reverse determination unit 113 determines that the “forward direction” is selected, the output combining unit 112 reads the data in the output buffer 117 in the forward direction to obtain the first half of the frame data. Data is read in the forward direction to obtain data in the latter half of the frame, which are combined and output as one frame of data. If the training / forward / reverse direction determination unit 113 determines “reverse direction” and selects, the data in the output buffer 116 is read in the reverse direction to be the first half frame data, and the data in the output buffer 117 is the reverse direction. Are combined into the data in the latter half of the frame, and these are combined and output as one frame of data.

Note that when the output combining unit 112 combines the first frame data and the second frame data to acquire a signal for one frame, if the SW 305 overlaps with the first frame data and the second frame data, for example, either One SW 305 can be employed, or the average value of both SW 305 can be used.
Further, in the output combining unit 112, for example, only data (DATA) 302, 304, 306, and 308 portions can be combined.

The accumulation in the forward buffers 102 and 103 and the backward buffers 104 and 105 in FIG. 7 is the same as in the case of the first embodiment described above.
FIG. 16 is a block diagram illustrating a configuration example of the equalization processing unit 106 according to an embodiment of the present invention. The configuration and operation of the equalization processing unit 106 of this example are the same as those of the first embodiment shown in FIG. 2 except that the terminal 213 is provided.
The configuration and operation of the decision feedback equalizers (DFE) 203-1 and 203-2 in FIG. 9 are the same as those in the first embodiment described above.
The configuration and operation of the non-judgment output feedback processing unit 204 in FIG. 10 are the same as in the case of the first embodiment described above.

FIG. 17 is a diagram illustrating processing operations of the training / forward / reverse direction determination unit 113 and the equalization processing unit 106 according to an embodiment of the present invention.
The training / forward / reverse determination unit 113 performs forward training and backward training of the synchronization word (SW), and the equalization processing unit 106 performs forward equalization of the first half frame data and the second half frame data according to the result. Reverse direction equalization is performed.

The training / forward / reverse direction determination unit 113 inputs the synchronization word (SW) portion signal of the forward buffer 102 in the forward direction with respect to the time axis, for example, an arbitrary number of times (for example, 16) according to the coefficient update algorithm. Repeat the training only once. Subsequently, the synchronization word (SW) portion signal of the backward buffer 104 is input in a direction going back the time axis, and similarly, training is performed by repeating an arbitrary number of times.
Then, the training / forward / reverse direction determination unit 113 compares the equalization errors obtained as a result of the training in the respective directions. If the equalization error due to the forward training is smaller, the training / forward / reverse direction determination unit 113 performs forward processing in the subsequent processes. Control is performed so that the direction equalization process is performed. If the equalization error due to the backward training is smaller, control is performed so that the reverse direction equalization process is performed in the subsequent processes.

When the forward equalization process is performed, the tap gain coefficient obtained by the forward training obtained by the training / forward / reverse determination unit 113 is input as an initial value from the terminal 213 of the equalization processing unit 106. Tracking is performed for the data of the leading data 802 to 803 (except for the SW 305), that is, the data of the symbols 306, 307, and 308. This tracking process is performed by the DFE 203-1.
When performing the reverse equalization process, the tap gain coefficient by the reverse training obtained by the training / forward / reverse direction determination unit 113 is input as an initial value from the terminal 213 of the equalization processing unit 106, and first, ( Tracking is performed on the input signals 802 to 803 for the data 802 to 803 as the end data (that is, the data of the symbols 304, 303, and 302) (excluding SW305).

  When performing wireless communication using an embodiment of the present invention, the equalization processing in the case where a frequency deviation occurs between the transmitting and receiving station oscillators is described with reference to FIG. This is the same as described using Equation 2.

FIG. 18 is a diagram showing a computer simulation result of the equalization error in one embodiment of the present invention.
In FIG. 18, the synchronization word when the intensity difference between the delay wave 501 and the delay wave 502 in FIG. 5 is 3 dB and the time difference is T / 2 (T: symbol period, T = 1 / 11.25 kHz = 88.9 μs). The equalization error due to the forward and backward training of the (SW) part and the equalization error of the forward equalization of the data part selected based on the training result are obtained by computer simulation. The first half of the frame is shown as forward equalization (2), and the second half of the frame is shown as forward equalization (1).
For example, in the case of the condition of FIG. 18, the training result of the synchronization word (SW) part has less equalization error in the forward training than in the backward training, and the forward equalization is performed on the data section. Is called.
The computer simulation result of the equalized output constellation in FIG. 13 is the same as in the case of the first embodiment described above.

In the above case, the forward equalized output of the second half frame data is accumulated in the output buffer 116 of FIG. 15, and the forward equalized output of the first half frame data is accumulated in the output buffer 117.
Then, the output combining unit 112 reads out the first half frame data stored in the output buffer 117 and the second frame data stored in the output buffer 116 in the forward direction, and outputs the combined data as one frame data. .

On the other hand, when the reverse equalization is performed, the reverse equalization output of the first half frame data is accumulated in the output buffer 116 of FIG. 15, and the reverse equalization output of the second half frame data is accumulated in the output buffer 117. Is done.
Then, in the output combining unit 112, the first half frame data accumulated in the output buffer 116 and the second half frame data accumulated in the output buffer 117 are read out in opposite directions, combined and output as one frame data. .

  From the above, according to the embodiment of the present invention, it is possible to select the equalization direction in which the equalization error becomes smaller when training with the synchronization word (SW) portion signal in the frame, and for all the data sections, Equalization processing can be performed in an equalization direction with smaller equalization errors, and the best equalization performance can be obtained.

  In addition, according to the embodiment of the present invention, for example, any frame can be implemented as long as it is a frame having data that becomes a known symbol and a pilot symbol in the frame. It is possible to provide an equalization processing method.

Also, according to the embodiment of the present invention, a communication that is a signal format in which a synchronization word that is a known symbol is arranged at the center of a frame, there is a data section on both sides thereof, and a pilot symbol is arranged in each data section. In the equalizer mounted on the receiver used in the system, the equalizer performs forward training for processing in the direction of time advance and backward training for processing in the direction of time backward for the synchronization word in the frame. To compare the equalization error between the forward training and the backward training, select the training result with the smaller equalization error, and equalize with the training for all signals in the frame An equalizer that performs an equalization process in a direction in which an error is reduced. When the equalization error due to the forward training is smaller than the equalization error due to the backward training, the forward equalization processing is performed from the synchronization word toward the end of the frame, and from the head of the frame toward the synchronization word. The forward equalization processing for processing from the beginning of the frame toward the synchronization word is performed by the tap equalized by the forward equalization processing from the synchronization word toward the end of the frame. The gain coefficient is corrected according to the equalization output in the pilot symbol (the pilot symbol in front of the two pilot symbols in the frame), and this is used as the initial value of the tap gain coefficient to perform forward equalization processing. Do. When the equalization error due to the backward training is smaller than the equalization error due to the forward training, the backward equalization processing is performed from the synchronization word toward the beginning of the frame, and from the end of the frame toward the synchronization word. Taps converged by backward equalization processing from the synchronization word toward the beginning of the frame. The gain coefficient is corrected according to the equalization output in the pilot symbol (the pilot symbol behind the two pilot symbols in the frame), and this is used as the initial value of the tap gain coefficient to perform the reverse equalization process. Do. As a result, equalization processing in an optimal direction is performed on all signals in the frame, and thus good equalization processing performance can be obtained.
Further, according to the embodiment of the present invention, the optimum equalization direction (forward equalization / reverse equalization) is determined at the time of training in the synchronization word in the frame, and the optimum for the data section. Since only the direction equalization processing is performed, the amount of processing can be reduced.

  Further, according to the embodiment of the present invention, the forward equalization processing processed from the head of the frame toward the synchronization word is the tap gain converged by the forward equalization processing processed from the synchronization word toward the end of the frame. Using the coefficient, the equalizer output is obtained by directly feeding back the equalizer output to the feedback tap from the head of the frame toward the pilot symbol (the pilot symbol in the front of the two pilot symbols). , A value k obtained by multiplying the output value for the pilot symbol by the complex conjugate of the value p ′ obtained by dividing the output value for the pilot symbol by the square of the size of the symbol p at the time of transmission of the pilot symbol is obtained. Find the value g divided by the square of the magnitude, multiply the equalized output from the beginning of the frame to the pilot symbol by the complex conjugate of the value g, The tap gain coefficient obtained by multiplying the tap gain coefficient of the feedforward tap among the tap gain coefficients converged by the forward equalization processing that is processed from the synchronization word toward the end of the frame as the equalized output up to the pilot symbol is multiplied by the value g. As an initial value, forward equalization processing is performed from the symbol next to the pilot symbol toward the synchronization word, and backward equalization processing from the end of the frame toward the synchronization word is performed from the synchronization word toward the beginning of the frame. Using the tap gain coefficient after performing the reverse equalization process, the equalized output is output from the end of the frame toward the pilot symbol (the pilot symbol behind the two pilot symbols in the frame). In the equalized output, the output value for the pilot symbol is added to the output value for the pilot symbol. A value k obtained by multiplying a complex value obtained by dividing the Bol value p by the square of the magnitude of p is obtained, and g obtained by dividing the k by the square of the magnitude of k is obtained to equalize from the frame end to the pilot symbol. The output is multiplied by the complex conjugate of the value g to obtain an equalized output from the end of the frame to the pilot symbol, and is fed from the tap gain coefficients converged by the reverse equalization processing that is processed from the synchronization word toward the beginning of the frame. It is possible to perform a reverse equalization process from the symbol before the pilot symbol toward the synchronization word with the tap gain coefficient obtained by multiplying the tap gain coefficient of the forward tap by the value g as an initial value.

Here, an example of the connection relationship of each terminal shown in FIG. 16, FIG. 9, and FIG. 10 is shown.
The configuration of FIG. 16 is applied to the equalization processing unit 106, a signal from the switch 114 is input to the terminal 201, a signal from the switch 115 is input to the terminal 202, and a signal from the terminal 211 is output to the output buffer 116. The signal from the terminal 212 is output to the output buffer 117, and the signal (initial value of the tap gain coefficient) from the training / forward / reverse direction determination unit 113 is input to the terminal 213.

9 is applied to the DFE 203-1, the signal from the terminal 201 is input to the terminal 901, the signal from the terminal 902 is output to the tap gain coefficient buffer 205, and the signal from the terminal 213 is the terminal. The signal (equalized output) from the terminal 916 is output to the terminal 211. Note that the signal (error power information) from the terminal 915 may not be input to other processing units.
When the configuration of FIG. 9 is applied to the DFE 203-2, a signal from the terminal 202 is input to the terminal 901, a signal (initial value of the tap gain coefficient) from the coefficient correction unit 209 is input to the terminal 903, A signal (equalized output) from the terminal 916 is output to the output coupling unit 210. Note that the signal (tap gain coefficient) from the terminal 902 does not have to be input to other processing units. Further, a signal (error power information) from the terminal 915 may not be input to another processing unit.

  The configuration of FIG. 10 is applied to the non-judgment output feedback processing unit 204, a signal from the terminal 202 is input to the terminal 1001, a predetermined tap gain coefficient is input to the terminal 1002, and a signal from the terminal 1008 (equalized output) Is output to the buffer 206.

Configuration examples (2-1) to (2-3) in the present embodiment are shown.
(2-1) In the equalizer 15 for equalizing a received signal including a frame including a known symbol part (SW),
The equalizer 15 performs equalization processing based on a signal to be equalized and obtains an equalization processing result signal; and
A first storage function unit 103 that stores the known symbol (SW) included in the frame constituting the reception signal and the reception signal in front of the known symbol (SW) in a forward direction;
A second storage function unit 102 for storing, in the forward direction, the known symbol (SW) included in the frame constituting the reception signal and the reception signal behind the known symbol (SW);
A third storage function unit 104 for storing the known symbol (SW) included in the frame constituting the received signal and the received signal in front of the known symbol (SW) in reverse order;
A fourth storage function unit 105 for storing the known symbol (SW) included in the frame constituting the reception signal and the reception signal behind the symbol in reverse order;
The information stored in the second storage function unit 102 is input, and the equalization function unit 113 uses all or part of the known symbol part (SW) included therein as an equalization target. A first control function unit (for example, a control unit (not shown)) that performs forward equalization processing (training);
The information stored in the third storage function unit 104 is input, and the equalization function unit 113 uses all or part of the known symbol part (SW) included in the information as an object to be equalized. A second control function unit (for example, a control unit (not shown)) that performs reverse direction equalization processing (training);
A comparison function for comparing an equalization error between an equalization process result obtained by performing a forward equalization process by the first control function unit and an equalization process result obtained by performing a reverse equalization process by the second control function unit Part 113;
Depending on the comparison result of the comparison function unit 113, information stored in the first storage function unit 103 and the second storage function unit 102 or the third storage function unit 104 and the fourth storage function unit 105 A third control function unit that individually inputs the information stored in the information and performs a forward equalization process or a reverse equalization process (tracking) on each of the information input by the equalization function unit 106 (E.g., a control unit (not shown)).

(2-2) In the equalizer 15 described in (2-1) above,
The first control function unit inputs the stored contents stored in the forward direction by the second storage function unit 102, and a plurality of all or part of the known symbol parts (SW) included therein are input. The equalization function unit 113 performs forward equalization processing (training) by repeatedly using it as an equalization processing target,
The second control function unit inputs the stored contents stored in reverse order by the third storage function unit 104, and all or a part of the known symbol part (SW) included in the stored contents is stored a plurality of times. An equalizer 15 characterized in that it is repeatedly used as an equalization target and subjected to backward equalization processing (training) by the equalization function unit 113.

(2-3) In an equalizer 15 for equalizing a received signal including a frame including a known symbol part (SW),
The equalizer 15 performs an equalization process based on a signal to be equalized and obtains an equalization process result signal; and
A first storage step of storing the known symbol (SW) included in the frame constituting the received signal and the received signal in front of the known symbol (SW) in a forward direction;
A second storage step of storing the known symbol (SW) included in the frame constituting the received signal and the received signal behind the second symbol in a forward direction;
A third storage step of storing the known symbol (SW) included in the frame constituting the received signal and the received signal in front of the known symbol (SW) in reverse order;
A fourth storage step of storing the known symbol (SW) included in the frame constituting the reception signal and the reception signal behind the symbol in reverse order;
The information stored in the second storage step is input, and all or a part of the known symbol part (SW) included in the information is used as an equalization target, and forward equalization is performed in the equalization step. A first control step for performing processing (training);
The information stored in the third storage step is input, and all or a part of the known symbol part (SW) included in the information is used as an equalization target, and the equalization process is performed in the reverse direction. A second control step for performing processing (training);
A comparison step for comparing an equalization error between an equalization process result obtained by performing a forward equalization process in the first control step and an equalization process result obtained by performing a reverse equalization process in the second control step;
Depending on the result of the comparison step, the information stored in the first storage step and the second storage step or the information stored in the third storage step and the fourth storage step are individually input. And a third control step for performing a forward equalization process or a reverse equalization process (tracking) on each of the information input in the equalization step. Method.

  As described above, according to this embodiment, for example, when a known symbol part is included inside a frame, such as a frame in which an information part, a known symbol part, and an information part are arranged side by side, Effective equalization processing can be performed by performing equalization in the optimal direction of the forward equalization or reverse equalization on the frame data. Also, by determining the optimal equalization direction in training with known symbols and performing only equalization processing in the optimal equalization direction for frame data, the amount of processing required for equalization processing is reduced. Can do.

As described above, an equalizer capable of performing effective equalization processing in a frame configuration including a known symbol portion can be provided.
Specifically, equalization processing in both directions is performed on a known symbol portion in the frame, an equalization direction with a smaller equalization error is selected, and more equalization error is performed on the data section in the frame. It is possible to obtain the best equalization performance by performing equalization processing in a small equalization direction.

  Here, in the present embodiment, accumulation as shown in FIG. 7 and FIG. 17 is performed in each of the forward buffers 102 and 103 and each of the backward buffers 104 and 105. However, this is one configuration example, A configuration may be used. For example, in this embodiment, the training is performed by inputting the synchronization word (SW) 305 included in the signals accumulated in the forward buffer 102 and the backward buffer 104 to the training / forward / reverse determination unit 113. However, as another configuration example, another buffer for storing a signal of the synchronization word (SW) 305 for training may be provided and input from the buffer to the training / forward / reverse determination unit 113. Good.

  In the equalizer 15 of this example, the symbol forward direction equalization processing means is provided by the function that the training / forward / reverse direction determination unit 113 performs equalization processing (training) in the forward direction for the known symbol portion (SW). The symbol reverse equalization processing means is configured by the function that the training / forward / reverse direction determination unit 113 performs equalization processing (training) in the reverse direction for the known symbol portion (SW). The direction selection means has a function of selecting a better direction based on an error in the forward and reverse equalization processing performed for the known symbol portion (SW) by the training / forward / reverse direction determination unit 113. The switches 114, 115 and the signals stored in the forward buffers 102, 103 or the backward buffers 104, 105 Equalization processing unit 106, output buffers 116, 117, and output combination unit 112 perform signal equalization processing by the function of performing equalization processing in the direction (forward direction or reverse direction) selected by training / forward / reverse direction determination unit 113 Means are configured.

Here, the configuration of the system and apparatus according to the present invention is not necessarily limited to the configuration described above, and various configurations may be used. The present invention can also be provided as, for example, a method or method for executing the processing according to the present invention, a program for realizing such a method or method, or a recording medium for recording the program. It is also possible to provide various systems and devices.
The application field of the present invention is not necessarily limited to the above-described fields, and the present invention can be applied to various fields.
In addition, as various processes performed in the system and apparatus according to the present invention, for example, the processor executes a control program stored in a ROM (Read Only Memory) in hardware resources including a processor and a memory. A controlled configuration may be used, and for example, each functional unit for executing the processing may be configured as an independent hardware circuit.
The present invention can also be understood as a computer-readable recording medium such as a floppy (registered trademark) disk or a CD (Compact Disc) -ROM storing the control program, and the program (itself). The processing according to the present invention can be performed by inputting the program from the recording medium to the computer and causing the processor to execute the program.

Z1, Z2,... Terminal, 1. demodulator, 2. demodulator, 11. RF unit, 12. A / D converter, 13. quadrature demodulator, 14. receive filter, 15 ... Adaptive equalizers,
101 ··· Accumulation processing unit, 102, 103 · · Forward buffer, 104, 105 · · Reverse buffer, 106, 107 · · Equalization processing unit, 108, 109 · · Forward output buffer, 110, 111 ··· Reverse output buffer, 112..
201, 202, 211, 212,..., 203, ・ Decision feedback equalizer (DFE), 204, ・ Non-deterministic output feedback processor, 205, ・ Tap gain coefficient buffer, 206 ・ ・ Buffer, 207 ・・ Amplitude and phase correction coefficient calculation section (amplitude and phase correction coefficient calculation section), 208 ・ ・ Amplitude and phase correction section (amplitude and phase correction section), 209 ・ ・ Coefficient correction section, 210 ・ ・ Output coupling section,
301 .. Ramp time for burst transient response, 302, 304, 306, 308 .. data, 303, 307 .. pilot, 305 .. sync word, 309 .. guard time,
501, 502.. Delayed wave,
701-704 .. position,
801-806 .. position,
901, 902, 903, 915, 916 ... terminal, 904, 905 ... delay circuit, 906, 907 ... complex multiplier, 908 ... complex adder, 909 ... complex subtractor, 910 ... error power calculation 911... Symbol determination unit 912... Switch 913... Synchronous word symbol storage memory 914.
1001, 1002, 1008 .. terminal, 1003, 1004 .. delay circuit, 1005, 1006 .. complex multiplier, 1007 .. complex adder,
113 ··· Training · Forward / reverse direction determination unit, 114, 115 · · Switch, 116, 117 · · Output buffer,
213 .. terminal,

Claims (3)

In an equalizer for equalizing a received signal consisting of a frame in which one synchronization word which is a known symbol part is arranged in the center and pilot symbols are arranged on both sides of the synchronization word,
An equalization means for performing equalization processing based on a signal to be equalized and obtaining a signal of an equalization processing result;
First storage means for storing, in the forward direction, the synchronization word included in the frame constituting the reception signal and the reception signal in front of the synchronization word;
Second storage means for storing, in the forward direction, the synchronization word included in the frame constituting the reception signal and the reception signal behind the synchronization word;
Third storage means for storing the synchronization word included in the frame constituting the reception signal and the reception signal ahead thereof in reverse order;
A fourth storage means for storing the synchronization word included in the frame constituting the reception signal and the reception signal behind the synchronization word in reverse order;
The information stored in the second storage means is input, and the equalization means performs forward equalization processing using all or part of the synchronization word portion included in the information as an equalization target. 1 control means;
The information stored in the third storage means is input, and all or a part of the synchronization word part included in the information is used as an equalization target to perform reverse equalization processing by the equalization means. Two control means;
A comparison means for comparing an equalization error between an equalization process result obtained by performing a forward equalization process by the first control means and an equalization process result obtained by performing a reverse equalization process by the second control means;
Depending on the comparison result of the comparison means, the information stored in the first storage means and the second storage means or the information stored in the third storage means and the fourth storage means are individually input. Te, e Bei and a third control means for performing a forward equalization or backward equalization processing for each of the information the input by the equalizing means,
The third control means includes
When the forward equalization process is performed on the information stored in the first storage unit, the phase of the tap gain coefficient converged by the forward equalization process by the first control unit is corrected, and the tap gain coefficient is corrected. A forward equalization process is performed by the equalization means as an initial value of the coefficient,
When performing reverse equalization processing on the information stored in the fourth storage means, the phase of the tap gain coefficient converged by the reverse equalization processing by the second control means is corrected, and this is used as tap gain. A reverse equalization process is performed by the equalization means as an initial value of the coefficient,
An equalizer characterized by that. The equalizer of claim 1, wherein
The first control means receives the stored contents stored in the forward direction by the second storage means, and repeats all or part of the synchronization word part included therein for multiple equalization processing targets. To perform forward equalization processing by the equalization means,
The second control means inputs the storage contents stored in the reverse order by the third storage means, and repeats all or part of the synchronization word part included therein for multiple equalization processing targets. Using the equalization means to perform reverse equalization processing,
An equalizer characterized by that.   The equalizer according to claim 1 or 2,
  The third control means includes
    When performing forward equalization processing on the information stored in the first storage means, the tap gain coefficient converged by the forward equalization processing by the first control means is used as the initial value, and the first The information stored in the storage means is subjected to forward equalization processing up to the pilot symbol, and the value of the pilot symbol in the result is divided by the square of the size of the symbol p at the time of transmitting the pilot symbol. By obtaining a value k obtained by multiplying the conjugate, obtaining a value g obtained by dividing the value k by the square of the magnitude of the value k, and multiplying the tap gain coefficient of the feedforward tap in the converged tap gain coefficient by the value g. A pilot symbol in the information stored in the first storage means by correcting the phase of the tap gain coefficient of the feedforward tap and using the corrected tap gain coefficient as an initial value. It performs a forward equalization process from the next symbol,
    When performing reverse equalization processing on the information stored in the fourth storage means, the tap gain coefficient converged by the reverse equalization processing by the second control means is used as an initial value, and the fourth The information stored in the storage means is subjected to backward equalization processing up to the pilot symbol, and the value of the pilot symbol in the result is divided by the square of the size of the symbol p at the time of transmitting the pilot symbol. By obtaining a value k obtained by multiplying the conjugate, obtaining a value g obtained by dividing the value k by the square of the magnitude of the value k, and multiplying the tap gain coefficient of the feedforward tap in the converged tap gain coefficient by the value g. A pilot symbol in the information stored in the fourth storage means by correcting the phase of the tap gain coefficient of the feedforward tap and using the corrected tap gain coefficient as an initial value. Performing backward equalization processing from the previous symbol,
  An equalizer characterized by that.

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