JP5478415B2 - Deviation detection apparatus and method - Google Patents

Description

  The present invention relates to a digital transmission system for accommodating a client signal in a digital frame and transmitting it. The present invention relates to an apparatus and a method for detecting a frequency deviation between a clock of a client signal and a clock of a transmission frame particularly when accommodating the client signal asynchronously.

  As a multiplexing hierarchy of a photonic transport network that efficiently transfers client signals over a wide area, OTN (Optical Transport Network) is recommended as a standardization technology by ITU-T (Non-patent Document 1). OTN is able to efficiently transfer client signals over a wide area by using an operation and monitoring system that incorporates the concept of optical paths and the FEC (Forward Error Correction) function. Ethernet (registered trademark), which has been widely used for legacy digital networks such as SDH / SONET (Synchronous Digital Hierarchy / Synchronous Optical Network), LAN (Local Area Network), WAN (Wide Area Network), etc. The GMP (Generic Mapping Procedure) and ODUflex (Optical Data Channel Unit flex) were newly defined in 2009, and client signals other than the above signals are also uniquely accommodated in OTN. It became possible to do. GMP is a method for general-purpose mapping of client signals of any bit rate to OTN frames. ODUflex is a conventional ODU0 (1.25 Gbit / s), ODU1 (2.5 Gbit / s), ODU2 (10 Gbit / s) ), ODU3 (40 Gbit / s), ODU4 (100 Gbit / s), and an ODU frame that can provide a payload of an arbitrary bit rate in units of 1.25 Gbit / s.

  In recent years, with the expansion of ICT services, demand for wide-area transport networks has been increasing year by year, and client signals accommodated in OTN are becoming increasingly diverse. The Fiber Channel that connects the storage in the data center can connect storage between different bases by transferring over a wide area using OTN. In addition, SDI (Serial Digital Interface) that connects video devices can directly transmit uncompressed video signals to different locations by using OTN.

JP 2008-92408 A

ITU-T G.709 "Interfaces for the Optical Transport Network (OTN)"

  In OTN, stuff processing is performed to absorb a frequency deviation generated between the clock of the client signal and the clock of the transmission frame when accommodating the client signal asynchronously. OTN has a stuff area to absorb the frequency deviation of ± 20 ppm or ± 100 ppm, and justify adjusting the bits in the frame according to the frequency deviation between the clock of the client signal and the clock of the transmission frame. Fication control processing (hereinafter referred to as JC processing) is performed. At the receiving end of the OTN frame, when restoring the client signal from the OTN frame, stuff bytes are removed by JC processing. The removal of the stuff byte is normally controlled by inputting the data of the OTN frame into a FIFO (First In First Out) memory and reading out only the data of the client signal. Usually, the clock of the client signal used for reading is reproduced from the missing data sequence from which the stuff bytes are removed, so that destuffing jitter due to phase fluctuation occurs. Destuff jitter includes jitter of low frequency components, so it is difficult to suppress it with PLL (Phase Locked Loop), etc., and it is difficult to accommodate video signals with severe jitter specifications in OTN due to the influence of destuff jitter It is. In order to suppress the destuffing jitter, it is necessary to narrow the PLL loop filter. However, when the bandwidth is narrowed, it takes time until synchronization. In addition, since the sensitivity is reduced due to the narrowing of the band, there may be a problem that synchronization is not achieved. On the other hand, as another approach for suppressing destuffing jitter, a method of transmitting a frequency deviation between a client signal clock and a transmission frame clock and regenerating the client signal clock based on the frequency deviation is considered. Therefore, it is necessary to detect the frequency deviation at high speed and with high accuracy. Patent Document 1 describes a frequency deviation detection method for accommodating client signals asynchronously in a transmission frame. In Patent Document 1, as shown in FIG. 1, the clock A of the client signal is counted up to a certain value by the first counter 11 and the clock B of the transmission frame is counted using the second counter 12 in the counted period. To do. The frequency deviation is detected by comparing the value counted by the second counter 12 by the comparator 13. The nominal value of the clock frequency of the client signal and the clock frequency of the transmission frame is known, the value output from the comparator 13 is stored in the shift register 14, the sum of the values measured in the past is taken, and the numerical value conversion unit 15 The frequency deviation is detected by averaging processing. In the above method, it is difficult to speed up the frequency deviation detection because the measurement results of a plurality of times are averaged.

  Accordingly, an object of the present invention is to provide a deviation detecting apparatus and method capable of detecting a frequency deviation between a clock of a transmission frame and a clock of a client signal with high accuracy and high speed in view of the above problems. .

  In order to solve the above problems, one aspect of the present invention is a deviation detection device that detects a frequency deviation between a clock of a client signal and a clock of a transmission frame, and a first counter that counts the clock of the client signal; A phase shifter that gives a plurality of phase differences to the clock of the transmission frame, a second counter that counts in parallel each clock of the transmission frame to which the plurality of phase differences are given, and the second counter output An addition processing unit for adding the count values of the respective clocks, and averaging the added total count values by the number of clocks of the transmission frame to which the plurality of phase differences are given, and calculating the calculated average value as the frequency deviation The deviation detection apparatus has an average processing unit that outputs the difference as an error.

  Another aspect of the present invention is a deviation detecting method for detecting a frequency deviation between a clock of a client signal and a clock of a transmission frame, wherein the first counter counts the clock of the client signal, and the count value is set to a predetermined value. A step of determining whether or not the count value has reached a predetermined value, the second counter counts in parallel each clock of the transmission frame to which a plurality of phase differences have been added, and The step of outputting each count value when the count value of the first counter next reaches the predetermined value, the step of adding the count value of each clock output from the second counter, and the added sum The count value is averaged by the number of clocks of the transmission frame to which the plurality of phase differences are added, and the calculated average value is calculated in advance. Relating to a deviation detecting method and a step of outputting a frequency deviation.

  According to the present invention, the frequency deviation between the clock of the transmission frame and the clock of the client signal can be detected with high accuracy and high speed.

FIG. 1 shows a conventional frequency deviation detection circuit. FIG. 2 shows a frequency deviation detection circuit according to the first embodiment of the present invention. FIG. 3 shows a frequency deviation detection circuit according to the second embodiment of the present invention. FIG. 4 shows a mapping circuit using the frequency deviation detection circuit according to the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  The frequency deviation detection circuit according to the first embodiment of the present invention will be described with reference to FIG. In the frequency deviation detection circuit according to the first embodiment, a configuration for counting each clock of the transmission frame to which the phase difference is added is provided in parallel corresponding to each phase difference given to the clock. As a result, multiple clocks with different phase differences are derived in parallel from the clock of the transmission frame, multiple count values are obtained from these multiple clocks, and the number of counts obtained by averaging the obtained multiple count values By using the frequency deviation according to the above, it becomes possible to detect the frequency deviation with higher accuracy at high speed.

FIG. 2 shows a configuration as an example of a frequency deviation detection circuit according to the first embodiment. 2, the frequency deviation detection circuit 100 includes a first counter 110 ₁ , 110 ₂ , 110 ₃ ,..., A second counter 120 ₁ , 120 ₂ , 120 ₃ ,. Shifters 130 ₁ , 130 ₂ , 130 ₃ ,..., An addition processing unit 140, and an average processing unit 150.

The first counters 110 ₁ , 110 ₂ , 110 ₃ ,... Count the clocks of the input client signals for a certain period, and when they reach a predetermined count value, the second counters 120 ₁ , 120 ₂ , 120 _3. Output trigger signal to.

The second counters 120 ₁ , 120 ₂ , 120 ₃ ,... Start counting from the trigger signals received from the first counters 110 ₁ , 110 ₂ , 110 ₃ ,. Until input, the transmission frame clocks supplied from the phase shifters 130 ₁ , 130 ₂ , 130 ₃ ,... Are counted.

The phase shifters 130 ₁ , 130 ₂ , 130 ₃ ,... Add different phase differences of 0 to 2π to the clock of the transmission frame. For example, when N second counters 120 are used, the transmission frame clocks are (1 / N) · 2π, (2 / N) · 2π, ..., ((N-1) / N) · 2π, respectively. , 2π phase difference is given. Each count value counted by the second counters 120 ₁ , 120 ₂ , 120 ₃ ,... Is passed to the addition processing unit 140.

  The addition processing unit 140 adds the received count values and passes the added total count value to the average processing unit 150.

  The average processing unit 150 detects the frequency deviation by averaging the values output from the addition processing unit 140 by N.

In the present embodiment, in the second counter 120, a phase is added to the clock of the transmission frame input from the phase shifter 130. Therefore, the measurement value counted by the second counter 120 is Fc as the clock frequency of the client and Fo as the clock frequency of the transmission frame.
INT (Fo / Fc) or INT ((Fo / Fc) +1)
(However, INT indicates the minimum integer value of the argument). The measured values given from the second counters 120 ₁ , 120 ₂ , 120 ₃ ,... Are added and averaged by the total number N of the second counters 120 (INT (Fo / Fc)) × x1 + INT ((Fo / Fc) +1) x2) / N
Is detected as a frequency deviation. Note that x1 and x2 indicate the number of second counters whose count values output from the second counter 120 are INT (Fo / Fc) and INT ((Fo / Fc) +1), respectively.

  As a specific example, a frequency deviation detection method when STM-64 (9.95 Gbit / s) is accommodated in OTU2 (10.07 Gbit / s) will be described as an example. Normally, the upper limit of the frequency that can be handled by an integrated circuit such as an FPGA or ASIC is about several hundred MHz, so the clock of the STM-64 signal and the OTU2 signal is divided by 64 respectively (STM-64: 9.95 Gbit / s ÷ 64 = 155.52 MHz, OTU2: 10.7 Gbit / s ÷ 64 = 167.49 MHz). When the frequency deviation detection range is set to the standard ± 20 ppm, for example, the number of client signal clocks observed within 12.19 us per frame time is 155.52 MHz x ( Since 1−20 ppm) × 12.19 us = 1895.75, it is 1895 or 1896. When the frequency deviation is +20 ppm, 155.52 MHz × (1 + 20 ppm) × 12.19 us = 1895.83, so 1895 or 1896. Here, assuming that the number of clocks measured by the first counter 110 is 1895, the number of clocks of the transmission frame to be measured is 1895 × 255/237 = 2038.92, and the maximum value and the minimum value are 2038.92 × (1 + 20 ppm) = 2038.96. Since 208.992 × (1−20 ppm) = 2038.88, the counted value is 2038 or 2039. These are counted in parallel by N counters, and an average process is performed on the added result. When N = 10, the added value takes a value in the range of 20380 to 20390, and a frequency deviation of about 1 / 20380≈50 ppm can be detected for every change.

  In the first embodiment, the phase difference is given to the clock of the transmission frame. However, the frequency deviation can be detected in the same manner even when the phase difference is given to the clock of the client signal. In this case, the first counter 110 receives the transmission frame, counts the clock signal of the transmission frame, and the phase shifter 130 receives the clock of the client signal and provides a phase difference.

  In FIG. 2, a plurality of phase shifters 130 are provided according to the number of phase differences to be applied, but the present invention is not limited to this. That is, when a phase shifter that can simultaneously output a plurality of phase differences to an input clock and output a clock with a plurality of phase differences is used, the number of one or the number of phase differences to be applied A small number of phase shifters may be utilized.

Next, a frequency deviation detection circuit according to the second embodiment of the present invention will be described with reference to FIG. In the frequency deviation detection circuit according to the second embodiment, the first counter 110 ₁ , 110 ₂ , 110 ₃ ,... Corresponds to each phase difference given to the clock of the transmission frame by the frequency deviation detection circuit according to the first embodiment. Are provided in common, and one first counter is used. Thereby, since the first counter is shared, a more simplified frequency deviation detection circuit is possible.

FIG. 3 shows a configuration as an example of a frequency deviation detection circuit according to the second embodiment. 3, the frequency deviation detection circuit 200 includes a first counter 210, second counters 220 ₁ , 220 ₂ , 220 ₃ ,..., And phase shifters 230 ₁ , 230 ₂ , 230 ₃ ,. .., And an addition processing unit 240 and an average processing unit 250. Here, the second counters 220 ₁ , 220 ₂ , 220 ₃ ,..., The phase shifters 230 ₁ , 230 ₂ , 230 ₃ ,..., The addition processing unit 240, and the average processing unit 250 are respectively Similar to the second counters 120 ₁ , 120 ₂ , 120 ₃ ,..., The phase shifters 130 ₁ , 130 ₂ , 130 ₃ ,. Because of this configuration, redundant description is omitted.

The first counter 210 is connected to the second counters 220 ₁ , 220 ₂ , 220 ₃ ,..., Counts the clock of the input client signal for a certain period, and reaches the predetermined count value when the second counter is reached. A trigger signal is output simultaneously to 220 ₁ , 220 ₂ , 220 ₃ ,. In response to receiving the trigger signal, the second counters 220 ₁ , 220 ₂ , 220 ₃ ,... Start counting the clocks of the transmission frames to which different phase differences are applied, and the next trigger signal is input. In the meantime, the clocks of the transmission frames supplied from the phase shifters 230 ₁ , 230 ₂ , 230 ₃ ,.

  In the second embodiment, the phase difference is given to the clock of the transmission frame. However, the frequency deviation can be detected in the same manner even when the phase difference is given to the clock of the client signal. In this case, the first counter 210 receives the transmission frame, counts the clock signal of the transmission frame, and the phase shifter 230 receives the clock of the client signal and provides the phase difference.

  In FIG. 3, a plurality of phase shifters 230 are provided according to the number of phase differences to be applied, but the present invention is not limited to this. That is, when a phase shifter that can simultaneously output a plurality of phase differences to an input clock and output a clock with a plurality of phase differences is used, the number of one or the number of phase differences to be applied A small number of phase shifters may be utilized.

  Next, referring to FIG. 4, a mapping circuit according to an embodiment of the present invention using the above-described frequency deviation detection circuit will be described.

  FIG. 4 shows a configuration as an example of a mapping circuit using the frequency deviation detection circuit according to the present invention. As illustrated in FIG. 4, the mapping circuit 300 includes a frequency deviation detection unit 310, a frequency deviation accumulation holding unit 320, a FIFO (First-In First-Out) unit 330, and a frame processing unit 340.

  The frequency deviation detection unit 310 includes the frequency deviation detection circuit according to the first embodiment or the second embodiment described above, detects the frequency deviation between the clock of the client signal and the clock of the transmission frame, and the frequency deviation accumulation holding unit 320. Output to.

When the frequency deviation accumulating unit 320 receives the frequency deviation from the frequency deviation detecting unit 310, the frequency deviation accumulating unit 320 adds the received frequency deviation to the previously received and held frequency deviation, and the accumulated frequency deviation is justified. It is determined whether a predetermined threshold set for the control (JC) process has been exceeded. When the accumulated frequency deviation exceeds the threshold, the frequency deviation accumulation holding unit 320 calculates a JC processing amount corresponding to the bit adjusted in the frame according to the frequency deviation, and outputs the JC processing amount to the frame processing unit 340. To do. On the other hand, when the accumulated frequency deviation does not exceed the threshold, the frequency deviation accumulation holding unit 320 holds the updated accumulated value of the frequency deviation.
Even when the JC processing threshold value is not exceeded, the frequency deviation accumulation holding unit 320 outputs the frequency deviation value of each frame or the accumulated frequency deviation value to the frame processing unit, and the frame processing unit puts it in the overhead (OH). It is also possible to insert frequency deviation values or accumulated frequency deviation values.
The FIFO unit 330 temporarily stores client signal data, and supplies the data stored by the FIFO method to the frame processing unit 340.

  The frame processing unit 340 performs OH insertion, JC processing, and FEC (Forward Error Correction) insertion on the data received from the FIFO unit 330 based on the JC processing amount received from the frequency deviation accumulation holding unit 320, Output data of transmission frame.

  As mentioned above, although the Example of this invention was explained in full detail, this invention is not limited to the specific embodiment mentioned above, In the range of the summary of this invention described in the claim, various deformation | transformation・ Change is possible.

100, 200 Frequency deviation detection circuit 110, 120, 210, 220 Counter 130, 230 Phase shifter 140, 240 Addition processing unit 150, 250 Average processing unit

Claims (9)

A deviation detecting device for detecting a frequency deviation between a clock of a client signal and a clock of a transmission frame,
A first counter for counting a clock of the client signal;
A phase shifter for adding a plurality of phase differences to the clock of the transmission frame;
When the count value of the first counter reaches a predetermined value, the clocks of the transmission frames to which the plurality of phase differences are added are counted in parallel, and the count value of the first counter next reaches the predetermined value. A second counter that outputs each count value at the time of
An addition processing unit for adding the count value of each clock output from the second counter;
An average processing unit that averages the added total count value by the number of clocks of the transmission frame to which the plurality of phase differences are given, and outputs the calculated average value as the frequency deviation;
A deviation detecting device.   When the count value of the first counter reaches a predetermined value, the first counter generates a trigger signal for causing the second counter to start counting each clock of the transmission frame to which the plurality of phase differences are added. The deviation detecting apparatus according to claim 1, wherein the deviation detecting apparatus transmits the second counter. The second counter is composed of a plurality of counters that respectively count in parallel each clock of the transmission frame to which the plurality of phase differences are given,
The deviation detection device according to claim 2, wherein the phase shifter outputs a clock corresponding to a transmission frame in which the plurality of phase differences are added to the plurality of counters.   The deviation detecting device according to claim 3, wherein a plurality of the first counters are provided corresponding to the number of the plurality of counters of the second counter.   The deviation detection device according to claim 3, wherein the first counter transmits the trigger signal simultaneously to a plurality of counters of the second counter.   When the number of the plurality of phase differences is N, the phase shifter has (1 / N) · 2π, (2 / N) · 2π, ..., ((N-1 The deviation detecting device according to any one of claims 1 to 5, wherein each phase difference of) / N) · 2π, 2π is given. A deviation detecting device for detecting a frequency deviation between a clock of a client signal and a clock of a transmission frame,
A first counter that counts the clock of the transmission frame;
A phase shifter for adding a plurality of phase differences to the clock of the client signal;
When the count value of the first counter reaches a predetermined value, the clocks of the client signals to which the plurality of phase differences are added are counted in parallel, and the count value of the first counter next reaches the predetermined value. A second counter that outputs each count value at the time of
An addition processing unit for adding the count value of each clock output from the second counter;
An average processing unit that averages the added total count value by the number of clocks of the client signal to which the plurality of phase differences are given, and outputs the calculated average value as the frequency deviation;
A deviation detecting device. A deviation detection method for detecting a frequency deviation between a clock of a client signal and a clock of a transmission frame,
Counting a clock of the client signal in a first counter and determining whether the count value has reached a predetermined value;
When it is determined that the count value has reached a predetermined value, the second counter counts each clock of the transmission frame to which a plurality of phase differences are added in parallel, and the count value of the first counter is Outputting each count value when the predetermined value is reached,
Adding a count value of each clock output from the second counter;
Averaging the added total count value by the number of clocks of the transmission frame to which the plurality of phase differences are given, and outputting the calculated average value as the frequency deviation;
A deviation detection method. A deviation detection method for detecting a frequency deviation between a clock of a client signal and a clock of a transmission frame,
Counting the clock of the transmission frame in a first counter and determining whether the count value has reached a predetermined value;
When it is determined that the count value has reached a predetermined value, the second counter counts each clock of the client signal to which a plurality of phase differences are given in parallel, and the count value of the first counter is Outputting each count value when the predetermined value is reached,
Adding a count value of each clock output from the second counter;
Averaging the added total count value by the number of clocks of the client signal to which the plurality of phase differences are given, and outputting the calculated average value as the frequency deviation;
A deviation detection method.

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