JP5475975B2 - Semiconductor device and adjustment method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and an adjustment method thereof, and more particularly to a semiconductor device including a plurality of memory cells that store data based on a threshold voltage and an adjustment method thereof.

  2. Description of the Related Art Semiconductor devices that can store information by injecting electrons into or extracting electrons from a floating gate or a charge storage layer, such as flash memories, have been developed. The flash memory includes a memory cell having a floating gate, a control gate, a source, and a drain. In the memory cell, the threshold voltage increases when electrons are injected into the floating gate, and the threshold voltage decreases when electrons are extracted from the floating gate.

  As an example of such a flash memory, for example, Patent Document 1 discloses the following configuration. That is, a nonvolatile memory including a memory cell composed of a floating gate field-effect transistor having a control gate, a drain, a source, and a floating gate and capable of electrically writing and erasing information, and a reading means having a first reference cell A second reference cell, threshold value comparing means for comparing the threshold value of the first reference cell and the threshold value of the second reference cell, and threshold value comparing means Comprises threshold setting means for setting the threshold value of the first reference cell based on the result of comparing the threshold value of the first reference cell and the threshold value of the second reference cell.

Further, Patent Document 2 discloses a configuration for preventing erroneous reading of stored data by suppressing variations in read current flowing through each memory transistor in a flash memory. That is, a current generation circuit that generates a reference current to be supplied to a bit line includes a first main electrode connected to a first power supply line, a first transistor having a second main electrode and a control electrode connected to each other, and A resistor having a first end connected to the second main electrode of the first transistor and a second end connected to the second power supply line; a first main electrode connected to the first power supply line; A plurality of second transistors having a control electrode connected to the control electrode of one transistor; a first main electrode provided for each second transistor and connected to a second main electrode of the corresponding second transistor; A plurality of third transistors having a second main electrode to which a reference current is output, and a current control circuit for individually controlling on / off of the third transistors.
JP 2004-39075 A JP 2005-149625 A

  In the configuration described in Patent Document 2, in a current mirror circuit that supplies a read current to a memory transistor, the read current is adjusted by controlling the number of transistors that supply the read current, that is, the number of transistors that are turned on. However, in such a configuration, the adjustment is digital, and the adjustment unit is a transistor unit, so that variations in transistor characteristics cannot be suppressed.

  Therefore, an object of the present invention is to provide a semiconductor device capable of reducing the influence of manufacturing variations of a sense circuit including a constant current source, and an adjustment method thereof.

  In order to solve the above problems, a semiconductor device according to an aspect of the present invention is provided corresponding to a plurality of first constant current sources and a first constant current source, and the corresponding first constant current source. A plurality of memory cells having a conduction electrode coupled to the output terminal of the first and second terminals, the threshold voltage being changeable, and storing data based on the threshold voltage; a second constant current source; and a second constant current source A variable resistance element coupled to the output terminal of the first constant current source, and a potential of the output terminal of the corresponding first constant current source and a potential of the output terminal of the second constant current source. A plurality of sense amplifiers for outputting a signal indicating the comparison result, and a conduction electrode provided corresponding to the first constant current source and coupled to the output terminal of the corresponding first constant current source A plurality of first adjustment memory cells whose threshold voltage can be changed, and an output terminal of a second constant current source It has engaged the conductive electrode, and a second adjustment memory cell threshold voltage is changeable.

  Preferably, the semiconductor device further includes a first word line coupled to the control electrode of the first adjustment memory cell and the control electrode of the second adjustment memory cell.

  More preferably, the variable resistance element is a reference memory cell whose threshold voltage can be changed, and the semiconductor device further includes a second word line coupled to the control electrode of the memory cell and the control electrode of the reference memory cell. Is provided.

  More preferably, the memory cell, the reference memory cell, the first adjustment memory cell, and the second adjustment memory cell have the same structure.

  Preferably, the memory cell, the first adjustment memory cell, and the second adjustment memory cell have the same structure.

  Preferably, the plurality of memory cells are arranged in a matrix, and the first constant current source is provided corresponding to the memory cell column and has an output terminal coupled to the conduction electrode of each corresponding memory cell. The semiconductor device further includes a plurality of selection transistors provided corresponding to the memory cells and connected between the conduction electrode of the corresponding memory cell, the output terminal of the first constant current source, and the sense amplifier.

  In order to solve the above problems, a method for adjusting a semiconductor device according to an aspect of the present invention is provided corresponding to a plurality of first constant current sources and a first constant current source. A plurality of memory cells having a conduction electrode coupled to the output terminal of the constant current source, the threshold voltage being changeable, and storing data based on the threshold voltage; a second constant current source; A variable resistance element coupled to the output terminal of the constant current source and the potential of the output terminal of the corresponding first constant current source and the output of the second constant current source provided corresponding to the first constant current source A plurality of sense amplifiers for comparing the potentials of the terminals and outputting a signal indicating the comparison result, provided corresponding to the first constant current source, and coupled to the output terminal of the corresponding first constant current source A plurality of first adjustment memory cells each having a conduction electrode and capable of changing a threshold voltage; and a second constant current source A method for adjusting a semiconductor device comprising a second adjustment memory cell having a conduction electrode coupled to a power terminal and capable of changing a threshold voltage, wherein an output current of a second constant current source is set to a predetermined value Adjusting the resistance value of the variable resistance element so as to be, measuring the output current value of each first constant current source in which the logic level of the signal indicating the comparison result output from each sense amplifier is inverted, and A current flowing from each first constant current source to the corresponding memory cell and the corresponding first adjustment memory cell, and a current flowing from the second constant current source to the variable resistance element and the second adjustment memory cell. Adjusting the threshold voltage of each of the first adjustment memory cells and the second adjustment memory cells so as to be a predetermined value and the maximum value of the measured output current value of each first constant current source. Including.

According to the present invention, it is possible to reduce the influence of manufacturing variations of a sense circuit including a constant current source.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

FIG. 1 is a diagram showing a configuration of a semiconductor device according to an embodiment of the present invention.
Referring to FIG. 1, a semiconductor device 101 includes a memory array 1, an X decoder 2, a Y decoder 3, a sense circuit (read circuit) 4, a command decoder 5, a memory controller 6, an address latch & command. A generator 7, an address decoder 8, a data buffer 9, and a latch circuit 10 are provided.

  Memory array 1 is arranged in a matrix and includes, for example, a plurality of memory cells that store data in a nonvolatile manner.

  The address latch & command generator 7 latches the address signal AD input from the outside in response to the timing signal received from the memory controller 6, and outputs the latched address signal AD to the address decoder 8. The address latch & command generator 7 outputs a command signal to the command decoder 5 based on the latched address signal AD.

  Address decoder 8 decodes address signal AD received from address latch & command generator 7 to generate internal address signal IAD, and outputs it to X decoder 2 and Y decoder 3.

  X decoder 2 selects a word line corresponding to memory cell MC to be accessed based on internal address signal IAD received from address decoder 8.

  Y decoder 3 selects a bit line corresponding to memory cell MC to be accessed based on internal address signal IAD received from address decoder 8.

  The memory cells to be written, read and erased are specified by the selection of the word line by the X decoder 2 and the selection of the bit line by the Y decoder 3.

  Command decoder 5 decodes a command signal input from the outside and a command signal received from address latch & command generator 7, and outputs a signal indicating the decoding result to memory controller 6.

  The memory controller 6 outputs various control signals to the X decoder 2, the Y decoder 3, and the like based on the signal received from the command decoder 5, thereby performing data writing, data reading, data erasing, and the like with respect to the memory cell.

  Data read from the memory array 1 via the sense circuit 4 is output to the outside via the latch circuit 10 and the data buffer 9.

  Data DQ input from the outside is output to the latch circuit 10 via the data buffer 9.

FIG. 2 is a diagram showing a configuration of a readout circuit in the semiconductor device according to the embodiment of the present invention. FIG. 2 representatively shows a circuit corresponding to a memory cell of 2 rows and 2 columns. Hereinafter, this circuit will be described as a representative.

  Referring to FIG. 2, semiconductor device 101 includes sense amplifiers SA1, SA2, constant current sources IS1, IS2, ISR, memory cells MC1A, MC1B, MC2A, MC2B arranged in a matrix, and reference memory cells. MCRA, MCRB, adjustment memory cells MCT1, MCT2, MCTR, switches SW1A, SW1B, SW1C, switches SW2A, SW2B, SW2C, selection transistors TRS1A, TRS1B, TRS2A, TRS2B, and external pads P1A, P1B, P2A , P2B, word lines WLA, WLB, adjustment word line WLTN, and bit line BL.

  The sense circuit (read circuit) 4 shown in FIG. 1 includes sense amplifiers SA1, SA2, constant current sources IS1, IS2, ISR, adjustment memory cells MCT1, MCT2, MCTR, switches SW1A, SW1B, SW1C, and switches SW2A, SW2B, and SW2C are included.

  Hereinafter, the rows and columns of the memory cells MC1A, MC1B, MC2A, MC2B arranged in a matrix are also referred to as memory cell rows and memory cell columns, respectively.

  In addition, each of the constant current sources IS1, IS2, and ISR may be referred to as a constant current source IS. In addition, each of the memory cells MC1A and MC1B may be referred to as a memory cell MC1. In addition, each of the memory cells MC2A and MC2B may be referred to as a memory cell MC2. Further, each of the reference memory cells MCRA and MCRB may be referred to as a reference memory cell MCR. Further, each of the memory cells MC1 and MC2 may be referred to as a memory cell MC. Each of the adjustment memory cells MCT1, MCT2, and MCTR may be referred to as an adjustment memory cell MCT. Each of sense amplifiers SA1 and SA2 may be referred to as sense amplifier SA. Each of the selection transistors TRS1A and TRS1B may be referred to as a selection transistor TRS1. Each of the selection transistors TRS2A and TRS2B may be referred to as a selection transistor TRS2. Each of the word lines WLA and WLB may be referred to as a word line WL.

  Memory cell MC1A has a control gate connected to word line WLA, a drain connected to the source of select transistor TRS1A, and a source connected to a ground node to which a ground voltage is supplied. Memory cell MC2A has a control gate connected to word line WLA, a drain connected to the source of select transistor TRS2A, and a source connected to a ground node to which a ground voltage is supplied. Memory cell MC1B has a control gate connected to word line WLB, a drain connected to the source of select transistor TRS1B, and a source connected to a ground node to which a ground voltage is supplied. Memory cell MC2B has a control gate connected to word line WLB, a drain connected to the source of select transistor TRS2B, and a source connected to a ground node to which a ground voltage is supplied.

  Select transistor TRS1A has a gate, a drain connected to the first end of switch SW1C, and a source connected to the drain of memory cell MC1A. Select transistor TRS2A has a gate, a drain connected to the first end of switch SW2C, and a source connected to the drain of memory cell MC2A. Select transistor TRS1B has a gate, a drain connected to the first end of switch SW1C, and a source connected to the drain of memory cell MC1B. Select transistor TRS2B has a gate, a drain connected to the first end of switch SW2C, and a source connected to the drain of memory cell MC2B.

  Adjustment memory cell MCT1 has a control gate connected to adjustment word line WLTN, a drain connected to the first end of switch SW1C, and a source connected to a ground node to which a ground voltage is supplied. Adjustment memory cell MCT2 has a control gate connected to adjustment word line WLTN, a drain connected to the first end of switch SW2C, and a source connected to a ground node to which a ground voltage is supplied.

  Reference memory cell MCRA has a control gate connected to word line WLA, a drain connected to the source of select transistor TRSRA, and a source connected to a ground node to which a ground voltage is supplied. Reference memory cell MCRB has a control gate connected to word line WLB, a drain connected to the source of select transistor TRSRB, and a source connected to a ground node to which a ground voltage is supplied.

  Select transistor TRSRA has a gate, a drain connected to the output terminal of constant current source ISR, and a source connected to the drain of reference memory cell MCRA. Select transistor TRSRB has a gate, a drain connected to the output terminal of constant current source ISR, and a source connected to the drain of reference memory cell MCRB.

  Adjustment memory cell MCTR has a control gate connected to adjustment word line WLTN, a drain connected to the output terminal of constant current source ISR, and a source connected to a ground node to which a ground voltage is supplied. .

  The sense amplifier SA1 and the constant current source IS1 are provided corresponding to the memory cell column constituted by the memory cells MC1A and MC1B. The sense amplifier SA2 and the constant current source IS2 are provided corresponding to the memory cell column constituted by the memory cells MC2A and MC2B.

  The sense amplifier SA1 includes an output terminal of the constant current source ISR, an inverting input terminal connected to the drain of the selection transistor TRSRA and the drain of the adjustment memory cell MCTR, an output terminal of the constant current source IS1, a second end of the switch SW1C, and It has a non-inverting input terminal connected to the first end of the switch SW1A, and an output terminal connected to the first end of the switch SW1B and the input of the latch circuit 10. The sense amplifier SA2 includes an output terminal of the constant current source ISR, an inverting input terminal connected to the drain of the selection transistor TRSRA and the drain of the adjustment memory cell MCTR, an output terminal of the constant current source IS2, a second end of the switch SW2C, and It has a non-inverting input terminal connected to the first end of the switch SW2A, and an output terminal connected to the first end of the switch SW2B and the input of the latch circuit 10.

  Switch SW1A has a first end connected to the output terminal of constant current source IS1, and a second end connected to external pad P1A. Switch SW2A has a first end connected to the output terminal of constant current source IS2, and a second end connected to external pad P2A.

  Switch SW1B has a first end connected to the output terminal of sense amplifier SA1, and a second end connected to external pad P1B. Switch SW2B has a first end connected to the output terminal of sense amplifier SA2, and a second end connected to external pad P2B.

  The constant current sources IS1, IS2, and ISR are connected to a power supply node to which a power supply voltage VDD is supplied.

Memory cells MC1A, MC1B, MC2A, MC2B, reference memory cells MCRA, MCRB, and adjustment memory cells MCT1, MCT2, MCTR have the same structure, for example. That is, these memory cells have, for example, a floating gate, a control gate, a source, and a drain. With such a configuration, various characteristics of the semiconductor device 101 can be improved and adjustment can be facilitated.

  The memory cells MC1A, MC1B, MC2A, MC2B, the reference memory cells MCRA, MCRB, and the adjustment memory cells MCT1, MCT2, MCTR are not limited to such a configuration, and the threshold voltage can be changed. Any element that stores data based on a threshold voltage may be used.

  The constant current source IS1 supplies current to the drain of the memory cell MC1A via the switch SW1C and the selection transistor TRS1A. The constant current source IS1 supplies current to the drain of the memory cell MC1B through the switch SW1C and the selection transistor TRS1B. The constant current source IS1 supplies a current to the drain of the adjustment memory cell MCT1 via the switch SW1C.

  The constant current source IS2 supplies current to the drain of the memory cell MC2A through the switch SW2C and the selection transistor TRS2A. The constant current source IS2 supplies current to the drain of the memory cell MC2B via the switch SW2C and the selection transistor TRS2B. The constant current source IS2 supplies a current to the drain of the adjustment memory cell MCT2 via the switch SW2C.

  The constant current source ISR supplies current to the drain of the reference memory cell MCRA via the selection transistor TRSRA. The constant current source ISR supplies a current to the drain of the reference memory cell MCRB via the selection transistor TRSRB. The constant current source ISR supplies current to the drain of the adjustment memory cell MCTR.

  The sense amplifier SA1 compares the potential of the connection node N1 of the second end of the switch SW1C and the output terminal of the constant current source IS1 with the potential of the connection node REFN of the drains of the selection transistors TRSRA and TRSRB and the output terminal of the constant current source ISR. Then, the signal RD1 indicating the comparison result is output to the latch circuit 10. Further, the sense amplifier SA2 has the potential of the connection node N2 of the second end of the switch SW2C and the output terminal of the constant current source IS2, the potential of the connection node REFN of the drains of the selection transistors TRSRA and TRSRB and the output terminal of the constant current source ISR. And a signal RD2 indicating the comparison result is output to the latch circuit 10.

  By selectively turning on the select transistors TRS1A and TRS1B, one of the memory cells MC1A and MC1B is connected to the sense amplifier SA1. By selectively turning on select transistors TRS2A and TRS2B, one of memory cells MC2A and MC2B is connected to sense amplifier SA2.

  The control gates of the memory cells MC1A and MC2A and the control gate of the reference memory cell MCRA are connected to the word line WLA. The control gates of the memory cells MC1B and MC2B and the control gate of the reference memory cell MCRB are connected to the word line WLB.

  The control gates of the adjustment memory cells MCT1 and MCT2 and the control memory cell MCTR are connected to the adjustment word line WLTN. With such a configuration, the configuration of the semiconductor device 101 can be simplified.

The magnitude of the current flowing through the reference memory cell MCR varies depending on the voltage supplied to the control gate of the reference memory cell MCR and the threshold voltage of the reference memory cell MCR. Here, when it is assumed that the semiconductor device 101 does not include the adjustment memory cells MCT1, MCT2, and MCTR, the potential of the connection node REFN is the output current IREF of the constant current source ISR and the current flowing through the reference memory cell MCR. For example, 1V. The potential of the connection node N1 is determined by the output current of the constant current source IS1 and the current flowing through the memory cell MC1, and the threshold voltage of the memory cell MC1 is equal to the threshold voltage of the reference memory cell MCR. When the output current of the constant current source ISR is equal to the output current of the constant current source IS1, it is also 1V. The potential of the connection node N2 is determined by the output current of the constant current source IS2 and the current flowing through the memory cell MC2, and the threshold voltage of the memory cell MC2 is equal to the threshold voltage of the reference memory cell MCR. When the output current of the constant current source ISR is equal to the output current of the constant current source IS2, the voltage is also 1V.

  However, the constant currents output from the constant current source ISR and each of the constant current sources IS1 and IS2 may differ due to manufacturing variations. In this case, the potential of the connection node SAREF and the potentials of the connection nodes N1 and N2 are different, and erroneous reading of stored data is likely to occur.

  Therefore, in the semiconductor device according to the embodiment of the present invention, the following adjustment method prevents the influence due to the characteristic variation of the constant current source IS. Hereinafter, a method for adjusting the readout circuit in the semiconductor device according to the embodiment of the present invention will be described. Here, an adjustment method in the case where memory cells MC1A and MC2A are typically used will be described.

  FIG. 3 is a flowchart defining an operation procedure when the semiconductor device according to the embodiment of the present invention adjusts the readout circuit. FIG. 4 is a diagram showing adjustment contents of the readout circuit in the semiconductor device according to the embodiment of the present invention.

  First, the selection transistors TRS1A, TRS2A, and TRSRA are turned on, and the selection transistors TRS1B, TRS2B, and TRSRB are turned off.

  Next, the output current of the constant current source ISR is set to an initial value. More specifically, when a voltage of, for example, 5V is supplied to the word line WLA, the reference memory cell MCRA is turned on, and an initial current of, for example, 10 microamperes (initial value in FIG. 4) flows through the reference memory cell MCRA. As described above, the threshold voltage of the reference memory cell MCRA is adjusted (step S1).

  Next, by turning on the switches SW1A and SW2A, the output terminals of the constant current sources IS1 and IS2 are connected to the external pads P1A and P2A, respectively. Further, by turning on the switches SW1B and SW2B, the output terminals of the sense amplifiers SA1 and SA2 are connected to the external pads P1B and P2B, respectively (step S2).

  Further, by turning off the switch SW1C, the connection between the memory cells MC1A and MC1B and the adjustment memory cell MCT1 and the constant current source IS1 is cut off. Further, by turning off the switch SW2C, the connection between the memory cells MC2A and MC2B and the adjustment memory cell MCT2 and the constant current source IS2 is cut off (step S3).

  Next, the external pads P1A and P2A and the external pads P1B and P2B are connected to a tester (not shown), and a current flows from the constant current sources IS1 and IS2 to the tester. At this time, the output currents of the constant current sources IS1 and IS2 are changed by adjusting the resistance values of the loads connected to the output terminals of the constant current sources IS1 and IS2 on the tester side.

The tester monitors the output signals RD1 and RD2 of the sense amplifiers SA1 and SA2, and the constant current sources IS1 and IS2 when the logic levels of these output signals are inverted.
Output current values (hereinafter also referred to as inversion current values) are measured (step S4).

  The difference between each measured inversion current value and 10 microamperes flowing through the reference memory cell MCRA corresponds to variations in the constant current source ISR and the constant current sources IS1 and IS2.

  For example, when the output current of the constant current source IS1 when the logic level of the output signal of the sense amplifier SA1 is inverted is 12 microamperes (the initial value in FIG. 4), the outputs of the constant current source ISR and the constant current source IS1 The variation in current is +2 microamperes. Further, when the output current of the constant current source IS2 when the logic level of the output signal of the sense amplifier SA2 is inverted is 8 microamperes (the initial value in FIG. 4), the outputs of the constant current source ISR and the constant current source IS2 The variation in current is -2 microamperes.

  Next, the output current from the constant current source ISR and the constant current sources IS1 and IS2 to each memory cell becomes the maximum value among the initial current of the constant current source ISR and the inverted current of the constant current sources IS1 and IS2. Set. In the case of the above specific example, the threshold voltage of the adjustment memory cell MCT1 coupled to the output terminal of the constant current source IS1 is passed through the adjustment memory cell MCT1 when a voltage of, for example, 1 V is supplied to the adjustment word line WLTN. It is set so that a current of 0 microamperes (correction value in FIG. 4) flows. Further, the threshold voltage of the adjustment memory cell MCT2 coupled to the output terminal of the constant current source IS2 is set to 4 microamperes through the adjustment memory cell MCT2 when a voltage of, for example, 1 V is supplied to the adjustment word line WLTN (FIG. 4) (correction value 4). Further, the threshold voltage of the adjustment memory cell MCTR connected to the output terminal of the constant current source ISR is set to 2 microamperes (FIG. 2) through the adjustment memory cell MCTR when a voltage of, for example, 1 V is supplied to the adjustment word line WLTN. (A correction value of 4) is set to flow (step S5).

  The adjustment as described above is performed, and the same 1 V voltage as that at the time of adjustment is supplied to the adjustment word line WLTN in verification of data reading, data writing and data erasing. Thus, the current flowing from the constant current source IS1 to the memory cell MC1 and the adjustment memory cell MCT1, the current flowing from the constant current source IS2 to the memory cell MC2 and the adjustment memory cell MCT2, and the reference memory cell MCR from the constant current source ISR. In addition, all the currents flowing through the adjustment memory cells MCTR can be set to 12 microamperes (the total value in FIG. 4). Therefore, in the semiconductor device according to the embodiment of the present invention, it is possible to prevent the influence due to the characteristic variation of each constant current source IS.

  In the semiconductor device according to the embodiment of the present invention, the number of adjustment memory cells MCT for correcting the characteristic variation of the constant current source in the read circuit is small, and an increase in layout area can be suppressed.

  In the semiconductor device according to the embodiment of the present invention, an adjustment word line WLTN connected to the control gate of the adjustment memory cell MCT is provided separately from the word line WL connected to the control gate of the memory cell MC. . With such a configuration, a voltage lower than the voltage to be supplied to the control gate of the memory cell MC can be supplied to the control gate of the adjustment memory cell MCT. That is, even if the threshold voltage of the adjustment memory cell MCT is set low, a desired current can be passed from the constant current source IS through the adjustment memory cell MCT. Therefore, the setting time of the threshold voltage of the adjustment memory cell MCT can be shortened.

In data reading, a margin for variation in threshold voltage is relatively large. However, in data writing and data erasing, the threshold voltage of the memory cell is adjusted to a predetermined value by verification, so The margin is small. In the flash memory, since each memory cell is collectively written or erased, the threshold voltage of each memory cell varies due to variation in characteristics of each constant current source, and the memory cell may be overerased.

  However, in the semiconductor device according to the embodiment of the present invention, the current flowing from the constant current sources IS1 and IS2 to the memory cell MC and the adjustment memory cell MCT as described above, and the reference memory cell MCR from the constant current source ISR and The current flowing through the adjustment memory cell MCT can be set equal. Thereby, variation in threshold voltage of each memory cell can be prevented, and over-erasure of the memory cell can be prevented.

  In the semiconductor device according to the embodiment of the present invention, the reference memory cell MCR is coupled to the output terminal of the constant current source ISR. However, the present invention is not limited to this. It may be an element. However, in the semiconductor device according to the embodiment of the present invention, by using the reference memory cell MCR having the same structure as the memory cell MC, the gate voltage vs. drain current characteristic becomes the same. The read margin can be prevented from being reduced and the noise resistance can be improved.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a figure which shows the structure of the semiconductor device which concerns on embodiment of this invention. It is a figure which shows the structure of the read-out circuit in the semiconductor device which concerns on embodiment of this invention. 6 is a flowchart defining an operation procedure when the semiconductor device according to the embodiment of the present invention adjusts a read circuit. It is a figure which shows the adjustment content of the read-out circuit in the semiconductor device which concerns on embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Memory array, 2 X decoder, 3 Y decoder, 4 Sense circuit (read circuit), 5 Command decoder, 6 Memory controller, 7 Address latch & command generator, 8 Address decoder, 9 Data buffer, 10 Latch circuit, 101 Semiconductor device , SA1, SA2 sense amplifier, IS1, IS2, ISR constant current source, MC1A, MC1B, MC2A, MC2B memory cell, MCRA, MCRB reference memory cell, MCT1, MCT2, MCTR adjustment memory cell, SW1A, SW1B, SW1C, SW2A, SW2B, SW2C switch, TRS1A, TRS1B, TRS2A, TRS2B selection transistor, P1A, P1B, P2A, P2B external pad, WLA, WLB word line, WLTN adjustment word , BL bit line.

Claims (7)

A plurality of first constant current sources;
A conductive electrode provided corresponding to the first constant current source and coupled to an output terminal of the corresponding first constant current source, the threshold voltage being changeable; and data based on the threshold voltage A plurality of memory cells for storing
A second constant current source;
A variable resistance element coupled to the output terminal of the second constant current source;
Comparing the potential of the output terminal of the corresponding first constant current source with the potential of the output terminal of the second constant current source provided corresponding to the first constant current source, the comparison A plurality of sense amplifiers for outputting a signal indicating the result;
A plurality of first adjustments which are provided corresponding to the first constant current sources and have conduction electrodes coupled to the output terminals of the corresponding first constant current sources, and whose threshold voltage can be changed. A memory cell;
A second adjustment memory cell having a conduction electrode coupled to the output terminal of the second constant current source and capable of changing a threshold voltage ;
The resistance value of the variable resistance element is adjusted so that the output current of the second constant current source becomes a predetermined value,
An output current value of each of the first constant current sources at which the logic level of the signal indicating the comparison result output from each of the sense amplifiers is inverted is measured,
Current flowing from each of the first constant current sources to the corresponding memory cell and the corresponding first adjustment memory cell, and from the second constant current source to the variable resistance element and the second adjustment memory The first adjustment memory cell and the second adjustment so that the current flowing to the cell becomes the predetermined value and the measured maximum value of the output current value of each of the first constant current sources. A semiconductor device in which the threshold voltage of a memory cell is adjusted . The semiconductor device further includes:
2. The semiconductor device according to claim 1, further comprising a first word line coupled to a control electrode of the first adjustment memory cell and a control electrode of the second adjustment memory cell. The variable resistance element is a reference memory cell whose threshold voltage can be changed,
The semiconductor device further includes:
3. The semiconductor device according to claim 2, further comprising a second word line coupled to the control electrode of the memory cell and the control electrode of the reference memory cell.   4. The semiconductor device according to claim 3, wherein the memory cell, the reference memory cell, the first adjustment memory cell, and the second adjustment memory cell have the same structure.   The semiconductor device according to claim 1, wherein the memory cell, the first adjustment memory cell, and the second adjustment memory cell have the same structure. The plurality of memory cells are arranged in a matrix,
The first constant current source is provided corresponding to the memory cell column and has the output terminal coupled to a conduction electrode of each corresponding memory cell;
The semiconductor device further includes:
A plurality of selection transistors are provided corresponding to the memory cells and connected between the conduction electrodes of the corresponding memory cells, the output terminals of the first constant current sources, and the sense amplifiers. 2. The semiconductor device according to 1. A plurality of first constant current sources, and a conduction electrode provided corresponding to the first constant current source and coupled to an output terminal of the corresponding first constant current source, and the threshold voltage is changed A plurality of memory cells that store data based on a threshold voltage; a second constant current source; a variable resistance element coupled to an output terminal of the second constant current source; A signal provided corresponding to a constant current source, comparing the potential of the output terminal of the corresponding first constant current source with the potential of the output terminal of the second constant current source, and indicating the comparison result A plurality of sense amplifiers, and a conduction electrode provided corresponding to the first constant current source and coupled to the output terminal of the corresponding first constant current source, and the threshold voltage is changed A plurality of possible first adjustment memory cells and coupled to the output terminal of the second constant current source Has a through electrode, a method of adjusting a semiconductor device and a second adjustment memory cell threshold voltage is changeable,
Adjusting a resistance value of the variable resistance element so that an output current of the second constant current source becomes a predetermined value;
Measuring an output current value of each of the first constant current sources in which a logic level of a signal indicating the comparison result output from each of the sense amplifiers is inverted;
Current flowing from each of the first constant current sources to the corresponding memory cell and the corresponding first adjustment memory cell, and from the second constant current source to the variable resistance element and the second adjustment memory The first adjustment memory cell and the second adjustment so that the current flowing to the cell becomes the predetermined value and the measured maximum value of the output current value of each of the first constant current sources. Adjusting the threshold voltage of the memory cell for a semiconductor device.

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