JPH10228784A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory which can control more efficiently threshold value distribution of a memory cell. SOLUTION: In a verifying operation of a flash memory, plural different verifying levels are generated, and pulse voltage for writing or erasing operation are generated plural times until voltage exceeds a verifying level. Threshold value distribution is varied at high speed using high verifying voltage, and threshold values distribution is narrowed using low verifying voltage. For example, pulse voltage applied to a memory cell is made to have a constant voltage value, and a pulse width is generated by increasing it with a power. Also, pulse width is made constant, and a voltage value is generated by increasing it with a power. Or, the same verifying function is achieved by making the sensitivity of a sense amplifier variable.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device such as a flash memory for electrically writing and erasing data.

[0002]

2. Description of the Related Art A non-volatile semiconductor memory device such as a flash memory for electrically writing or erasing is used to inject electrons into a floating gate or to withdraw injected electrons by applying a high voltage to a memory cell. Change the threshold value V _{th of the} memory cell,
For example, in the DINOR type flash memory, the "0" state is a state in which electrons are removed from the floating gate, that is, a state where the threshold value is low. "0" state is a state where electrons are injected from the floating gate,
That is, the threshold value is high. Also,"
The 1 "state is the opposite state. As described above, each state differs depending on the method of writing or erasing. The threshold value must take a value specified in the standard. The verify operation The term “operation” refers to an operation of using an internally generated reference voltage (verify potential) to verify whether data having a desired expected value has been obtained when data is read at that voltage. To change the value, a high voltage application and a verify operation using a reference voltage generated by the high voltage are repeated until expected data is obtained.

[0003]

In a nonvolatile semiconductor memory device, the distribution of threshold values at the time of writing and erasing is as follows.
It is determined by the method of applying a high voltage, and usually has a width of about 0.5 to 1.0 V. In the future, as the power supply voltage decreases to 1.8 V or the like, the lower limit of the threshold distribution becomes. The voltage drops to about 0.5 to 1.0 V, which slows down the read access time, and the excessively lowered bits cause memory cells on the same bit line to appear to have a lower threshold than the actual one. Inconveniences such as not falling down easily occur. Therefore, it is necessary to narrow the threshold distribution and raise the lower limit of the distribution. In addition, there is a demand for multi-valued storage in which one memory cell has not only two values of “1” and “0” but also a large amount of information. In this case as well, a plurality of threshold distributions are provided. It is necessary to narrow the threshold distribution. In order to narrow the threshold distribution, it is considered that a voltage or time should be set so as to reduce the amount of change in the threshold by one application of a high voltage. However, this method has a problem that the operation time is greatly increased because the number of applied pulses increases accordingly. Also, when writing and erasing are repeated, the threshold value of the memory cell deviates from the distribution, and the threshold value becomes 0.2.
A cell that drops to 5V or less occurs accidentally. Due to this phenomenon, the same problem as in the case of operating at a low power supply voltage is caused.

An object of the present invention is to provide a nonvolatile semiconductor memory device capable of controlling the threshold distribution of a memory cell more efficiently.

[0005]

A nonvolatile semiconductor memory device according to the present invention decodes an externally input address signal to select a row, and outputs an externally input address signal. A second decoder for decoding and selecting a column; and a plurality of decoders arranged in the row and column directions and electrically writing or erasing external information based on the outputs of the first and second decoders. A memory array including memory cells, a sense amplifier that determines whether information stored in the memory cells is in a predetermined state, a high voltage generation circuit that generates a voltage different from a power supply voltage,
And a control circuit for controlling the operation of the second decoder and the high voltage generation circuit. In the verify operation, the high voltage generating circuit generates a plurality of different verify potentials in a verify operation, and generates a plurality of pulse voltages for a memory cell write or erase operation until the verify potential is exceeded. Further, in the nonvolatile semiconductor memory device according to the present invention, the control circuit causes the high voltage generating circuit to generate the first verify potential higher than the second verify potential. Further, in the nonvolatile semiconductor memory device according to the present invention, the control circuit generates a plurality of pulse voltages in the high voltage generation circuit, the pulse voltage changing the variation of the threshold value of the memory cell at the same verify potential. Let it. Further, in the nonvolatile semiconductor memory device according to the present invention, the control circuit may further include:
In the verify operation, a pulse voltage to be applied to the memory cell is generated by increasing the voltage value while keeping the pulse width constant, and increasing the voltage value at the first verify potential by the second verify voltage.
Larger than the increase in the verify potential. In the nonvolatile semiconductor memory device according to the present invention, the control circuit may control the high voltage generation circuit to increase a pulse width of the pulse voltage applied to the memory cell in the verify operation by making the voltage value constant and increasing the pulse width. The increase in the pulse width at the first verify potential is made larger than the increase at the second verify potential. Also, the nonvolatile semiconductor memory device according to the present invention decodes an externally input address signal to select a row, and decodes an externally input address signal to select a column. And a memory array comprising a plurality of memory cells arranged in a row and column direction and electrically writing or erasing external information based on the outputs of the first and second decoders. , A sense amplifier for determining whether the information stored in these memory cells is in a predetermined state, a high voltage generating circuit for generating a voltage different from the power supply voltage, first and second decoders, and a high voltage generating circuit And a control circuit for controlling the operation of the sense amplifier, and the sensitivity of the sense amplifier can be changed. Further, in the nonvolatile semiconductor memory device according to the present invention, the sense amplifier includes transistors having different sensitivities connected in parallel.

[0006]

Embodiments of the present invention will be described below with reference to the accompanying drawings. Embodiment 1 FIG. 1 shows an overall configuration of a flash memory which is an embodiment of a semiconductor memory device according to the present invention. Around a memory array 2 composed of a matrix of a plurality of memory cells,
X decoder 4 and Y for selecting rows and columns of the matrix
A decoder 6 is provided. Further, a write circuit 8 for data input and a sense amplifier 10 for data output are connected to the memory array 2 via the Y decoder 6. Control circuit 12
Receives various control signals from the outside and generates various control signals for controlling the inside of the memory. For example, the control circuit 12 includes a counter and supplies an address signal to the X decoder 4 and the Y decoder 6. High voltage generation circuit 14
Is an internal step-down circuit, based on the control signal received from the control circuit 12, and stores the data in a built-in register, on the basis of the data given in the register is different from the power supply voltage V _cc supplied from outside various Generates a voltage of This high voltage generating circuit 14 also generates a verify potential for a verify operation. Here, the voltage value or time of the verify potential is changed according to the data supplied from the control circuit 12 to the register. The generated verify potential is output to X decoder 4 and Y decoder 6. The sense amplifier 10 also outputs a signal read from the memory cell to the control circuit 12 for a verify operation.

FIGS. 2 and 3 schematically show the movement of electrons in a write / erase operation in a memory cell of a DINOR type flash memory. 2 and 3 show a schematic cross section of one memory cell constituting the memory array 2 shown in FIG. Each memory cell includes a source diffusion region 42 and a drain diffusion region 4 formed on a semiconductor substrate 40.
4, floating gate 46, control gate 4
8 is provided. The connection with the circuit around the memory cell is the same as in the prior art. The control gate 48 is connected to a word line, and the word line is connected to the X decoder 4. The drain region 44 is connected to a bit line. The bit line is connected to an I / O line via a Y gate transistor to which an output of the Y decoder 6 is input to its gate. The writing circuit 8 is connected. The source line is connected to a source line switch. As shown in FIG. 2, at the time of writing, electrons from the floating gate 46 to the drain diffusion region 44 (e ^-) are moved, as shown in FIG. 3, at the time of erasing, the floating gate 4 from the substrate 40
The electrons are transferred to 6.

FIG. 4 shows a basic flow of programming of a write / erase operation by the control circuit 12 in the DINOR type flash memory. Here, the writing or erasing operation is performed a plurality of times using a plurality of different verify potentials. In the first operation, the first verify potential generated by the high voltage generation circuit 14 is higher than the second verify potential generated in the second operation. As described below, different high voltages are sequentially applied to the memory cells for each verify potential. When a verify command is input (step S10), first, as a first operation, a voltage and a time are set such that the threshold value fluctuates in the same manner as in the related art or with a larger change than in the related art (step S12). ). Next, the set voltage is applied (step S14), and the first verify potential, which is higher than the conventional verify potential, is set as the word line potential for the cell to which the high voltage is applied (step S1).
6) Read the data and determine whether the read data has the expected value (step S1).
8). At this time, if there is a cell that does not have the expected value (NO in step S20), the flow returns to step S12, a high voltage is applied again to the memory cell, and the verify operation with the first verify potential is repeated. This series of operations is performed until all the memory cells to which the high voltage is applied are determined by the verify operation to the expected value. If the threshold values of all the memory cells reach the expected values (step S
(YES at 20), and then proceed to the second operation. As a second operation, first, a voltage and a time corresponding to the second operation are set (step S22). Next, the set voltage is applied (step S24), and a second verify potential, which is a verify potential higher than that of the conventional cell, is set as a word line potential for the cell to which the high voltage is applied (step S26), and reading is performed. To determine whether the read data has the expected value (step S28). The second verify potential is lower than the first verify potential. In the second operation, the potential and time for applying the high voltage are set so that the change in the threshold value is smaller than in the first operation. At this time, if there is a cell that has not reached the expected value (NO in step S30),
Returning to step S22, a high voltage is again applied to the memory cell, and a verify operation using the second verify potential is performed. In this series of operations, all cells to which a high voltage has been applied are determined by the verify operation to be expected values (step S
30 until YES).

Next, the setting of the voltage and the time for applying the high voltage (steps S12 and S22) will be described more specifically. FIG. 5 shows a method of applying a high voltage in a write operation in a DINOR type flash memory. here,
The time for applying one high voltage is fixed at 500 μs. When a negative voltage of, for example, -11 V is applied to the gate of the memory cell and the source and the well are made to float, the high voltage applied to the drain in the first operation is:
For example, by increasing the voltage from 5 V in steps of 0.4 V, the variation of the threshold value is made constant. Thus, in the first operation, as shown in FIG. 6, the threshold value V _th is distributed with the first verify potential as the upper limit. In the second operation, the applied voltage is changed from 5 V to 0.2.
By changing the threshold value in increments of V, the amount of change in the threshold value is kept constant. As a result, the change in the threshold value is constant, and the change can be smaller than in the first operation.
Thus, as shown in FIG. 6, the thresholds are distributed in a narrow range with the second verify potential as an upper limit. In this way, a plurality of writing operations are performed under different voltage application conditions.

As shown in FIGS. 5 and 6, in the first operation, when a high voltage is applied, the voltage and time are set so as to increase the change in the threshold value, thereby enabling a high-speed threshold. Change the value. In the next second operation, the voltage and time are set so that the amount of change in the threshold value is smaller than in the first operation. Thus, the threshold distribution can be narrowed. As a result, the threshold can be changed at a high speed, and the threshold distribution of the memory can be narrowed. In addition, the first threshold value is also set for cells whose threshold value generated during repetition of writing and erasing deviates from the distribution.
By setting a higher verify potential in the above operation, it is possible to prevent a large deviation from the distribution.

Second Embodiment A semiconductor memory device according to a second embodiment is a DINOR type flash memory similarly to the first embodiment, and FIG.
A method for applying a high voltage during a write operation in an INOR type flash memory will be described. In the first embodiment, the voltage applied to the drain of the memory cell is changed. In the present embodiment, the time during which the voltage is applied to the drain of the memory cell is changed. As in the example of FIG. 5, a negative voltage of, for example, -11 V is applied to the gate of the memory cell so that the source and the well are floating, and the drain is, for example, 1 V.
A fixed voltage of 0 V is applied. In the first operation, the application time is set to, for example, (200 μs × 1.5 ° times)
In the second operation, the application time is increased by a power of, for example, (200 μs × 1.2 ° times). Thus, the variation of the threshold value is made constant, and the variation of the threshold value is smaller in the second operation than in the first operation. As described above, in the first and second operations, a plurality of writing operations are performed under different voltage application conditions. By using such a high voltage application, as in the first embodiment, the threshold can be changed at high speed, and the threshold distribution of the memory can be narrowed.

Third Embodiment A flash memory according to a third embodiment is a NOR flash memory. 8 and 9 are schematic cross-sectional views of one memory cell constituting the memory array 2 shown in FIG. 1, and schematically show the movement of electrons in the write / erase operation in the NOR flash memory. . The memory cell is
The semiconductor device includes a source diffusion region 62 and a drain diffusion region 64 formed on a semiconductor substrate 60, a floating gate 66, and a control gate 68. As shown in FIG. 8, at the time of writing, electrons (e ⁻ ) are moved from the drain region 64 to the floating gate 66, and as shown in FIG.
At the time of erasing, electrons are moved from the floating gate 66 to the substrate 60.

FIG. 10 shows a method of applying a high voltage during an erasing operation in a NOR type flash memory. The gate 68 of the memory cell has a voltage of 0 V (or a negative voltage), for example.
To make the drain 64 floating. The time for applying one high voltage is fixed at 500 μs. In the first operation, for example, in the first operation, the source 62 and the well 64 are applied with an applied voltage of 5 V to 0.4 at the first verify potential.
By changing the threshold value in increments of V, the amount of change in the threshold value is kept constant. Further, in the second operation, the applied voltage is increased from 5 V to 0.2 V at the second verify potential, so that the variation of the threshold value is made constant. As a result, the change in the threshold value is constant,
The change can be made smaller than in the first operation. In this manner, a plurality of erasing operations are performed under different voltage application conditions. Note that the erasing operation is performed simultaneously on a plurality of memory cells. By using such a high voltage application, as in the first embodiment, the threshold can be changed at high speed, and the threshold distribution of the memory can be narrowed.

Fourth Embodiment A semiconductor memory device according to a fourth embodiment is a NOR type flash memory similarly to the third embodiment, and FIG.
4 shows a method of applying a high voltage during an erase operation in an R-type flash memory. In the first and second operations, a plurality of writing operations are performed under different voltage application conditions. In the third embodiment, the voltage applied to the source of the memory cell is changed. In this embodiment, the time during which the voltage is applied to the source of the memory cell is changed.
For example, a voltage of 0 V is applied to the gate of the memory cell,
The drain potential is made floating, and a fixed voltage of, for example, 10.0 V is applied to the source and the well. In the first operation, the application time is set to, for example, (200 μs
× 1.5 times) and in the second operation, the application time is set to, for example, (200 μs × 1.2 times)
And increase by powers. Thus, the variation of the threshold value is made constant, and the variation of the threshold value is smaller in the second operation than in the first operation. By using such a high voltage application, as in the third embodiment,
The threshold can be changed at high speed, and the threshold distribution of the memory can be narrowed.

Fifth Embodiment In the above-described embodiment, the detection level is changed by using a plurality of reference voltages (verify potentials) generated by the high-voltage generating circuit. The detection level is changed in a pseudo manner by changing the sensitivity.
FIG. 12 shows the sense amplifier 1 connected to the memory cell 80.
Indicates 0 '. The control gate of the memory cell 80
The source is connected to the word line signal WL, and the source is grounded in this figure. The drain is connected to the sense amplifier 10 'via the NMOS transistor 82. This transistor 82 is selected by a column signal (Y selection signal). The NMOS transistor 84 suppresses the potential of the bit line to around 1 V by a bias circuit 86. In the sense amplifier 10 ', the load circuit includes two PMOS transistors 102 and 104. In the case of a normal operation, that is, a read operation, the gate of the first PMOS transistor 102 is set to 0 V, and the gate of the second PMOS transistor 104 is set to the power supply voltage. This first PMOS transistor 102 has the same size as a conventional sense amplifier. At the time of the verify operation, the second PMOS transistor 104 having a smaller driving capability than the first PMOS transistor 102, that is, a smaller size, is turned on. Thereby, even if the gate voltage of the memory cell is constant, the gate voltage can be made apparently higher. FIG. 13 shows the relationship between the gate potential WL of the memory cell and the current I _cell flowing in the memory cell. By reducing the size of the PMOS transistor 104 as a load, the sensitivity becomes equal to the normal sensitivity (PM
From the OS transistor 102) to the sensitivity indicated by the broken line. Thus, it can be seen as if the gate voltage is being changed. In the verify operation, the flow shown in FIG. 4 is similarly used, but a PMOS transistor is selected instead of setting the verify potential in steps S16 and S26. Thus, in the verify operation, the distribution of threshold values can be changed at high speed, and the threshold value of the memory cell can be narrowed. In addition, it is possible to eliminate bits that largely deviate from the distribution. As a result, the sensitivity of the sense amplifier can be changed without providing a plurality of circuits for generating the above-described verify potential therein, the same function can be achieved, and the number of circuits can be reduced. In the sense amplifier, the number of PMOS transistors having different driving capabilities is three.
The number may be more than one.

A plurality of high voltage application methods have been described above.
However, other simpler methods of applying a constant voltage and a high voltage in a fixed time, and a combination of these methods are also conceivable.
In the above-described embodiment, the operation of lowering the threshold value of the memory cell has been described. However, it is obvious that the operation can be applied to the operation of increasing the threshold value of the memory cell as a matter of course.

[0017]

The nonvolatile semiconductor memory device according to the present invention decodes an externally input address signal to select a row, and decodes an externally input address signal to a column. And a second decoder, which is arranged in the row and column directions,
A memory array consisting of a plurality of memory cells in which information from the outside is electrically written or erased based on the output of the decoder, a sense amplifier that determines whether the information stored in the memory cells is in a predetermined state, A high voltage generating circuit for generating a voltage different from the power supply voltage, a first and a second decoder, and a control circuit for controlling the operation of the high voltage generating circuit are provided. In the verify operation, the control circuit generates a plurality of different verify potentials in the high voltage generation circuit,
Since the pulse voltage for the writing or erasing operation of the memory cell is generated a plurality of times until the verify potential is exceeded, the distribution of the threshold value can be changed at a high speed, and the threshold value of the memory cell can be narrowed. In addition, it is possible to eliminate bits that largely deviate from the distribution.

Further, in the nonvolatile semiconductor memory device according to the present invention, the control circuit causes the high voltage generating circuit to generate the first verify potential higher than the second verify potential, so that the write and read operations can be performed. By using the higher verify potential in the first operation, it is possible to prevent the threshold value generated during repeated erasure from being out of distribution by using a higher verify potential. Over programming is less likely to occur. First
The threshold value can be changed at high speed by using the high verify potential, and the threshold distribution can be narrowed by using the second low verify potential. Further, in the nonvolatile semiconductor memory device according to the present invention, the control circuit generates a plurality of pulse voltages in the high voltage generation circuit, the pulse voltage changing the variation of the threshold value of the memory cell at the same verify potential. Therefore, the width of the distribution can be narrowed and the program time can be shortened. For example, the control circuit generates a pulse voltage to be applied to the memory cell in the verify operation with a constant pulse width and an increased voltage value in the high voltage generation circuit, Since the increase in the voltage value is made larger than the increase in the second verify potential, the width of the distribution can be narrowed and the programming time can be shortened. For example, the above-described control circuit generates a pulse voltage applied to the memory cell with a constant voltage value and an increased pulse width, and generates an increase in the pulse width at the first verify potential in the second verify voltage. Since it is larger than the increase in the potential, the width of the distribution can be narrowed and the program time can be shortened.

Further, the nonvolatile semiconductor memory device according to the present invention decodes an externally input address signal to select a row, and decodes an externally input address signal to a column. Second choice
And a memory array comprising a plurality of memory cells arranged in the row and column directions and electrically writing or erasing external information based on the outputs of the first and second decoders. , A sense amplifier that determines whether the information stored in the memory cell is in a predetermined state, a high voltage generation circuit that generates a voltage different from the power supply voltage, and operations of the first and second decoders and the high voltage generation circuit. And a control circuit for controlling the sense amplifier. Since the sensitivity of the sense amplifier can be changed, the threshold distribution can be changed at a high speed by changing the sensitivity of the sense amplifier. Can be narrowed. By changing the sensitivity of the sense amplifier, the detection level can be changed in a pseudo manner without providing a circuit for internally generating a plurality of verify potentials.
Thereby, by changing the sensitivity of the sense amplifier,
Similarly, the threshold distribution can be changed at a high speed, and the threshold of the memory cell can be narrowed. In addition, it is possible to eliminate bits that largely deviate from the distribution. Further, in the nonvolatile semiconductor memory device according to the present invention, since the sense amplifier is configured by connecting transistors having different sensitivities in parallel, the sensitivity of the sense amplifier can be changed by selectively using one of the transistors. It is.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a flash memory as an example of a semiconductor integrated circuit device according to the present invention.

FIG. 2 is a diagram showing the movement of electrons in the writing operation of the DINOR type flash memory.

FIG. 3 is a diagram showing movement of electrons in an erasing operation of the DINOR type flash memory.

FIG. 4 is a basic flowchart of a write / erase operation in the flash memory according to the first embodiment of the present invention.

FIG. 5 is a time chart showing application of a high voltage in a write operation in a DINOR type flash memory.

FIG. 6 is a schematic graph showing a distribution of threshold values in the flash memory according to the first embodiment of the present invention;

FIG. 7 is a time chart showing high voltage application at the time of writing in the DINOR type flash memory according to the second embodiment of the present invention;

FIG. 8 is a diagram showing the movement of electrons in a write operation of a DINOR type flash memory.

FIG. 9 is a diagram showing a movement of electrons in an erase operation of the DINOR type flash memory.

FIG. 10 is a time chart showing application of a high voltage during an erasing operation in a NOR flash memory according to a third embodiment of the present invention;

FIG. 11 is a time chart showing high voltage application during an erasing operation in a NOR flash memory according to a fourth embodiment of the present invention.

FIG. 12 is a circuit diagram including a memory cell and a sense amplifier in a flash memory according to a fifth embodiment of the present invention;

FIG. 13 is a graph showing a relationship between a gate potential (WL) of a memory cell and a current (I _cell ) flowing through the memory cell in the flash memory according to the fifth embodiment of the present invention.

[Explanation of symbols]

2 memory array, 4 X decoder, 6 Y decoder, 10 sense amplifier, 12 control circuit, 14
High voltage generation circuit.

Claims (7)

[Claims] A first decoder for decoding an externally input address signal to select a row; a second decoder for decoding an externally input address signal to select a column; A memory array composed of a plurality of memory cells arranged in a column direction and electrically writing or erasing external information based on the outputs of the first and second decoders; and information stored in the memory cells. Includes a sense amplifier that determines whether the voltage is in a predetermined state, a high voltage generation circuit that generates a voltage different from the power supply voltage, and a control circuit that controls operations of the first and second decoders and the high voltage generation circuit. In the verify operation, the control circuit generates a plurality of different verify potentials in the high voltage generating circuit, and performs a write or erase operation of the memory cell until the verify potential exceeds the verify potential. A nonvolatile semiconductor memory device characterized by generating a pulse voltage for operation a plurality of times. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said control circuit causes said high voltage generation circuit to generate a first verify potential higher than a second verify potential. A nonvolatile semiconductor memory device characterized by the above-mentioned. 3. The non-volatile semiconductor memory device according to claim 1, wherein said control circuit is configured to control said high voltage generation circuit to change a threshold voltage variation of a memory cell at the same verify potential. A non-volatile semiconductor memory device which generates a pulse voltage twice. 4. The nonvolatile semiconductor memory device according to claim 3, wherein said control circuit controls said high voltage generating circuit to apply a pulse voltage applied to a memory cell in a verify operation to a constant pulse width. Is generated by increasing the voltage value,
A non-volatile semiconductor memory device characterized in that the increase in the voltage value at the verify potential is larger than the increase at the second verify potential. 5. The nonvolatile semiconductor memory device according to claim 3, wherein said control circuit controls said high voltage generating circuit to apply a pulse voltage applied to a memory cell in a verify operation to a constant voltage value. , The pulse width is increased and the first
A non-volatile semiconductor memory device characterized in that the increase in pulse width at the verify potential is larger than the increase at the second verify potential. 6. A first decoder that decodes an externally input address signal to select a row, a second decoder that decodes an externally input address signal to select a column, And a memory array composed of a plurality of memory cells arranged in a column direction and electrically writing or erasing external information based on the outputs of the first and second decoders, and storing the information in these memory cells. A sense amplifier for determining whether the obtained information is in a predetermined state, a high voltage generating circuit for generating a voltage different from the power supply voltage, a control circuit for controlling operations of the first and second decoders and the high voltage generating circuit, And the sensitivity of the sense amplifier is changeable. 7. The nonvolatile semiconductor memory device according to claim 6, wherein said sense amplifier is configured by connecting transistors having different sensitivities in parallel.