JP5474684B2 - Drive control circuit, control device, switching power supply device, and control method - Google Patents

Description

  The present invention relates to a drive control circuit, a control device, a switching power supply device, and a control method for alternately turning on / off a high-side switch element and a low-side switch element connected in series.

  In a drive control circuit for a high voltage power element, for example, a circuit for transmitting a low voltage logic signal to a gate control unit of a high side switch element (output element) is required.

  Conventionally, in such a drive control circuit, a method of transmitting a signal using a high-breakdown-voltage MOS transistor is used (for example, see Patent Document 1).

  In the conventional drive control circuit, for example, the high-side drive signal SDH and the low-side drive signal SDL are alternately input, and the high-side switch element and the low-side switch element that are high breakdown voltage power elements are alternately turned on / off.

  Thereby, the intermediate potential VS between the high-side switch element and the low-side switch element changes according to the high-side drive signal SDH and the low-side drive signal SDL.

JP 2006-270382 A

  By the way, in the conventional drive control circuit, for example, when the intermediate potential VS between the high-side switch element and the low-side switch element suddenly changes due to a sudden change in the input voltage or loss of resonance of the resonance circuit when the load is short-circuited. The potential of the terminal from which the rise signal Rise is output becomes higher due to the influence of the parasitic capacitance of the MOS transistor M1.

  At this time, even if the MOS transistor M1 is turned on by the edge detection signal V1 corresponding to the rising edge of the high side drive signal SDH and the current Irise flows, the peak level of the rise signal Rise does not decrease below the specified value.

  Therefore, the drive SR latch circuit is not set by the rise signal Rise, and the high side driver does not output the control signal VGH at the “High” level.

  That is, in the conventional drive control circuit described above, when the intermediate potential VS changes suddenly due to, for example, sudden change in input voltage or loss of resonance when the load is short-circuited, a predetermined value is determined according to the high side drive signal SDH and the low side drive signal SDL. There is a problem that can not work.

A drive control circuit according to an embodiment of one aspect of the present invention includes:
A drive control circuit for alternately turning on and off a high-side switch element and a low-side switch element connected in series between two different potentials,
An edge of a high side drive signal for on / off control of the high side switch element is detected, and a first edge according to a first edge of the high side drive signal for turning on the high side switch element An edge detection circuit that outputs a detection signal and outputs a second edge detection signal in response to a second edge of the high-side drive signal for turning off the high-side switch element;
A first resistor having one end connected to a first potential line of a first potential;
A first MOS transistor having one end connected to the other end of the first resistor and turned on in response to the first edge detection signal;
A first current limiting element connected between the other end of the first MOS transistor and a second potential line having a second potential lower than the first potential;
A second resistor having one end connected to the first potential line;
A second MOS transistor having one end connected to the other end of the second resistor and turned on in response to the second edge detection signal;
A second current limiting element connected between the other end of the second MOS transistor and the second potential line;
A rise signal that is a potential between the other end of the first resistor and one end of the first MOS transistor is input to a set terminal, and the other end of the second resistor and one end of the second MOS transistor are input. An SR latch circuit for driving, in which a fall signal, which is a potential between the two, is input to the reset terminal;
A high-side driver that outputs a first control signal for controlling the high-side switch element in accordance with an output of the driving SR latch circuit;
In response to a state detection signal obtained by detecting a state of a resonance circuit connected to an intermediate terminal between the high-side switch element and the low-side switch element, the other end of the first MOS transistor and the And a resistance control circuit for reducing a resistance value between the second potential line and the second potential line.

In the drive control circuit,
The state detection signal may be a signal obtained by detecting an out-of-resonance state of the resonance circuit.

In the drive control circuit,
The resistance control circuit includes:
The resistance value between the other end of the first MOS transistor and the second potential line is lowered from the input of the state detection signal to the input of the second edge detection signal. May be.

In the drive control circuit,
The resistance control circuit is:
An SR latch circuit for resistance in which the state detection signal is input to a set terminal and the second edge detection signal is input to a reset terminal;
The first MOS transistor is connected in parallel with the first current limiting element between the other end of the first MOS transistor and the second potential line, and according to the output of the resistance SR latch circuit, the first MOS transistor You may make it have a switch element which conducts between the other end of a transistor, and the said 2nd potential line.

In the drive control circuit,
The switch element is
A resistance MOS transistor connected in parallel with the first current limiting element between the other end of the first MOS transistor and the second potential, and an output of the resistance SR latch circuit being input to a gate You may make it be.

In the drive control circuit,
You may make it further provide the low side driver which outputs the 2nd control signal for controlling the said low side switch element according to the low side drive signal for carrying out on / off control of the said low side switch element.

In the drive control circuit,
A bootstrap capacitor may be connected between the first potential line and the intermediate terminal.

In the drive control circuit,
The first MOS transistor is an nMOS transistor in which the first edge detection signal is input to a gate;
The second MOS transistor may be an nMOS transistor in which the second edge detection signal is input to the gate.

In the drive control circuit,
The first MOS transistor is turned on for a certain period according to the first edge detection signal,
The second MOS transistor may be turned on for a certain period in accordance with the second edge detection signal.

In the drive control circuit,
The first current limiting element and the second current limiting element may be resistors.

In the drive control circuit,
The high side driver may be a buffer.

In the drive control circuit,
The low side driver may be a buffer.

A drive control circuit according to an embodiment of one aspect of the present invention includes:
A drive signal generation circuit for outputting a high-side drive signal and a low-side drive signal for alternately controlling on / off of a high-side switch element and a low-side switch element connected in series between two different potentials;
A first control signal is generated according to the high-side drive signal and a second control signal is generated according to the low-side drive signal. The high-side switch element and the low-side switch element are connected to the first and second A drive control circuit that alternately performs on / off control according to two control signals,
The drive control circuit includes:
An edge of a high side drive signal for on / off control of the high side switch element is detected, and a first edge according to a first edge of the high side drive signal for turning on the high side switch element An edge detection circuit that outputs a detection signal and outputs a second edge detection signal in response to a second edge of the high-side drive signal for turning off the high-side switch element;
A first resistor having one end connected to a first potential line of a first potential;
A first MOS transistor having one end connected to the other end of the first resistor and turned on in response to the first edge detection signal;
A first current limiting element connected between the other end of the first MOS transistor and a second potential line having a second potential lower than the first potential;
A second resistor having one end connected to the first potential line;
A second MOS transistor having one end connected to the other end of the second resistor and turned on in response to the second edge detection signal;
A second current limiting element connected between the other end of the second MOS transistor and the second potential line;
A rise signal that is a potential between the other end of the first resistor and one end of the first MOS transistor is input to a set terminal, and the other end of the second resistor and one end of the second MOS transistor are input. An SR latch circuit for driving, in which a fall signal, which is a potential between the two, is input to the reset terminal;
A high-side driver that outputs a first control signal for controlling the high-side switch element in accordance with an output of the driving SR latch circuit;
In response to a detection signal obtained by detecting a state of a resonance circuit connected to an intermediate terminal between the high-side switch element and the low-side switch element, the other end of the first MOS transistor and the first And a resistance control circuit for reducing a resistance value between the two potential lines.

A switching power supply device according to an embodiment of one aspect of the present invention includes:
The control device;
DC power supply,
A high-side switch element having one end connected to the first terminal of the DC power supply and controlled by the first control signal;
One end is connected to the other end of the high-side switch element, the other end is connected to a second terminal of the DC power supply, and the low-side switch element is controlled by the second control signal;
A transformer including a primary side winding and a secondary side winding for generating an output voltage;
A capacitor connected in series with the primary winding between one end and the other end of the low-side switch element, and constituting a resonance circuit with the primary winding;
And a detection circuit that outputs the state detection signal obtained by detecting the state of the resonance circuit by monitoring a current flowing through the capacitor.

In the drive control circuit,
The state detection signal is
The signal may be obtained by detecting a state of resonance resonance of the resonance circuit.

A control method according to an embodiment according to an aspect of the present invention includes:
A drive control circuit for alternately turning on / off a high-side switch element and a low-side switch element connected in series between two different potentials for controlling the on / off of the high-side switch element An edge of a high side drive signal is detected, a first edge detection signal is output in response to a first edge of the high side drive signal for turning on the high side switch element, and the high side switch element An edge detection circuit that outputs a second edge detection signal in response to a second edge of the high-side drive signal for turning off the first side, and a first terminal having one end connected to the first potential line of the first potential A first MOS transistor having one end connected to the other end of the first resistor and turned on in response to the first edge detection signal; and A first current limiting element connected between the other end of the MOS transistor and a second potential line having a second potential lower than the first potential, and one end of the first potential line. , A second MOS transistor having one end connected to the other end of the second resistor and turned on in response to the second edge detection signal, and a second MOS transistor A second current limiting element connected between the other end and the second potential line, and a rise signal that is a potential between the other end of the first resistor and one end of the first MOS transistor Is input to the set terminal, and a drive SR latch circuit in which a fall signal, which is a potential between the other end of the second resistor and one end of the second MOS transistor, is input to the reset terminal, and the drive Depending on the output of the SR latch circuit, Drive control circuit comprising a high side driver for outputting a first control signal for controlling the side switch element, a control method,
In response to a state detection signal obtained by detecting a state of a resonance circuit connected to an intermediate terminal between the high-side switch element and the low-side switch element, the other end of the first MOS transistor and the The resistance value between the second potential line is lowered.

In the control method,
The state detection signal is
The signal may be obtained by detecting a state of resonance resonance of the resonance circuit.

  According to the drive control circuit of one aspect of the present invention, the resistance control circuit is obtained by detecting the resonance loss of the resonance circuit connected to the intermediate terminal between the high-side switch element and the low-side switch element. In response to the state detection signal Des, the resistance value between the other end of the first MOS transistor and the second potential line is lowered.

  That is, when the resonance out of the resonance circuit is detected, the output Las of the resistance SR latch circuit becomes “High” level, and the resistance MOS transistor is turned on.

  At this time, when the first MOS transistor is turned on in response to the high side drive signal SDH, the peak level of the rise signal Rise is further lowered (lowered to a predetermined level).

  Accordingly, in response to the rise signal Rise, the driving SR latch circuit is set, and the high-side driver outputs the first control signal VGH having a desired “High” level.

  That is, according to the drive control circuit, the control device, and the control method according to one aspect of the present invention, even when the intermediate potential VS is suddenly changed due to sudden change of input voltage or loss of resonance at the time of load short-circuiting, etc. A predetermined operation can be performed according to the signal SDH and the low-side drive signal SDL.

  Furthermore, according to the switching power supply device according to one aspect of the present invention, even when the intermediate potential VS suddenly changes, the high-side switch element and the low-side switch element are operated in a prescribed manner to output a predetermined output voltage. can do.

FIG. 1 is a diagram illustrating an example of a configuration of a switching power supply apparatus 1000 according to a first embodiment which is an aspect of the present invention. FIG. 2 is a diagram showing an example of the configuration of the control device 100 of the switching power supply device 1000 shown in FIG. FIG. 3 is a diagram showing an example of the configuration of the drive control circuit 101 of the control device 100 shown in FIG. FIG. 4 is a waveform diagram showing an example of each waveform of the drive control circuit 101 shown in FIG.

  Embodiments according to the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram illustrating an example of a configuration of a switching power supply apparatus 1000 according to a first embodiment which is an aspect of the present invention.

  As shown in FIG. 1, the switching power supply device 1000 includes a control device 100, a DC power supply Vin, a high-side switch element (nMOS transistor) Q1, a low-side switch element (nMOS transistor) Q2, a transformer T, and a diode D3. , D4, capacitors C3 and C4, output terminals out1 and out2, and a detection circuit 1001.

  The control device 100 outputs a first control signal VGH and a second control signal VGL for alternately turning on / off the high-side switch element Q1 and the low-side switch element Q2.

  The direct current power source Vin outputs a direct current voltage.

  The high-side switch element Q1 has one end (drain) connected to the first terminal (positive electrode) of the DC power supply Vin, and the first control signal VGH is input to the gate. That is, the high side switch element Q1 is controlled by the first control signal VGH.

  The low-side switch element Q2 has one end (drain) connected to the other end (source) of the high-side switch element Q1, and the other end (source) connected to the second terminal (negative electrode) of the DC power source Vin. A control signal VGL is input to the gate. That is, the low side switch element Q2 is controlled by the second control signal VGL.

  Thus, the high side switch element Q1 and the low side switch element Q2 are connected in series between two different potentials. Note that the other end (source) of the low-side switch element Q2 may be further connected to ground.

  The transformer T for generating the output voltage includes a primary side winding T1 and secondary side windings T2 and T3.

  The capacitor C3 is connected in series with the primary winding T1 between one end (drain) and the other end (source) of the low-side switch element Q2. This capacitor C3 forms a resonance circuit with the primary winding T1.

  Secondary windings T2 and T3 are connected in series. One end of the secondary winding T2 is connected to the output terminal out1 via the diode D3, and the other end of the secondary winding T2 is connected to the output terminal out2. One end of the secondary winding T3 is connected to the output terminal out2, and the other end of the secondary winding T3 is connected to the output terminal out1 via the diode D4.

  The capacitor C4 is connected between the output terminal out1 and the output terminal out2.

  The control device 100 outputs a first control signal VGH and a second control signal VGL for alternately turning on / off the high-side switch element Q1 and the low-side switch element Q2.

  The detection circuit 1001 outputs a state detection signal Des obtained by detecting the state of the resonance circuit (in this case, for example, out of resonance) by monitoring the current flowing through the capacitor C3. Yes. For example, when the detection circuit 1001 determines that the state of the resonance circuit is out of resonance based on a change in the current flowing through the capacitor C3, the detection circuit 1001 outputs a “High” level state detection signal Des.

  In the switching power supply device 1000 having the above-described configuration, the control device 100 alternately turns on / off the high-side switch element Q1 and the low-side switch element Q2 so that the high-side switch element and the low-side switch element are connected. The intermediate potential changes. As a result, the resonance circuit undergoes current resonance, and a voltage is supplied from the transformer T to the load Load connected to the output terminals out1 and out2.

  Here, an example of the configuration of the control device 100 will be described. FIG. 2 is a diagram showing an example of the configuration of the control device 100 of the switching power supply device 1000 shown in FIG.

  As illustrated in FIG. 2, the control device 100 includes a drive control circuit 101 and a drive signal generation circuit 102.

  The drive signal generation circuit 102 outputs a high side drive signal SDH and a low side drive signal SDL for alternately turning on / off the high side switch element Q1 and the low side switch element Q2.

  The drive control circuit 101 generates the first control signal VGH in response to the high side drive signal SDH and generates the second control signal VGL in response to the low side drive signal SDL. That is, the drive control circuit 101 alternately controls on / off of the high-side switch element Q1 and the low-side switch element Q2 by the high-side drive signal and the low-side drive signals SDH, SDL.

  Here, an example of the configuration of the drive control circuit 101 will be described. FIG. 3 is a diagram showing an example of the configuration of the drive control circuit 101 of the control device 100 shown in FIG.

  As shown in FIG. 3, the drive control circuit 101 includes an edge detection circuit 1, a resistance control circuit 2, a first current limiting element 3, a second current limiting element 4, and a driving SR latch circuit 5. The high side driver 6, the low side driver 7, the first potential line 8, the second potential line 9, the third potential line 10, the first resistor R1, the second resistor R2, It has a first MOS transistor M1, a second MOS transistor M2, and a bootstrap capacitor Cbs.

  The edge detection circuit 1 detects the edge of the high side drive signal SDH for on / off control of the high side switch element Q1.

  The edge detection circuit 1 is, for example, in response to the first edge of the high-side drive signal SDH for turning on the high-side switch element Q1 (for example, the rising edge of the pulse signal). 1 edge detection signal V1 is output.

  On the other hand, the edge detection circuit 1 outputs the second edge detection signal V2 in accordance with the second edge (for example, the falling edge of the pulse signal) of the high side drive signal SDH for turning off the high side switch element Q1. Output.

  One end of the first resistor R1 is connected to the first potential line 8 of the first potential (for example, power supply potential) VB.

  The first MOS transistor M1 has one end (drain) connected to the other end of the first resistor R1. In the first MOS transistor M1, the first edge detection signal V1 is input to the gate, and the first MOS transistor M1 is turned on in response to the first edge detection signal V1. The parasitic capacitance Cp1 of the first MOS transistor M1 exists so as to be connected between the drain of the first MOS transistor M1 and the second potential line 9.

  Here, for example, when the first MOS transistor M1 is turned on, the current Irise flows through the first MOS transistor M1, thereby causing the other end of the first resistor R1 and one end (drain) of the first MOS transistor M1 to The level of the rise signal Rise, which is the potential between the two, decreases.

  The first current limiting element 3 includes the other end (source) of the first MOS transistor M1 and a second potential line having a second potential (for example, ground potential) PG lower than the first potential VB. 9 is connected. The first current limiting element 3 is constituted by a resistor R3, for example.

  One end of the second resistor R 2 is connected to the first potential line 8.

  The second MOS transistor M2 has one end (drain) connected to the other end of the second resistor R2. The second MOS transistor M2 is turned on in response to the second edge detection signal V2 when the second edge detection signal V2 is input to the gate. The parasitic capacitance Cp2 of the second MOS transistor M2 exists so as to be connected between the drain of the second MOS transistor M2 and the second potential line 9.

  Here, for example, when the second MOS transistor M2 is turned on, the current Ifall flows to the second MOS transistor M2, thereby causing the other end of the second resistor R2 and one end (drain) of the second MOS transistor M2 to The level of the fall signal Fall, which is a potential between the two, decreases.

  The second current limiting element 4 is connected between the other end (source) of the second MOS transistor M 2 and the second potential line 9. The second current limiting element 4 is composed of, for example, a resistor R4.

  In the driving SR latch circuit 5, a rise signal Rise, which is a potential between the other end of the first resistor R1 and one end (drain) of the first MOS transistor M1, is input to the set terminal S, and the second resistor A fall signal Fall, which is a potential between the other end of R2 and one end (drain) of the second MOS transistor M2, is input to the reset terminal R.

  The high side driver 6 outputs a first control signal VGH for controlling the high side switch element Q1 in accordance with the output of the driving SR latch circuit 5. The high-side driver 6 is, for example, a buffer that amplifies the output of the driving SR latch circuit 5 and outputs the first control signal VGH.

  The driving SR latch circuit 5 and the high-side driver 6 are connected between the first potential line 8 and the third potential line 10 and are supplied with an operating voltage.

  The third potential line 10 is connected to the intermediate terminal X. A bootstrap capacitor Cbs for maintaining a potential difference between the first potential line 8 and the third potential line 10 is connected between the third potential line 10 and the first potential line 8. ing. Thereby, when the intermediate potential VS varies, the first potential of the first potential line 8 also varies.

  Therefore, for example, when the intermediate potential VS of the intermediate terminal X changes due to the resonance of the resonance circuit, the first potential VB changes according to the change of the intermediate potential VS. For example, when the intermediate potential VS rises and the first potential VB also rises, the levels of the rise signal Rise and the fall signal Fall are lowered due to the influence of the parasitic capacitances Cp1 and Cp2. On the other hand, when the intermediate potential VS decreases and the first potential VB also decreases, the levels of the rise signal Rise and the fall signal Fall increase due to the influence of the parasitic capacitances Cp1 and Cp2.

  In addition, the resistance control circuit 2 detects the state of the resonance circuit (T1, C3) connected to the intermediate terminal X between the high-side switch element Q1 and the low-side switch element Q2 and obtains a state detection signal Des. Accordingly, the resistance value between the other end (drain) of the first MOS transistor M1 and the second potential line 9 is lowered.

  For example, the resistance control circuit 2 includes the other end (drain) of the first MOS transistor M1 and the second potential from when the state detection signal Des is input to when the second edge detection signal V2 is input. The resistance value between the line 9 is lowered.

  As shown in FIG. 3, the resistance control circuit 2 includes, for example, a resistance SR latch circuit 2a and a switch element MR.

  In the resistance SR latch circuit 2a, the state detection signal Des is input to the set terminal S, and the second edge detection signal V2 is input to the reset terminal R.

  The switch element MR is connected in parallel with the first current limiting element 3 between the other end (source) of the first MOS transistor M1 and the second potential line 9, and the output of the resistance SR latch circuit 2a. In response to the signal Las, the other end (source) of the first MOS transistor M and the second potential line 9 are made conductive. As a result, the resistance value between the other end (source) of the first MOS transistor M1 and the second potential line 9 decreases.

  For example, as shown in FIG. 3, the switch element MR is connected in parallel with the first current limiting element 3 between the other end (source) of the first MOS transistor M1 and the second potential line 9. This is a resistance MOS transistor. The resistance MOS transistor has its gate connected to the output of the resistance SR latch circuit 2a, and is turned on / off by the output signal Las of the resistance SR latch circuit 2a.

  The low-side driver 7 outputs a second control signal VGL for controlling the low-side switch element Q2 in response to a low-side drive signal SDL for controlling on / off of the low-side switch element Q2. The low side driver 7 is, for example, a buffer that amplifies the low side drive signal SDL and outputs the second control signal VGL.

  Next, an example of the operation of the drive control circuit 101 having the above configuration will be described.

FIG. 4 is a waveform diagram showing an example of each waveform of the drive control circuit 101 shown in FIG. In FIG. 4, for the sake of explanation, the period from time t1 to t5 represents a case where the state detection signal Des is not input to the drive control circuit 101, while the period from time t6 to t12 represents the state detection signal Des. The case where it inputs into the drive control circuit 101 is represented.
As shown in FIG. 4, for example, when the first potential VB also decreases due to the sudden change (decrease) in the intermediate potential VS, as described above, the rise signal Rise increases from the normal level (time t1). ~ T4).

  When the high-side drive signal SDH becomes “High” level at time t2, the edge detection circuit 1 causes the first edge detection signal V1 of “High” level according to the rising edge of the high-side drive signal SDH. Is output.

  As a result, the first MOS transistor M1 is turned on for a certain period (time t2 to t3) and the current Irise flows, but the peak level of the rise signal Rise does not fall below the specified value (time t2 to t3).

  Therefore, the drive SR latch circuit 5 is not set by the rise signal Rise, and the high-side driver 6 does not output the first control signal VGH of “High” level (time t2 to t5).

  At time t4, the intermediate potential VS returns to a predetermined level, so that the level of the rise signal Rise also returns to the normal level.

  At time t5, the edge detection circuit 1 outputs the second edge detection signal V2 according to the falling edge of the high side drive signal SDH.

  As a result, the second MOS transistor M2 is turned on for a certain period and the current Ifall flows, but the peak level of the fall signal Fall is lowered.

  As described above, when the intermediate potential VS is suddenly changed, if the state detection signal Des is not input (in other words, when there is no resistance control circuit 2 (prior art)), the drive control circuit 101 performs the first operation at a predetermined level. The control signal VGH is not output.

  Next, at time t6 to t8, for example, when the first potential VB also decreases due to a sudden change (decrease) in the intermediate potential VS, the rise signal Rise increases from the normal level as described above.

  On the other hand, at time t7, the resistance SR latch circuit 2a of the resistance control circuit 2 outputs a “High” level signal Las in response to the state detection signal Des. As a result, the switch element MR is turned on, and the other end (source) of the first MOS transistor M and the second potential line 9 are made conductive. Therefore, the resistance value between the other end (source) of the first MOS transistor M1 and the second potential line 9 decreases.

  In other words, the resistance control circuit 2 has the other end (drain) of the first MOS transistor M1 during the period from when the state detection signal Des is input to when the second edge detection signal V2 is input (time t7 to t12). And the resistance value between the second potential line 9 is lowered.

  When the high side drive signal SDH becomes “High” level at time t9, the edge detection circuit 1 causes the first edge detection signal V1 of “High” level according to the rising edge of the high side drive signal SDH. Is output.

  As a result, the first MOS transistor M1 is turned on for a certain period (time t9 to t10), and the current Irise flows. Here, since the other end (source) of the first MOS transistor M and the second potential line 9 are electrically connected, the current Irise increases more than the period of time t2 to t3, and therefore the rise signal Rise. Will be lower than the specified value (time t9 to t10).

  Accordingly, the drive SR latch circuit 5 is set by the rise signal Rise, and the high-side driver 6 outputs the first control signal VGH of “High” level (time t9 to t12).

  At time t11, the intermediate potential VS returns to a predetermined level, so that the level of the rise signal Rise also returns to the normal level.

  At time t12, the edge detection circuit 1 outputs the second edge detection signal V2 in accordance with the falling edge of the high side drive signal SDH.

  As a result, the second MOS transistor M2 is turned on for a certain period, the current Ifall flows, and the peak level of the fall signal Fall is lowered. The drive SR latch circuit 5 is reset by the fall signal Fall, and the high-side driver 6 outputs the “Low” level level.

  Thus, when the intermediate potential VS changes suddenly, the state detection signal Des is input, whereby the drive control circuit 101 can output the first control signal VGH having a predetermined level.

  As described above, according to the drive control circuit 101, the control device 100, and the control method according to the present embodiment, even when the intermediate potential VS is suddenly changed due to sudden change of input voltage or loss of resonance at the time of load short circuit, A predetermined operation can be performed in accordance with the high side drive signal SDH and the low side drive signal SDL.

  Furthermore, according to the switching power supply apparatus 1000 according to an aspect of the present invention, even when the intermediate potential VS changes suddenly, the high-side switch element Q1 and the low-side switch element Q2 are operated with each other as prescribed, and a predetermined output A voltage can be output.

DESCRIPTION OF SYMBOLS 1 Edge detection circuit 2 Resistance control circuit 2a Resistor SR latch circuit 3 1st current limiting element 4 2nd current limiting element 5 Drive SR latch circuit 6 High side driver 7 Low side driver 8 1st electric potential line 9 2nd Potential line 10 third potential line 100 control device 101 drive control circuit 102 drive signal generation circuit 1000 switching power supply device 1001 detection circuit Vin DC power source Q1 high side switch element Q2 low side switch element T transformer T1 primary windings T2, T3 Secondary winding D3, D4 Diode C3, C4 Capacitor Cbs Bootstrap capacitor out1, out2 Output terminal R1 First resistor R2 Second resistor M1 First MOS transistor M2 Second MOS transistor MR Switch element

Claims (14)

A drive control circuit for alternately turning on and off a high-side switch element and a low-side switch element connected in series between two different potentials,
An edge of a high side drive signal for on / off control of the high side switch element is detected, and a first edge according to a first edge of the high side drive signal for turning on the high side switch element An edge detection circuit that outputs a detection signal and outputs a second edge detection signal in response to a second edge of the high-side drive signal for turning off the high-side switch element;
A first resistor having one end connected to a first potential line of a first potential;
A first MOS transistor having one end connected to the other end of the first resistor and turned on in response to the first edge detection signal;
A first current limiting element connected between the other end of the first MOS transistor and a second potential line having a second potential lower than the first potential;
A second resistor having one end connected to the first potential line;
A second MOS transistor having one end connected to the other end of the second resistor and turned on in response to the second edge detection signal;
A second current limiting element connected between the other end of the second MOS transistor and the second potential line;
A rise signal that is a potential between the other end of the first resistor and one end of the first MOS transistor is input to a set terminal, and the other end of the second resistor and one end of the second MOS transistor are input. An SR latch circuit for driving, in which a fall signal, which is a potential between the two, is input to the reset terminal;
A high-side driver that outputs a first control signal for controlling the high-side switch element in accordance with an output of the driving SR latch circuit;
In response to a state detection signal obtained by detecting a state of a resonance circuit connected to an intermediate terminal between the high-side switch element and the low-side switch element, the other end of the first MOS transistor and the and a resistance control circuit to reduce the resistance value between the second potential line,
The drive control circuit according to claim 1, wherein the state detection signal is a signal obtained by detecting an out-of-resonance state of the resonance circuit. The resistance control circuit includes:
The resistance value between the other end of the first MOS transistor and the second potential line is lowered from when the state detection signal is input to when the second edge detection signal is input. The drive control circuit according to claim 1 , wherein: The resistance control circuit is:
An SR latch circuit for resistance in which the state detection signal is input to a set terminal and the second edge detection signal is input to a reset terminal;
The first MOS transistor is connected in parallel with the first current limiting element between the other end of the first MOS transistor and the second potential line, and according to the output of the resistance SR latch circuit, the first MOS transistor the drive control circuit according to claim 1 or 2, characterized in that it comprises a switching element for electrically connecting between the other end and said second potential line of the transistor, a. The switch element is
A resistance MOS transistor connected in parallel with the first current limiting element between the other end of the first MOS transistor and the second potential, and an output of the resistance SR latch circuit being input to a gate The drive control circuit according to claim 3 , wherein: The low side driver which outputs the 2nd control signal for controlling the low side switch element according to the low side drive signal for on / off control of the low side switch element is further provided. The drive control circuit as described in any one of thru | or 4 . The drive control circuit according to any one of claims 1 to 5 , wherein a bootstrap capacitor is connected between the first potential line and the intermediate terminal. The first MOS transistor is an nMOS transistor in which the first edge detection signal is input to a gate;
The drive control circuit according to any one of claims 1 to 6 , wherein the second MOS transistor is an nMOS transistor to which the second edge detection signal is input to a gate. The first MOS transistor is turned on for a certain period according to the first edge detection signal,
The drive control circuit according to any one of claims 1 to 7 , wherein the second MOS transistor is turned on for a certain period in accordance with the second edge detection signal. Said first current limiting element and said second current limiting element, the drive control circuit according to any one of claims 1 to 8, characterized in that a resistor. The high side driver, the drive control circuit according to any one of claims 1 to 9, characterized in that a buffer. The drive control circuit according to claim 5 , wherein the low-side driver is a buffer. A drive signal generation circuit for outputting a high-side drive signal and a low-side drive signal for alternately controlling on / off of a high-side switch element and a low-side switch element connected in series between two different potentials;
A first control signal is generated according to the high-side drive signal and a second control signal is generated according to the low-side drive signal. The high-side switch element and the low-side switch element are connected to the first and second A drive control circuit that alternately performs on / off control according to two control signals,
The drive control circuit includes:
An edge of a high side drive signal for on / off control of the high side switch element is detected, and a first edge according to a first edge of the high side drive signal for turning on the high side switch element An edge detection circuit that outputs a detection signal and outputs a second edge detection signal in response to a second edge of the high-side drive signal for turning off the high-side switch element;
A first resistor having one end connected to a first potential line of a first potential;
A first MOS transistor having one end connected to the other end of the first resistor and turned on in response to the first edge detection signal;
A first current limiting element connected between the other end of the first MOS transistor and a second potential line having a second potential lower than the first potential;
A second resistor having one end connected to the first potential line;
A second MOS transistor having one end connected to the other end of the second resistor and turned on in response to the second edge detection signal;
A second current limiting element connected between the other end of the second MOS transistor and the second potential line;
A rise signal that is a potential between the other end of the first resistor and one end of the first MOS transistor is input to a set terminal, and the other end of the second resistor and one end of the second MOS transistor are input. An SR latch circuit for driving, in which a fall signal, which is a potential between the two, is input to the reset terminal;
A high-side driver that outputs a first control signal for controlling the high-side switch element in accordance with an output of the driving SR latch circuit;
In response to a state detection signal obtained by detecting a state of a resonance circuit connected to an intermediate terminal between the high-side switch element and the low-side switch element, the other end of the first MOS transistor and the a resistance control circuit to reduce the resistance value between the second potential line, possess,
The control device according to claim 1, wherein the state detection signal is a signal obtained by detecting an out-of-resonance state of the resonance circuit . The control device according to claim 12 ,
DC power supply,
A high-side switch element having one end connected to the first terminal of the DC power supply and controlled by the first control signal;
One end is connected to the other end of the high-side switch element, the other end is connected to a second terminal of the DC power supply, and the low-side switch element is controlled by the second control signal;
A transformer including a primary side winding and a secondary side winding for generating an output voltage;
A capacitor connected in series with the primary winding between one end and the other end of the low-side switch element, and constituting a resonance circuit with the primary winding;
A switching power supply comprising: a detection circuit that outputs the state detection signal obtained by detecting a state of the resonance circuit by monitoring a current flowing through the capacitor. A drive control circuit for alternately turning on / off a high-side switch element and a low-side switch element connected in series between two different potentials for controlling the on / off of the high-side switch element An edge of a high side drive signal is detected, a first edge detection signal is output in response to a first edge of the high side drive signal for turning on the high side switch element, and the high side switch element An edge detection circuit that outputs a second edge detection signal in response to a second edge of the high-side drive signal for turning off the first side, and a first terminal having one end connected to the first potential line of the first potential A first MOS transistor having one end connected to the other end of the first resistor and turned on in response to the first edge detection signal; and A first current limiting element connected between the other end of the MOS transistor and a second potential line having a second potential lower than the first potential, and one end of the first potential line. , A second MOS transistor having one end connected to the other end of the second resistor and turned on in response to the second edge detection signal, and a second MOS transistor A second current limiting element connected between the other end and the second potential line, and a rise signal that is a potential between the other end of the first resistor and one end of the first MOS transistor Is input to the set terminal, and a drive SR latch circuit in which a fall signal, which is a potential between the other end of the second resistor and one end of the second MOS transistor, is input to the reset terminal, and the drive Depending on the output of the SR latch circuit, Drive control circuit comprising a high side driver for outputting a first control signal for controlling the side switch element, a control method,
In response to a state detection signal obtained by detecting a state of a resonance circuit connected to an intermediate terminal between the high-side switch element and the low-side switch element, the other end of the first MOS transistor and the Decrease the resistance value between the second potential line ,
The control method according to claim 1, wherein the state detection signal is a signal obtained by detecting an out-of-resonance state of the resonance circuit .

Images