JP2014175816A - Pulse generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure a reliable circuit operation by reliably suppressing or reducing repetition frequency fluctuations, waveform separations and others due to noise superimposition.SOLUTION: A pulse generation circuit includes: a triangular wave generation circuit 100 configured to generate a triangular wave in a triangular wave timing capacitor 21; an offset circuit 300 configured to add an offset voltage to the triangular wave in the vicinity of charge/discharge changeovers of the triangular wave timing capacitor 21; and a PWM generating comparison circuit 200 for comparing an output of the offset circuit 300 with a desired voltage and generating a PWM signal depending on the result of comparison. This can produce a triangular wave with a voltage variation with respect to a time axis increased in each of the vicinity of an upper limit voltage and the vicinity of a lower limit voltage of the triangular wave to thereby ensure a noise-tolerant circuit operation.

Description

  The present invention relates to a pulse generation circuit that generates a pulse signal, and more particularly to a circuit that improves noise resistance in a pulse generation circuit that generates a PWM pulse signal.

As this type of conventional circuit, for example, one having a configuration as shown in FIG. 7 is well known.
Hereinafter, this conventional circuit will be described with reference to FIG.
This conventional pulse generation circuit is roughly divided into a triangular wave generation circuit 100C and a PWM generation comparison circuit 200C.
The triangular wave generating circuit 100C mainly includes two reference voltage sources V1, V2, a reference voltage changeover switch SW1, a first comparator CP1, two constant current sources I1, I2, and two transistors M1, M2. The triangular wave timing capacitor C1 is connected to the output terminal P1. Note that a P-channel MOS FET is used for the transistor M1, and an N-channel MOS FET is used for the transistor M2.
Further, the PWM generation comparison circuit 200C is configured to include a second comparator CP2.

Next, the circuit operation in such a configuration will be schematically described with reference to FIG.
First, the operation of the triangular wave generation circuit 100C will be schematically described first.
In the triangular wave generating circuit 100C, when the reference voltage changeover switch SW1 is switched to the reference voltage source V1 side, the transistor M1 is turned on, while the transistor M2 is turned off, and the triangular wave timing capacitor C1 is connected to the constant current source. Charged by I1.

Then, when charging of the triangular wave timing capacitor C1 is started, the voltage of the output terminal P1 rises linearly with the passage of time, and when the voltage of the output terminal P1 and the voltage of the reference voltage source V1 eventually become equal, the first comparator CP1. Are switched (see FIGS. 8A and 8B).
Here, FIG. 8A is a waveform diagram showing a change in the output voltage at the output terminal P1, and FIG. 8B is a waveform diagram showing a change in the PWM pulse signal at the PWM pulse output terminal P3.

  When the output of the first comparator CP1 is switched, the transistor M1 is turned off, while the transistor M2 is turned on. At the same time, the reference voltage switch SW1 is switched to the reference voltage source V2 side. As a result, the triangular wave timing capacitor C1 transitions from the charged state by the constant current source I1 to the discharged state by the constant current source I2, and the voltage at the output terminal P1 decreases linearly with time (see FIG. 8A). ).

When the voltage of the output terminal P1 becomes equal to the voltage of the reference voltage source V2, the output of the first comparator CP1 is switched again, the transistor M1 is turned on, and the transistor M2 is turned off. It will return to the initial state.
Therefore, as a result of repeating such a state, a triangular wave is generated at the output terminal P1 (see FIG. 8A).

Next, the operation of the PWM generation comparison circuit 200C will be generally described.
In the PWM generation comparison circuit 200C, the triangular wave generated as described above is applied to the inverting input terminal of the second comparator CP2, while the voltage input connected to the non-inverting input terminal of the second comparator CP2. An arbitrarily set voltage is applied to the terminal P2, and the two voltages are compared.
As a result, a PWM pulse signal having a duty ratio corresponding to the magnitude relationship between the triangular wave and the voltage at the voltage input terminal P2 is output to the PWM pulse output terminal P3 (see FIG. 8B).

In such a circuit, if the circuit operation is in an ideal state, as shown in FIG. 8, a PWM pulse signal corresponding to the triangular wave and the voltage applied to the voltage input terminal P2 is generated, and the voltage input terminal P2 is applied. By changing the voltage, the duty ratio of the PWM pulse signal can be set to a desired magnitude.
As such a pulse generation circuit for generating a PWM pulse signal, for example, an example in which the pulse generation circuit is used as a load drive signal source of an LED driver is disclosed in Patent Document 1 and the like.

Japanese Patent Laying-Open No. 2011-9253 (page 5-8, FIGS. 1 to 5)

However, in the actual pulse generation circuit, in the vicinity of the upper limit value and lower limit value of the triangular wave at the output terminal P1, it is a peripheral circuit, such as a switching power supply or a switching driver, and the voltage / current changes sharply. There is a case where the shape of the triangular wave collapses due to the influence of noise or the like from the circuit that emits noise to the circuit, and an ideal PWM pulse cannot be generated.
In particular, in the vicinity of the upper limit value and lower limit value of the triangular wave, the triangular wave timing capacitor C1 is switched from the charging state to the discharging state, or from the discharging state to the charging state, so the charging / discharging current to the triangular wave timing capacitor C1 is small or zero. State (period) exists, the amount of voltage fluctuation (tilt) with respect to the time axis of the triangular wave is reduced, and it is easily affected by noise (voltage / current).

For example, FIG. 9 shows a waveform example due to the influence of noise in the vicinity of the upper limit value of the triangular wave, and the influence of noise in the conventional circuit shown in FIG. 7 will be described with reference to FIG. When the noise is superimposed near the upper limit value of the triangular wave (see FIG. 9A) and compared with the voltage applied to the voltage input terminal P2, it is output from the PWM pulse output terminal P3. The PWM pulse signal is a signal including problems such as waveform breakage (see FIG. 9B). Furthermore, the duty is different from the original value corresponding to the voltage applied to the voltage input terminal P2, and there is a problem that a desired value cannot be obtained.
In addition, when noise is superimposed on a triangular wave as described above, the apparent amplitude of the triangular wave varies, which causes a problem that the frequency of the triangular wave shifts and varies.

  The present invention has been made in view of the above circumstances, and a pulse generation circuit capable of reliably suppressing and reducing repetition frequency fluctuations and waveform breakage due to noise superposition and generating a reliable PWM pulse signal. Is to provide.

In order to achieve the above object of the present invention, a pulse generation circuit according to the present invention includes:
Two constant current sources that charge and discharge the triangular wave capacitor, a triangular wave circuit semiconductor element that switches connection of the two constant current sources to the triangular wave capacitor, a terminal voltage and a reference voltage of the triangular wave capacitor, A triangular wave generation circuit configured to generate a triangular wave in the triangular wave capacitor, and charging of the triangular wave capacitor. An offset circuit configured to add an offset voltage to the triangular wave in the vicinity of discharge switching;
It comprises a PWM generation comparison circuit that compares the output of the offset circuit with a desired voltage and generates a PWM signal according to the comparison result.
A pulse generation circuit characterized by the above.
In this configuration, it is also preferable that the first comparator is configured to compare the output voltage of the offset circuit and the reference voltage instead of the terminal voltage of the triangular wave capacitor.
Further, in the above configuration, the offset circuit includes an offset constant current source, an offset semiconductor element, and an offset resistor, and passes through the offset semiconductor element in accordance with an output of the first comparator. And controlling the connection between the offset constant current source and the offset resistor, and the offset voltage generated by energizing the offset resistor by the offset constant current source is used as the terminal voltage of the triangular wave capacitor. What is comprised so that addition and subtraction is possible is suitable.
Further, the offset circuit includes an offset comparator that compares a terminal voltage of the triangular wave capacitor and a midpoint voltage of the triangular wave, an offset capacitor, and an offset switch element, and the offset comparator and the The charge / discharge of the offset capacitor is switched via the offset switch element according to the output of the first comparator, and an offset voltage whose amplitude changes with time can be added to or subtracted from the terminal voltage of the triangular wave capacitor. Are also suitable.

According to the present invention, a triangular wave having a large voltage fluctuation amount with respect to the time axis in the vicinity of the upper limit voltage and lower limit voltage of the triangular wave can be obtained. Reliable and reliable circuit operation can be ensured.
In particular, in the triangular wave generation circuit, by adopting a configuration that compares the output voltage of the offset circuit with the reference voltage, voltage fluctuations with respect to the time axis increase near the upper limit voltage and lower limit voltage of the triangular wave, and the comparator of the triangular wave generation circuit When the output state is switched, the operation is equivalent to providing a so-called hysteresis, so the comparison operation of the triangular wave generator circuit is less affected by noise from peripheral circuits, etc., and highly reliable and reliable circuit operation And the noise resistance of the amplitude and frequency of the triangular wave can be improved.
Furthermore, by adopting a configuration that uses capacitor charging / discharging to generate the offset voltage in the offset circuit, it is possible to obtain a triangular wave with an offset that has a larger voltage change with respect to the time axis in the vicinity of the upper limit voltage and lower limit voltage of the triangular wave. The tolerance can be further improved, and the tip shape of the triangular wave with offset can be adjusted by adjusting the time constant of the voltage change, and the optimum noise tolerance can be obtained according to the noise environment of the peripheral circuit etc. This is an effect.

It is a circuit diagram in the 1st example of a pulse generation circuit in an embodiment of the invention. 2A is a waveform diagram showing signal waveforms of main parts in the pulse generation circuit shown in FIG. 1, FIG. 2A is a waveform diagram showing waveforms of output signals of a triangular wave generation circuit, and FIG. 2B is an output of an offset circuit; It is a wave form diagram which shows the waveform of a signal. It is a circuit diagram in the 2nd example of a pulse generation circuit in an embodiment of the invention. FIG. 4A is a waveform diagram showing a signal change of a main part in the pulse generation circuit shown in FIG. 3, FIG. 4A is a waveform diagram showing a waveform of an output signal of the triangular wave generation circuit, and FIG. 4B is an output of the offset circuit. It is a wave form diagram which shows the waveform of a signal. It is a circuit diagram in the 3rd example of the pulse generation circuit in an embodiment of the invention. FIG. 6A is a signal diagram showing a change in the main signal in the pulse generation circuit shown in FIG. 5, FIG. 6A is a waveform diagram showing a waveform of an output signal of the triangular wave generation circuit, and FIG. 6B is a triangular wave with an offset. FIG. 6C is a timing chart showing the switching operation of the capacity charge / discharge switch, FIG. 6D is a waveform chart showing the charge / discharge state of the offset capacitor, and FIG. It is a wave form diagram which shows the waveform of the output signal of an offset circuit. It is a circuit diagram which shows one circuit structural example of the conventional pulse generation circuit. FIG. 8A is a waveform diagram showing a signal waveform of a main part of the conventional circuit shown in FIG. 7, FIG. 8A is a waveform diagram showing a waveform of an output signal of a triangular wave generation circuit, and FIG. 8B is a comparison for generating PWM pulses. It is a wave form diagram which shows the waveform of the output signal of a circuit. FIG. 9A is a waveform diagram showing the signal waveform of the main part when there is an influence of noise in the conventional circuit. FIG. 9A is a waveform diagram showing the waveform when noise is superimposed near the upper limit value of the triangular wave, and FIG. FIG. 10 is a waveform diagram showing a PWM pulse signal output for the triangular wave shown in FIG.

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 6.
The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.
First, a first embodiment will be described with reference to FIGS. 1 and 2.
The pulse generation circuit in the first embodiment is roughly divided into a triangular wave generation circuit 100, a PWM generation comparison circuit 200, and an offset circuit 300, and is basically similar to the conventional one. An offset circuit 300 is newly provided between the triangular wave generation circuit 100 having the configuration and the PWM generation comparison circuit 200.

  The triangular wave generation circuit 100 includes first and second reference voltage sources (indicated as “V1” and “V2” in FIG. 1) 15 and 16, and a reference voltage changeover switch (in FIG. 1, “SW1”). (Notation) 40, first comparator (indicated as “CP1” in FIG. 1) 4, first and second transistors (indicated as “M1” and “M2” in FIG. 1, respectively) 1,2 The first and second constant current sources (represented as “I1” and “I2” in FIG. 1, respectively) 11 and 12 are configured as main components.

The triangular wave generating circuit 100 basically has a circuit configuration similar to that of the conventional circuit.
The circuit configuration will be specifically described below. First, either the first reference voltage source 15 or the second reference voltage source 16 is connected to the first comparator 4 as a reference voltage switch. 40 is connected alternatively.
That is, the reference voltage changeover switch 40 is a so-called electronic switch that includes a changeover terminal 40c, a first terminal 40a, and a second terminal 40b, and uses, for example, a semiconductor element. In the reference voltage changeover switch 40, when the output of the first comparator 4 is at a level corresponding to the logic value Low, the changeover terminal 40c is connected to the first terminal 40a, while the first comparator 4 When the output is at a level corresponding to the logical value High, the switching terminal 40c is connected to the second terminal 40b.

One end of the switching terminal 40c is connected to the inverting input terminal of the first comparator 4, and the other end is alternatively connected to the first terminal 40a or the second terminal 40b as described above. It is like that.
On the other hand, the first terminal 40a is connected to the positive side of the first constant voltage source 15, and the negative side of the first constant voltage source 15 is connected to the ground.
The second terminal 40b is connected to the positive electrode side of the second constant voltage source 16, and the negative electrode side of the second constant voltage source 16 is connected to the ground.

  The first constant voltage source 15 is for setting the upper limit voltage of the triangular wave output from the triangular wave generation circuit 100, and the second constant voltage source 16 is for setting the lower limit voltage of the triangular wave output from the triangular wave generation circuit 100. is there. Then, assuming that the output voltage of the first constant voltage source 15 is the upper limit reference voltage V1 for convenience and the output voltage of the second constant voltage source 16 is the lower limit reference voltage V2 for convenience, V1> V2. .

In the embodiment of the present invention, the first transistor (triangular wave circuit semiconductor element) 1 is a P-channel MOS FET, and the second transistor (triangular wave circuit semiconductor element) 2 is an N-channel MOS FET. Each is used.
The gates of the first and second transistors 1 and 2 are connected to each other and to the output terminal of the first comparator 4.

  Further, the first and second transistors 1 and 2 have the drain of the first transistor 1 and the drain of the second transistor 2 connected to each other, and the non-inverting input terminal of the first comparator 4 and the triangular wave output. A terminal (denoted as “P1” in FIG. 1) 51 and an offset circuit 300 described later are connected.

On the other hand, a first constant current source 11 is connected to the source of the first transistor 1, and a power supply voltage is applied to the first constant current source 11.
A second constant current source 12 is connected in series between the source of the second transistor 2 and the ground.
Further, outside the triangular wave generation circuit 100, a triangular wave timing capacitor (indicated as “C1” in FIG. 1) 21 is provided in series between the triangular wave output terminal 51 and the ground. .

Next, the PWM generation comparison circuit 200 is configured using the second comparator 5.
That is, an output voltage of an offset circuit 300 described later is applied to the inverting input terminal of the second comparator 5, while an analog voltage input terminal (indicated as “P2” in FIG. 1) is applied to the non-inverting input terminal. A desired analog voltage can be applied via 52.
The second comparator 5 can output a PWM pulse signal as will be described later via a PWM pulse output terminal (indicated as “P3” in FIG. 1) 53.

  Next, the offset circuit 300 includes a third transistor (denoted as “M3” in FIG. 1) 3, an inverting circuit (“INV1” in FIG. 1) 7, and a third constant current source (in FIG. 1). Includes an offset resistor (indicated as “R1” in FIG. 1) 25, and an offset is applied to the triangular wave output from the triangular wave generating circuit 100, as will be described later. It is configured as follows.

Hereinafter, a specific circuit configuration will be described. First, a P-channel MOS FET is used for the third transistor (offset semiconductor element) 3, and the output terminal of the inverting circuit 7 is connected to the gate thereof. The input stage of the inverting circuit 7 is connected to the output terminal of the first comparator 4 of the triangular wave generating circuit 100.
The source of the third transistor 3 is connected to a third constant current source (offset constant current source) 13, and a power supply voltage is applied to the third constant current source 13. Yes.

On the other hand, the drain of the third transistor 3 is connected to the inverting input terminal of the second comparator 5 of the PWM generation comparison circuit 200 via an offset triangular wave output terminal (indicated as “P4” in FIG. 1) 54. At the same time, it is connected to the triangular wave output terminal 51 via the offset resistor 25.
The offset voltage generated in the offset circuit 300 is set by the third constant current source 13 and the offset resistor 25 as described later.

Next, the operation and the like in the above configuration will be described with reference to the waveform diagram shown in FIG.
First, since the operation of the triangular wave generation circuit 100 is basically the same as that of the conventional circuit, the operation will be described generally, and the operation of the offset circuit 300 will be mainly described below.
In the triangular wave generating circuit 100, when the reference voltage changeover switch 40 is switched to the first terminal 40a side, the first transistor 1 is turned on, while the second transistor 2 is turned off, and the triangular wave timing is changed. The capacitor 21 is charged by the first constant current source 11.

  When the charging of the triangular wave timing capacitor 21 is started, the terminal voltage of the triangular wave output terminal 51 rises linearly with time, and eventually the first voltage when the terminal voltage of the triangular wave output terminal 51 becomes equal to the upper limit reference voltage V1. The output state of the comparator 4 is switched.

  When the output state of the first comparator 4 is switched, the first transistor 1 is turned off, while the second transistor 2 is turned on. At the same time, the reference voltage changeover switch 40 is moved to the second terminal 40b side. It will be switched. As a result, the triangular wave timing capacitor 21 transitions from the charged state by the first constant current source 11 to the discharged state by the second constant current source 12, and the voltage at the triangular wave output terminal 51 decreases linearly with time. .

When the terminal voltage of the triangular wave output terminal 51 becomes equal to the lower limit reference voltage V2, the output state of the first comparator 4 is switched again, and the first transistor 1 is turned on, while the second transistor 2 is turned off. It will be in a state, and it will return to the first state demonstrated previously.
Thus, as a result of such a state being repeated, a triangular wave is obtained at the triangular wave output terminal 51.

  Next, the generation of the offset voltage in the offset circuit 300 is controlled by the output signal of the first comparator 4 of the triangular wave generation circuit 100. That is, when the output of the first comparator 4 becomes a level corresponding to the logical value High, in other words, when the triangular wave timing capacitor (triangular wave capacitor) 21 is in the discharging state, the third transistor 3 is in the on state. Thus, an offset voltage is generated when the current of the third constant current source 13 flows through the offset resistor 25.

The offset voltage obtained by the voltage drop of the offset resistor 25 is added to or subtracted from the voltage at the triangular wave output terminal 51, and the triangular wave with offset is output from the triangular wave output terminal with offset 54.
In the PWM generation comparison circuit 200, the triangular wave with offset output from the offset circuit 300 as described above is compared with the analog input voltage arbitrarily set at the analog voltage input terminal 52, and the comparison result is obtained. Accordingly, the PWM pulse signal is output from the PWM pulse output terminal 53.

Next, the difference in waveform between the triangular wave output from the triangular wave generation circuit 100 and the triangular wave with offset output from the offset circuit 300 will be described more specifically with reference to FIG.
An offset voltage (I3 × R1) is added to the triangular wave output from the triangular wave generating circuit 100 when the triangular wave timing capacitor 21 switches from the charged state to the discharged state, while the triangular wave timing capacitor 21 is charged from the discharged state. The offset voltage (I3 × R1) is subtracted when switching to the state.

As a result, as shown in FIG. 2B, steep voltage fluctuations with respect to the time axis can be obtained in the vicinity of the upper limit reference voltage V1 and the lower limit reference voltage V2 of the triangular wave with offset.
Here, for convenience, I3 is an output current of the third constant current source 13, and R1 is a resistance value of the offset resistor 25.

  By this operation, the triangular wave with offset (see FIG. 2B) is compared with the original triangular wave (see FIG. 2A) at the upper reference voltage V1 and the lower reference voltage V2, respectively, with respect to the time axis. In the comparison operation with the analog input voltage applied to the analog voltage input terminal 52 in the PWM generation comparison circuit 200, the voltage fluctuation amount (in other words, the slope of the characteristic line representing the voltage fluctuation with respect to the time axis) increases. It becomes difficult to be influenced by noise from a circuit or the like, and a reliable comparison operation in the second comparator 5 is obtained. In particular, when the analog input voltage is greater than or equal to the upper limit value V1 of the triangular wave or less than or equal to the lower limit value (V2 + I3 × R1), the reliability and stability of the comparison operation in the second comparator 5 with respect to noise is higher than before. And become more prominent.

Next, a second embodiment will be described with reference to FIGS.
The same components as those in the circuit of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, detailed description thereof will be omitted, and different points will be mainly described below. I decided to.
The pulse generation circuit in the second embodiment is also roughly divided into a triangular wave generation circuit 100, a PWM generation comparison circuit 200, and an offset circuit 300. The point in the first embodiment is that Although it is basically the same as the pulse generation circuit, the setting of the comparison voltage at the non-inverting input terminal of the first comparator 4 of the triangular wave generation circuit 100 is different from that of the first embodiment, as will be described in detail below. .

  That is, the non-inverting input terminal of the first comparator 4 of the triangular wave generation circuit 100 is connected to the drain of the third transistor 3 of the offset circuit 300, in other words, the triangular wave output terminal 54 with offset, and the triangular wave with offset. Is applied to the non-inverting input terminal of the first comparator 4 so that a comparison operation is performed.

Next, the operation in this configuration will be described with reference to FIG.
In the first comparator 4 of the triangular wave generation circuit 100, the output signal is switched when the amplitude voltage of the triangular wave with offset becomes the upper limit reference voltage V1 or the lower limit reference voltage V2 of the triangular wave. Specifically, the amplitude of the triangular wave output terminal 51 is V1 as the upper limit value and (V2-I3 × R1) as the lower limit value (see FIGS. 4A and 4B).

  Thus, in the second embodiment, in the vicinity of the upper limit voltage (V1 + I3 × R1) and the lower limit voltage (V2−I3 × R1) of the triangular wave with offset input to the non-inverting input terminal of the first comparator 4, The amount of voltage fluctuation with respect to the time axis increases. As a result, the operation is equivalent to the case where hysteresis is provided when the output of the first comparator 4 is switched. Therefore, in the comparison operation with the upper limit reference voltage V1 and the lower limit reference voltage V2, noise from peripheral circuits and the like is reduced. It becomes difficult to be affected, and a reliable comparison operation in the first comparator 4 is obtained.

Therefore, unlike the conventional case, the stability of the triangular wave with respect to amplitude and frequency noise is improved.
Further, as described above, since the voltage fluctuation amount with respect to the time axis near the upper limit voltage (V1 + I3 × R1) and the lower limit voltage (V2−I3 × R1) of the triangular wave with offset increases, as in the first embodiment, The certainty and stability with respect to noise of the comparison operation in the comparator 5 of FIG.

Next, a third embodiment will be described with reference to FIGS.
The same components as those in the circuit of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, detailed description thereof will be omitted, and different points will be mainly described below. I decided to.
The pulse generation circuit in the third embodiment is roughly divided into a triangular wave generation circuit 100A, a PWM generation comparison circuit 200, and an offset circuit 300A. In particular, the triangular wave generation circuit 100A and the offset circuit 300A are offset. Each circuit configuration of the circuit 300A is different from that of the first embodiment (details will be described later).

The following description will focus on differences from the circuit configuration of the first embodiment.
First, the triangular wave generating circuit 100A is different from the triangular wave generating circuit 100 shown in FIG. 1 in that the two reference voltages V1 and V2 are obtained by voltage drop across the resistor. Other circuit configurations are basically the same as those of the triangular wave generation circuit 100.

That is, in the triangular wave generating circuit 100A, instead of the first and second constant voltage sources 15 and 16 (see FIG. 1), first to fourth reference voltage generating voltage dividing resistors (in FIG. 5, (Referred to as “RD1”, “RD2”, “RD3”, and “RD4”, respectively) 31 to 34 are used to obtain an upper limit reference voltage V1 and a lower limit reference voltage V2.
Specifically, first to fourth reference voltage generating voltage dividing resistors 31 to 34 are connected in series from the power source side between a power source (not shown) and the ground.

The first terminal 40 a of the reference voltage changeover switch 40 is connected to a connection point between the first reference voltage generating voltage dividing resistor 31 and the second reference voltage generating voltage dividing resistor 32.
The second terminal 40 b of the reference voltage changeover switch 40 is connected to the connection point between the third reference voltage generating voltage dividing resistor 33 and the fourth reference voltage generating voltage dividing resistor 34.

One end of the switching terminal 40 c is connected to the inverting input terminal of the first comparator 4, while the other end is connected to the first terminal 40 a or the second terminal 40 b according to the output of the first comparator 4. The point of being connected alternatively is the same as the first embodiment shown in FIG.
The connection point between the second reference voltage generating voltage dividing resistor 32 and the third reference voltage generating voltage dividing resistor 33 is connected to an offset circuit 300A described later.

Further, the triangular wave generating circuit 100A is different from the triangular wave generating circuit 100 shown in FIG. 1 in that the non-inverting input terminal of the first comparator 4 is connected to an offset circuit 300A described later. ing.
As described above, the portion subsequent to the output terminal of the first comparator 4 is the same as the circuit configuration shown in FIG. 1, and therefore detailed description thereof will be omitted here.

Next, the offset circuit 300A will be described.
The offset circuit 300A includes a third comparator (indicated as “CP3” in FIG. 5) 6, an exclusive OR circuit (indicated as “EX1” in FIG. 5) 8, a first and a second offset. Generating resistors (represented as “RO1” and “RO2” in FIG. 5) 26 and 27, an offset capacitor (denoted as “C2” in FIG. 5) 22, and a capacity charge / discharge switch (FIG. 5). In FIG. 4, the reference numeral 41 is expressed as “SW2”).

Hereinafter, the circuit configuration of the offset circuit 300A will be specifically described.
First, the second reference voltage generating voltage dividing resistor 32 and the third reference voltage generating voltage dividing resistor of the triangular wave generating circuit 100A are connected to the inverting input terminal of the third comparator (offset comparator) 6. 33 mutual connection points are connected, and a voltage (V1 + V2) / 2 which is a half of the sum of the upper limit reference voltage V1 and the lower limit reference voltage V2 is applied.

The non-inverting input terminal of the third comparator 6 is connected to the triangular wave timing capacitor 21 via the triangular wave output terminal 51.
On the other hand, the output terminal of the third comparator 6 is connected to one input terminal of the exclusive OR circuit 8, and the other input terminal of the exclusive OR circuit 8 is the first comparator of the triangular wave generating circuit 100A. 4 is connected to the output terminal.

The output terminal of the exclusive OR circuit 8 is used as a control signal for controlling the opening / closing of the capacity charge / discharge switch (offset switch element) 41.
That is, the capacity charge / discharge changeover switch 41 is a well-known so-called electronic switch constituted by a semiconductor element or the like, like the reference voltage changeover switch 40. The capacity charge / discharge changeover switch 41 has a changeover terminal 41c, a first terminal 41a, and a second terminal 41b, and the changeover terminal 41c is either the first terminal 41a or the second terminal 41b by external control. It is designed to be connected alternatively to one.

In this embodiment, when the output of the exclusive OR circuit 8 is at a level corresponding to the logical value Low, the switching terminal 41c is connected to the second terminal 41b, while the output of the exclusive OR circuit 8 is connected. Is at a level corresponding to the logical value High, the switching terminal 41c is connected to the first terminal 41a.
An offset capacitor 22 is connected between the switching terminal 41c of the capacitance charge / discharge switching switch 41 and the ground, while the first terminal 41a is connected to the first and second transistors 1 and 2 of the triangular wave generating circuit 100A. Are connected to the first triangular wave output terminal 55 with an offset.

In addition, the second terminal 41b of the capacitor charge / discharge changeover switch 41 is connected to the triangular wave output terminal 51 through the second offset generating resistor 27 together with the non-inverting input terminal of the eleventh comparator 4, It is connected to the second triangular wave output terminal 56 with an offset. The second triangular wave output terminal with offset 56 is connected to the inverting input terminal of the second comparator 5 constituting the PWM generating comparison circuit 200.
A first offset generating resistor 26 is connected in series between the first triangular wave output terminal with offset 55 and the triangular wave output terminal 51.

Next, the operation in this configuration will be described with reference to FIG.
First, in the triangular wave generating circuit 100A, the reference for determining the amplitude (V1, V2) of the triangular wave and the operation timing of the offset circuit 300A by the first to fourth voltage dividing resistors 31 to 34 for generating the reference voltage. Except that the voltage (V1 + V2) / 2 is generated, the basic circuit operation is the same as that of the triangular wave generation circuit 100 in the first embodiment shown in FIG.

  Next, in the offset circuit 300A, the charging / discharging operation of the offset capacitor 22 is switched by the capacitance charge / discharge switching switch 41, and the switching terminal 41c is connected to the first terminal 41a. In the meantime, the offset capacitor 22 is in a charged state, whereas when the switching terminal 41c is connected to the second terminal 41b, the offset capacitor 22 is in a discharged state. The charging voltage of the offset capacitor 22 causes a voltage change corresponding to charging / discharging of the triangular wave timing capacitor 21 as will be described later.

That is, when the triangular wave timing capacitor 21 is in a charged state, a voltage obtained by adding the offset voltage (I1 × RO1) generated by the first offset generating resistor 26 to the voltage at the triangular wave output terminal 51 is the offset capacitor. The charging voltage is 22 (see FIGS. 6B and 6D). On the other hand, when the triangular wave timing capacitor 21 is in a discharged state, a voltage obtained by subtracting the offset voltage (I2 × RO1) generated by the first offset generating resistor 26 from the voltage at the triangular wave output terminal 51 is the offset capacitor. The charging voltage is 22 (see FIGS. 6B and 6D).
Here, I1 is an output current of the first constant current source 11 for convenience, I2 is an output current of the second constant current source 12 for convenience, and RO1 is a first offset generating resistor for convenience. The resistance values of the devices 26 will be represented respectively.

  On the other hand, when the switching terminal 41 c is connected to the second terminal 41 b and the offset capacitor 22 is discharged, the offset capacitor 22 has a capacitance value and the second offset generating resistor 27 Discharging is performed while converging toward the voltage of the triangular wave output terminal 51 (see FIG. 6A) with a time constant determined by the resistance value. In other words, the offset capacitor 22 is charged to the voltage of the triangular wave output terminal 51 by the above-described discharge, and during this time, the discharge voltage having the time constant C2 × RO2 is added to the voltage of the triangular wave output terminal 51. And output to the second triangular wave output terminal 54 with offset (see FIG. 6E).

Switching between charging and discharging of the offset capacitor 22 in the offset generation circuit 300A is performed at a timing synchronized with the triangular wave by the third comparator 6 and the exclusive OR circuit 8. That is, the third comparator 6 compares the voltage of the triangular wave output terminal 51 with the midpoint voltage (V1 + V2) / 2 of the triangular wave, and the output is switched according to the comparison result.
Further, the outputs of the third comparator 6 and the first comparator 4 are input to the exclusive OR circuit 8, so that the triangular wave timing capacitor 21 is switched between charging and discharging from an intermediate point in one cycle of the triangular wave. Until the timing of switching, the output of the exclusive OR circuit 8 is at a level corresponding to the logical value High, and the switching terminal 41c of the capacity charge / discharge switching switch 41 is connected to the first terminal 41a. The battery is charged.

On the other hand, during the period from the start of charging or discharging of the triangular wave timing capacitor 21 to the intermediate point in one cycle of the triangular wave, the output of the exclusive OR circuit 8 is at a level corresponding to the logical value Low, and the capacity charge / discharge switching switch 41 The switching terminal 41c is connected to the second terminal 41b, and the offset capacitor 22 is discharged.
Here, if the capacitance value C1 of the triangular wave timing capacitor 21 is very large (C1 >> C2) compared to the capacitance value C2 of the offset capacitor 22, both the triangular wave timing capacitor 21 and the offset capacitor 22 are respectively The charging / discharging operation of each other is not affected.

  That is, when the relationship of C1 >> C2 is established, the charging operation of the offset capacitor 22 when the switching terminal 41c of the capacity charge / discharge switching switch 41 is switched to the first terminal 41a is immediately completed, and the triangular wave The charging / discharging operation of the timing capacitor 21 is not affected. In this case, a part of the current of the first and second constant current sources 11 and 12 becomes the charging current of the offset capacitor 22. Further, the discharging operation of the offset capacitor 22 when the switching terminal 41c of the capacity charge / discharge switching switch 41 is switched to the second terminal 41b converges to the voltage of the triangular wave output terminal 51 with a discharge time constant of C2 × RO2. Even in this case, the charging operation of the triangular wave timing capacitor 21 is not affected. In this case, a part of the discharge current of the offset capacitor 22 becomes the charging current of the triangular wave timing capacitor 21.

  Through the operation as described above, the triangular wave with offset at the second triangular wave output terminal with offset 54 (see FIG. 6E) is higher than the original triangular wave at the triangular wave output terminal 51 (V1 + I1 × RO1). The voltage fluctuation amount with respect to the time axis (in other words, the slope of the characteristic line representing the voltage fluctuation with respect to the time axis) increases in the vicinity and in the vicinity of the lower limit voltage (V2-I2 × RO1) (see FIG. 6E). In the comparison operation with the analog input voltage in the PWM generation comparison circuit 200, it becomes difficult to be influenced by noise from the peripheral circuit and the like, and a reliable comparison operation in the second comparator 5 is obtained.

In the case of the third embodiment, the voltage change with respect to the time axis becomes a larger triangular wave with an offset than in the first and second embodiments, so the first and second embodiments. As a result, the circuit is more resistant to noise.
In the case of the third embodiment, the discharge curve of the offset capacitor 22 that determines the time constant of the voltage change amount is appropriately selected as the capacitance value of the offset capacitor 22 and the resistance value of the second offset generating resistor 27. This makes it easy to adjust to any curve. That is, in other words, by appropriately selecting the capacitance value of the offset capacitor 22 and the resistance value of the second offset generating resistor 27, the offset voltage is changed from the charged state to the discharged state by the triangular wave timing capacitor 21 or the discharge state. It can be set from the time when the state is switched to the state of charge to the desired time. As a result, in the third embodiment, the circuit operation can be optimally set according to the noise environment of the peripheral circuit.

  The present invention can be applied to a pulse generation circuit for generating a PWM pulse signal in which higher noise tolerance is desired.

DESCRIPTION OF SYMBOLS 100 ... Triangular wave generation circuit 200 ... PWM generation comparison circuit 300 ... Offset circuit 4 ... First comparator 5 ... Second comparator 6 ... Third comparator 21 ... Triangular wave timing capacitor 22 ... Offset capacitor 40 ... Reference voltage changeover switch 41 ... Capacity charge / discharge switch

Claims (4)

Two constant current sources that charge and discharge the triangular wave capacitor, a triangular wave circuit semiconductor element that switches connection of the two constant current sources to the triangular wave capacitor, a terminal voltage and a reference voltage of the triangular wave capacitor, A triangular wave generation circuit configured to generate a triangular wave in the triangular wave capacitor, and charging of the triangular wave capacitor. An offset circuit configured to add an offset voltage to the triangular wave in the vicinity of discharge switching;
A pulse generation circuit comprising: a PWM generation comparison circuit that compares the output of the offset circuit with a desired voltage and generates a PWM signal according to the comparison result.   2. The pulse generation according to claim 1, wherein the first comparator is configured to compare the output voltage of the offset circuit and the reference voltage instead of the terminal voltage of the triangular wave capacitor. circuit.   The offset circuit includes an offset constant current source, an offset semiconductor element, and an offset resistor, and the offset constant current is passed through the offset semiconductor element in accordance with an output of the first comparator. The offset voltage generated by energizing the offset resistor by the constant current source for offset is controlled to be added to and subtracted from the terminal voltage of the triangular wave capacitor. The pulse generation circuit according to claim 1, wherein:   The offset circuit includes an offset comparator that compares a terminal voltage of the triangular wave capacitor with a midpoint voltage of the triangular wave, an offset capacitor, and an offset switch element. The offset comparator and the first The charge / discharge of the offset capacitor is switched via the offset switch element in accordance with the output of the comparator, and an offset voltage whose amplitude changes with time can be added to or subtracted from the terminal voltage of the triangular wave capacitor. The pulse generation circuit according to claim 2.

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