JP2011091937A - Power supply circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a constant voltage output by a PWM signal with a high duty ratio. <P>SOLUTION: An output signal is negatively fed back to an error amplifier 12, and the amplifier compares it with a reference signal and outputs an error signal. A PWM comparator 20 compares an error signal from the error amplifier 12 with a triangular wave, and outputs a PWM signal with a duty ratio in accordance with the comparison results. The circuit drives an output transistor 22 according to the PWM signal and regulates the voltage of the output signal so that it may be the one to which the reference voltage corresponds. Moreover, a short pulse generating circuit (NAND gate) 16 generates a short pulse signal being a pulse signal for a predetermined short period of time, separately from the PWM signal. A duty ratio adjusting circuit (AND gate) 18 combines the short pulse signal with the PWM signal and prevents the duty ratio of the PWM signal from becoming 100%. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a power supply circuit for obtaining a constant voltage output.

  Conventionally, a power supply circuit IC for supplying a constant voltage to a semiconductor integrated circuit (IC) has been widely used. In this power supply circuit IC, a constant voltage output is obtained from the output of the battery that changes with normal use. For example, a constant voltage output of about 5V is obtained from a battery voltage of about 12V.

  In this power supply circuit IC, the output voltage is fed back to the error amplifier, compared with the reference voltage, an error signal is obtained, and PWM control according to the error signal is performed to control the output voltage to correspond to the reference voltage. ing.

  Here, the output stage by the PWM control is performed by turning on and off the output transistor with a PWM signal having a duty ratio corresponding to the level of the error signal, and supplying the output of the output transistor to the capacitor via the coil.

  Here, when the battery voltage decreases, the duty ratio increases. On the other hand, when the duty ratio is 100%, current continuously flows through the coil, the coil L is saturated, the inductance is lowered, and a large current is output. Then, the upper limit of the duty ratio is set to about 90% in consideration of error amplifiers and variations in circuit characteristics such as a reference voltage.

JP 2001-238440 A

  However, setting the upper limit duty ratio to 90% in this way makes it impossible to maintain the output voltage relatively early when the battery voltage approaches the output voltage of the power supply IC. Therefore, there is a demand for further increasing the upper limit duty ratio on condition that the upper limit duty ratio is not 100% (the coil is not saturated).

  In the power supply circuit according to the present invention, an output signal is negatively fed back, an error amplifier that outputs an error signal compared with a reference voltage, an error signal from the error amplifier is compared with a triangular wave, and a duty according to the comparison result A PWM comparator that outputs a PWM signal of a ratio, and a voltage adjustment that drives an output transistor according to the PWM signal from the PWM comparison and adjusts the voltage of the output signal to correspond to the reference voltage A short pulse generation circuit that generates a short pulse signal that is a predetermined short-time pulse signal separately from the PWM signal, and a short pulse signal from the short-time pulse generation circuit is combined with the PWM signal, and the PWM signal A duty ratio adjusting circuit for preventing the duty ratio from becoming 100%.

  Further, it is preferable that the short pulse generating circuit generates a short pulse signal in synchronization with the apex of the triangular wave.

  The short pulse generation circuit preferably includes a logical operation circuit and generates a short pulse signal by logical operation of two signals.

  According to the present invention, it is possible to obtain a PWM signal with a duty ratio approaching 100% while maintaining an L level period.

It is a figure which shows the example of whole structure. It is a figure which shows the waveform of a signal. It is a figure which shows the circuit example for a triangular wave generation | occurrence | production. It is a figure which shows the waveform of a signal.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a circuit diagram illustrating an overall configuration of a power supply circuit according to the embodiment. The voltage dividing circuit 10 is composed of resistors R1 and R2 connected in series, and outputs a voltage obtained by dividing the output voltage Vout of the power supply circuit by the resistors R1 and R2 from an intermediate point between the resistors R1 and R2. The power supply circuit as a whole is a circuit that negatively feeds back the output voltage Vout to an error amplifier to which a reference voltage is input, and matches the voltage obtained by dividing the output voltage Vout with the reference voltage. By configuring the voltage dividing circuit 10 with a resistor ladder and changing the output voltage from the voltage dividing circuit 10, the output voltage Vout can be changed without changing the reference voltage.

  The output voltage of the voltage dividing circuit 10 is input to the negative input terminal of the error amplifier 12. The reference voltage Vref is input to the positive input terminal of the error amplifier 12, and the error amplifier 12 compares the input voltages to both input terminals and outputs a signal (error signal) regarding the comparison result.

  Here, the reference voltage Vref is an output of the reference power supply 14, and the reference power supply 14 is connected to the positive input terminal of the error amplifier 12. Therefore, the error amplifier 12 outputs an error signal regarding the difference voltage between the output voltage of the voltage dividing circuit 10 and the reference voltage Vref. This error signal becomes a larger positive signal as the output voltage Vout is lower, and a larger negative signal as the output voltage Vout is higher.

  This error signal is input to the positive input terminal of the comparator (PWM comparator) 20, where it is compared with the triangular wave input to the negative input terminal. For example, the output of the comparator 20 has a duty ratio of 50% when the error signal is 0, and the duty ratio decreases as the error signal becomes a large positive signal, and the duty ratio increases as the negative signal increases.

  The output of the comparator 20 is supplied to the gate of a transistor (output transistor) 22 via an AND gate (duty ratio adjustment circuit) 18. In the transistor 22, the power source Vin is supplied to the drain, and the source is connected to the output terminal Vout of the output voltage Vout through the coil 24. In addition, a cathode of a diode 28 whose anode is connected to the ground is connected to an intermediate portion between the transistor 22 and the coil 24, and one end of a capacitor 26 whose other end is connected to the ground is connected to the output terminal Vout. . Therefore, the output voltage Vout obtained by stepping down the power supply Vin according to the switching duty ratio of the transistor 22 is obtained at the output terminal Vout. The output terminal Vout is connected to the voltage dividing circuit 10.

  Therefore, the output of the error amplifier 12 is determined so that Vout × R1 / (R1 + R2) = Vref is satisfied, and the transistor 22 is PWM-controlled with the duty ratio corresponding to this, so that the output voltage Vout is controlled. For example, a stepped down output voltage of about Vin = 5V and Vout = 3V can be obtained. In the case of boosting, a transistor may be provided in parallel with the diode 28 to switch the transistor.

  In the present embodiment, the output of the NAND gate 16 is supplied to the other input terminal of the AND gate 18 described above. The NAND gate 16 is a circuit that takes a pulse signal synchronized with a triangular wave input to the comparator 20 and a signal obtained by delaying the pulse signal by a delay circuit 30 for a predetermined short time. A signal having a level pulse.

  Since the comparator 20 outputs an L level when the triangular wave exceeds the error signal, the PWM signal that is the output of the comparator 20 has an L level near the apex of the triangular wave when the error signal is located below the triangular wave. It has become. Therefore, even if an L level short pulse is input to the AND gate 18, the output is not affected.

  On the other hand, when the duty ratio of the PWM signal that is the output of the comparator 20 is 100%, the L level of the output from the NAND gate 16 becomes the L level of the PWM signal. For example, if the L level of the output from the NAND gate 16 corresponds to a PWM signal duty of 1%, the duty ratio of the PWM signal is 99%. Since the signal with such a duty ratio can be reliably obtained in the NAND gate 16, a signal with a duty ratio of 99% can be reliably obtained as the PWM signal.

  Here, FIG. 2 shows a comparison state of a triangular wave and an error signal, an example of a PWM signal, and an example of a short pulse signal. In the case of the error signal indicated by the alternate long and short dash line, since the level is lower than the apex of the triangular wave, a PWM signal that becomes the L level during the period in which the error signal is lower than the triangular wave is obtained. The short pulse signal is a signal that becomes L level near the apex of the triangular wave, and only becomes L level within the L level period in the output of the comparator 20, and there is no change in the PWM signal obtained at the output of the AND gate 18. .

  On the other hand, in the case of the error signal indicated by the broken line, since the level is higher than the apex of the triangular wave, all PWM signals obtained by comparison are H level signals. At this time, since the short pulse signal is supplied to the AND gate 18, the PWM signal that is the output of the AND gate 18 has the same L level period as the short pulse signal.

  Here, the triangular wave can be formed by a circuit as shown in FIG. The power source Vin is connected to the ground via a constant current source 50, a switch 52, and a capacitor 54. An intermediate point between the switch 52 and the capacitor 54 is connected to the ground via the switch 56 and the constant current source 58. Then, a triangular wave is output from an intermediate point (output terminal) between the switch 52 and the capacitor 54.

  That is, when the switch 52 is turned on and the switch 56 is turned off, the capacitor 54 is charged by the constant current from the constant current source 50, and the voltage at the output end increases. On the other hand, when the switch 52 is turned off and the switch 56 is turned on, the capacitor 54 is discharged by the constant current of the constant current source 58, and the voltage at the output terminal decreases. Therefore, the switches 52 and 56 are complementarily turned on by a pulse signal having the same frequency as the PWM signal, whereby a triangular wave is formed by repeatedly charging and discharging the capacitor 54. By changing the constant current amounts of the constant current sources 50 and 58, the upward and downward gradients of the triangular wave can be changed, and a sawtooth triangular wave and the like can be easily formed.

  Therefore, the timing of the apex of the triangular wave is determined by the pulse signal that controls the switches 52 and 56. Therefore, by using this pulse signal as the input of the NAND gate 16 described above, a short pulse signal that becomes L level in synchronization with the apex of the triangular wave can be obtained at the output of the NAND gate 16. It is also preferable that the center of the L level period of the short pulse signal coincides with the apex of the triangular wave by inputting a delay circuit to the input path to the triangular wave comparator 20. Further, a signal having a duty ratio of 50% corresponding to the center level of the generated triangular wave is generated, and a short pulse signal can be formed based on a signal delayed by about 90 degrees.

  For example, as shown in FIG. 4, a switching signal for controlling switching of the switches 52 and 56 and an inverted signal obtained by delaying and inverting the switching signal by a delay circuit 30 are input to the NAND gate 16 to thereby input a short pulse having a predetermined width. A signal can be obtained.

  In this manner, by providing a short pulse signal having an L level period in synchronization with the apex of the triangular wave, even by constantly multiplying the PWM signal by the short pulse signal, without adding an extra L level period, The L level period can be given only when necessary.

  Accordingly, if the period during which the coil 24 can be prevented from being saturated is 1% of the duty ratio of the PWM signal, the L level period of the short pulse signal is set to 1% to stabilize the output voltage with the duty ratio of 99%. Obtainable.

  That is, even when the output voltage of the comparator 20 exceeds the voltage at the apex of the triangular wave, an L level period is secured in the short pulse signal, and saturation of the coil 24 can be prevented.

  Note that the short pulse signal may not be generated by the NAND gate 16, but may be configured by other logic operation circuits by appropriately inverting the polarity. Further, by controlling the delay amount of the delay circuit 30, the pulse width of the short pulse signal can be controlled. Furthermore, it is also preferable to control the delay amount to an appropriate amount according to the frequency of the triangular wave.

  10 voltage divider circuit, 12 error amplifier, 14 reference power supply, 16 NAND gate, 18 AND gate, 20 comparator, 22 transistor, 24 coil, 26, 54 capacitor, 28 diode, 30 delay circuit, 50, 58 constant current source, 52, 56 switches.

Claims (3)

An error amplifier that outputs an error signal in comparison with a reference voltage, and the output signal is negatively fed back;
A PWM comparator that compares the error signal from the error amplifier with a triangular wave and outputs a PWM signal having a duty ratio according to the comparison result;
A voltage adjustment circuit that drives the output transistor in accordance with the PWM signal from the PWM comparison and adjusts the voltage of the output signal to correspond to the reference voltage;
A short pulse generating circuit for generating a short pulse signal which is a predetermined short time pulse signal separately from the PWM signal;
A duty ratio adjustment circuit that combines a short pulse signal from a short time pulse generation circuit with the PWM signal to prevent the duty ratio of the PWM signal from reaching 100%;
A power circuit. The power supply circuit according to claim 1,
The short pulse generation circuit is a power supply circuit that generates a short pulse signal in synchronization with the apex of the triangular wave. The power supply circuit according to claim 1 or 2,
The short pulse generation circuit includes a logical operation circuit and generates a short pulse signal by logical operation of two signals.

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