JP5473817B2 - Programmable controller and bus converter - Google Patents

Description

  The present invention relates to a programmable controller and a bus converter that control a controlled device such as an industrial device.

  2. Description of the Related Art Conventionally, there are programmable controllers (hereinafter simply referred to as PLCs) that are configured by mounting one or more functional units on a base unit. In addition to the CPU unit that controls the entire PLC, the functional unit includes an analog input unit, an analog output unit, a temperature control unit, a motion controller unit, and the like that are selected according to the control purpose of the PLC. Functional units other than these CPU units are collectively referred to as auxiliary units. The CPU unit communicates with the auxiliary unit via a bus provided in the base unit, and executes control of the auxiliary unit.

  In addition, the base unit can be added (see, for example, Patent Document 1, Patent Document 2, Patent Document 3, and Patent Document 4), and there is a shortage of slots for mounting the auxiliary unit by adding the base unit. In addition, by controlling the distance between the base units, it is possible to cope with the control of the controlled device installed at a distant position. Hereinafter, in a PLC having a plurality of base units, a base unit to which a CPU unit is attached is added to a basic base and a basic base, and a base unit that operates as a slave with respect to the basic base is referred to as an extended base.

JP 2000-47766 A JP-A-6-124103 Japanese Patent Laid-Open No. 7-311605 JP-A-4-373002

  Now, the higher the processing speed of the CPU unit and the faster the bus, the faster the control can be performed. Therefore, PLC manufacturers develop base units with faster buses in order to provide better performance products. On the other hand, every time a base unit having a higher speed bus is released, it is burdensome for the user to replace the auxiliary unit constituting the PLC with one corresponding to the high speed bus. Therefore, in order to be able to use an existing auxiliary unit that does not support the high-speed bus, a basic base equipped with a high-speed bus, an extension base having a lower bus speed than the basic base for the existing auxiliary unit, It is convenient to be able to connect and use.

  However, when the high-speed bus and the low-speed bus are simply connected, there is a problem that the performance of the entire PLC is reduced to the performance of the low-speed bus. For example, according to the technique disclosed in Patent Document 4, the CPU unit on the basic base accesses the low speed bus by dropping the bus clock.

  The present invention has been made in view of the above, and an object of the present invention is to obtain a PLC and a bus converter that can perform efficient communication between functional units via buses having different speeds.

In order to solve the above-described problems and achieve the object, the present invention includes a CPU unit, an auxiliary unit controlled by the CPU unit, and a first bus, and the auxiliary unit is included in the first bus. A first base unit to be mounted; and a second bus that is faster than the first bus. The second bus includes an internal bus and an external bus, and the CPU unit is mounted on the internal bus. A second base unit, and a bus converter connected to the first bus and the external bus and transferring control data transmitted and received between the CPU unit and the auxiliary unit, When the bus converter receives a request for the auxiliary unit transmitted by the CPU unit, the bus converter generates an ID for each request and returns the generated ID to the CPU unit. When receiving the ID, the CPU unit executes transmission of the next request via the second bus without waiting for reception of a response from the auxiliary unit corresponding to the transmitted request. And

  According to the present invention, after completing the reception of the request via the second bus, the bus converter returns the ID without waiting for the response to be transferred, and the CPU unit receives the ID, Since the second bus can be used without waiting for a response to be received using the first bus, which is slower than the bus, efficient communication can be performed between functional units via buses with different speeds. There is an effect.

FIG. 1 is a diagram showing a configuration of the PLC according to the first embodiment. FIG. 2 is a diagram illustrating the configuration of the bus converter according to the first embodiment. FIG. 3 is a flowchart for explaining the operation related to communication via the external bus of the CPU unit. FIG. 4 is a flowchart for explaining the transfer operation by the bus converter. FIG. 5 is a block diagram for explaining an operation of transferring a request among the transfer operations by the bus converter. FIG. 6 is a block diagram for explaining the operation of transferring the result data in the transfer operation by the bus converter. FIG. 7 is a flowchart for explaining the result data transfer process in detail. FIG. 8 is a timing chart for explaining the effect of the PLC according to the first embodiment. FIG. 9 is a diagram illustrating a configuration of the PLC according to the second embodiment. FIG. 10 is a diagram for explaining the configuration of the bus converter according to the second embodiment. FIG. 11 is a flowchart for explaining result data transfer processing by the bus converter according to the second embodiment. FIG. 12 is a diagram illustrating a configuration of the PLC according to the third embodiment. FIG. 13 is a diagram illustrating the configuration of the bus converter according to the third embodiment. FIG. 14 is a flowchart for explaining an operation related to communication via the external bus of the CPU unit. FIG. 15 is a flowchart for explaining the result data transfer process. FIG. 16 is a diagram for explaining the connection between the bases and the configuration of the first bus I / F included in the bus converter. FIG. 17 is a flowchart for explaining the operation when receiving a request for the first bus I / F. FIG. 18 is a diagram illustrating the configuration of the PLC according to the fifth embodiment.

  Embodiments of a programmable controller (PLC) and a bus converter according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
FIG. 1 is a diagram showing the configuration of the PLC according to the first embodiment of the present invention.

As shown in the figure, the PLC 100 is configured by connecting a basic base 1 and expansion bases 2 a and 2 b via an external bus 3. The basic base 1 includes a CPU unit 13, four auxiliary units 12, and an expansion bus interface (I / F) 14, and the respective constituent elements are connected by an internal bus 11.

  The extension base 2a includes four auxiliary units 22a and a bus converter 23a, and the respective components are connected by an internal bus 21a. Similarly, the extension base 2b includes four auxiliary units 22b and a bus converter 23b, and the respective components are connected to each other by an internal bus 21b.

  The number of extension bases connected to the basic base 1 may be any number as long as it is one or more. Further, the number of auxiliary units 12, 22a, and 22b included in each of the bases 1, 2a, and 2b may be any number as long as it is one or more. Since the extension base 2a and the extension base 2b have the same configuration, hereinafter, only the extension base 2a may be described as a representative when explaining the extension base.

  The expansion bus I / F 14 is an interface for connecting the internal bus 11 and the external bus 3. The bus converter 23a is an interface for connecting the external bus 3 and the internal bus 21a.

  The CPU unit 13 controls the auxiliary units 12, 22a and 22b by transmitting and receiving control data to and from the auxiliary units 12, 22a and 22b included in the PLC 100. Specifically, the CPU unit 13 transmits a request to the auxiliary unit 12 via the internal bus 11. The auxiliary unit 12 that has received the request from the CPU unit 13 performs the requested operation, and then transmits the result data (response) corresponding to the request to the CPU unit 13 via the internal bus 11. For example, as a request, when the auxiliary unit 12 is a temperature control unit, there is a request for setting the temperature of the controlled device. The temperature control unit that has received the request, when setting the target temperature to the requested temperature, transmits result data to notify the completion of the setting. As another example of the request, there is a request for reading an input value when the auxiliary unit 12 is an analog input unit. The analog input unit that has received the request reads the input value and transmits the read input value as result data. Similarly, the CPU unit 13 transmits a request to the auxiliary unit 22a via the expansion bus I / F 14, the external bus 3, the bus converter 23a, and the internal bus 21a. The auxiliary unit 22 a transmits result data corresponding to the request to the CPU unit 13.

  The internal bus 11 is faster than the internal bus 21a and the internal bus 21b. The external bus 3 is assumed to have the same speed as the internal bus 11 and the same transmission method.

  Here, if a transaction is constituted by the request and the result data, the performance of the internal bus 21a becomes a bottleneck, which causes a problem that efficient communication cannot be performed. That is, while the CPU unit 13 and the auxiliary unit 12 can operate at a higher speed than the expansion base 2a, the CPU unit 13 and the auxiliary unit 12 are forced to wait until the access is completed while accessing the expansion base 2a. Therefore, in the first embodiment, after the bus converter 23a has received the request via the external bus 3, the external bus 3 is released without waiting for the transfer of the result data. Thereby, the CPU unit 13 can perform the next communication without waiting until the result data is received, and can perform efficient communication.

  Specifically, the bus converter 23a issues an ID every time a request is received, and returns the issued ID. A transaction is composed of the request and the ID. The ID issuance is executed at a higher speed than the auxiliary unit 22a that is the access destination transmits the result data, and the issued ID is transmitted without passing through the low-speed internal bus 21a. ID can be received earlier than receiving. As a result, the occupation time of the external bus 3, in other words, the waiting time of the CPU unit 13 is shortened.

  FIG. 2 is a diagram illustrating the configuration of the bus converter 23a according to the first embodiment. As illustrated, the bus converter 23 a includes a control unit 24, a first bus I / F 25, a second bus I / F 26, a bus conversion unit 27, an ID management unit 28, and a buffer 29.

  The first bus I / F 25 is an interface for communicating with the basic base 1 via the external bus 3. The second bus I / F 26 is an interface for communicating with the auxiliary unit 22a via the internal bus 21a. The bus conversion unit 27 converts the transmission method between the external bus 3 and the internal bus 21a. For example, assuming that the external bus 3 is a serial transmission method and the internal bus 21a is a parallel transmission method, the bus conversion unit 27 converts the parallel data received from the internal bus 21a into serial data and passes it to the control unit 24. In addition, the bus conversion unit 27 converts the serial data received from the control unit 24 into parallel data and passes it to the second bus I / F 26.

  The control unit 24 uses the ID management unit 28 and the buffer 29 to transfer a request received via the first bus I / F 25 and a result data received via the second bus I / F 26 and the bus conversion unit 27. Run.

  The ID management unit 28 issues an ID for each request received by the bus converter 23a. The ID is an identifier that allows the CPU unit 13 to identify requests that have already been issued.

  In the buffer 29, a request storage area 29-1 and a result storage area 29-2 are secured. In the request storage area 29-1, a request received via the external bus 3 is stored, and in the result storage area 29-2, result data received via the internal bus 21a is temporarily associated with the ID according to the FIFO method. Stored. The requests stored in the request storage area 29-1 are sequentially transmitted to the auxiliary unit 22a, and the result data stored in the result storage area 29-2 are sequentially transmitted to the CPU unit 13 by the control unit 24.

Next, the operation | movement concerning communication of PLC100 of Embodiment 1 is demonstrated. FIG. 3 is a flowchart for explaining the operation of the CPU unit 13 related to the communication via the external bus 3. As shown in the drawing, the CPU unit 13 transmits a request to the auxiliary unit 22 (auxiliary unit 22a, auxiliary unit 22b) to be accessed via the external bus 3 (step S1). Bus converter 23 to the access destination of the auxiliary unit 22 is provided (bus converter 23a, a bus converter 23 b) ID is sent back from, CPU unit 13 receives the ID (Step S2). Then, the CPU unit 13 monitors the reception of the result data (step S3). When the result data is not received (step S3, No), the CPU unit 13 proceeds to step S1 and requests to the auxiliary unit 22 for another access Send. When the result data is received (step S3, Yes), the CPU unit 13 associates the request with the transmitted request based on the ID added to the received result data, and processes the result data ( Step S4). After step S4, the process proceeds to step S1, and the CPU unit 13 transmits a request to the auxiliary unit 22 related to another access.

  FIG. 4 is a flowchart for explaining the transfer operation by the bus converter 23a, FIG. 5 is a block diagram for explaining an operation of transferring a request among the transfer operations, and FIG. 6 is a diagram of the transfer operation. It is a block diagram explaining the operation | movement which transfers the result data.

  First, when the control unit 24 recognizes a request received from the external bus 3 (step S11), the control unit 24 requests the ID management unit 28 to issue an ID (step S12). When the ID is issued, the control unit 24 returns the issued ID to the CPU unit 13 via the external bus 3 (step S13), and the control unit 24 corresponds the content of the received request to the ID. Then, it is stored in the request storage area 29-1 (step S14). When the requests are received continuously from the external bus 3, the control unit 24 repeats the operations in steps S11 to S14 every time a request is received, and accumulates the received requests in the request storage area 29-1.

Subsequently, the control unit 24 transmits the request stored in the request storage area 29-1 to the auxiliary unit 22a via the internal bus 21a (step S15). Then, the control unit 24 stores the result data returned from the auxiliary unit 22a in the result storage area 29-2 in association with the ID (step S16). And the control part 24 performs the result data transfer process which transmits the result data stored in the result storage area 29-2 to CPU unit 13 with corresponding ID (step S17), and complete | finishes transfer operation.

  FIG. 7 is a flowchart for explaining the result data transfer process in detail. In the first embodiment, it is assumed that the bus converter 23a transmits the result data to the external bus 3 based on the CSMA / CD (Carrier Sense Multiple Access with Collision Detection) method. The CSMA / CD method can be implemented relatively easily in the bus arbitration method.

  As shown in FIG. 7, first, the control unit 24 determines whether or not the external bus 3 is free (step S21). The case where the external bus 3 is not free includes the case where the CPU unit 13 is executing request transmission, ID reception, and result data reception. If the external bus 3 is not free (No in step S21), the process waits until the external bus 3 is free by repeating step S21. When the external bus 3 is free (step S21, Yes), the control unit 24 starts transmitting the result data stored in the result storage area 29-2 to the CPU unit 13 together with the corresponding ID (step S22). The control unit 24 monitors whether or not the external bus 3 collides with another access during transmission of the result data (step S23), and when an access collision is detected (step S23, Yes), the process proceeds to step S21. Wait until the collision is resolved. Note that if the transmission is interrupted due to access collision and the collision is resolved (Yes in step S21), the control unit 24 does not start from the interrupted portion of one result data, but first of one result data. Send from.

  When an access collision is not detected in the external bus 3 (No at Step S23), when transmission of one result data is completed (Step S24), the control unit 24 proceeds to Step S21 and results storage area 29-2 It is determined whether the external bus 3 is free for transmission of the next result data stored in.

  In this way, the received result data is temporarily stored in the result storage area 29-2, and the result storage area is estimated in case the external bus 3 is free so as not to prevent the CPU unit 13 from using the external bus 3. The result data temporarily stored in 29-2 is sequentially transmitted.

  Next, the effect of the PLC 100 that operates in this way will be described. FIG. 8 is a timing chart for explaining the effect of the PLC 100 of the first embodiment. In FIG. 8, the communication states of the external bus 3, the bus converter 23a, the internal bus 21a, the bus converter 23b, and the internal bus 21b are shown in order from the top. As shown in the figure, after the transmission of the request between the basic base 1 and the expansion base 2a and the return of the ID are completed, the external bus 3 is released, and the transmission of the basic base 1 request and the ID of the expansion base 2b Reply and are executed. During this time, the internal bus 21a, which is slower than the external bus 3, is accessed. Further access is possible after receiving the ID from the extension base 2b until receiving the result data from the extension base 2a. As described above, according to the first embodiment, the request and the ID constitute a transaction, and the CPU unit 13 uses the high-speed external bus 3 and the internal bus 11 without waiting for the completion of the low-speed bus access. And another access can be performed.

  As described above, according to the first embodiment of the present invention, when the bus converter 23 receives a request for the auxiliary unit 22 transmitted by the CPU unit 13, the bus converter 23 generates an ID for each request and generates the generated ID. When the CPU unit 13 receives the ID, the CPU unit 13 does not wait for reception of the result data from the auxiliary unit corresponding to the transmitted request, or the internal bus 11 (or the internal bus 11 and the external bus 3). Since the transmission of the next request is performed through the network, efficient communication can be performed between the functional units via the buses having different speeds.

  The bus converter 23 includes a result storage area 29-2 for temporarily storing the result data transmitted from the auxiliary unit 22, and transmits the result data temporarily stored in the result storage area 29-2 to the CPU unit 13. Since the result data can be temporarily stored in the result storage area 29-2 until the external bus 3 becomes empty, the bus converter 23 uses the external bus 3 and the internal bus 11 by the CPU unit 13. The result data can be transmitted without disturbing.

  In addition, the bus converter 23 is configured to transmit the result data temporarily stored in the result storage area 29-2 to the CPU unit 13 based on the CSMA / CD method. The result data can be transmitted without hindering the use of the external bus 3 and the internal bus 11. Further, since the CSMA / CD method is a method that is relatively easy to implement among the bus arbitration methods, the bus arbitration of the external bus 3 and the internal bus 11 can be performed with a simple configuration.

Embodiment 2. FIG.
In the first embodiment, the bus converter adjusts the transfer timing of the result data based on the CSMA / CD method. In the second embodiment, an arbiter (bus arbitration unit) that performs bus arbitration for the external bus and the internal bus in the basic base is provided.

  FIG. 9 is a diagram showing a configuration of the PLC according to the second embodiment of the present invention. As shown in the figure, the PLC 200 is configured by connecting a basic base 1 and additional bases 2 a and 2 b via an external bus 3. The basic base 1 includes an auxiliary unit 12, a CPU unit 13, an expansion bus I / F 14, and an arbiter 41 that performs bus arbitration for the external bus 3. The auxiliary unit 12, the CPU unit 13, the extension bus I / F 14, and the arbiter 41 are connected to each other via the internal bus 11.

  On the other hand, the extension base 2a includes an auxiliary unit 22a and a bus converter 42a. The extension base 2b includes an auxiliary unit 22b and a bus converter 42b.

  The bus converter 42a included in the extension base 2a is connected to the arbiter 41 by a REQUEST signal and a GRANT signal. The bus converter 42a outputs a REQUEST signal to the arbiter 41 to request a bus use right. The arbiter 41 outputs a GRANT signal to the bus converter 42a when giving the bus use right to the bus converter 42a as a result of the bus arbitration.

  Similarly, the bus converter 42b included in the extension base 2b is connected to the arbiter 41 by a REQUEST signal and a GRANT signal. The bus converter 42b outputs a REQUEST signal to the arbiter 41 to request a bus use right. When the arbiter 41 gives the bus use right to the bus converter 42b as a result of the bus arbitration, the arbiter 41 outputs a GRANT signal to the bus converter 42b.

  Hereinafter, only the expansion base 2a will be described as a representative regarding the expansion base.

  FIG. 10 is a diagram illustrating the configuration of the bus converter 42a according to the second embodiment. As illustrated, the bus converter 42 a includes a control unit 43, a first bus I / F 25, a second bus I / F 26, a bus conversion unit 27, an ID management unit 28, and a buffer 29. As shown in the figure, when the REQUEST signal and the GRANT signal are connected to the control unit 43 and the result data is transmitted to the CPU unit 13, the result is obtained after securing the bus use right using the REQUEST signal and the GRANT signal. Start sending data. The other components having the same names and the same reference numerals as those of the first embodiment perform the same operations as those of the first embodiment, and thus detailed description thereof is omitted here.

  FIG. 11 is a flowchart for explaining result data transfer processing by the bus converter 42a of the second embodiment. As illustrated, the control unit 43 first outputs a REQUEST signal (step S31). And the control part 43 determines whether the GRANT signal from the arbiter 41 was received (step S32). When there is no GRANT signal output (step S32, No), the control unit 43 repeats the determination of step S32.

  When the GRANT signal is received (step S32, Yes), the result data is transmitted to the CPU unit 13 together with the corresponding ID (step S33), and the process proceeds to step S31 to output a REQUEST signal for transmission of the next result data. .

  As described above, according to the second embodiment of the present invention, the bus converter 23 outputs the REQUEST signal to the arbiter 41, and after the arbiter 41 outputs the GRANT signal, the result data is transmitted to the CPU unit 13. Thus, the bus converter 23 can transmit the result data without interfering with the use of the external bus 3 and the internal bus 11 by the CPU unit 13 by a bus arbitration method different from that of the first embodiment.

Embodiment 3 FIG.
In the first embodiment and the second embodiment, the bus converter operates as a bus master for the external bus 3. In the third embodiment, a configuration example in the case where the external bus 3 operates as a bus slave will be described.

  FIG. 12 is a diagram illustrating a configuration of the PLC according to the third embodiment. As shown in the figure, the PLC 300 is configured by connecting a basic base 1 and additional bases 2 a and 2 b via an external bus 3. The basic base 1 includes an auxiliary unit 12, a CPU unit 51, and an expansion bus I / F 14. The auxiliary unit 12, the CPU unit 51, and the expansion bus I / F 14 are connected to each other via the internal bus 11.

  On the other hand, the extension base 2a includes an auxiliary unit 22a and a bus converter 52a. The extension base 2b includes an auxiliary unit 22b and a bus converter 52b. Hereinafter, only the expansion base 2a will be described as a representative regarding the expansion base.

  After issuing the request and receiving the ID corresponding to the request, the CPU unit 51 sends the result to the bus converter 52 (the bus converter 52a or the bus converter 52b) provided in the request issue destination extension base at a desired timing. The result data is read from the target bus converter 52 by sending a data confirmation. In the result data confirmation, it is assumed that the ID of the result data to be read is added.

  FIG. 13 is a diagram illustrating the configuration of the bus converter 52a according to the third embodiment. As illustrated, the bus converter 52a includes a control unit 53, a first bus I / F 25, a second bus I / F 26, a bus conversion unit 27, an ID management unit 28, and a buffer 54. In the buffer 54, a request storage area 29-1 and a result storage area 54-2 are secured. When receiving the result data confirmation from the CPU unit 51, the control unit 53 reads the result data corresponding to the added ID from the result storage area 54-2, and transmits the read result data to the CPU unit 51 together with the ID. . In the first and second embodiments, the result storage area 29-2 stores the result data in accordance with the FIFO method. However, the result storage area 54-2 of the third embodiment uses the FIFO method. The desired data can be read instead of being read based on this.

  FIG. 14 is a flowchart illustrating an operation related to communication via the external bus 3 of the CPU unit 51. As shown in the figure, the CPU unit 51 transmits a request to the access destination auxiliary unit 22 (auxiliary unit 22a or auxiliary unit 22b) via the external bus 3 (step S41). An ID is returned from the bus converter 52 provided in the auxiliary unit 22 to be accessed, and the CPU unit 51 receives the ID (step S42). Thereafter, the CPU unit 51 transmits a result data confirmation (step S43). The CPU unit 51 receives the result data and processes the received result data (step S44). After step S44, the CPU unit 51 proceeds to step S41 and performs the next access. Note that the CPU unit 51 continuously executes the operations of step S41 and step S42 for the number of accesses, and executes the operations of step S43 and step S44 after completing the repeated operations of step S41 and step S42. It is also possible.

  FIG. 15 is a flowchart for explaining the result data transfer process. As shown in the figure, when receiving the result data confirmation (Step S51), the control unit 53 reads the corresponding result data from the result storage area 54-2, and transmits the read result data to the CPU unit 51 together with the ID ( Step S52). Then, the CPU unit 51 waits for reception of new result data confirmation, and proceeds to step S51.

  As described above, according to the third embodiment of the present invention, the CPU unit 51 is configured to read the result data temporarily stored in the result storage area 54-2 at an arbitrary timing. It is also possible to configure the device 52 to operate as a bus slave.

Embodiment 4 FIG.
The external bus 3 according to the first to third embodiments may be configured so that it can be connected in a daisy chain between expansion bases. In the fourth embodiment, a configuration in which the external bus 3 of the first embodiment can be connected in a daisy chain as an example will be described.

  FIG. 16 is a diagram for explaining the connection between the bases and the configuration of the first bus I / F 25 provided in the bus converter 23. As shown in the figure, in the PLC 400 of the fourth embodiment, the basic base 1 and the extension base 2a are one-to-one via the external bus 3 via the first bus I / F 25 provided in the extension bus I / F 14 and the bus converter 23a. The extension base 2a and the extension base 2b are connected by the external bus 3 on a one-to-one basis via the first bus I / F 25 provided in the bus converter 23a and the first bus I / F 25 provided in the bus converter 23b. Yes. That is, the expansion bases 2a and 2b are connected to the basic base 1 in a daisy chain shape.

  Further, the first bus I / F 25 provided in each extension base further includes a request transfer unit 61. The request transfer unit 61 determines whether or not the transmission destination of the request received via the external bus 3 is the auxiliary unit 22 connected to the own expansion base 2 via the internal bus 21. Decide whether to forward to.

  In general, the CPU unit 13 detects the connection relationship of the connected extension bases 2 when the PLC 400 is started up and registers a unique identification number for each extension base 2 in the management table in the CPU unit 13. The identification number for each extension base 2 is given by, for example, a setting pin provided in the extension base 2. When the CPU unit 13 transmits a request via the external bus 3, the CPU unit 13 attaches the identification number of the extension base 2 to which the auxiliary unit 22 to be accessed belongs to the request. The request transfer unit 61 compares the identification number of the own extension base 2 with the identification number attached to the received request to determine whether or not the auxiliary unit 22 connected to the own extension base 2 is an access target. Determine.

  The extension base at the rear stage refers to the extension base 2 connected to the base extension base 2 and connected to the side far from the base base 1 when a plurality of extension bases 2 are connected. For example, when the extension base 2a is used as a reference, the extension base 2b is connected to the extension base 2a and is connected to the side farther than the basic base 1, so that the extension base 2b is the subsequent extension base.

  FIG. 17 is a flowchart for explaining the operation at the time of request reception of the first bus I / F 25. As shown in the figure, first, when the first bus I / F 25 receives a request (step S61), the request transfer unit 61 sends the own extension base 2 (more precisely, the own extension base 2 via the internal bus 21). It is determined whether or not the connected auxiliary unit 22) is an access target (step S62). When the own extension base 2 is an access target (step S62, Yes), the request transfer unit 61 transmits the received request to the control unit 24 (step S63), and the operation at the time of receiving the request ends. When the own extension base 2 is not an access target (No at Step S62), the request transfer unit 61 transfers the received request to the subsequent extension base 2 (Step S64), and ends the operation when the request is received.

  As described above, according to the fourth embodiment of the present invention, the bus converters 23 are connected in a daisy chain by the external bus 3, and each of the bus converters 23 receives a request from the CPU unit 13. If the transmission destination of the received request is not the auxiliary unit 22 connected to the own bus converter 23 via the internal bus 21, the received request is transferred to the subsequent bus converter 23, and the transmission destination of the received request Is an auxiliary unit 22 connected to the own bus converter 23 via the internal bus 21, the received request is not transferred to the subsequent bus converter 23. In addition to preventing this, it is possible to prevent the subsequent bus converter 23 from performing unnecessary operations.

Embodiment 5 FIG.
In the description of the first to fourth embodiments, the bus converter has been described as being provided in the extension base. However, the bus converter and the extension base may be configured as separate units.

  FIG. 18 is a diagram illustrating the configuration of the PLC according to the fifth embodiment. As shown in the figure, the PLC 500 includes a basic base 1, a plurality of extension bases 4 (here, an extension base 4 a and an extension base 4 b), and a bus converter 71. The bus converter 71 is connected to the basic base 1 and the external bus 3. The bus converter 71 is connected to the extension base 4 a and the extension base 4 b by the external bus 5.

  The expansion base 4a includes an internal bus 21a to which a plurality of auxiliary units 22a are connected, and an expansion bus I / F 72a for connecting the internal bus 21a and the external bus 5. Similarly, the expansion base 4b includes an internal bus 21b to which a plurality of auxiliary units 22b are connected, and an expansion bus I / F 72b for connecting the internal bus 21b and the external bus 5. The external bus 5 has a lower bus speed than the external bus 3, and for example, the same bus speed and transmission method as the internal bus 21a and the internal bus 21b are adopted. The bus converter 71 connects the external bus 3 and the external bus 5, and connects the CPU unit 13 mounted on the basic base 1 and the auxiliary unit 22 mounted on the expansion base 4 (extension base 4a, expansion base 4b). Data transfer to (auxiliary unit 22a, auxiliary unit 22b) is executed.

  The bus converter 71 may employ any of the configurations described in the first to fourth embodiments. The external bus 5 is connected to the second bus I / F 26.

Thus, the bus converter and the extension base can be configured as separate units. When the bus converter and the extension base are configured as separate units, the user can install the extension base 4a, the extension base 4b, and the external bus even after installing the basic base 1 or the external bus 3 with a high bus speed. as 5, since it is possible to utilize hardware asset that the user already has, convenience is improved I bets the user.

  In the first to fifth embodiments, the CPU unit is described as a request transmission source. However, when a motion CPU unit is included as the auxiliary unit 12 included in the basic base 1, the motion CPU unit also transmits a request. You may make it comprise so that it may become the origin.

  As described above, the programmable controller and the bus converter according to the present invention are suitable for application to a programmable controller and a bus converter that control a controlled device such as an industrial device.

1 Basic base , 2, 2a, 2b, 4, 4a, 4b Extension base, 3 External bus, 5 External bus, 11 Internal bus, 12, 22, 22a, 22b Auxiliary unit, 13, 51 CPU unit, 21, 21a, 21b Internal bus, 23, 23a, 23b, 42a, 42b, 52, 52a, 52b, 71 Bus converter, 24, 43, 53 Control unit, 25 First bus I / F, 26 Second bus I / F, 27 Bus conversion unit, 28 ID management unit, 29, 54 buffer, 29-1 request storage area, 29-2, 54-2 result storage area, 41 arbiter, 61 request transfer unit, 71 bus converter.

Claims (8)

A CPU unit;
An auxiliary unit controlled by the CPU unit;
A first base unit comprising a first bus, the auxiliary unit being mounted on the first bus;
A second base unit that includes a second bus that is faster than the first bus, the second bus includes an internal bus and an external bus, and the CPU unit is mounted on the internal bus;
A bus converter connected to the first bus and the external bus for transferring control data transmitted and received between the CPU unit and the auxiliary unit;
When the bus converter receives a request for the auxiliary unit transmitted by the CPU unit, it generates an ID for each request and returns the generated ID to the CPU unit.
When the CPU unit receives the ID, it executes transmission of the next request via the second bus without waiting for reception of a response from the auxiliary unit corresponding to the transmitted request.
A programmable controller characterized by that. When the bus converter receives a response transmitted from the auxiliary unit to the CPU unit, the bus converter transfers the received response to the CPU unit together with an ID of a request corresponding to the received response.
When the CPU unit receives the response transmitted by the auxiliary unit, the CPU unit associates the request with the transmitted request based on the ID received together with the response.
The programmable controller according to claim 1. The bus converter includes a response storage area for temporarily storing the response transmitted by the auxiliary unit, and transmits the response temporarily stored in the response storage area to the CPU unit.
The programmable controller according to claim 2. The bus converter transmits a response temporarily stored in the response storage area to the CPU unit based on the CSMA / CD method.
The programmable controller according to claim 3. A bus arbitration unit for arbitrating the second bus;
The bus converter requests access permission from the bus arbitration unit, and after obtaining the access permission, transmits a response temporarily stored in the response storage area to the CPU unit.
The programmable controller according to claim 3. The bus converter includes a response storage area for temporarily storing a response transmitted by the auxiliary unit,
The CPU unit reads a response temporarily stored in the response storage area at an arbitrary timing.
The programmable controller according to claim 1. A plurality of the bus converters, and the plurality of bus converters are connected in a daisy chain with the external bus,
When each of the bus converters receives a request from the CPU unit via the external bus, the transmission destination of the received request is connected to the own bus converter via the first bus. If it is not a unit, the received request is transferred to a subsequent bus converter, and when the destination of the received request is an auxiliary unit connected to the own bus converter via the first bus, Do not forward the received request to the subsequent bus converter,
The programmable controller according to any one of claims 1 to 6. Comprising a first bus, comprising: a first bus of a first base unit the auxiliary unit is mounted to said first bus, said first high speed second bus than the bus, the second The second bus includes an internal bus and an external bus, and is connected to the external bus of the second base unit to which the CPU unit for controlling the auxiliary unit is mounted. The CPU unit and the auxiliary unit A bus converter that transfers control data sent to and received from
When a request for the auxiliary unit transmitted by the CPU unit is received, an ID for each request transmitted by the CPU unit is generated and the generated ID is returned to the CPU unit, and the ID is transmitted to the CPU unit. After receiving, it is possible to execute transmission of the next request through the second bus without waiting for reception of a response from the auxiliary unit corresponding to the transmitted request.
A bus converter characterized by that.

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