JP5455011B2 - LCD panel - Google Patents

Description

The present invention relates to an FFS (Fringe Field Switching) mode liquid crystal display panel in which an electric field is applied to a liquid crystal layer by a common electrode electrically connected to a common wiring and a pixel electrode having a plurality of slit-like openings. Specifically, in the present invention, the common wiring is formed so as to be in direct contact with the front surface or the back surface of the common electrode, and the common wiring is partially formed to be wide.
The present invention relates to an FS mode liquid crystal display panel.

As a liquid crystal display panel, a vertical electric field type panel in which a liquid crystal layer is sandwiched between a pair of transparent substrates each having an electrode formed on the surface thereof is widely known. This vertical electric field type liquid crystal display panel generates an electric field in a liquid crystal layer by applying a voltage to a pixel electrode disposed on one transparent substrate and a common electrode disposed on the other transparent substrate. Various information is displayed by utilizing the rearranged characteristics. As a vertical electric field type liquid crystal display panel, TN (Twiste
d Nematic) mode is common, but because of the problem of narrow viewing angle, various improved modes such as VA (Vertical Alignment) mode and MVA (Multidomain Vertical Alignment) mode are also available. Has been developed.

On the other hand, unlike a vertical electric field type liquid crystal display panel, a horizontal electric field type liquid crystal display panel in which a pixel electrode and a common electrode are arranged only on one transparent substrate is also known. This horizontal electric field type liquid crystal display panel is roughly classified into an IPS (In-Plane Switching) mode and an FFS mode.

In the IPS mode liquid crystal display panel, the pixel electrode and the common electrode are arranged in the same layer, and the direction of the electric field applied to the liquid crystal layer is made substantially parallel to the substrate so that the liquid crystal molecules are parallel to the substrate (lateral direction).
It is known that a very wide viewing angle can be obtained as compared with the above-described vertical electric field type liquid crystal display panel. In the IPS mode liquid crystal display panel, the pixel electrode for generating an electric field in the liquid crystal layer and the common electrode are arranged side by side in the same layer, so the liquid crystal molecules on the pixel electrode are not driven sufficiently, and the transmittance, etc. It has the problem of causing a decline.

In order to solve such problems of the IPS mode liquid crystal display panel, an FFS mode liquid crystal display panel has been developed. In this FFS mode liquid crystal display panel, a pair of electrodes for applying a voltage to a liquid crystal layer are arranged in different layers.

This FFS mode liquid crystal display panel has features that it has a wider viewing angle and higher contrast than an IPS mode liquid crystal display panel, can be driven at a lower voltage, and has a higher transmittance, enabling bright display. . In addition, since the overlapping area of the pixel electrode and the common electrode is larger in a plan view than in the IPS mode liquid crystal display panel, a larger auxiliary capacitance can be obtained as a secondary, so there is no need to provide a separate auxiliary capacitance electrode. Also, it has a feature that an aperture ratio higher than that of an IPS mode liquid crystal display panel can be obtained.

FIG. 5A is a schematic plan view of one sub-pixel region showing an example of a conventional FFS mode liquid crystal display panel. In the following description, it is assumed that the upper electrode operates as a pixel electrode and the lower electrode operates as a common electrode. As shown in FIG. 5A, the FFS mode liquid crystal display panel has a pixel electrode 103 and a common electrode (not shown) on the array substrate so as to cover a sub-pixel region defined by the scanning line 101 and the signal line 102. A plurality of slit openings (hereinafter simply referred to as “slits”) are formed in the pixel electrode 103 in order to generate a fringe electric field. As a liquid crystal display panel having such a slit, for example, as shown in FIG. 5A, a slit located in the center is formed in a U-shape by inverting the inclination direction of the slit S vertically in the column direction within one subpixel region. In other cases, liquid crystal display panels having various slit shapes or slit arrangements have been proposed in order to obtain better images (see Patent Document 1 below).

In the dual-domain FFS mode liquid crystal display panel as shown in FIG. 5A, the center in the column direction is a boundary between regions in which the liquid crystal tilt directions are opposite to each other. Since image display is not possible, as shown by reference numeral 104 ′ in FIG. 5A, common wiring is also arranged at the center in the column direction (see Patent Document 1 below). Further, in an FFS mode liquid crystal display panel, in order to achieve a bright display, it is common practice to make the width of the slit formed in the pixel electrode wider than the width of the pixel electrode portion existing between the slits. It has been broken.

A common wiring 104A made of a metal material such as aluminum is formed in the sub-pixel region. This is the ITO (Indium Tin) widely used for pixel electrodes and common electrodes.
Oxide), transparent conductive material such as IZO (Indium Zinc Oxide) has a larger electric resistance than a general metal material, so that the common electrode is applied to the common electrode by conducting the common wiring 104A. This is to stabilize the common potential.

The common wiring 104A is connected to the scanning line 101 and the signal line 102, for example, in a lower layer of a gate insulating film (not shown) interposed between the scanning line 101 and the signal line 102 so as not to be short-circuited with the scanning line 101 or the signal line 102. The signal lines 102 are formed so as to intersect in parallel and in plan view. The common wiring 104A is electrically connected to the common electrode by being covered with the common electrode that covers the sub-pixel region while avoiding the TFT or the like, or by being formed on the surface of the common electrode. (See Patent Documents 2 and 3 below).

JP 2007-264231 A JP 2008-304744 A JP 2008-310210 A

With the recent progress of miniaturization and high definition of liquid crystal display panels, the size of each sub-pixel region has been reduced. In order to cope with this situation, reducing the thickness of the common wiring increases the resistance of the common wiring and decreases the contact area between the common wiring and the common electrode, thereby increasing the contact resistance. The potential of the electrode becomes unstable. Therefore, it is necessary to maintain a certain thickness for the common wiring.

Therefore, as shown in FIG. 5B, it is conceivable to increase the thickness of the common wiring 104B in each sub-pixel region. In FIG. 5B, the signal line 102 and the common wiring 1
The thickness of the common wiring 104 at the intersection with 04B is thinned.
This is for suppressing parasitic capacitance formed between 02 and the common wiring 104B. With such a configuration, the contact area between the common wiring 104B and the common electrode is increased, and the electric resistance of the common wiring 104B can be reduced, and the reference potential applied to the common electrode is stable. It becomes.

However, when forming such a wide common wiring 104B, as shown in Figure 5B, forming defective portion P occurs in a pixel electrode 103 that overlaps with the common line 104B in plan view, the slit between S ₁ adjacent and It has been found that S ₂ to S ₁ and S ₃ are connected to each other, and that a new problem that the pixel electrode 103 portion to be formed between adjacent slits is cut occurs.

The reason why such a problem occurs will be described with reference to FIG. 6A to 6C are schematic cross-sectional views showing a slit forming process to the pixel electrode by a photolithography method in the case where the wide common wiring is arranged at the center of the sub-pixel region.

The common wiring 104B is formed on the surface of the transparent substrate 106 in the same layer as the scanning lines (not shown). A common electrode that covers the surface of the common wiring 104B, a scanning line, a gate electrode of a TFT as a switching element, and a gate insulating film that covers the surface of the common electrode and the like are formed on the common wiring 104B. Yes. Furthermore, on the surface of the gate insulating film, a signal line,
A source electrode and a drain electrode of the TFT, and a passivation film are formed (both not shown). Note that the common electrode, the gate insulating film, the passivation film, and the like are shown as a structure 107 in FIGS. 6A to 6C.

Then, in the slit forming step by photolithography on the upper electrode, FIG.
As shown in A, a resist is applied to the entire surface of the transparent conductive film 108 to be the upper electrode, and the entire surface of the resist film 109 is used by using a mask member 110 having an upper electrode pattern formed thereon. The exposure process is performed by irradiating ultraviolet rays UV.

However, the upper portion of the wide common wiring 104B is covered only with a transparent material such as a common electrode made of ITO or IZO, a pixel electrode, a gate insulating film made of silicon nitride or silicon oxide, or a passivation film. For this reason, the ultraviolet ray UV irradiated from above is reflected on the surface of the common wiring 104B made of a metal material, and the reflected ultraviolet ray RU is reflected.
V exposes the non-exposure scheduled resist portion above the common wiring 104B from below. As a result, as shown in FIG. 6B, the cross-sectional shape of the resist pattern 109B above the developed common wiring 104B is the resist pattern 109A in the other region,
Compared to 109C, it will be much thinner than the planned shape. This is a phenomenon that cannot be reliably avoided by taking a measure that a large mask is provided in advance by predicting that the ultraviolet ray R-UV reflected by the common wiring 104B exposes the resist excessively.

For the reasons described above, after the transparent conductive film 108 is etched, FIG.
As shown and C, wide and made results from above the slit S ₁ is the planned common wiring 104B, forming defective portion P to the pixel electrode 103 is caused as shown in FIG. 5B, connected is adjacent slits each other (A pixel electrode between slits is divided) occurs. Such a phenomenon also causes an increase in the electrical resistance value of the pixel electrode, and hinders good image display.

As a result of various studies to solve the above-mentioned problems, the inventor does not contribute to image display because the area where the common wiring is formed does not transmit light from the backlight,
In addition, since it is a region shielded from light by a black matrix or the like, it has been found that the formation failure of the pixel electrode as described above can be suppressed unless the slit is formed at a position overlapping the common wiring in plan view. Has been completed.

That is, an object of the present invention is to provide an FFS mode liquid crystal display panel in which formation of a slit or a pixel electrode portion between the slits hardly occurs in a portion of the pixel electrode located above the wide common wiring.

In order to achieve the above object, in the liquid crystal display panel of the present invention, a liquid crystal layer is sandwiched between a first transparent substrate and a second transparent substrate, and an insulating film is formed on the liquid crystal layer side of the first transparent substrate. across are formed in different layers from each other, a plurality of signal lines and scanning lines for partitioning the display area to each sub-pixel region, run parallel between 査線, a plurality of common formed run査線the same layer A liquid crystal display panel comprising a wiring and a pixel electrode disposed in each sub-pixel region and formed in different layers with an insulating film interposed therebetween and a pixel electrode having a plurality of slit-like openings , Mon wire is disposed at a center portion of the sub-pixel regions in a direction parallel to the signal lines are wider formation in sub pixel region than the width of the portion intersecting with the signal line in plan view, the pixel electrodes Is a strip-shaped pixel electrode sandwiched between slit-shaped openings A is, and adjacent to each other across the common wiring in plan view, partially sandwiched between the slit-shaped opening that overlaps the common wiring, and a first strip pixel electrodes overlap with the common wiring in plan view, the common wiring in a plan view and a second band-shaped pixel electrode portions not overlapping, the width of the first strip pixel electrode portions that are wider than the width of the second strip-shaped pixel electrode portions.

The liquid crystal display panel of the present invention is formed on the liquid crystal layer side of the first transparent substrate in different layers with an insulating film interposed therebetween, and a plurality of signal lines and scanning lines that divide the display area into sub-pixel areas , run parallel between 査線, run a plurality of common wiring in the same layer and 査線, arranged in each sub-pixel area, the common electrode and a plurality of slits formed in different layers from each other across the insulating film And a pixel electrode in which an aperture is formed, and operates as an FFS mode liquid crystal display panel.

With the configuration as described above, when the pixel electrode is formed by applying the photolithography method, the width of the band-like pixel electrode portion is reduced even if the resist above the common wiring is excessively exposed. Narrowing is suppressed, and a portion that does not overlap with the common wiring is normally exposed. Therefore, the width of the band-like pixel electrode portion does not become narrow and adjacent slits are not connected. Therefore, according to the liquid crystal display panel of the present invention, by increasing the common wiring in the sub-pixel region, the electric resistance of the common wiring is reduced and the adjacent slits are connected to each other. Since the increase in the resistance value is suppressed, the common potential applied to the pixel electrode does not deteriorate, and the liquid crystal display panel can obtain a good display image quality.

Further, in the liquid crystal display panel of the present invention, a plurality of slit-shaped opening formed in the image pixel electrode is inclined in opposite directions to each other as a boundary central portion in the sub pixel area in a direction parallel to the signal lines Tei It is preferable.

According to the above arrangement, since the alignment direction of liquid crystal molecules as a boundary central portion in the sub-pixel regions are two domains different are formed, the viewing angle is very wide.

Further, in the liquid crystal display panel of the present invention, the shortest distance between two slit-shaped openings adjacent to each other across a first strip pixel electrode portion of the picture element electrodes are adjacent across the second strip-shaped pixel electrode portions It is preferable that the distance is 1.5 to 2 times the distance between the two slit-shaped openings.

The shortest distance between two adjacent slit-shaped openings across the first strip-shaped pixel electrode portion of the pixel electrode is 1.5 times the distance between the two adjacent slit-shaped openings across the second strip-shaped pixel electrode portion. If the above is applied, even if the resist above the common wiring is excessively exposed when the pixel electrode is formed by applying the photolithography method, the two slit-shaped openings adjacent to each other with the common wiring interposed therebetween Will not be connected. Note that the upper limit of the shortest distance between two slit-shaped openings adjacent to each other across the first strip-shaped electrode portion of the pixel electrode is the distance between the two slit-shaped openings adjacent to each other across the second strip-shaped pixel electrode portion. If it is too large, the fringe electric field effective for display cannot be applied to the liquid crystal molecules and the display becomes dark.

It is a schematic plan view which shows the array substrate of the liquid crystal display panel of this embodiment. It is a top view for 1 sub pixel area | region of the liquid crystal display panel of this embodiment. It is the III-III sectional view taken on the line of FIG. It is process drawing which shows the manufacture procedure of the liquid crystal display panel of this embodiment. FIG. 5A is a plan view of one sub-pixel region of a conventional liquid crystal display panel, and FIG. 5B is a plan view of one sub-pixel region when the common wiring is wide in the conventional liquid crystal display panel. It is a figure which shows the slit formation process to the pixel electrode in a liquid crystal display panel.

Hereinafter, the best embodiment of the present invention will be described with reference to the drawings. However, the embodiment described below exemplifies a liquid crystal display panel for embodying the technical idea of the present invention, and is not intended to specify the present invention for this liquid crystal display panel. Other embodiments within the scope of the claims are equally applicable. In each drawing used for the description in this specification, each layer and each member are displayed in different scales so that each layer and each member can be recognized on the drawing. However, it is not necessarily displayed in proportion to the actual dimensions.

An FFS mode liquid crystal display panel 10 according to the present embodiment will be described with reference to FIGS.
As shown in FIG. 3, the schematic configuration of the liquid crystal display panel 10 is that the liquid crystal layer LC is an array substrate AR
And the color filter substrate CF, and the thickness of the liquid crystal layer LC is uniformly maintained by columnar spacers (not shown). A polarizing plate is formed on each of the back surface of the array substrate AR and the front surface of the color filter substrate CF, and a backlight is disposed on the back surface side of the array substrate AR (all not shown).

As shown in FIG. 1, the liquid crystal display panel 10 includes a display area DA in which various images are displayed.
And a frame area PF that surrounds the display area DA, a driver connection terminal portion Dr for placing a driver IC on one end of the frame area PF, and an external device connection terminal for connecting to an external device Part TP is formed. The frame area PF includes a display area DA.
The scanning line routing wiring 11 for routing the scanning line to the driver connection terminal portion Dr, the signal line routing wiring 12 for routing the signal line to the driver connection terminal portion Dr, and the common wiring connected to the lower electrode serving as the common electrode The driver connection terminal part Dr and the external device connection terminal part T
A common routing wiring 13 leading to P is formed.

Next, the detailed configuration of the array substrate AR will be described with reference to FIGS. The array substrate AR is based on a first transparent substrate 14 made of a transparent insulating material such as glass, quartz, or plastic. On the liquid crystal layer LC side of the first transparent substrate 14, a plurality of scanning lines 15 and signal lines 16 are arranged so as to intersect with each other, thereby dividing the display area DA into a plurality of sub-pixel areas. .

The scanning line 15 is made of a metal material such as aluminum, aluminum alloy, molybdenum,
The first transparent substrate 14 is formed to be parallel to each other in the row direction on the surface. A part of the scanning line 15 is partially widened and extends to the vicinity of the intersection of the scanning line 15 and the signal line 16 to constitute the gate electrode G of the TFT. Further, when the scanning line 15 is formed, the scanning line routing wiring 11 in the frame region PF shown in FIG.
5 is electrically connected to the driver connection terminal portion Dr.

A common wiring 17 is formed on the surface of the first transparent substrate 14. The common wiring 17 is formed simultaneously with the same material as the scanning line 15, and the scanning line 15 and the signal line 16 are formed.
In the lower layer of the gate insulating film 19 interposed therebetween, the contact with the scanning line 15 is avoided to be parallel to the scanning line 15 and to intersect with the signal line 16 in plan view. In the present embodiment, the common wiring 1 includes the purpose of suppressing a short circuit between the common wiring 17 and the scanning line 15.
Reference numeral 7 is arranged at substantially the center of the sub-pixel region. When the common wiring 17 is formed, the common routing wiring 13 in the frame region PF shown in FIG. 1 is formed integrally at the same time, whereby the common wiring 17 is connected to the driver connecting terminal portion Dr and the external device connecting terminal portion TP. Conducted.

Further, a common electrode 18 made of ITO or IZO is formed in each sub-pixel region so as to cover the surface of the common wiring 17 together with the exposed surface of the first transparent substrate 14. The scanning line 15, the gate electrode G, the common electrode 18 and the exposed surface of the first transparent substrate 14 are covered with a gate insulating film 19 from a transparent insulating material such as silicon nitride or silicon oxide. Further, a semiconductor layer 20 made of amorphous silicon, polycrystalline silicon or the like is formed on the surface of the gate insulating film 19 at a position overlapping the gate electrode G in plan view.

A plurality of signal lines 16 made of a metal material such as aluminum, aluminum alloy, or molybdenum are formed on the surface of the gate insulating film 19 so as to be parallel to each other in the column direction. A part of the signal line 16 extends to the TFT formation region, and this extended part is in partial contact with the surface of the semiconductor layer 20 and constitutes the source electrode S of the TFT. Further, when the signal line 16 is formed, the signal line routing wiring 12 in the frame region PF shown in FIG. 1 is integrally formed at the same time, whereby the signal line 16 is electrically connected to the driver connecting terminal portion Dr.

Further, the drain electrode D constituting the TFT is formed on the surface of the gate insulating film 19. The drain electrode D is formed of the same material as the signal line 16 and the source electrode S at the same time, and is in partial contact with the semiconductor layer 20 at a predetermined distance from the source electrode S in order to form a channel region. . The gate electrode G, the gate insulating film 19, and the semiconductor layer 20
The source electrode S and the drain electrode D constitute a TFT as a switching element.

The signal line 16, the source electrode S, the drain electrode D, the channel region of the TFT, and the exposed surface of the gate insulating film 19 are covered with a passivation film 21 made of a transparent insulating material such as silicon nitride or silicon oxide. Has been. And this passivation film 21
A pixel electrode 22 provided with a plurality of slits 22S is formed for each sub-pixel region. Like the common electrode 18, the pixel electrode 22 is made of a transparent conductive material such as ITO or IZO, and is connected to the drain electrode D through a contact hole 21CH provided so as to pass through the passivation film 21 and reach the drain electrode D. Conducted. Further, the surface of the pixel electrode 22 is covered with an alignment film (not shown). The specific configuration of the pixel electrode 22 and the slit 22S will be described later.

Next, the color filter substrate CF will be described. As shown in FIG. 3, the color filter substrate CF is based on a second transparent substrate 23 made of a transparent insulating material such as glass, quartz, or plastic. The second transparent substrate 23 has different colors of light for each sub-pixel region (
R, G, B or colorless) color filter layer 24 and black matrix 25
Is formed. In this example, the black matrix 25 is arranged above the common wiring 17 as well as the TFT formation region and the upper region of the scanning line. A top coat layer 26 is formed so as to cover the color filter layer 24 and the black matrix 25, and an alignment film (not shown) is formed so as to cover the top coat layer 26.

Then, the array substrate AR and the color filter substrate CF formed as described above are arranged to face each other, the peripheral portion is sealed with a sealing material (not shown), and the liquid crystal layer LC is placed in the array substrate AR.
The liquid crystal display panel 10 of this embodiment is obtained by sealing in a sealing area formed between the color filter substrate CF and the color filter substrate CF.

Here, a specific configuration of the common wiring 17, the pixel electrode 22, and the slit 22S in the FFS mode liquid crystal display panel 10 of the present embodiment will be described in detail. This pixel electrode 22
As shown in FIG. 2, the plurality of slits 22S are inclined in directions opposite to each other on the upper and lower sides around the center in the column direction of the sub-pixel region, thereby achieving dual domain. doing. The common wiring 17 is formed at the boundary between two domains, which is a region where normal image display cannot be performed, that is, at the center in the column direction of the sub-pixel region.
With such a configuration, a short circuit between the common wiring 17 and the scanning line 15 can be suppressed. Further, between the slits 22S of the pixel electrode 22, a strip-shaped pixel electrode portion 22 is provided.
A and 22B are formed. Here, in order to brighten the display, the width of each slit 22S is made wider than the width of the strip-shaped pixel electrode portion 22B existing between the common wiring 17 and the slit 22SB that does not overlap in plan view.

In the liquid crystal display panel 10 of the present embodiment, the strip-shaped pixel electrode portion 22A that overlaps the common wiring 17 in plan view is wider than the other strip-shaped pixel electrode portions 22B. That is, the shortest distance L1 between two adjacent slits 22SA across the strip-shaped pixel electrode portion 22A that overlaps the wide common wiring 17 in plan view is any two of the portions that do not overlap with the wide common wiring 17 in plan view. It is longer than the shortest distance L2 between adjacent slits 22SB. More specifically, in this example, L1 is about 1.5 times L2.

As described above, when the pixel electrode is formed by applying the photolithography method, the common wiring 1 is formed by forming the slit L1> L2 without forming the slit in the center of the sub-pixel region.
Even if the resist above 7 is excessively exposed, the other portions are normally exposed, so that the width of the band-like pixel electrode portions 22A to 22B is suppressed, and the adjacent slits 22SA to 22A are suppressed. 22SBs are not connected to each other. As a result, an increase in the electrical resistance value of the pixel electrode 22 is suppressed, so that an effect of enabling good image display is also produced. Note that the region where the wide common wiring 17 is formed is a region shielded by a black matrix or the like as a region which does not contribute to image display since it does not transmit light from the backlight. Even if no slit is formed above, there is no particular disadvantage.

In this example, an example is shown in which a part of the slit 22SA is also formed in the upper region of the wide common wiring 17; however, no slit is formed in the upper region of the common wiring 17 at all. May be. In this example, the slits are all formed in a bar shape, but there are various shapes such as a shape having a bent portion so that all the scanning lines 15 or signal lines 16 are “<”. Shapes can be applied. Furthermore, as an example of the slit arrangement, the inclination direction is inverted between the upper side and the lower side around the center in the column direction of the sub-pixel region. However, the slit may be inclined in only one direction. In some cases, the common wiring 17 may be arranged close to one side of the scanning line positioned above and below the subpixel in the column direction.

Next, with reference to FIG. 4, the manufacturing process of the liquid crystal display panel 10 of this embodiment is demonstrated. First, after forming a metal thin film having, for example, an Al / Mo two-layer structure over the entire surface of the first transparent substrate 14, a plurality of scanning lines 15 and a plurality of wide lines are formed by a photolithography method and an etching method. The common wiring 17 is formed so as to be parallel to each other as shown in FIG. 2 and so that the common wiring 17 is located at the center of the sub-pixel region. At this time, the scanning line 15
A part of the TFT is partially widened and extended to the vicinity of the intersection of the scanning line 15 and the signal line 16, thereby simultaneously forming the gate electrode G of the TFT (FIG. 4A).

Next, the entire surface of the substrate obtained by the above process is covered with a transparent conductive film made of, for example, ITO by a sputtering method, and a common electrode 18 serving as a lower electrode is formed by a photolithography method and an etching method (FIG. 4B). . The common electrode 18 is connected to the common wiring 17.
Are electrically connected to each other by a direct contact with the wide portion of the pixel, but are independent for each sub-pixel region so as not to be electrically connected to the scanning line 15 or the gate electrode G and to overlap the signal line 16 in plan view. It is formed as.

Next, the entire surface of the substrate obtained by the above process is covered with a gate insulating film 19 made of silicon nitride or silicon oxide by plasma CVD (FIG. 4C).

Subsequently, for example, amorphous silicon (hereinafter referred to as “a-Si”) is formed by plasma CVD.
" ) And the n ⁺ a-Si layer to be the ohmit layer are formed over the entire surface of the gate insulating film 19, and then the a-Si layer and the n ⁺ a-Si are formed in the TFT formation region by a photolithography method and an etching method. A semiconductor layer 20 composed of layers is formed (FIG. 4D).

Next, the entire surface of the substrate obtained by the above process is covered with a metal thin film having a three-layer structure of, for example, Mo / Al / Mo, and then the TFT is formed by photolithography and etching.
Source electrode S (part of signal line 16) and drain electrode D are formed (FIG. 4E). Both the source electrode S portion and the drain electrode D portion partially overlap the surface of the semiconductor layer 20, and the exposed region of the semiconductor layer 20 that is not covered between the two electrodes is the channel region T of the TFT.
FT-ch.

Next, the entire surface of the substrate obtained by the above process is coated with a passivation film 21 made of silicon nitride or silicon oxide by plasma CVD, and then the passivation film 21 in contact with the drain electrode D is plasma etched. A contact hole 21CH is formed to expose part of the drain electrode D (FIG. 4F).

Next, the entire surface of the substrate obtained by the above process is covered with a transparent conductive film 220 made of, for example, ITO by a sputtering method (FIG. 4G). Then, by the photolithography method and the etching method, as shown in FIG. 2, the strip-shaped pixel electrode portion 22A that overlaps the wide common wiring 17 in plan view becomes wider than the other strip-shaped pixel electrode portions 22B. A pixel electrode 22 having the same structure is formed (FIG. 4H). Note that such a wide band-like pixel electrode portion 22A can be easily formed by slightly making the pattern portion of the mask arranged in a region overlapping the common wiring 17 in a plan view during exposure slightly larger than usual. . At this time, the pixel electrode 22 is contacted with the contact hole 21 of the passivation film 21.
It is electrically connected to the drain electrode via CH.

Further, the array substrate AR is completed by forming a predetermined alignment film (not shown) over the entire surface. Then, the array substrate AR manufactured in this way and the separately manufactured color filter substrate CF are opposed to each other, the periphery is sealed with a sealing material, and liquid crystal is injected between the two substrates, whereby the FFS mode according to the embodiment is performed. The liquid crystal display panel 10 is obtained.

DESCRIPTION OF SYMBOLS 10 ... Liquid crystal display panel 11 ... Scanning line routing wiring 12 ... Signal line routing wiring 13
... Common routing wiring 14 ... First transparent substrate 15 ... Scanning line 16 ... Signal line 17 ... Common wiring 18 ... Common electrode 19 ... Gate insulating film 20 ... Semiconductor layer 21 ... Passivation film 21CH ... Contact hole 22 ... Pixel electrodes 22A, 22B ... Striped pixel electrode portion 22S, 22SA, 22SB ... Slit of pixel electrode 23 ... Second transparent substrate 24 ... Color filter layer 25 ... Black matrix 26 ... Top coat layer AR ... Array substrate LC ... Liquid crystal layer CF ... Color filter substrate DA ... Display area PF ... Frame area D
r ... Terminal for driver connection TP ... Terminal for external device connection

Claims (4)

A liquid crystal layer is sandwiched between the first transparent substrate and the second transparent substrate, and the liquid crystal layer side of the first transparent substrate is formed in different layers with an insulating film interposed therebetween, and the display area is divided into each sub-region. A plurality of signal lines and scanning lines partitioned into a pixel region; a plurality of common wirings formed in the same layer as the scanning line in parallel between the scanning lines; and an insulating film disposed in each sub-pixel region. A liquid crystal display panel comprising a common electrode formed on different layers and a pixel electrode formed with a plurality of slit-shaped openings,
The common wiring is disposed in a central portion of the sub-pixel region in a direction parallel to the signal line, and has a width in the sub-pixel region wider than a width of a portion intersecting the signal line in plan view. And
The pixel electrode is a band-like pixel electrode portion sandwiched by the slit-shaped openings, is adjacent to the common wiring in plan view, and is sandwiched by the slit-shaped openings partially overlapping the common wiring, and the common A first strip pixel electrode portion that overlaps the wiring in a plan view, and a second strip pixel electrode portion that does not overlap the common wiring in a plan view, and the width of the first strip pixel electrode portion is It is wider than the width of the second strip pixel electrode portion ,
Liquid crystal display panel. A plurality of slit-shaped opening formed in the pixel electrode are inclined in opposite directions as a boundary a central portion of the sub-pixel area in a direction parallel to said signal line,
The liquid crystal display panel according to claim 1. The shortest distance between two slit-shaped openings adjacent to each other across the first strip-shaped pixel electrode portion of the pixel electrode is the distance between two slit-shaped openings adjacent to each other across the second strip-shaped pixel electrode portion . 1.5 to 2 times ,
The liquid crystal display panel according to 請 Motomeko 1. In the pixel electrode, the width of the slit-shaped opening is wider than the width of the second strip-shaped pixel electrode portion.
  The liquid crystal display panel according to claim 1.

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