JP5452041B2 - Data processing device - Google Patents

Description

  The present invention relates to a data processing device (a logical operation circuit, a logical operation device, a CPU [Central Processing Unit], a MPU [Micro Processing Unit], a DSP [Digital Signal Processor], etc.) having a function of making data nonvolatile. , Personal computers using these, network servers, mobile devices, game machines, etc.).

  Conventionally, various techniques have been disclosed and proposed by the applicant of the present application for data processing devices having a function of making data nonvolatile (see, for example, Patent Document 1).

JP 2008-210358 A

  However, there are many problems to be examined in putting the conventional data processing apparatus into practical use.

  In view of the problem in putting a data processing device having a function of making data nonvolatile, the present invention is capable of restoring data read from a memory together with data restoration of an electronic circuit. An object is to provide a processing apparatus.

  In order to achieve the above object, a data processing apparatus according to the present invention includes an electronic circuit for handling register data, a control circuit for saving / restoring the register data, a memory used by the electronic circuit, A memory control circuit that controls access to the memory in response to an instruction. The control circuit checks an address output from the electronic circuit when the register data is restored, and stores the address in the address. The memory control circuit is instructed to read out the read data from the memory (first configuration).

  In the data processing device having the first configuration, the control circuit saves the register data when the data processing device or the electronic circuit is turned off, and the data processing device or the electronic circuit is turned on. At this time, it is preferable that the register data be restored (second configuration).

  In the data processing device having the second configuration, the control circuit performs a saving process of the register data and a power-off process of the electronic circuit using a wait instruction for the electronic circuit as a trigger, A configuration (third configuration) in which a power-on process of the electronic circuit and a return process of the register data are performed using a wait release instruction as a trigger is preferable.

  In the data processing apparatus having any one of the first to third configurations, the electronic circuit includes a volatile storage unit and a nonvolatile storage unit as means for holding the register data. A configuration that is a CPU (fourth configuration) is preferable.

  With the data processing apparatus according to the present invention, the data read from the memory can be restored together with the data restoration of the electronic circuit.

It is a typical block block diagram explaining the operation | movement principle of the data control apparatus which concerns on the 1st Embodiment of this invention. It is a typical operation | movement waveform diagram explaining the operation | movement principle of the data control apparatus which concerns on the 1st Embodiment of this invention. It is a typical block block diagram of the data control apparatus which concerns on the comparative example of the 1st Embodiment of this invention. It is a typical operation | movement waveform diagram of the data control apparatus which concerns on the comparative example of the 1st Embodiment of this invention. It is a typical block block diagram of the data control apparatus which concerns on the 1st Embodiment of this invention. 4 is an operation example of the data control apparatus according to the first embodiment of the present invention, and is an operation waveform of a primary power supply voltage VDD1, a secondary power supply voltage VDD2, a reset signal RSTn, a voltage level detection signal VDT, and a control signal CLS. FIG. FIG. 6 is a schematic block configuration diagram of a data control apparatus according to a second embodiment of the present invention, which executes data save / restore control. It is a state transition diagram explaining the operation | movement sequence of the data control apparatus which concerns on the 2nd Embodiment of this invention. FIG. 6 is an operation example of the data control apparatus according to the second embodiment of the present invention, which includes a primary power supply voltage VDD1, a secondary power supply voltage VDD2, a reset signal RSTn, a voltage level detection signal VDT, a data return control signal DSCS, and It is an operation | movement waveform diagram of the data saving control signal DRCS. FIG. 10 is a schematic block configuration diagram of a data control apparatus according to a third embodiment of the present invention, which is applicable to a nonvolatile CPU. It is a typical block structural example of the non-volatile CPU to which the data control device according to the third embodiment of the present invention is applied. 12 is a schematic circuit configuration example of a nonvolatile memory gate applied to the nonvolatile CPU shown in FIG. It is an operation | movement waveform of the data control apparatus which concerns on the 3rd Embodiment of this invention, Comprising: It is an operation | movement timing chart figure when controlling a non-volatile CPU. It is a block diagram showing one embodiment of a data processor concerning the present invention. It is a flowchart which shows an example of an initialization / data restoration process. It is a flowchart which shows an example of normal operation. It is a flowchart which shows an example of the data saving process at the time of a power supply fall. It is a timing chart (with initial reading) for demonstrating the effect | action of initial reading. 3 is a timing chart (without initial reading) for explaining the operation of initial reading. 6 is a timing chart for explaining data saving processing (mirroring processing) of the video memory 330;

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic and different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the embodiment described below exemplifies an apparatus and a method for embodying the technical idea of the present invention. The technical idea of the present invention is the arrangement of each component as described below. It is not something specific. The technical idea of the present invention can be variously modified within the scope of the claims.

[First Embodiment]
As shown in FIG. 1, the basic block configuration of the data control device 12 according to the first embodiment of the present invention includes a primary power supply line VDL1 to which a primary power supply voltage VDD1 is supplied, and a secondary power supply voltage. Power supply voltage conversion that is arranged between the secondary power supply line VDL2 to which VDD2 is supplied and between the primary power supply line VDL1 and the secondary power supply line VDL2 and converts the primary power supply voltage VDD1 to the secondary power supply voltage VDD2. And a detection / control unit 15 disposed between the primary power supply line VDL1 and the secondary power supply line VDL2. As shown in FIG. 1, the control target circuit 10 connected to the secondary power supply line VDL2 is also connected to the primary power supply line VDL1 via the detection / control unit 15.

  Here, in the case of the data control device 12 that uses two power sources including the primary power source voltage VDD1 and the secondary power source voltage VDD2, the control target circuit 10 that uses the power source of the secondary power source voltage VDD2 is Assume that the secondary side power supply voltage VDD2 ± 10% VDD2 can be operated.

  The operation of the data control device 12 shown in FIG. 1 is expressed as shown in FIG.

(A) In FIG. 2, before the power supply is turned off, the primary power supply voltage VDD1 and the secondary power supply voltage VDD2 (VDD2 <VDD1) are supplied to the primary power supply line VDL1 and the secondary power supply line VDL2, respectively. .

(B) Next, by the primary power supply voltage VDD1 supplied to the primary side power supply line VDL1 senses compared to power-off (power OFF) and VDD1 detection voltage level V _LV 1 level (90% VDD1) The primary side power supply voltage VDD1 is regarded as the power supply OFF. As shown in FIG. 2, the primary power supply voltage VDD1 supplied to the primary power supply line VDL1 drops with a predetermined time constant. On the other hand, the secondary power supply voltage VDD2 supplied to the secondary power supply line VDL2 drops with a predetermined time constant after a constant state is maintained.

(C) Next, the secondary-side power supply voltage VDD2 supplied to the secondary power supply line VDL2 is possible to detect the comparison to power-off (power OFF) and VDD2 detection voltage level V _LV 2 (90% VDD2) Thus, the secondary power supply voltage VDD2 is regarded as the power supply OFF, and the control target circuit 10 becomes inoperable.

When the primary side power supply voltage VDD1 becomes the VDD1 detection voltage level V _LV 1 and the primary side power supply voltage VDD1 is regarded as the power supply OFF, the secondary side power supply voltage VDD2 becomes the VDD2 detection voltage level V _LV 2 and the control target circuit 10 The period up to the point of time when the operation becomes impossible is a backup processable period TW1 such as data saving / restoring of the control target circuit 10 after the power-off detection.

According to the data control device of the first embodiment of the present invention, the primary power supply voltage VDD1 (VDD2 <VDD1) of another system whose supply voltage is higher than the secondary power supply voltage VDD2 is monitored, and the primary power supply voltage is monitored. By detecting the power supply interruption (power supply OFF) in comparison with the VDD1 detection voltage level V _LV 1, the power supply interruption can be detected before the secondary power supply voltage VDD2 of the secondary power supply line VDL2 drops. It becomes possible. Therefore, the processable period TW1 of the control target circuit 10 after detection of power-off can be set widely.

  On the other hand, the schematic block configuration of the data control device according to the comparative example of the first embodiment of the present invention includes a primary power supply line VDL1 to which a primary power supply voltage VDD1 is supplied, The secondary side power supply line VDL2 to which the secondary side power supply voltage VDD2 is supplied and the primary side power supply line VDL1 and the secondary side power supply line VDL2 are arranged to convert the primary side power supply voltage VDD1 to the secondary side power supply voltage VDD2. The voltage converter 4 is provided. As shown in FIG. 3, the control target circuit 3 connected to the secondary power supply line VDL2 is not connected to the primary power supply line VDL1.

  The operation of the data control apparatus shown in FIG. 3 is expressed as shown in FIG.

(A) In FIG. 3, before the power is turned off, the secondary power supply voltage VDD2 is supplied to the secondary power supply line VDL2. Similarly, the primary power supply voltage VDD1 is supplied to the primary power supply line VDL1.

(B) Next, the secondary-side power supply voltage VDD2 supplied to the secondary-side power supply line VDL2 detects a power shutdown (power OFF) as compared with the VDD2 detection voltage level V _LV 2 level (95% VDD2). Thus, the secondary side power supply voltage VDD2 is regarded as the power supply OFF. As shown in FIG. 4, the secondary power supply voltage VDD2 supplied to the secondary power supply line VDL2 drops with a predetermined time constant.

(C) Next, the secondary-side power supply voltage VDD2 supplied to the secondary power supply line VDL2 is, by detecting the to power-off compared to VDD2 detection voltage level _{V LV 2 (90% VDD2)} , the control target The circuit 3 becomes inoperable.

The secondary power supply voltage VDD2 becomes the VDD2 detection voltage level V _LV2 (95% VDD2), and from the point of time when the power supply is regarded as OFF, the VDD2 detection voltage level _VLV2 (90% VDD2) is reached. The period until the time when the operation becomes impossible is a backup processable period TW2 such as data saving / restoring of the control target circuit 3 after the power-off detection.

  As shown in FIG. 4, the operation of the data control apparatus according to the comparative example monitors only the secondary power supply voltage VDD2 of the secondary power supply line VDL2 to which the control target circuit 3 is connected, and detects power shutdown. That is, since the power-off is detected after the secondary-side power supply voltage VDD2 drops, the processable time TW2 after the power-off detection is short.

  When the power supply shutdown is detected by monitoring the voltage level of the primary power supply voltage VDD1 of another system, the detected voltage level is set lower than when the power supply shutdown is detected by monitoring the secondary power supply voltage VDD2. can do.

When monitoring the primary power supply voltage VDD1 of another system, as described above, the primary power supply voltage VDD1 detects the power supply cutoff (power OFF) compared to the VDD1 detection voltage level V _LV 1 level (90% VDD1). Thus, since the primary side power supply voltage VDD1 is regarded as the power supply OFF, the detection level is 90% of the normal operation voltage (VDD1).

  On the other hand, when the secondary power supply voltage VDD2 of the secondary power supply line VDL2 is monitored, as shown in FIG. 4, the detection level is 95% of the normal operating voltage (VDD2).

  Therefore, the data control apparatus according to the first embodiment of the present invention has a higher probability of absorbing power supply fluctuations than the comparative example.

(Detailed block configuration)
The data control apparatus 12 according to the first embodiment of the present invention includes a primary power supply line VDL1 to which a primary power supply voltage VDD1 is supplied and a secondary side as shown in FIG. A voltage that is arranged between the secondary power supply line VDL2 to which the power supply voltage VDD2 is supplied and the primary power supply line VDL1 and the secondary power supply line VDL2, and converts the primary power supply voltage VDD1 into the secondary power supply voltage VDD2. A conversion unit 14, a voltage level detection unit 18 connected to the primary power supply line VDL1 and outputting the voltage level detection signal VDT, and a reset signal generation unit 16 connected to the secondary power supply line VDL2 and outputting the reset signal RSTn. When receiving the voltage level detection signal VDT from the voltage level detection unit 18 and the reset signal RSTn from the reset signal generation unit 16, the control signal is generated to output the control signal CLS. And a section 20.

  As shown in FIG. 5, the control target circuit 10 is connected to the secondary power supply line VDL2, and the reset signal RSTn is received from the reset signal generator 16 in the data control device 12, and the control signal CLS is sent from the control signal generator 20. Receiving.

  In FIG. 5, capacitors C1 and C2 are parasitic capacitors included in the primary power supply line VDL1 and the secondary power supply line VDL2, respectively.

(Operation timing chart)
FIG. 6 shows an operation example of the data control apparatus shown in FIG. In FIG. 6, power supply fluctuation waveforms of the primary power supply voltage VDD1 and the secondary power supply voltage VDD2 are shown, and further, the reset signal RSTn, the voltage level detection signal VDT, and the control signal CLS corresponding to these power supply fluctuation waveforms. The operation waveforms are respectively shown.

(A) First, during the period from time t0 to time t1, the power supply is in an off state. The negative logic reset signal RSTn is on, the voltage level detection signal VDT is off, and the control signal CLS is on standby.

(B) Next, at time t1, the power is turned on.

(C) Next, during the period from time t1 to time t2, the operation waveforms of the primary power supply voltage VDD1 and the secondary power supply voltage VDD2 rise, and the value of the secondary power supply voltage VDD2 becomes the reset voltage level _VRST . When reaching, the reset signal RSTn is turned off.

(D) Next, at time t2, when the value of the primary power supply voltage VDD1 reaches the VDD1 detection voltage level V _LV 1, the voltage level detection signal VDT is turned on.

(E) Next, in the period from time t2 to time t3, both the primary power supply voltage VDD1 and the secondary power supply voltage VDD2 are kept on. Immediately after time t2, the control signal CLS is turned on from the standby state, and the control signal CLS is output from the control signal generator 20 to the control target circuit 10. Thereafter, the standby state is maintained.

(F) Next, in a period of time t3 to t4, the value of the primary power supply voltage VDD1 is lower than VDD1 detection voltage level V _LV 1, also decreases the value of the secondary-side power supply voltage VDD2, and the reset voltage level If higher than V _RST is a reset signal RSTn is maintained in the oFF state, the voltage level detection signal VDT is turned off. The control signal CLS is kept in a standby state.

(G) Next, in a period of time t4 to t5, the value of the primary power supply voltage VDD1 is higher than VDD1 detection voltage level V _LV 1, and also increases the value of the secondary-side power supply voltage VDD2, the reset voltage level If higher than V _RST is a reset signal RSTn is maintained in the oFF state, the voltage level detection signal VDT is turned on. The control signal CLS is kept in a standby state.

(H) In a period of time t5 to t6, when the value of the primary power supply voltage VDD1 is lower than VDD1 detection voltage level V _LV 1, the voltage level detection signal VDT is turned off. The control signal CLS is turned on, and the control signal CLS is output from the control signal generator 20 to the control target circuit 10. Thereafter, the standby state is maintained.

Further decreases the value of the primary power supply voltage VDD 1, the value of the secondary-side power supply voltage VDD2 is to be lower than the reset voltage level V _RST, the reset signal RSTn are turned on.

Furthermore, the primary power supply voltage VDD1 rises, if the value of the secondary-side power supply voltage VDD2 is higher than the reset voltage level V _RST, the reset signal RSTn are turned off.

Furthermore, the increase in the primary power supply voltage VDD1, if higher than VDD1 detection voltage level V _LV 1, the reset signal RSTn the OFF state is maintained, the voltage level detection signal VDT is turned on.

(I) Next, during the period from time t6 to time t7, both the primary power supply voltage VDD1 and the secondary power supply voltage VDD2 are kept on. Immediately after time t6, the control signal CLS is turned on from the standby state, and the control signal CLS is output from the control signal generator 20 to the control target circuit 10. Thereafter, the standby state is maintained.

(J) Next, at time t7, the power is turned off.

(K) Next, during the period from time t7 to time t8, the operation waveform of the primary power supply voltage VDD1 drops, while the operation waveform of the secondary power supply voltage VDD2 holds a substantially constant value.

(L) Next, when the value of the primary power supply voltage VDD1 reaches the VDD1 detection voltage level V _LV 1 at time t8, the reset signal RSTn is maintained in the off state, but the voltage level detection signal VDT is in the off state. .

(M) Next, in the period from time t8 to time t9, the primary power supply voltage VDD1 drops with a predetermined time constant as shown in FIG. On the other hand, the secondary power supply voltage VDD2 drops with a predetermined time constant after a constant state is maintained. Immediately after time t8, the control signal CLS is turned on from the standby state, and the control signal CLS is output from the control signal generator 20 to the control target circuit 10.

(N) Next, at time t9, the secondary power supply voltage VDD2 reaches the reset voltage level V _RST and detects power shutoff (power OFF), so that the control target circuit 10 becomes inoperable. . At the same time, the reset signal RSTn is turned on, the voltage level detection signal VDT is kept off, and the control signal CLS is in a standby state.

  According to the data control device of the first embodiment of the present invention, when applied to a control target circuit system having two power supply lines, the time constant due to the capacitor of the power supply line is not used. The capacity of the capacitor for securing the voltage after the interruption can be reduced.

  In addition, according to the data control device of the first embodiment of the present invention, even when the value of the power supply voltage fluctuates due to noise on the power supply line or the like, useless backup processing (data save / restore) is suppressed. be able to.

[Second Embodiment]
(Data control device)
The data control apparatus 12 according to the second embodiment of the present invention, which executes the data saving / restoring control operation, is supplied with the primary power supply voltage VDD1 as shown in FIG. Are arranged between the primary power supply line VDL1, the secondary power supply line VDL2 to which the secondary power supply voltage VDD2 is supplied, and the primary power supply line VDL1 and the secondary power supply line VDL2. A voltage conversion unit 14 for converting to the secondary power supply voltage VDD2, a voltage level detection unit 18 for outputting the voltage level detection signal VDT connected to the primary power supply line VDL1, and a secondary power supply line VDL2, and a reset signal. The reset signal generation unit 16 that outputs RSTn, the voltage level detection signal VDT from the voltage level detection unit 18, and the reset signal RSTn from the reset signal generation unit 16 are received. And a control signal generating unit 20 for outputting the data saving control signal DRCS and the data recovery control signal DSCS.

  As shown in FIG. 7, a control target circuit 30 is connected to the secondary power supply line VDL2, and the reset signal RSTn is received from the reset signal generator 16 in the data control device 12, and the data saving control signal is sent from the control signal generator 20. The DRCS and data return control signal DSCS are received.

  As illustrated in FIG. 7, the control target circuit 30 includes a main operation unit 32, a nonvolatile storage unit 36, and a data interface control unit 34 between the main operation unit 32 and the nonvolatile storage unit 36.

  As shown in FIG. 7, the main operation unit 32, the data interface control unit 34, and the nonvolatile storage unit 36 in the control target circuit 30 receive the reset signal RSTn from the reset signal generation unit 16 in the data control device 12. In addition, the data interface control unit 34 receives the data save control signal DRCS and the data return control signal DSCS from the control signal generation unit 20.

  In FIG. 7, capacitors C1 and C2 are parasitic capacitors included in the primary power supply line VDL1 and the secondary power supply line VDL2, respectively.

(Operation sequence of data controller)
The operation sequence of the data control apparatus 12 according to the second embodiment of the present invention will be described with reference to the state transition diagram shown in FIG.

  The reset state S1 indicates a state in which the data control device 12 is held in the reset state and is not operating.

The power recovery waiting state S2 indicates a state of waiting until the primary power supply voltage VDD1 reaches a predetermined threshold voltage Vth1 (for example, VDD1 detection voltage level V _LV 1).

  The data return signal output state S3 is a state in which the data return control signal DSCS is transmitted from the data control device 12 to the control target circuit 30 and data is returned from the nonvolatile storage unit 36 in the control target circuit 30. Show.

The power supply monitoring state S4 indicates a state where the primary side power supply voltage VDD1 is checked by checking whether or not it is at a level lower than a predetermined threshold voltage Vth1 (for example, VDD1 detection voltage level _VLV1 ).

  The data save signal output state S5 is a state where the data save control signal DRCS is transmitted from the data control device 12 to the control target circuit 30 and the data is saved in the nonvolatile storage unit 36 in the control target circuit 30. Show.

―Operation sequence―
(A) First, when the reset signal RSTn is turned off as indicated by RSTn = “1” in the reset state S1, the state transitions from the reset state S1 to the power recovery waiting state S2.

(B) Next, when the reset signal RSTn is turned on as indicated by RSTn = “0” in the power recovery wait state S2, the state transitions from the power recovery wait state S2 to the reset state S1.

(C) Next, in the power recovery waiting state S2, when the voltage level detection signal VDT is turned on as indicated by VDT = “1”, the state transitions from the power recovery waiting state S2 to the data recovery signal output state S3. To do.

(D) Next, state transition is made from the data return signal output state S3 to the power monitoring state S4.

(E) Next, in the power monitoring state S4, when the voltage level detection signal VDT is turned off as indicated by VDT = "0", the state transitions from the power monitoring state S4 to the data save signal output state S5.

(F) Next, the state transition is made from the data saving signal output state S5 to the power recovery waiting state S6.

(G) Next, in the power recovery waiting state S6, when the voltage level detection signal VDT is turned on as indicated by VDT = "1", the state transitions from the power recovery waiting state S6 to the data save signal output state S5. To do.

(H) Next, when the reset signal RSTn is turned off in the power recovery waiting state S6 as indicated by RSTn = “0”, the state transitions from the power recovery waiting state S6 to the reset state S1.

(Operation timing chart)
FIG. 9 shows an operation example of the data control device 12 shown in FIG. In FIG. 9, power supply fluctuation waveforms of the primary power supply voltage VDD1 and the secondary power supply voltage VDD2 are shown, and further, the reset signal RSTn, the voltage level detection signal VDT, and the data recovery control corresponding to these power supply fluctuation waveforms. Operation waveforms of the signal DSCS and the data save control signal DRCS are shown.

(A) First, during the period from time t0 to time t1, the power supply is in an off state. The negative logic reset signal RSTn is in the on state, the voltage level detection signal VDT is in the off state, and the data save control signal DRCS and the data return control signal DSCS are in the off state.

(B) Next, at time t1, the power is turned on.

(C) Next, during the period from time t1 to time t2, the operation waveforms of the primary power supply voltage VDD1 and the secondary power supply voltage VDD2 rise, and the value of the secondary power supply voltage VDD2 becomes the reset voltage level _VRST . When reaching, the reset signal RSTn is turned off.

(D) Next, at time t2, when the value of the primary power supply voltage VDD1 reaches the VDD1 detection voltage level V _LV 1, the voltage level detection signal VDT is turned on.

(E) Next, in the period from time t2 to time t3, both the primary power supply voltage VDD1 and the secondary power supply voltage VDD2 are kept on. Immediately after time t2, the data return control signal DSCS changes from the OFF state to the ON state, and the data return control signal DSCS is output from the control signal generation unit 20 to the data interface control unit 34 of the control target circuit 30. Thereafter, the off state is maintained.

(F) Next, in a period of time t3 to t4, the value of the primary power supply voltage VDD1 is lower than VDD1 detection voltage level V _LV 1, and also decreases the value of the secondary-side power supply voltage VDD2, the reset voltage level If higher than V _RST is a reset signal RSTn is maintained in the oFF state, the voltage level detection signal VDT is turned off. The data recovery control signal DSCS is kept off.

(G) Next, in a period of time t4 to t5, the value of the primary power supply voltage VDD1 is higher than VDD1 detection voltage level V _LV 1, and also increases the value of the secondary-side power supply voltage VDD2, the reset voltage level If higher than V _RST is a reset signal RSTn is maintained in the oFF state, the voltage level detection signal VDT is turned on. Data save control signal DRCS and data return control signal DSCS are in the off state.

(H) In a period of time t5 to t6, when the value of the primary power supply voltage VDD1 is lower than VDD1 detection voltage level V _LV 1, the voltage level detection signal VDT is turned off. Here, the data save control signal DRCS is turned on, and the data save control signal DRCS is output from the control signal generator 20 to the data interface controller 34 of the control target circuit 30. Thereafter, the off state is maintained.

Further decreases the value of the primary power supply voltage VDD 1, the value of the secondary-side power supply voltage VDD2 is to be lower than the reset voltage level V _RST, the reset signal RSTn are turned on.

Further, to rise the primary power supply voltage VDD 1, when the secondary power supply voltage VDD2 is higher than the reset voltage level V _RST, the reset signal RSTn are turned off.

Furthermore, the increase in the primary power supply voltage VDD1, if higher than VDD1 detection voltage level V _LV 1, the reset signal RSTn the OFF state is maintained, the voltage level detection signal VDT is turned on.

(I) Next, during the period from time t6 to time t7, both the primary power supply voltage VDD1 and the secondary power supply voltage VDD2 are kept on. Immediately after time t6, the data return control signal DSCS changes from the OFF state to the ON state, and the data return control signal DSCS is output from the control signal generation unit 20 to the data interface control unit 34 of the control target circuit 30. Thereafter, the off state is maintained.

(J) Next, at time t7, the power is turned off.

(K) Next, during the period from time t7 to time t8, the operation waveform of the primary power supply voltage VDD1 drops, while the operation waveform of the secondary power supply voltage VDD2 is maintained at a substantially constant value.

(L) Next, when the value of the primary power supply voltage VDD1 reaches the VDD1 detection voltage level V _LV 1 at time t8, the reset signal RSTn is maintained in the off state, but the voltage level detection signal VDT is in the off state. .

(M) Next, in the period from time t8 to time t9, the primary power supply voltage VDD1 drops with a predetermined time constant as shown in FIG. On the other hand, the secondary power supply voltage VDD2 drops with a predetermined time constant after a constant state is maintained. Immediately after time t8, the data save control signal DRCS changes from the OFF state to the ON state, and the data save control signal DRCS is output from the control signal generation unit 20 to the data interface control unit 34 of the control target circuit 30.

(N) Next, at time t9, when the secondary power supply voltage VDD2 reaches the reset voltage level _VRST and detects power shutdown (power OFF), the secondary power supply voltage VDD2 is turned off. Therefore, the control target circuit 30 becomes inoperable. At the same time, the reset signal RSTn is turned on, the voltage level detection signal VDT is kept in the off state, and both the data saving control signal DRCS and the data return control signal DSCS are turned off.

During power restoration, it monitors the voltage level of the primary power supply voltage VDD1, compared the primary power supply voltage VDD1 is the VDD1 detection voltage level V _LV 1, detects that it is now VDD1> V _LV 1, Detects power recovery status. As a result, the data control device 12 outputs the data return control signal DSCS to the data interface control unit 34 of the control target circuit 30. In the above case, the power supply monitoring of the secondary power supply voltage VDD2 is applied only to the reset signal generator 16 of the data control device 12 that is supplied with power from the secondary power supply voltage VDD2.

  According to the data control device of the second embodiment of the present invention, when a power-off / on is detected and a signal for requesting data backup (data save / restore) is output, sufficient backup processing is performed. Can be secured.

  In addition, according to the data control device of the second embodiment of the present invention, when applied to a control target circuit system having two power supply lines, the time constant due to the capacitor of the power supply line is not used. The capacity of the capacitor for securing the voltage after the power supply is cut off can be reduced.

  Further, according to the data control device of the second embodiment of the present invention, even when the value of the power supply voltage fluctuates due to noise on the power supply line or the like, useless backup processing (data save / restore) is suppressed. be able to.

[Third Embodiment]
(Data control device)
As shown in FIG. 10, the data control device 12 according to the third embodiment of the present invention, which controls the nonvolatile CPU 40, is supplied with the primary power supply voltage VDD1. The power supply line VDL1, the secondary power supply line VDL2 supplied with the secondary power supply voltage VDD2, and the primary power supply line VDL1 and the secondary power supply line VDL2 are arranged between the primary power supply voltage VDD1 and the secondary power supply voltage VDD1. A voltage conversion unit 14 that converts the power supply voltage VDD2 to the primary power supply line VDL1, a voltage level detection unit 18 that outputs the voltage level detection signal VDT, and a secondary power supply line VDL2 that are connected to the reset signal RSTn. A reset signal generator 16 for outputting a voltage, a voltage level detection signal VDT from the voltage level detector 18, and a reset signal RSTn from the reset signal generator 16. And a signal generator 20.

  The control signal generator 20 outputs a ferroelectric element write signal E1, a normal operation signal E2, a ferroelectric element both-ends short circuit signal FRST, and ferroelectric element driving signals PL1 and PL2 to the nonvolatile CPU 40. . The clock enable signal CLKEN output from the control signal generator 20 and the output signal from the clock generator 42 are input to the AND gate 44, and the output signal of the AND gate 44 is input to the nonvolatile CPU 40.

  As shown in FIG. 10, the non-volatile CPU 40 is connected to the secondary power supply line VDL2, and the reset signal RSTn from the reset signal generator 16 in the data control device 12 and the ferroelectric element from the control signal generator 20 are connected. A write signal E1, a normal operation signal E2, a ferroelectric element both-ends short circuit signal FRST, and ferroelectric element driving signals PL1 and PL2 are received. The nonvolatile CPU 40 receives the clock signal CLK via the AND gate 44.

  In FIG. 10, capacitors C1 and C2 are parasitic capacitors included in the primary power supply line VDL1 and the secondary power supply line VDL2, respectively.

(Configuration example of non-volatile CPU)
A schematic block configuration of a nonvolatile CPU 40 to which a data control device according to the third embodiment of the present invention is applied is connected to an instruction processing unit 102 and an instruction processing unit 102 as shown in FIG. An arithmetic processing unit 110 that receives an arithmetic control signal ACS from the unit 102, an arithmetic result storage unit 104 that is connected to the arithmetic processing unit 110 and receives an arithmetic output signal z from the arithmetic processing unit 110, an arithmetic result storage unit 104, and an instruction The switch block 106 connected to the processing unit 102 and supplying the output signal a to the arithmetic processing unit 110, and connected to the switch block 106 and the command processing unit 102, receives the switch control signal SCS from the command processing unit 102, and outputs the output signal and a switch block 108 for supplying b to the arithmetic processing unit 110.

  A program / data input terminal 112 a is connected to the instruction processing unit 102 via the program / data input / output line 112, and a program / data output terminal 112 b is connected to the switch block 108.

  Further, as shown in FIG. 11, a control signal input terminal 114 b and a control signal output terminal 114 a are connected to the nonvolatile CPU 40 via a control signal input / output line 114.

  Further, as shown in FIG. 11, the clock signal CLK is supplied to the nonvolatile CPU 40 via the clock control terminal 92, and the ferroelectric CPU 40 receives the ferroelectric via the nonvolatile operation control terminal 94 connected to the nonvolatile operation control line 100. The body element write signal E1, the normal operation signal E2, the ferroelectric element driving signals PL1 and PL2, and the ferroelectric element both-end short circuit signal FRST are supplied.

  As shown in FIG. 11, the instruction processing unit 102 includes a logic circuit block 58 having a nonvolatile storage gate 50, and the operation result storage unit 104 includes a logic circuit block 54 having a nonvolatile storage gate 50, The arithmetic processing unit 110 includes a logic circuit block 56 having a nonvolatile storage gate 50.

(Configuration example of nonvolatile memory gate)
As shown in FIG. 12, the configuration example of the nonvolatile storage gate 50 applicable to the nonvolatile CPU 40 to be controlled by the data control apparatus according to the third embodiment of the present invention includes the first and second nonvolatile memories. Data storage units (NVSE) 36 ₁ , 36 ₂ and a first non-volatile storage unit 36 ₁ arranged adjacent to the first non-volatile storage unit 36 ₁ and the first non-volatile storage unit 36. The _first data interface control unit 34 ₁ that receives an external control signal for reading data from 36 ₁ and the second non-volatile storage unit 36 ₂ are arranged adjacent to each other, and the second non-volatile storage unit 36 a second data interface control unit 34 ₂ for receiving an external control signal for reading data from the data writing and the second nonvolatile storage unit 36 ₂ to _2, the first data interface control unit 34 ₁ and the second 2 Over data interface control unit 34 ₂ is disposed adjacent to, the data input signal from the data input terminal D, receives a clock signal CLK from the clock input terminal, a volatile storage unit for outputting the data output signal Q from the data output terminal ( VSE) 35.

As shown in FIG. 12, the first non-volatile storage unit (NVSE) 36 ₁ is provided with MOS transistors Q1a, and Q1b, ferroelectric capacitor 51a, and 51b, the second non-volatile storage unit (NVSE) 36 ₂ includes MOS transistors Q2a and Q2b and ferroelectric capacitors 52a and 52b.

  As shown in FIG. 12, the volatile storage unit (VSE) 35 includes inverters 60, 61, 64, 70, 72, 74, path switches 62, 66, 68, and multiplexers 84, 86.

As shown in FIG. 12, the first data interface control unit 34 ₁ includes an inverter 76, and a path switch 78, a second data interface control unit 34 _2, an inverter 80, and a path switch 82.

  The input end of the inverter 61 is connected to the application end of the data input signal D. The output end of the inverter 61 is connected to the input end of the inverter 60. The output terminal of the inverter 60 is connected to the first input terminal (1) of the multiplexer 84 via the path switch 66. Further, the output end of the inverter 60 is connected to the input end of the inverter 64, and the output end of the inverter 64 is connected to the input end of the inverter 60 via the path switch 62.

  The output terminal of the multiplexer 84 is connected to the input terminal of the inverter 72. The output terminal of the inverter 72 is connected to the input terminal of the inverter 74. The output terminal of the inverter 74 is connected to the data output signal Q extraction terminal. The first input terminal (1) of the multiplexer 86 is connected to the output terminal of the inverter 72. The output terminal of the multiplexer 86 is connected to the input terminal of the inverter 70. The output terminal of the inverter 70 is connected to the first input terminal (1) of the multiplexer 84 via the path switch 68.

  As described above, the nonvolatile storage gate 50 holds the input data input signal D using two logic gates (inverters 72 and 70 in FIG. 12) connected in a loop as shown in FIG. A volatile storage unit (VSE) 35 having a loop structure portion LOOP (portion surrounded by 84, 72, 86, and 70 in the figure) is provided.

  The input terminal of the inverter 76 is connected to the first input terminal (1) of the multiplexer 84. The output terminal of the inverter 76 is connected to the second input terminal (0) of the multiplexer 86 via the path switch 78. The input end of the inverter 80 is connected to the first input end (1) of the multiplexer 86. The output terminal of the inverter 80 is connected to the second input terminal (0) of the multiplexer 84 via the path switch 82.

  The positive end of the ferroelectric capacitor 51a is connected to the first plate line, and is supplied with a ferroelectric element driving signal PL1. The negative terminal of the ferroelectric capacitor 51 a is connected to the second input terminal (0) of the multiplexer 86. A MOS transistor Q1a is connected between both ends of the ferroelectric capacitor 51a. The gate of the MOS transistor Q1a is connected to the application terminal of the ferroelectric element both-ends short circuit signal FRST.

  The positive terminal of the ferroelectric capacitor 51 b is connected to the second input terminal (0) of the multiplexer 86. The negative end of the ferroelectric capacitor 51b is connected to the second plate line, and the ferroelectric element driving signal PL2 is supplied. A MOS transistor Q1b is connected between both ends of the ferroelectric capacitor 51b. The gate of the MOS transistor Q1b is connected to the application terminal of the ferroelectric element both-ends short circuit signal FRST.

  The positive end of the ferroelectric capacitor 52a is connected to the first plate line and supplied with a ferroelectric element driving signal PL1. The negative electrode terminal of the ferroelectric capacitor 52 a is connected to the second input terminal (0) of the multiplexer 84. A MOS transistor Q2a is connected between both ends of the ferroelectric capacitor 52a. The gate of the MOS transistor Q2a is connected to the application terminal of the ferroelectric element both-ends short circuit signal FRST.

  The positive terminal of the ferroelectric capacitor 52 b is connected to the second input terminal (0) of the multiplexer 84. The negative electrode end of the ferroelectric capacitor 52b is connected to the second plate line and supplied with a ferroelectric element driving signal PL2. A MOS transistor Q2b is connected between both ends of the ferroelectric capacitor 52b. The gate of the MOS transistor Q2b is connected to the application terminal of the ferroelectric element both-ends short circuit signal FRST.

  Of the above components, the path switches 62 and 66 are turned on / off in response to the clock signal CLK, and the path switch 68 is turned on / off in response to the inverted clock signal CLKB (logically inverted signal of the clock signal CLK). Turned off. That is, the path switches 62 and 66 and the path switch 68 are turned on / off exclusively (complementarily). On the other hand, both the pass switches 78 and 82 are turned on / off in response to the ferroelectric element write signal E1. In addition, the signal paths of the multiplexers 84 and 86 are switched according to the normal operation signal E2.

  In the configuration example of the nonvolatile memory gate 50 shown in FIG. 12, a data write driver (inverters 76 and 80) and multiplexers 84 and 86 are newly required. Since the area occupied by the nonvolatile storage gate 50 in the unit 110 and the calculation result storage unit 104 is only a few percent, the area increase on the entire nonvolatile CPU 40 is hardly affected.

(Operation timing chart when controlling non-volatile CPU)
FIG. 13 shows an operation timing chart of the data control apparatus according to the third embodiment of the present invention, which is an operation timing chart when the nonvolatile CPU 40 is controlled. In FIG. 13, the power supply fluctuation waveforms of the primary power supply voltage VDD1 and the secondary power supply voltage VDD2 are shown. Further, in response to these power supply fluctuation waveforms, the reset signal RSTn, the voltage level detection signal VDT, the clock signal CLK, Clock enable signal CLKEN, ferroelectric element write signal E1, normal operation signal E2, ferroelectric element both-end short circuit signal FRST, ferroelectric element driving signals PL1 and PL2, volatile data signal VSEDATA, and nonvolatile data signal NVSEDATA It is shown.

  In the following description, as shown in FIG. 12, the voltage appearing at the connection node of the ferroelectric capacitors 51a and 51b is V1, the voltage appearing at the connection node of the ferroelectric capacitors 52a and 52b is V2, and the input terminal of the inverter 70 is shown. The voltage that appears is V3, the voltage that appears at the output terminal of the inverter 70 is V4, the voltage that appears at the input terminal of the inverter 72 is V5, and the voltage that appears at the output terminal of the inverter 72 is V6.

―Normal operation―
First, normal operation will be described.

(A) The power supply is in an on state during a period T1 from time t0 to time t1 up to time W1. The negative logic reset signal RSTn is off and the voltage level detection signal VDT is on. When the power is turned off at a predetermined time t01 within the time t0 to the time t1, the primary power supply voltage VDD1 drops with a predetermined time constant, but the secondary power supply voltage VDD2 remains constant. is there.

  The nonvolatile CPU 40 is in a normal operation state. The ferroelectric element both-ends short circuit signal FRST is set to “H (high level)”, the MOS transistors Q1a, Q1b, Q2a, and Q2b are turned on, and between both ends of the ferroelectric capacitors 51a, 51b, 52a, and 52b. Are short-circuited, so that no voltage is applied to these ferroelectric capacitors 51a, 51b, 52a, 52b. The ferroelectric element driving signals PL1 and PL2 applied to the first plate line and the second plate line are both “L (low level)”.

  Further, until the time point W1, since the ferroelectric element write signal E1 is “L” and the path switch 78 and the path switch 82 are turned off, the data write driver (inverter 76, in the example of FIG. 12). 82) are all invalid.

  Further, until the time point W1, the normal operation signal E2 is set to “H”, and the multiplexer 84 and the first input terminal (1) of the multiplexer 86 are selected, so that the loop structure portion LOOP (84, A normal loop is formed at a portion surrounded by 72, 86, and 70).

  In the volatile memory unit 35, when the clock signal CLK is at a high level, the inverter 61 is turned off, the path switch 62 is turned on, the path switch 66 is turned on, and the path switch 68 is turned off. Therefore, in the loop composed of the inverter 60 and the inverter 64, the captured data input signal D is held when the clock signal CLK is switched from the low level to the high level. Then, in the loop structure section (84, 72, 86, 70), the data is passed as it is, and the data output signal Q is output from the volatile storage section 35.

  On the other hand, when the clock signal CLK is at the low level, the loop structure portion (84, 72, 86, 70) holds the data input signal D that is captured when the clock signal CLK is switched from the high level to the low level. A data output signal Q is output.

―Data save operation to ferroelectric device―
Next, the data saving operation to the ferroelectric element will be described.

(B) When the value of the primary power supply voltage VDD1 reaches the VDD1 detection voltage level V _LV 1 at time t1, the voltage level detection signal VDT is turned off. The reset signal RSTn is kept on.

(C) In the period T2 from the time points W1 to W3 indicated by the times t1 to t3 and the period T3 from the time points W3 to W4 indicated by the times t3 to t4, the nonvolatile CPU 40 is in the data saving state, and the nonvolatile memory gate 50 A data write operation to the ferroelectric element is performed.

  The clock signal CLK is set to “L” and the inverted clock signal CLKB is set to “H”. Accordingly, the path switch 66 is turned off and the path switch 68 is turned on.

In particular, data writing from the volatile storage unit (VSE) 35 to the non-volatile storage units (NVSE) 36 ₁ and 36 ₂ is executed in the period of time points W2 to W3 indicated by times t2 to t3. This data write operation is indicated by an arrow A from the volatile data signal VSEDATA to the nonvolatile data signal NVSEDATA.

  At time points W1 to W3, the ferroelectric element both-end short circuit signal FRST is set to “L”, the MOS transistors Q1a, Q1b, Q2a, Q2b are turned off, and the voltages to the ferroelectric capacitors 51a, 51b, 52a, 52b are turned on. Application is possible.

  At time points W1 to W3, the ferroelectric element write signal E1 is set to “H”, and the path switch 78 and the path switch 82 are turned on. Therefore, both the data write drivers (inverters 76 and 82 in the example of FIG. 12) are validated.

  At the time points W1 to W3, the normal operation signal E2 is set to “H” and the first input terminal (1) of the multiplexer 84 and the multiplexer 86 is selected as before, so that the loop structure unit A normal loop is formed at LOOP (portion surrounded by 84, 72, 86, and 70 in the figure).

  At time points W1 to W2, the ferroelectric element driving signal PL1 applied to the first plate line and the ferroelectric element driving signal PL2 applied to the second plate line are set to “L”, and the time points W2 to W2 are set. In W3, the ferroelectric element driving signals PL1 and PL2 are set to “H”. That is, the same pulse voltage is applied to the first plate line and the second plate line. By applying such a pulse voltage, the remanent polarization state inside the ferroelectric capacitor is set to either the inversion state or the non-inversion state.

  More specifically, referring to the example of FIG. 12, since the output signal Q is “H” at the time point W1, the node voltage V1 becomes “L” and the node voltage V2 becomes “H”. Therefore, at time points W1 to W2, while the ferroelectric element driving signal PL1 applied to the first plate line and the ferroelectric element driving signal PL2 applied to the second plate line are set to “L”. In this state, no voltage is applied across the ferroelectric capacitors 51a and 51b, and a negative voltage is applied across the ferroelectric capacitor 52a. Is in a state where a positive voltage is applied.

  On the other hand, at time points W2 to W3, while the ferroelectric element driving signal PL1 applied to the first plate line and the ferroelectric element driving signal PL2 applied to the second plate line are set to “H”. In this state, no voltage is applied across the ferroelectric capacitors 52a and 52b, and a positive voltage is applied across the ferroelectric capacitor 51a, and between the both ends of the ferroelectric capacitor 51b. Is in a state where a negative voltage is applied.

  As described above, by applying the pulse voltage to the first plate line and the second plate line, the remanent polarization state inside the ferroelectric element is set to either the inversion state or the non-inversion state. Note that the remanent polarization state is opposite between the ferroelectric capacitors 51a and 51b and between the ferroelectric capacitors 52a and 52b. Also, the remanent polarization state is reversed between the ferroelectric capacitors 51a and 52a and between the ferroelectric capacitors 51b and 52b.

(D) In a period T3 from time points W3 to W4 indicated by time points t3 to t4, the power supply is waiting to be cut off. At the time point W3, the ferroelectric element both-ends short circuit signal FRST is set to “1” again, the MOS transistors Q1a, Q1b, Q2a, and Q2b are turned on, and between the both ends of the ferroelectric capacitors 51a, 51b, 52a, and 52b. Since both are short-circuited, no voltage is applied to these ferroelectric capacitors 51a, 51b, 52a, 52b. At this time, both the ferroelectric element driving signal PL1 applied to the first plate line and the ferroelectric element driving signal PL2 applied to the second plate line are set to “L”.

  At time W3, the ferroelectric element write signal E1 is set to “L” again, and the path switch 78 and the path switch 82 are turned off, so that the data write driver (inverters 76 and 80 in the example of FIG. 12) Both are invalid. The normal operation signal E2 is not questioned, but is “L” in the example of FIG.

(E) Next, in a period T4 between time points W4 and W6 indicated by time points t4 to t6, the power supply is cut off. That is, at the time point W4 indicated by time t4, the secondary power supply voltage VDD2 reaches the reset voltage level _VRST . Further, when the value of the primary power supply voltage VDD1 decreases and the value of the secondary power supply voltage VDD2 becomes lower than the reset voltage level _VRST , the nonvolatile CPU 40 enters a power shut-off state. The negative logic reset signal RSTn is on, the voltage level detection signal VDT is off, the ferroelectric element write signal E1, the normal operation signal E2, and the ferroelectric element driving signals PL1 and PL2 are off. In particular, at a predetermined time t41 within the time t4 to t5, the nonvolatile CPU 40 connected to the secondary power supply line VDL2 is turned off, and during the period from the time t41 to t42, the nonvolatile CPU 40 is turned off. .

  The ferroelectric element both-ends short circuit signal FRST is maintained at “H” from the time point W3, the MOS transistors Q1a, Q1b, Q2a, Q2b are turned on, and between the both ends of the ferroelectric capacitors 51a, 51b, 52a, 52b. Are short-circuited. Therefore, since no voltage is applied to the ferroelectric capacitors 51a, 51b, 52a, 52b, the ferroelectric capacitors 51a, 51b, 52a, An unintended voltage is not applied to 52b, and garbled data can be avoided.

-Data recovery operation from ferroelectric elements-
Next, the data recovery operation from the ferroelectric element will be described.

(F) At time t42, the power is turned on. Operation waveforms of the primary power supply voltage VDD1 and the secondary-side power supply voltage VDD2 is increased, the value of the secondary-side power supply voltage VDD2 reaches a reset voltage level V _RST, the reset signal RSTn are turned off.

(G) At time points R1 to R5 indicated by time points t5 to t9, the clock signal CLK is set to “L” and the inverted clock signal CLKB is set to “H”. Therefore, the path switch 66 is turned off and the path switch 68 is turned on. At time R1, the ferroelectric element driving signal PL1 applied to the first plate line and the ferroelectric element driving signal PL2 applied to the second plate line are both “L”. .

(H) In a period T5 between time points R2 and R3 indicated by time points t6 to t7, the power supply is waiting to be restored. At the time point R2, the ferroelectric element write signal E1 and the normal operation signal E2 are both in the “L” state (that is, the data write driver is invalidated and a normal loop is formed in the loop structure portion LOOP. In this state, the secondary power supply voltage VDD2 reaches the reset voltage level _VRST . Further, when the value of the primary power supply voltage VDD1 rises and the value of the secondary power supply voltage VDD2 becomes higher than the reset voltage level _VRST , the nonvolatile CPU 40 enters a power recovery waiting state.

(I) Next, at time t7, the when the value of the primary power supply voltage VDD1 reaches the VDD1 detection voltage level V _LV 1, the voltage level detection signal VDT is turned on. Here, the data recovery operation is started.

(J) Next, in the period from time t7 to time t10, both the primary power supply voltage VDD1 and the secondary power supply voltage VDD2 are kept on. Immediately after time t7, the ferroelectric element driving signal PL1 changes from the OFF state to the ON state, and the data read operation indicated by the arrow B from the nonvolatile data signal NVSEDATA to the volatile data signal VSEDATA is executed.

In particular, in the period T6 from the time point R3 to R5, data is read from the nonvolatile storage units (NVSE) 36 ₁ and 36 ₂ to the volatile storage unit (VSE) 35.

  At the time point R3, the ferroelectric element both-end short circuit signal FRST is set to “L”, the MOS transistors Q1a, Q1b, Q2a, and Q2b are turned off, and voltage application to the ferroelectric capacitors 51a, 51b, 52a, and 52b is possible. On the other hand, while the ferroelectric element driving signal PL2 applied to the second plate line is maintained at “L”, the ferroelectric element driving signal PL1 applied to the first plate line is “ H ”. By applying such a pulse voltage, voltage signals corresponding to the remanent polarization state in the ferroelectric capacitor appear as the node voltage V1 and the node voltage V2.

  More specifically, referring to the example of FIG. 12, a relatively low voltage signal (hereinafter, the logic is referred to as WL [Weak Low]) appears as the node voltage V1, and the node voltage V2 is relatively A high voltage signal (hereinafter, its logic is called WH [Weak Hi]) appears. That is, a voltage difference is generated between the node voltage V1 and the node voltage V2 in accordance with the difference in the remanent polarization state in the ferroelectric capacitor.

  At this time, at the time points R3 to R4, the normal operation signal E2 is set to “L” and the second input terminal (0) of the multiplexer 84 and the multiplexer 86 is selected, so that the logic of the node voltage V3 becomes WL and the node voltage The logic of V4 is WH. The logic of the node voltage V5 is WH, and the logic of the node voltage V6 is WL. As described above, at the time points R3 to R4, the node voltages V1 to V6 are still unstable (the logic inversion in the inverter 76 and the inverter 80 is not completely performed, and the output logic is surely “L” / “H”. It is a state that is not).

  At the time point R4, the normal operation signal E2 is set to “H”, and the multiplexer 84 and the first input terminal (1) of the multiplexer 86 are selected, so that a normal loop is formed in the loop structure section LOOP. With such switching of the signal path, the output terminal (logic: WH) of the inverter 70 and the input terminal (logic: WH) of the inverter 72 are connected, and the output terminal (logic: WL) of the inverter 72 and the inverter 70 are connected. An input terminal (logic: WL) is connected. Therefore, there is no mismatch in the signal logic (WH / WL) of each node, and thereafter, while the normal loop is formed in the loop structure section LOOP, the inverter 72 receives the input of the logic WL and outputs it. The inverter 70 tries to raise the logic to “H”, and the inverter 70 receives the input of the logic WH and tries to lower its output logic to “L”. As a result, the output logic of the inverter 72 is determined from the unstable logic WL to “L”, and the output logic of the inverter 70 is determined from the unstable logic WH to “H”.

  At the time point R4, a signal (potential difference between the node voltage V1 and the node voltage V2) read out from the ferroelectric capacitor is amplified by the loop structure portion LOOP when the loop structure portion LOOP is set to the normal loop. Thus, the data held before the power is turned off is restored.

  At the time point R5, the ferroelectric element both-ends short circuit signal FRST is set to “H” again, the MOS transistors Q1a, Q1b, Q2a, Q2b are turned on, and both ends of the ferroelectric capacitors 51a, 51b, 52a, 52b are connected. Since both are short-circuited, no voltage is applied to these ferroelectric capacitors 51a, 51b, 52a, 52b. At this time, both the ferroelectric element driving signal PL1 applied to the first plate line and the ferroelectric element driving signal PL2 applied to the second plate line are set to “L”. Accordingly, the normal operation state is restored as before time point W1.

  According to the third embodiment of the present invention, when a control target is a non-volatile CPU, power-off / turn-on is detected, and a signal requesting data backup (data save / restore) is output. It is possible to provide a data control apparatus that can secure a processable period for sufficient backup processing.

  According to the data control device of the third embodiment of the present invention, even when the control target is a non-volatile CPU having two power supply lines, the capacitance of the capacitor for securing the voltage after power-off Can be reduced.

  Further, according to the data control device of the third embodiment of the present invention, even when the control target is a non-volatile CPU, it is useless when the value of the power supply voltage fluctuates due to noise on the power supply line or the like. Backup processing (data saving / restoring) can be suppressed.

[Other embodiments]
As described above, the present invention has been described according to the first to third embodiments. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  As described above, the present invention naturally includes various embodiments that are not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

[Application examples for actual applications]

  FIG. 14 is a block diagram showing an embodiment of a data processing apparatus according to the present invention. The data processing apparatus according to the present embodiment includes a nonvolatile CPU 210 (hereinafter simply referred to as CPU 210), a CPU / memory control circuit 220, an I / O control circuit 230, a power switch 240, a JTAG control circuit 250, and a CPU input. Side switches 261 to 269, CPU output side switches 271 and 272, power supply check circuit 280, RS232C port 290, main memory 300, video DAC [Digital Analog Converter] 310, LCD [Liquid Crystal Display] 320 , A video memory 330, a C / F card 340, a PS / 2 interface 350, a mouse 360, and a bus monitor 370.

  In the present embodiment, the configuration in which the present invention is applied to a personal computer will be described as an example. However, the application target of the present invention is not limited to this, and the present invention is used for other purposes. The present invention can be widely applied to all data processing apparatuses.

  The CPU 210 includes a volatile storage unit (VSE) and a nonvolatile storage unit (NVSE) as means for holding register data handled by a CPU core (not shown), and is supplied from the CPU / memory control circuit 220. Based on the instruction, it has a function of performing saving / restoring processing of register data in synchronization with power on / off to the CPU core. The register data saving process in the CPU 210 is a process for storing the register data held in the volatile storage unit in the nonvolatile storage unit based on an instruction from the CPU controller 221. The register data restoration process in the CPU 210 is a process for returning the register data stored in the nonvolatile storage unit to the volatile storage unit based on an instruction from the CPU controller 221. As described above, if the CPU 210 has a register data saving / restoring function, the register data can be held in a nonvolatile manner even when the power is turned off. Therefore, when the power is turned on, the operating state immediately before the power is turned off is restored. It is possible. Note that the CPU 210 corresponds to the nonvolatile CPU 40 of the third embodiment described above, and therefore, a redundant description of its configuration and operation is omitted.

  The CPU / memory control circuit 220 is a main body that controls the CPU 210 and the main memory 300 in an integrated manner, and includes a nonvolatile CPU logic controller 221 (hereinafter simply referred to as a CPU controller 221) and a memory interface controller 222 (hereinafter referred to as a memory I / O). / F controller 222), a debug controller 223, and a JTAG [Joint Test Action Group] controller 224.

  The CPU controller 221 is a circuit block that forms the core of the CPU / memory control circuit 220. The CPU controller 221 controls the memory I / F controller 222, the debug controller 223, and the JTAG controller 224, as well as various controls (power on / off) of the CPU 210. Off control, nonvolatile register control, clock signal and reset signal supply control, etc.) and enable control of the CPU input side switches 263 to 269 using the enable signal Sen. The CPU controller 221 also has a monitoring function for an address bus, a data bus (both are 32-bit buses in FIG. 14), a CPU wait signal line, and an interrupt control signal line.

  The memory I / F controller 222 is a circuit block that performs access control (read / write control) of the main memory 300 based on an instruction from the CPU controller 221 and has a monitoring function of an address bus and a memory control signal. The memory I / F controller 222 also has a function of performing enable control of the CPU output side switches 271 and 272 using the enable signals OEn and AEn based on an instruction from the CPU controller 221. The memory I / F controller 222 also has a function of performing data saving / restoring processing of the main memory 300 based on the first system reset signal RSTn and the second system reset signal RST2n. The first system reset signal RSTn corresponds to the reset signal RSTn of the first to third embodiments described above, and the second system reset signal RST2n corresponds to the voltage level detection signal VDT. For this reason, a duplicate description of the generation method is omitted.

  The debug controller 223 is a circuit block that performs debug control and scan / test control of the CPU 210 based on an instruction from the CPU controller 221.

  The JTAG controller 224 is a circuit block that performs JTAG test control of the CPU 210 based on an instruction from the CPU controller 221. The JTAG controller 224 also has a function of performing enable control of the CPU input side switches 261 and 262 using the enable signals JEn1 and JEn2 in response to an instruction from the CPU controller 221.

  The I / O control circuit 230 is a main body that performs input / output control between the CPU 210 and various devices connected thereto, and includes an I / O controller 231, a graphic controller 232, a C / F controller 233, a PS / 2 controller 234 and a bus monitor controller 235.

  The I / O controller 231 is a circuit block forming the core of the I / O control circuit 230, and controls the graphic controller 232, the C / F controller 233, the PS / 2 controller 234, and the bus monitor controller 235. The CPU 210 performs various controls (CPU wait control, interrupt control, etc.). The I / O controller 231 also has a monitoring function for an address bus, a data bus, and a memory control signal line.

  The graphic controller 232 is a circuit block that performs access control (read / write control) to the video memory 330 and video data output control to the video DAC 310 based on an instruction from the I / O controller 231. In FIG. 14, an 18-bit bus is used as an address bus to the video memory 330, and a 64-bit bus is used as a data bus.

  The C / F controller 233 is a circuit block that performs access control (read / write control) to the C / F card 340 based on an instruction from the I / O controller 231.

  The PS / 2 controller 234 is a circuit block that appropriately processes input information from the mouse 360 connected via the PS / 2 interface 350 based on an instruction from the I / O controller 231.

  The bus monitor controller 235 is a circuit block that controls the bus monitor 370 based on an instruction from the I / O controller 231.

  The power switch 240 is inserted on the power supply line to the CPU 210 (particularly the CPU core and CPU input / output unit). Based on an instruction from the CPU controller 221, the CPU 210 is turned on / off (conduction / conduction of the power supply line). ).

  The JTAG control circuit 250 is a circuit block that performs JTAG test control of the CPU 210 based on an instruction from the outside of the apparatus.

  Each of the CPU input side switches 261 to 269 is inserted on a signal input line to the CPU 210, and an instruction from the CPU / memory control circuit 220 (specifically, an enable signal SEn output from the CPU controller 221) Based on the enable signals JEn1 and JEn2) output from the JTAG controller 224, the signal input line to the CPU 210 is turned on / off. As the CPU input side switches 261 to 269, a three-state buffer or the like can be suitably used.

  The CPU output side switches 271 and 272 are inserted on the signal output line from the CPU 210 (specifically, the data bus output line and the address bus output line), and an instruction (specifically, from the CPU / memory control circuit 220). Is means for conducting / interrupting the signal output line from the CPU 210 based on the enable signals OEn, AEn) output from the memory I / F controller 222. As the CPU output switches 271 and 272, a three-state buffer or the like can be preferably used.

  The power check circuit 280 is a circuit block that monitors the first power supply voltage VDD1 (for example, 5.0V) and the second power supply voltage VDD2 (for example, 3.3V), respectively, and generates the first system reset signals RSTn and RST2n. A reset IC or the like can be preferably used. The system reset signals RSTn and RST2n are input to the CPU / memory control circuit 220 and the I / O control circuit 230.

  The RS232C port 290 inputs and outputs various information between the CPU / memory control circuit 220 and the I / O control circuit 230 and an electronic device (such as another personal computer) externally connected to the data processing device. Is a serial interface.

  The main memory 300 is a storage means used as a work area or the like of the CPU 210, and includes a volatile memory 300a (SRAM [Static Random Access Memory] in FIG. 14) and a non-volatile memory 300b (FRAM [Ferroelectric Random Access Memory in FIG. 14). ]). The main memory 300 has a function of performing data save / restore processing in synchronization with the system reset signals RSTn and RST2n based on an instruction from the memory I / F controller 222. The data saving process in the main memory 300 is a process for storing the data held in the volatile memory 300a in the nonvolatile memory 300b based on an instruction from the memory I / F controller 222. . The data restoration process in the main memory 300 is a process for returning the data stored in the nonvolatile memory 300b to the volatile memory 300a based on an instruction from the memory I / F controller 222. As described above, if the main memory 300 has a data save / restore function, data can be held in a nonvolatile manner even when the power is turned off. Therefore, when the power is turned on, the operation state immediately before the power is turned off is restored. It is possible.

  The video DAC 310 is a circuit block that converts a digital signal input from the graphic controller 232 into an analog signal and supplies the analog signal to the LCD 320.

  The LCD 320 is a device that displays video based on an analog signal input from the video DAC 310.

  The video memory 330 is a storage means used as a work area of the graphic controller 232, and includes a volatile memory 330a (SRAM in FIG. 14) and a nonvolatile memory 330b (FRAM in FIG. 14). The video memory 330 has a function of performing data saving / restoring processing based on an instruction from the graphic controller 232. The data saving process in the video memory 330 is a process for storing data having the same contents in both the volatile memory 330a and the non-volatile memory 330b while mirroring based on an instruction from the graphic controller 232. . The data restoration process in the video memory 330 is a process for returning the data stored in the nonvolatile memory 330b to the volatile memory 330a based on an instruction from the graphic controller 232. As described above, the video memory 330 having a data saving / restoring function can hold data in a nonvolatile manner even when the power is turned off, so that when the power is turned on, the operation state immediately before the power is turned off is restored. It is possible.

  The C / F card 340 is a kind of detachable semiconductor recording medium using a flash memory or the like.

  The PS / 2 interface 350 is an input / output port for a personal computer or the like, and is used to connect a mouse 360 and a keyboard (not shown).

  The mouse 360 is a kind of pointing device that is used by being connected to a personal computer or the like. As a coordinate detection method, a ball method or an optical method is widely adopted.

  The bus monitor 370 is a device that monitors a bus to which a 7-segment display or the like is connected.

  In FIG. 14, the CPU 210, the CPU / memory control circuit 220, and the I / O control circuit 230 are depicted as independent circuit blocks. However, the configuration of the present invention is not limited to this, and the CPU 210 As a built-in module, a part or all of the CPU / memory control circuit 220 and the I / O control circuit 230 may be appropriately incorporated.

  Next, the operation of the data processing apparatus configured as described above will be described in detail with reference mainly to FIGS. FIG. 15 is a flowchart illustrating an example of initialization / data restoration processing when the system power is turned on. FIG. 16 is a flowchart illustrating an example of normal operation. FIG. 17 is a flowchart illustrating an example of a data saving process when the system power supply is reduced. 15 to 17, in order from the left side of the drawing, the CPU 210 (CPU core), the CPU controller 221, the memory I / F controller 222, the I / O controller 231, the graphic controller 232, and the C / F controller 233, respectively. , And a flowchart showing the operation of the PS / 2 controller 234 is depicted.

First, initialization / data restoration processing when the system power is turned on will be described in detail with reference to FIG. When the system power is turned on, the CPU controller 221, memory I / F controller 222, I / O controller 231, graphic controller 232, C / F controller 233, and PS / 2 controller 234 are all in the power-on state. It made it (step S201, S301, S401, S501, S601, S701), a second power supply voltage VDD2 reaches a predetermined threshold value V _RST, until the system reset signal RSTn rises from the low level to the high level, kept in the reset state (Steps S202, S302, S402, S502, S602, S702).

  Thereafter, when the system reset signal RSTn rises to a high level, the reset state of each controller is released, and the start-up process is started. Specifically, after the reset state is released, the CPU controller 221 turns on the power by turning on the power switch 240 (steps S203 and S101) and resets the CPU 210 (steps S204 and S102). The CPU 210 is instructed to restore the register data (step S205). Instructed to restore the register data, the CPU 210 performs a process for returning the register data stored in the nonvolatile storage unit of the CPU core to the volatile storage unit (step S103). Further, after the reset state is released, the memory I / F controller 222 performs a data restoration process of the main memory 300 (step S303), and then enters an access waiting state (step S304). By such start-up processing, the data held in the CPU 210 and the main memory 300 is restored to the state immediately before the system power supply is shut off.

  After instructing the CPU 210 to restore the register data, the CPU controller 221 determines whether or not the start-up process has been normally completed for the memory I / F controller 222 (whether it has shifted to an access wait state). Confirmation is made (step S206). The memory I / F controller 222 that has received the request for confirmation of startup transmits a startup end signal to the CPU controller 221 (step S305). The CPU controller 221 that has received the start end signal makes an initial read request to the memory I / F controller 222 (step S207). Receiving the initial read request, the memory I / F controller 222 reads data corresponding to the address currently output to the address bus from the main memory 300 (step S306), and then enters an access waiting state (step S306). S307).

  The above initial read request will be described in detail with reference to FIGS. 18A and 18B. 18A and 18B are timing charts for explaining the operation of initial reading. FIG. 18A shows a case where the initial read process is performed, and FIG. 18B shows a case where the initial read process is not executed.

  As shown in FIGS. 18A and 18B, the CPU 210 operates in synchronization with the clock signal. More specifically, the CPU 210 takes in the data flowing on the data bus at the rising edge of the clock signal and performs the next address designation on the address bus. If the system power supply is cut off at the time t11 shown in the figure, the CPU 210 outputs the address A2 to the address bus, and in response thereto, the data D2 output from the main memory 300 to the data bus is sent to the next clock signal. It is shut down while being held in a state where it tries to read at the rising edge.

  After that, when the system power is turned on again at time t12 and the data restoration process is performed at time t13, the CPU 210 is restored to the state immediately before the system power is shut off. That is, the CPU 210 tries to read the data D2 that should be output from the main memory 300 to the data bus in response to the address A2 output to the address bus at the rising edge of the next clock signal.

  However, since the memory I / F controller 222 is reset when the system power is turned on again at time t12, no data is output to the data bus simply by performing the data restoration processing at time t13. It becomes a state. Therefore, when the initial read process is not performed, the CPU 210 cannot read the desired data D2 at the rising edge of the clock signal after the system power is turned on again, causing the system to run out of control (see FIG. 18B). .

  On the other hand, in the data processing apparatus of this embodiment, as shown in FIG. 18A, the initial read process is performed at time t14. That is, the CPU controller 221 sends an instruction to the memory I / F controller 232 to read the data D2 corresponding to the address A2 output to the address bus at the time t14. By performing such an initial reading process, the data D2 is output to the data bus, so that the CPU 210 can normally read the desired data D2 at the rising edge of the clock signal.

  That is, it can be said that the initial reading process performed at time t14 is a process for returning not only the operation state of the CPU 210 but also the state of data flowing in the data bus to the state immediately before the system power supply is shut off. It should be noted that it is desirable to set the time t14 appropriately in consideration of the timing when the data restoration process at the time t13 is completed and the address immediately before the system power is shut off is output to the address bus.

It should be noted that the CPU controller 221 makes the startup process to the I / O controller 231 normally after making the above initial read request (whether it has shifted to an access wait state). After confirming (step S208), the first power supply voltage VDD1 reaches a predetermined threshold value V _LV 1 and the normal operation start is waited until the system reset signal RST2n rises from the low level to the high level. (Step S209).

  On the other hand, after the reset state is released, the I / O controller 231 has all I / O blocks connected to itself (in FIG. 15 to FIG. 17, the graphic controller 232, the C / F controller 233, and the PS / 2 controller). It is in a state of waiting for a return completion signal from (only 234 is depicted) (step S403).

  After canceling the reset state, the graphic controller 232 performs data restoration processing of the video memory 330 (that is, data transfer processing from the nonvolatile memory 330b to the volatile memory 330a) (step S503). By such data restoration processing, after the system power is turned on, the data held in the video memory 330 can be restored to the state immediately before the system power is shut off. Thereafter, the graphic controller 232 sends a return completion signal to the I / O controller 231 (step S504) and enters a graphic display state (step S505).

  After releasing the reset state, the C / F controller 233 performs initialization processing (operation check, etc.) of the C / F card 340 (step S603), and sends a return completion signal to the I / O controller 231 (step S604). ), An access waiting state is entered (step S605).

  After canceling the reset state, the PS / 2 controller 234 performs initialization processing (operation check, etc.) of the PS / 2 interface 350 and the mouse 360 connected to the PS / 2 interface 350 (step S703), and sends it to the I / O controller 231. After the return completion signal is transmitted (step S704), the access wait state is entered (step S705).

  The I / O controller 231 confirms that the return completion signal has arrived from all the I / O blocks connected to itself, and waits for access from the CPU 210 (step S404). When the I / O controller 231 receives the startup confirmation request from the CPU controller 221, the I / O controller 231 transmits a startup completion signal to the CPU controller 221 (step S405), and again enters the access waiting state. Return (step S406).

  Through the series of operations described above, the initialization / data restoration process of the entire system is completed, and the normal operation can be performed.

  Next, the normal operation after the system power is turned on will be described in detail with reference to FIG. Here, a case where data transfer from the C / F card 340 to the main memory 300 is described as an example.

  When the system reset signal RST2n rises to a high level in step S209 in FIG. 15, an enable signal is sent from the CPU controller 221 to the CPU 210, and normal operation of the CPU 210 is started (steps S210 and S104). When transferring data from the C / F card 340 to the main memory 300, the CPU 210 reads data from the C / F card 340 to the I / O controller 231 and writes the data to the main memory 300. An O request is transmitted (step S105). An I / O request from the CPU 210 to the I / O controller 231 is transmitted via an address bus by an address mapping method.

  As described above, in response to an I / O request from the CPU 210, data transfer processing (in this case, data from the C / F card 340 to the main memory 300 is mainly composed of the I / O controller 231 and the memory I / F controller 222). While the transfer process is being performed, the CPU 210 does not need to perform any special process. Therefore, when the I / O controller 231 receives an I / O request from the CPU 210, it sends a CPU wait signal to the CPU controller 221 to stop the processing of the CPU 210 (step S408).

  The above CPU wait processing is also performed in the conventional system. However, the data processing apparatus according to the present embodiment powers off the CPU 210 at the same time as the above CPU wait processing to save power in the system. It is intended. Hereinafter, more detailed description will be given along the flowchart of FIG.

  Upon receiving the CPU wait signal from the I / O controller 231, the CPU controller 221 starts the data saving process of the CPU 210 (step S211) prior to powering off the CPU 210, and instructs the CPU 210 to save the register data (step S211). Step S212). The CPU 210 instructed to save the register data performs a process for storing the register data stored in the volatile storage unit of the CPU core in the nonvolatile storage unit (step S106). Thereafter, the CPU controller 221 shuts off the power switch 240 to power off the CPU 210 (steps S213 and S107), and waits for a CPU wait release (step S214). That is, in the data processing apparatus of this embodiment, the CPU wait signal input from the I / O controller 232 is used as a power off trigger for the CPU 210.

  As described above, while the CPU 210 is shut down, data transfer processing from the C / F card 340 to the main memory 300 is performed mainly by the I / O controller 231 and the memory I / F controller 222. More specifically, the I / O controller 231 sends a CPU wait signal to the CPU controller 221, then reads data from the C / F card 340 to the C / F controller 233, and stores the data as main data. A processing request is sent to write to the memory 300 (step S409). Then, the I / O controller 231 enters a process completion waiting state of the C / F controller 233 (step S410).

  On the other hand, the C / F controller 233 that has been waiting for access from the I / O controller 231 (step S606) receives a processing request from the I / O controller 231 and receives data from the C / F card 340. In addition to starting reading, a write request is sent to the memory I / F controller 222 via the I / O controller 231 so as to write the data to the main memory 300 (step S607).

  Further, the memory I / F controller 222 that has been in an access waiting state from the CPU 210 or the I / O controller 231 (step S309) responds to a write request from the C / F controller 233 input via the I / O controller 231. In response, the data read from the C / F card 340 is written into the main memory 300 (in this case, the volatile memory 300a) (step S310), and then the access wait state is resumed (step S311).

  In the data writing process, a memory control signal for instructing a data writing operation and an address signal for instructing a data writing destination are respectively sent via a memory control signal line and an address bus. Input from the I / O controller 231 to the I / F controller 222. The data read from the C / F card 340 is input from the I / O controller 231 to the main memory 300 via the data bus. Further, the memory I / F controller 222 disables both the enable signals OEn and AEn during the above-described data writing process, thereby turning off the CPU output side switches 271 and 272 (output disabled state (output disabled state)). High impedance state)).

  When the data transfer process is completed, the C / F controller 233 sends a process completion signal to the I / O controller 231 (step S608), and again enters an access wait state (step S609). The I / O controller 231 that has received the processing completion signal sends an instruction to the CPU controller 221 so as to release the CPU wait (step S411), and then enters an access waiting state again (step S412).

  After releasing the CPU wait, the CPU controller 221 turns on the power to the CPU 210 by turning on the power switch 240 (steps S215 and S108), resets the CPU 210 (steps S216 and S109), and then stores the register data in the CPU 210. Is instructed (step S217). Instructed to restore the register data, the CPU 210 performs a process for returning the register data stored in the nonvolatile storage unit of the CPU core to the volatile storage unit (step S110). By such start-up processing, the data held in the CPU 210 is restored to the state immediately before power off.

  The CPU controller 221 makes an initial read request to the memory I / F controller 222 after the register data restoration processing in the CPU 210 (step S218), and starts normal operation of the CPU 210 (steps S219 and S111). On the other hand, the memory I / F controller 222 that has received the initial read request reads the data corresponding to the address currently output to the address bus from the main memory 300 (step S312), and then responds to the access request from the CPU 210. In response, the read / write control for the main memory 300 is performed (step S313). Note that the above initial read process is a process for returning the data bus to the state immediately before the CPU 210 is powered off, and is the same as the process described with reference to FIG. 18A.

  As described above, when processing that does not require the CPU 210 (in the above example, data transfer processing mainly including the I / O controller 231 and the memory I / F controller 222) is executed even during normal operation of the system. The system can save power by actively powering off the CPU 210.

  In the above embodiment, the data transfer process from the C / F card 340 to the main memory 300 has been described as an example. However, the opportunity to power off the CPU 210 is not limited to this, and the main memory is not limited to this. The CPU 210 may be powered off when performing data transfer processing from the 300 to the C / F card 340, and more generally, between the first module and the second module without going through the CPU 210. During direct data transfer, the CPU 210 can be actively powered off.

  However, in the data processing apparatus according to the present embodiment, there may naturally occur a state where only the power supply to the CPU 210 is cut off while the power supply to the entire system is maintained. Therefore, if the signal input line to the CPU 210 is not electrically insulated, a current flows into the CPU 210 that is powered off via the signal input line, and the CPU 210 unintentionally powers on. There is a risk of causing various problems.

  Therefore, the data processing apparatus according to the present embodiment is configured by inserting CPU input side switches (3-state buffers) 261 to 269 in all signal input lines to the CPU 210. The CPU controller 221 turns off the CPU input side switches 261 to 269 (output disabled state (output high impedance state)) when powering off the CPU 210, and turns on the CPU input side switch 261 when powering on the CPU 210. ˜269 are turned on (output enable state). 15 to 17, the step of turning off the CPU 210 (steps (steps S213 and S223) includes the turn-off control of the CPU input side switches 261 to 269, and the CPU 210 is turned on. The steps to be performed (steps S203 and S215) include turn-on control of the CPU input side switches 261 to 269.

  In FIG. 14, in view of the necessity to perform conduction / shut-off control of the JTAG input line regardless of the power-on / power-off control of the CPU 210, the CPU input-side switches 261 to 269 are inserted into the JTAG input line. As for the CPU input side switches 261 and 262, a configuration in which the JTAG controller 224 is a direct control subject and the other CPU input side switches 263 to 269 are depicted as having a CPU controller 221 as a direct control subject. The configuration of the present invention is not limited to this, and the CPU controller 221 may be the direct control subject for all the CPU input side switches 261 to 269.

Next, the data saving process when the system power is reduced will be described in detail with reference to FIG. When the first power supply voltage VDD1 falls below the predetermined threshold value V _LV 1 and the system reset signal RST2n falls from the high level to the low level (step S220), the CPU controller 221 starts the data saving process of the CPU 210 (step S221). The CPU 210 is instructed to save the register data (step S222). The CPU 210 instructed to save the register data performs a process for storing the register data stored in the volatile storage unit of the CPU core in the nonvolatile storage unit (step S112). Thereafter, the CPU controller 221 shuts off the power switch 240 to power off the CPU 210 (step S223), and checks whether the system reset signal RST2n has risen to the high level again (step S224). If the system reset signal RST2n rises to a high level, the CPU controller 221 sends an enable signal from the CPU controller 221 to the CPU 210, and normal operation of the CPU 210 is resumed (steps S225 and S113).

  On the other hand, the memory I / F controller 222 starts data saving processing of the main memory 300, performs data transfer processing from the volatile memory 300a to the nonvolatile memory 300b (steps S314 and S315), and then accesses from the CPU 210. In response to the request, the state returns to a state in which read / write control to the main memory 300 (particularly, the volatile memory 300a) is performed (step S316).

  In the flowchart of FIG. 17, only the data saving process of the main memory 300 is depicted, and the data saving process of the video memory 330 is not depicted at all. This is because the data saving process of the video memory 330 is sequentially executed as the mirroring process during the normal operation of the graphic controller 232 (steps S505 to S507 in FIGS. 15 to 17).

  The mirroring process of the video memory 330 will be described in detail with reference to FIG. FIG. 19 is a timing chart for explaining data saving processing (mirroring processing) of the video memory 330, and shows a clock signal, an address signal, and a data signal in order from the top.

  As described above, the data processing apparatus according to the present embodiment has a function of performing data saving processing when the system power supply is reduced. When such a data saving process is performed, the storage capacity of the main memory 300 is relatively small. Therefore, even if the data saving process is started after detecting a decrease in the system power supply, the main memory 300 can be normally completed. Is possible. On the other hand, since the storage capacity of the video memory 330 is very large, it may not be in time if the data saving process is started after a decrease in the system power supply is detected. For this reason, the data saving process in the video memory 330 is sequentially executed as a mirroring process during the normal operation of the graphic controller 232.

  The transfer rate (random access time: 55 ns) of the SRAM used as the volatile memory 330a is about twice the transfer rate (random access time: 110 ns) of the FRAM used as the nonvolatile memory 330b. During normal operation of the graphic controller 232, the SRAM used as the volatile memory 330a sequentially reads out already stored data and displays one frame image, and overwrites new data. Random writing is performed.

  More specifically, referring to FIG. 19, in the SRAM, data is read out in synchronization with one clock pulse, and new data is written in synchronization with the next clock pulse. At this time, data reading is performed sequentially according to continuous addressing (A0, A1, A2, A3,...), But data updating is necessary for writing new data. In order to overwrite only the pixel data, it is performed randomly according to discrete addressing (A50, A51, A100, A101,...).

  On the other hand, the FRAM used as the non-volatile memory 330b only mirrors data having the same content as that of the SRAM, so that only the random write operation described above is required. That is, while the read operation and the write operation are performed once for the SRAM, the write operation is performed only once for the FRAM. Therefore, even if there is a difference in access speed between SRAM and FRAM that is nearly double, mirroring processing of both is possible.

  As described above, when the data saving process of the video memory 330 is configured to sequentially perform the mirroring process of the video memory 330 during the normal operation, even when the system power supply is suddenly shut down, the nonvolatile memory can be used when the system power supply is turned on again. By reading the data mirrored in the memory 330b back to the volatile memory 330a, the data stored in the video memory 330 can be returned to the state immediately before the system power is shut off (Step S503 in FIG. 15 is performed). reference).

  The configuration of the present invention can be variously modified in addition to the above-described embodiment without departing from the gist of the invention.

  The present invention is a technique useful for practical application of a data processing device having a function of making data non-volatile, and its application target is a logic operation circuit, a logic operation device, a CPU, an MPU, a DSP, etc. It can be applied to a wide range of fields such as processors, game machines and mobile devices. In particular, battery-driven devices are advantageous in terms of data protection when the battery is exhausted.

2, 3, 10, 30 Control target circuit 4 Voltage converter 12 Data control device 14 Power supply voltage conversion unit 15 Detection / control unit 16 Reset signal generation unit 18 Voltage level detection unit 20 Control signal generation unit 32 Main operation unit 34, 34 ₁ , 34 ₂ Data interface (I / F) controller 35 Volatile memory (VSE)
36, 36 ₁ , 36 ₂ Nonvolatile storage (NVSE)
40 Nonvolatile CPU
42 Clock generator 44 AND gate 50 Non-volatile memory gate 51a, 51b, 52a, 52b Ferroelectric capacitor 54, 56, 58 Logic circuit block 60, 61, 64, 70, 72, 74, 76, 80 Inverter 62, 66 , 68, 78, 82 Path switch 84, 86 Multiplexer D Data input signal Q Data output signal CLK Clock signal CLKB Inverted clock signal E1 Ferroelectric element write signal E2 Normal operation signal FRST Ferroelectric element both-end short circuit PL1, PL2 Strong Dielectric element driving signal VDD Power supply voltage VDD1 Primary power supply voltage VDD2 Secondary power supply voltage VDL1 Primary power supply line VDL2 Secondary power supply line TW1, TW2 Processable period RSTn Reset signal (negative logic)
VDT voltage level detection signal CLS control signal V _LV 1 VDD1 detection voltage level V _LV 2 VDD2 detection voltage level V _RST reset voltage level C1, C2 capacitor DRCS data save control signal DSCS data return control signal 210 Non-volatile CPU
220 CPU / Memory Control Circuit 221 Non-volatile CPU Logic Controller 222 Memory Interface Controller 223 Debug Controller 224 JTAG Controller 230 I / O Control Circuit 231 I / O Controller 232 Graphic Controller 233 C / F Controller 234 PS / 2 Controller 235 Bus Monitor 240 Power switch 250 JTAG control circuit 261-269 CPU input side switch (3-state buffer)
271 and 272 CPU output side switch (3-state buffer)
280 Power Check Circuit (Reset IC)
290 RS232C port 300 Main memory 300a Volatile memory (SRAM)
300b Non-volatile memory (FRAM)
310 Video DAC
320 LCD
330 Video memory 330a Volatile memory (SRAM)
330b Non-volatile memory (FRAM)
340 C / F card 350 PS / 2 interface 360 Mouse 370 Bus monitor (7SEG)

Claims (4)

An electronic circuit for handling register data, a control circuit for saving / restoring the register data, a memory used by the electronic circuit, a memory control circuit for controlling access to the memory in accordance with an instruction from the electronic circuit, Comprising
The electronic circuit, which operates in synchronization with a clock signal supplied from said control circuit, said control circuit, after returning the register data, the electronic state of stopping the supply of the clock signal verify Tei Ru address is output from the circuit, data processing, characterized in that after the instruction to the memory control circuit to read data stored in that address from the memory, resuming supply of the clock signal apparatus.   The control circuit saves the register data when the data processing device or the electronic circuit is turned off, and restores the register data when the data processing device or the electronic circuit is turned on. Item 4. The data processing device according to Item 1.   The control circuit performs a saving process of the register data and a power-off process of the electronic circuit using a wait instruction for the electronic circuit as a trigger, and a power-on process of the electronic circuit using a wait release instruction for the electronic circuit as a trigger The data processing apparatus according to claim 2, wherein the register data is restored.   4. The electronic circuit according to claim 1, wherein the electronic circuit is a CPU having a volatile storage unit and a nonvolatile storage unit as means for holding the register data. The data processing apparatus described.

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