JP5450112B2 - Memory interface circuit - Google Patents

Description

  The present invention relates to a memory interface circuit that operates in synchronization with a clock signal and controls operations (data writing and reading) of a synchronous memory that transmits and receives data in synchronization with a data strobe signal.

  A synchronous memory such as a DDR memory operates in synchronization with the clock signal CLK, and transfers data DQ in synchronization with the data strobe signal DQS. For example, a memory interface circuit that controls the operation of the DDR memory transmits data DQ to the DDR memory in synchronization with the data strobe signal DQS at the time of data writing, and from the DDR memory in synchronization with the data strobe signal DQS at the time of data reading. Data DQ is received.

  The data strobe signal DQS is a bidirectional timing control signal used when data is written and read between the DDR memory and the memory interface circuit. Therefore, in the memory interface circuit, the data strobe signal DQS operates as an output signal when data is written, and as an input signal when data is read, and is in a Hi-Z (high impedance) state when no operation is performed.

  As described above, the memory interface circuit recognizes the data strobe signal DQS as an input signal at the time of data reading, but the data strobe signal DQS in the Hi-Z state is recognized as an input signal due to the delay of the data strobe signal DQS. There is. In the Hi-Z state, since the H level (high level) and L level (low level) of the input signal are not determined, the data strobe signal DQS may be erroneously recognized.

  Therefore, in the memory interface circuit, a mask signal for masking the indefinite period (Hi-Z state period) of the data strobe signal DQS is generated internally, and only the data strobe signal DQS in the effective range is used. Has been done.

  For example, Patent Document 1 discloses that a mask signal is generated by detecting a read preamble as a method of calculating an effective range of a data strobe signal DQS. However, it is difficult to determine whether the Hi-Z state has changed to the read preamble. For example, it is conceivable to detect a read preamble using an analog circuit, but circuit design is difficult.

  The mask period of the data strobe signal DQS is set in advance by calculating the delay value of the data strobe signal DQS. For this reason, for example, when the delay value varies greatly due to variations in PVT (P: process, V: power supply voltage, T: temperature) conditions, or wiring on a board on which a synchronous memory and a memory interface circuit are mounted ( In some cases, for example, when the board wiring) is longer than expected, the mask signal cannot be set at the optimum timing.

  FIG. 5 is an example timing chart showing the operation of the memory interface circuit. As shown in the figure, in a synchronous memory such as a DDR memory, transmission of an active data strobe signal DQS is started after a predetermined time after receiving a READ command. In the figure, after an L level read preamble is output as the data strobe signal DQS, an active state in which the change between the H level and the L level is repeated four times in the cycle of the clock signal CLK is performed. After the postamble is output, the state of returning to the inactive state is shown.

  As shown in the figure, between the minimum value (min condition) and the maximum value (max condition) of the delay value of the data strobe signal DQS, it exceeds one half of the period of the clock signal CLK and becomes one period. A closer difference may occur. There is almost no period that satisfies both of these conditions, and in some cases, the mask signal DQS_MASK cannot be set. Even if both conditions are satisfied, in the case of the minimum value condition, there is a possibility that the irregular data strobe signal DQS is taken in as the internal data strobe signal DQSI at the end of the mask signal DQS_MASK.

  Patent Documents 2 and 3 are prior art documents that the applicant considers relevant to the present invention.

  Patent Document 2 relates to a technique for synchronizing read data from a DDR memory with an internal clock on the memory interface controller side. In this document, the arrival delay of the data strobe signal relative to the internal clock signal is calculated using the data strobe signal, and the arrived read signal is sampled based on the signal obtained by shifting the phase of the arrived data strobe signal. It is disclosed.

  Patent Document 3 relates to a technique for generating a strobe signal for taking in a data signal by eliminating a high impedance state from a data strobe signal in a DDR memory. This document discloses that the measured latency value from the input of the read command signal to the effective edge of the data strobe signal is measured, and after waiting for the measured latency value, the block of the data strobe signal is released.

JP 2006-260322 A JP 2005-78547 A JP 2007-265399 A

  In both Patent Documents 2 and 3, the timing is adjusted based on the measurement result of the first rising timing of the data strobe signal DQS. In this case, it is assumed that there is a problem of erroneous measurement due to an indefinite period of the data strobe signal DQS, or a measure to prevent it is necessary.

  An object of the present invention is to provide a memory interface circuit that can solve the problems of the prior art and can always mask an indefinite period of a data strobe signal at an optimal timing.

In order to achieve the above object, according to the present invention, when a READ command is received, a change from the inactive state to the second level in the period of the clock signal, followed by the second command, A synchronous memory that transmits a data strobe signal that returns to an inactive state through an active state that repeats a change from a level to a first level and that transmits data in synchronization with the level change of the data strobe signal. A memory interface circuit that transmits a READ command, receives the data strobe signal, and reads the data in synchronization with a level change of the data strobe signal;
A detection circuit for detecting a level change of the data strobe signal and controlling a timing of reading the data;
A read mask control circuit that generates a read mask signal that prohibits detection by the detection circuit except for a non-mask period;
A delay value calculation circuit for detecting a level change of the data strobe signal and calculating a delay value of the data strobe signal with respect to the clock signal;
The mask control circuit further includes a delay value calculation mask for prohibiting detection by the delay value calculation circuit except for a non-mask period including only a part of the active state after a predetermined time from the READ command transmission. A memory interface, wherein the read mask signal is generated based on a delay value of the data strobe signal calculated by the delay value calculation circuit using the delay value calculation mask signal; A circuit is provided.

Here, even if the non-mask period of the delay value calculation mask signal is within an allowable range from the transmission of the READ command to the reception of the data strobe signal, the data strobe signal Preferably, the active state does not include at least one of a change from the first first level to the second level and a level change from the last second level to the first level.
In addition, even if the non-mask period of the delay value calculation mask signal is within an allowable range of delay time from transmission of the READ command to reception of the data strobe signal, the activation of the data strobe signal Preferably, the state does not include both a change from the first first level to the second level and a level change from the last second level to the first level.

  According to the present invention, when the delay value calculation circuit calculates the delay value of the data strobe signal, the delay value calculation mask signal is used to cause an indefinite period of the data strobe signal that causes the delay value calculation circuit to malfunction. By reliably masking, it is possible to prevent erroneous measurement and accurately calculate. Since the non-mask period of the read mask signal is set based on the delay value (actually measured value) of the data strobe signal, the non-mask period is always set to the optimum timing regardless of variations in PVT conditions, board wiring, and the like. be able to.

1 is a schematic diagram of an embodiment illustrating a configuration of a memory interface circuit of the present invention. FIG. 2 is a schematic diagram illustrating an example of a configuration of a delay value calculation circuit 16 illustrated in FIG. 1. 3 is a flowchart illustrating an example of an operation of the memory interface circuit 10 illustrated in FIG. 1. 3 is an example timing chart illustrating an operation of the memory interface circuit 10 illustrated in FIG. 1. 3 is an example timing chart illustrating an operation of a memory interface circuit.

  Hereinafter, a memory interface circuit of the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.

  FIG. 1 is a schematic diagram of an embodiment showing a configuration of a memory interface circuit of the present invention. The memory interface circuit 10 shown in the figure operates in synchronization with the clock signal CLK and controls the operation (data writing and reading) of the synchronous memory that transmits and receives data DQ in synchronization with the data strobe signal DQS. is there. For the sake of easy explanation, only the portion for controlling the reading of data is shown in FIG.

  For example, when the READ command is received during data reading, the synchronous memory outputs an L level read preamble from an inactive state, and repeats a change between the H level and the L level in the cycle of the clock signal CLK. After outputting the L level read postamble through the active state, a data strobe signal DQS that returns to the inactive state is transmitted to the memory interface circuit 10. Further, the data DQ is transmitted in synchronization with the level change of the data strobe signal DQS.

  The data strobe signal DQS transmitted from the memory is input to the memory interface circuit 10 after a delay time depending on the wiring design on the board after the memory interface circuit 10 transmits the READ command. The delay time is in a range between the minimum value and the maximum value of the delay time defined by the specification of the synchronous memory.

  When reading data, the memory interface circuit 10 transmits a READ command to the synchronous memory, receives the data strobe signal DQS transmitted from the synchronous memory, and reads the data DQ in synchronization with the level change of the data strobe signal DQS. . As shown in FIG. 1, the memory interface circuit 10 includes a read mask control circuit 12, an AND circuit 14, a delay value calculation circuit 16, a flip-flop 18, and the like.

  As a mask signal for masking the indefinite period of the data strobe signal DQS, the mask control circuit 12 performs a delay value calculation mask at the time of dummy data read (dummy read) performed to calculate the delay value of the data strobe signal DQS. A signal DQS_MASK1 is generated, and a read mask signal DQS_MASK2 is generated at the time of other normal data reading.

  The mask control circuit 12 receives an INIT (initialization) signal and a READ command. The INIT signal is a signal indicating whether the read is dummy read or normal data read. In the present embodiment, the INIT signal is activated when dummy reading is performed. The INIT signal and the READ command are generated by a circuit (not shown) of the memory interface circuit 10. The mask control circuit 12 also receives the delay value of the data strobe signal DQS calculated by the delay value calculation circuit 16 as described later.

  The mask control circuit 12 determines that the read is a dummy read when the READ command is activated when the INIT signal is activated. In this case, a delay value calculation mask signal DQS_MASK1 having a predetermined period after the predetermined time from the transmission of the READ command as a non-mask period is generated. The non-mask period of the delay value calculation mask signal DQS_MASK1 is set to an optimal timing in advance based on the minimum value and the maximum value of the output delay time of the data strobe signal DQS.

  Specifically, the non-mask period of delay value calculation mask signal DQS_MASK1 includes only a part of the active state of data strobe signal DQS received from the memory in the dummy read. That is, a part of the active state is masked. Thereby, the indefinite period that causes the malfunction of the delay value calculation circuit 16 can be reliably masked. More specifically, in the non-mask period of the delay value calculation mask signal DQS_MASK1, the delay value of the data strobe signal DQS is within an allowable range (a range between the minimum value and the maximum value of the delay time of the data strobe signal DQS). In either case, the timing is set so as not to include the timing of the first level change in the active state of the data strobe signal DQS. Or, the delay value of the data strobe signal DQS is set so as not to include the timing of the last level change in the active state, regardless of whether the delay value is within the allowable range.

  As described above, the time range from the transmission of the READ command to the reception of the data strobe signal DQS is known from the specifications of the synchronous memory. Therefore, it is possible to set such a non-mask period of the delay value calculation mask signal DQS_MASK1. The delay value calculation circuit 16 detects a level change of the data strobe signal DQS existing in the non-mask period of the delay value calculation mask signal DQS_MASK1, and calculates the timing with reference to the clock signal CLK. That is, the delay time (delay value) of the data strobe signal DQS with respect to the clock signal CLK is calculated.

  The mask control circuit 12 determines that normal data reading is performed when the READ command is activated when the INIT signal is inactive. In this case, based on the delay value of the data strobe signal DQS with respect to the clock signal CLK calculated by the delay value calculation circuit 16, the active state of the data strobe signal DQS received after a predetermined delay time from the transmission of the READ command A read mask signal DQS_MASK2 is generated in which the period including the timing of all the level changes is a non-mask period.

  Since the READ command and the delay value calculation mask signal DQS_MASK1 are generated based on the clock signal CLK, the time from the clock signal CLK to these commands and signals is known. Further, the delay value calculation circuit 16 calculates a delay value (actual value) of the received data strobe signal DQS with respect to the clock signal CLK. Based on these pieces of information, the mask control circuit 12 calculates an actual delay time from when the READ command is transmitted until the data strobe signal DQS is received.

  The non-mask period of the read mask signal DQS_MASK2 does not include an indefinite period before the read preamble and after the read postamble based on the delay time from the transmission of the READ command to the reception of the data strobe signal DQS and is in an active state Is set to include all level changes.

  Subsequently, the data strobe signal DQS transmitted from the synchronous memory and the mask signal generated by the mask control circuit 12 are input to the AND circuit 14 at the time of data reading. The AND circuit 14 is an example of the detection circuit of the present invention, and outputs an internal data strobe signal DQSI that detects a level change of the data strobe signal DQS and controls the timing of reading the data DQ.

  The internal data strobe signal DQSI is input to the clock input terminal CK of the flip-flop 18. The data input terminal D of the flip-flop 18 receives data DQ transmitted from the synchronous memory in synchronization with the data strobe signal DQS when reading data. The flip-flop 18 holds the data DQ in synchronization with the rising edge of the internal data strobe signal DQSI and outputs it as received data. In the case of a controller for a DDR (Double Data Rate) type synchronous memory, the data DQ is held in synchronization with not only the rising edge of the internal data strobe signal DQSI but also output as received data.

  Finally, the delay value calculation circuit 16 performs dummy read based on the internal data strobe signal DQSI (DQSI1) output from the AND circuit 14 and the clock signal CLK that is the reference for the operation of the synchronous memory and the memory interface circuit 10. Sometimes, the delay value (actual value) of the data strobe signal DQS with respect to the clock signal CLK is calculated by detecting the level change of the data strobe signal DQS existing in the non-mask period of the delay value calculation mask signal DQS_MASK1.

  Next, the delay value calculation circuit 16 will be described with an example.

  FIG. 2 is a schematic diagram illustrating an example of the configuration of the delay value calculation circuit 16 illustrated in FIG. The delay value calculation circuit 16 shown in FIG. 1 includes a clock delay circuit 20, four flip-flops 22a, 22b, 22c, and 22d, and a 0/1 discrimination circuit 24.

  The clock delay circuit 20 includes four delay elements (for example, buffer circuits) 26a, 26b, 26c, and 26d connected in series. The clock signal CLK is sequentially delayed by delay elements 26a to 26d constituting the clock delay circuit 20, and delayed clock signals CLK1, CLK2, CLK3, and CLK4 are output from the delay elements 26a to 26d, respectively.

  The internal data strobe signal DQSI is input to the data input terminal D of the flip-flops 22a to 22d. Delayed clock signals CLK1 to CLK4 are input to the clock input terminals CK of the flip-flops 22a to 22d, respectively. The internal data strobe signal DQSI is held in each of the flip-flops 22a to 22d in synchronization with the rising edges of the corresponding delay clocks CLK1 to CLK4.

  The output signals of the flip-flops 22a to 22d are input to the 0, 1 discrimination circuit 24. The 0, 1 discrimination circuit 24 calculates the delay value of the internal data strobe signal DQSI with respect to the rising edge of the clock signal CLK based on the output signals of the flip-flops 22a to 22d. From the 0, 1 discrimination circuit 24, the calculated delay value of the internal data strobe signal DQSI, that is, the delay value of the data strobe signal DQS is output.

  As shown in FIG. 1, the internal data strobe signal DQSI is generated by the AND circuit 14 in a mask signal (delay value calculation mask signal) generated by the mask control circuit 12 during a part of the active state of the data strobe signal DQS. DQS_MASK1) is masked. That is, when the mask signal is at L level (mask period), internal data strobe signal DQSI is at L level regardless of data strobe signal DQS.

  On the other hand, when the mask signal is at the H level (non-mask period), the internal data strobe signal DQSI is equivalent to the data strobe signal DQS. The flip-flops 22a to 22d are held at the L level or the H level according to the relationship between the delay time of the data strobe signal DQS with respect to the clock signal CLK and the delay times of the delayed clock signals CLK1 to CLK4.

  The 0, 1 discriminating circuit 24 has a delay value of the internal data strobe signal DQSI with respect to the rising edge of the clock signal CLK, depending on which of the output signals of the flip-flops 22a to 22d is L level and which is H level. That is, the delay value of the data strobe signal DQS is calculated.

  In FIG. 2, for ease of explanation, the number of stages of delay elements constituting the clock delay circuit 20 and the number of flip-flops corresponding thereto are set to 4, but by increasing this number, The detection accuracy of the delay value can be improved.

  Next, the operation of the memory interface circuit 10 will be described with reference to the flowchart of FIG. 3 and the timing chart of FIG.

  The synchronous memory and the memory interface circuit 10 are initialized after power-on or at an arbitrary timing as required (step S1 in FIG. 3).

  In this example, the INIT signal is activated by initialization, and the synchronous memory and the memory interface circuit 10 are set so that burst transfer of 4 cycles is performed at the time of dummy read described later. Note that the setting of burst transfer is not limited to initialization but can be performed in a timely manner before performing dummy reading. The period of data transfer by burst transfer, that is, the number of cycles of level change of the data strobe signal DQS is preferably 4 cycles or more as in this example.

  When the INIT signal is activated by initialization, the mask control circuit 12 is set to generate a delay value calculation mask signal DQS_MASK1 at the time of dummy reading (step S2 in FIG. 3).

  In the example shown in FIG. 4, the delay value calculation mask signal DQS_MASK1 is generated when the data strobe signal DQS received at the time of the dummy read changes in the second and third levels (from the L level to the H level and from the subsequent H level to the L level). Both level change to level) and the first and fourth level changes (either L level to H level and subsequent level change from H level to L level) A period in which the non-mask period is set (in the example of FIG. 4, the delay value calculation mask signal DQS_MASK1 is at the H level) is set.

  FIG. 4 shows a case where the delay time of the data strobe signal DQS is one value within a range between the minimum value and the maximum value. When the delay time of the data strobe signal DQS changes in the range between the maximum value and the minimum value according to the length of wiring on the board, etc., the latter half of the first level change (from H level to L level) Or the first half of the fourth level change (change from L level to H level) may be included in the non-mask period. However, the first change from the L level to the H level and the fourth change from the H level to the L level are not included in the non-mask period within the allowable range of the delay value. That is, the level change from the first L level to H level immediately after the read preamble ends and shifts to the active state, and the level change from the last H level to L level immediately before the active state ends are non- Not included in the mask period.

  In this way, by setting the non-mask period so as to mask the first level change of the data strobe signal DQS in the allowable delay time range (immediately after transition from the read preamble to the active state), A sufficiently long period can be provided between the start of reception of the data strobe signal DQS after transmission of the READ command and the start timing of the non-mask period of the delay value calculation mask signal DQS_MASK1. Therefore, even when the read preamble period is shortened, it is possible to mask the indefinite period before the read preamble with a delay value calculation mask signal DQS_MASK1 with a sufficient margin.

  Similarly, by setting a non-masking period so as to mask the level change at the end of the active state of the data strobe signal DQS (immediately before shifting from the active state to the read postamble) within the allowable delay time range, A sufficiently long period can be provided between the end timing of the non-mask period and the time when the data strobe signal DQS becomes an indefinite period. Therefore, even when the read postamble period is shortened, the indefinite period after the read postamble can be masked with a delay value calculation mask signal DQS_MASK1 with a sufficient margin.

  As described above, since the indefinite period of the data strobe signal DQS is masked with a sufficient margin, it can be prevented that the irregular data strobe signal DQS is taken into the delay value calculation circuit 16 and erroneously recognized. . However, depending on the configuration of the 0, 1 determination circuit 24, it is not always necessary to mask both the first and last level changes in the active state, and it is possible to prevent erroneous recognition by masking only one of them. In some cases.

  Subsequently, a READ command is output from a circuit (not shown) of the memory interface circuit 10 (dummy read is performed). The READ command is transmitted to the synchronous memory and is also input to the mask control circuit 12 (step S3 in FIG. 3).

  When the READ command is transmitted, transmission of the data strobe signal DQS is started by the synchronous memory after a predetermined time has elapsed since the READ command was received. In the example of FIG. 4, the data strobe signal DQS is an active state that repeats the level change between the H level and the L level four times in the cycle of the clock signal CLK after the L level read preamble is output from the inactive state. After an L level read postamble is output through the state, the state returns to the inactive state (Hi-Z state).

  In the memory interface circuit 10, the AND circuit 14 masks the data strobe signal DQS transmitted from the synchronous memory with the delay value calculation mask signal DQS_MASK1 generated by the mask control circuit 12, and outputs the internal data strobe signal DQSI1. Is done. In the example of FIG. 4, the internal data strobe signal DQSI1 has a waveform in which the second and third level changes of the data strobe signal DQS are extracted.

  Subsequently, the delay value calculation circuit 16 calculates the internal data strobe signal DQSI1 with respect to the rising edge of the clock signal CLK, that is, the delay value of the data strobe signal DQS, and feeds back to the mask control circuit 12. (Step S4 in FIG. 3).

  When the dummy read is completed, the INIT signal is deactivated. Thus, the mask control circuit 12 is set so that the read mask signal DQS_MASK2 is output during normal data reading (step S5 in FIG. 3).

  The read mask signal DQS_MASK2 has an indefinite period before and after the data strobe signal DQS masked based on the delay value of the data strobe signal DQS with respect to the clock signal CLK calculated in the dummy read period and the burst length, and in the active state. A period including all level changes is set to be a non-mask period.

  As described above, the non-mask period of the read mask signal DQS_MASK2 is set based on the delay value (actually measured value) of the data strobe signal DQS calculated by performing the dummy read. Regardless, the non-mask period can always be set to the optimum timing.

  At the time of normal data reading thereafter, the data strobe signal DQS transmitted from the synchronous memory is masked by the AND circuit 14 with the read mask signal DQS_MASK2 generated by the mask control circuit 12, and the internal data strobe signal DQSI2 is generated. Is done. In the example of FIG. 4, the internal data strobe signal DQSI2 has a waveform in which all level changes from the first to fourth times of the received data strobe signal DQS are extracted.

  The data DQ transmitted from the synchronous memory in synchronization with the level change of the data strobe signal DQS is sequentially held in the flip-flop 18 in synchronization with the rising edge of the internal data strobe signal DQSI2, and is output as received data. The

  The specific configurations of the mask control circuit 12, the detection circuit (AND circuit 14), and the delay value calculation circuit 16 are not limited at all, and various configurations that can perform the same function can be used.

  In the timing chart of FIG. 4, the data strobe signal DQS at the time of data reading is changed to the inactive state through the active state in which the level change between the H level and the L level is repeated following the L level read preamble. Although an example of returning is shown, the present invention is not limited to this. For example, on the contrary, the H level read preamble may be followed by an active state in which a level change between the L level and the H level is repeated, and then returned to the inactive state.

  Here, the operation of the delay value calculating circuit 16 will be further described with reference to FIGS.

  Although not shown, for example, the internal data strobe signal DQSI1 is supplied to the 0, 1 determination circuit 24, and the signals input from the flip-flops 22a to 22d are sent at the timing of the last rising edge of the data strobe signal DQS. It is possible to hold.

  More specifically, for example, a flip-flop in which each Q output of the flip-flops 22a to 22d is input to the data input terminal is provided in the 0, 1 determination circuit 24, and the internal data strobe signal DQSI1 is input to the clock terminal. To do. Accordingly, the Q outputs of the flip-flops 22a to 22d at the timing of the last rising edge of the internal data strobe signal DQSI1 are held.

  As described above, the delayed clock signals CLK1 to CLK4 sequentially delayed by the delay elements 26a to 26d are supplied to the flip-flops 22a to 22d. In the example of FIG. 4, the delay value calculation mask signal DQS_MASK1 is not masked so as to include two cycles of the change of the data strobe signal DQS from the L level to the H level and the subsequent change from the H level to the L level. A period has been set. In this case, at the timing of the last rising edge of the internal data strobe signal DQSI1, that is, the timing of the second rising edge of the internal data strobe signal DQSI1, the first falling edge of the internal data strobe signal DQSI1 among the flip-flops 22a to 22d. Although the delayed clock signal having the rising edge is supplied before (the second falling edge of the data strobe signal DQS), the Q output is H level, and the Q clock is supplied with the delayed clock signal having the rising edge after that. The output is L level. Therefore, based on the result held at the last rising edge of the internal data strobe signal DQSI1, the first falling edge of the internal data strobe signal DQSI1, that is, the second falling edge of the data strobe signal DQS, The delay time (delay value) from the rising edge can be calculated.

  When the delay value of the data strobe signal DQS further increases from the state shown in FIG. 4, the non-mask period of the delay value calculation mask signal DQS_MASK1 is a part of the period in which the data strobe signal DQS first becomes H level. Comes to include. Even in this case, if the third rising edge of the data strobe signal DQS is included in the non-mask period of the delay value calculation mask signal DQS_MASK1, the second rising edge is performed as in the state shown in FIG. The fall delay time can be calculated.

  Conversely, when the delay value of the data strobe signal DQS is reduced, the non-mask period of the delay value calculation mask signal DQS_MASK1 includes a part of the period when the data strobe signal DQS is at the H level for the fourth time. In this case, the Q outputs of the flip-flops 22a to 22d at the timing of the fourth rising edge of the data strobe signal DQS are held in the flip-flop of the 0, 1 determination circuit 24. Based on this holding result, the delay time of the third falling edge of the data strobe signal DQS with respect to the rising edge of the clock signal can be calculated. That is, as compared with the case shown in FIG. 4, the delay time of the next falling edge can be calculated. However, the rising edge of the clock signal CLK, which is a reference for calculating the delay time, is also one after the case shown in FIG. 4, and is continuous with the state shown in FIG. It is possible to calculate the delay time.

  However, if the delay value of the data strobe signal DQS is further reduced and the non-mask period of the delay value calculation mask signal DQS_MASK1 includes the fourth falling edge of the data strobe signal DQS, the read postamble is short. The subsequent indefinite period cannot be masked, and the delay value calculation circuit 16 may malfunction. In order to prevent this, the non-mask period of the delay value calculation mask signal DQS_MASK1 is set as follows. That is, when the data strobe signal DQS includes an active cycle and includes a change from L level to H level and a subsequent change from H level to L level for m cycles (m is an integer of 2 or more), n Is an integer not less than 1 and not more than m−1, and the delay value of the data strobe signal DQS is within the allowable range, the nth falling edge and the n + 1th rising edge of the data strobe signal DQS And the non-mask period of the delay value calculation mask signal DQS_MASK1 is set so as not to include the mth falling edge. As described above, since the width of the allowable range of the delay value of the data strobe signal DQS is smaller than one cycle of the clock signal CLK, it can be set in this way if m is 3 or more. Since the non-mask period does not include the mth falling edge, the indefinite period after the postamble can be reliably masked even when the postamble period is short. Malfunctions can be prevented.

  If the non-mask period of the delay value calculation mask signal DQS_MASK1 includes the first rising edge of the data strobe signal DQS, the indefinite period before the read preamble may not be masked if the read preamble is short. . However, when holding the Q output of the flip-flops 22a to 22d at the timing of the last rising edge of the internal data strobe signal DQSI1, even if the indefinite period before the read preamble cannot be masked, It will not cause malfunction. However, if m is 4 or more, the non-mask period of the delay value calculation mask signal DQS_MASK1 is set so as not to include the first rising edge regardless of the delay value of the data strobe signal DQS within the allowable range. In addition, the occurrence of malfunction can be prevented more reliably.

  In addition, the internal data strobe signal DQSI is not supplied as it is to the clock terminal of the flip-flop provided in the 0, 1 determination circuit 24 but through the gate circuit only during the period when the gate signal is valid. It is also possible to supply

  The gate signal can be generated as follows using, for example, two flip-flops and one AND gate. That is, the data input terminal of the first flip-flop is fixed to the H level, the Q output is supplied to the data input terminal of the second flip-flop, and the Q output of the first flip-flop is supplied to the positive logic input of the AND gate. The Q output of the second flip-flop is supplied to the negative logic input of the AND gate. Then, following the READ command, both flip-flops are initialized so that their Q outputs become L level, and then the internal data strobe signal DQSI is supplied to the clock terminals (negative logic) of both flip-flops. As a result, a gate signal that is valid (H level) only from the first falling edge to the second falling edge of the internal data strobe signal DQSI can be output from the AND gate.

  Then, another AND gate is used as a gate circuit, a gate signal and an internal data strobe signal DQSI are supplied to its input terminal (positive logic), and its output is used as a clock of the flip-flop of the 0, 1 decision circuit 24. Supply to the terminal. Accordingly, the Q outputs of the flip-flops 22a to 22d can be held at the timing of the rising edge sandwiched between the first falling edge and the second falling edge of the internal data strobe signal DQSI. At this timing, among the flip-flops 22a to 22d, although the delayed clock signal having the rising edge is supplied before the first falling edge of the internal data strobe signal DQSI1, the Q output has the H level and the rising edge after that. Although the delayed clock signal is supplied, the Q output is L level. Therefore, the delay time from the rising edge of the clock signal of the first falling edge of the internal data strobe signal DQSI 1 can be calculated based on the result held in the flip-flop of the 0, 1 determination circuit 24.

  In this case, if the non-mask period of the delay value calculation mask signal DQS_MASK1 includes the first rising edge of the data strobe signal DQS, if the preamble period is short, the indefinite period before the preamble cannot be masked. The delay value calculation circuit 16 may malfunction. Therefore, when n is an integer not less than 1 and not more than m−1, the first rising edge of the data strobe signal DQS is not included, regardless of the delay value of the data strobe signal DQS within the allowable range, and , The non-mask period of the delay value calculation mask signal DQS_MASK1 is set so as to include the nth and n + 1th falling edges. Since the width of the allowable range of the delay value of the data strobe signal DQS is smaller than one cycle of the clock signal CLK, it can be set in this way if m is 3 or more. Since the non-mask period of the delay value calculation mask signal DQS_MASK1 does not include the first rising edge of the data strobe signal DQS, even if the preamble period is short, the indefinite period before that is reliably masked, Malfunctions can be prevented.

  If the non-mask period of the delay value calculation mask signal DQS_MASK1 includes the mth falling edge of the data strobe signal DQS, the indefinite period after the postamble cannot be masked if the postamble period is short. there is a possibility. However, even if the indefinite period after the postamble cannot be masked by supplying the internal data strobe signal DQSI to the flip-flop of the 0, 1 decision circuit 24 only during the period when the gate signal is valid, the malfunction occurs. Can be prevented. However, if m is 4 or more, the non-mask period of the delay value calculation mask signal DQS_MASK1 is set so as not to include the mth falling edge regardless of the delay value of the data strobe signal DQS within the allowable range. It is possible to prevent the occurrence of malfunction even more reliably.

  In the example shown in FIG. 1, the level of the internal data strobe signal DQSI at the timing of the rising edge of the delayed clock signals CLK1 to CLK4 is held using the flip-flops 22a to 22d having the positive logic clock input terminal CK. doing. On the other hand, it is also possible to hold the level of the internal data strobe signal DQSI at the timing of the falling edges of the delayed clock signals CLK1 to CLK4 using the flip-flops 22a to 22d having the negative logic clock input terminal CK. It is. In this case, it is possible to calculate the delay value of the data strobe signal DQS from the falling edge of the clock signal CLK.

  Further, when the data strobe signal DQS includes an active state in which a change from the H level to the L level and a subsequent change from the L level to the H level are repeated a plurality of cycles between the H level preamble and the postamble. Even so, the delay value of the data strobe signal DQS can be calculated by appropriately setting the non-mask period of the delay value calculation mask signal DQS_MASK1.

The present invention is basically as described above.
Although the present invention has been described in detail above, the present invention is not limited to the above-described embodiment, and it is needless to say that various improvements and modifications may be made without departing from the gist of the present invention.

DESCRIPTION OF SYMBOLS 10 Memory interface circuit 12 Reading mask control circuit 14 AND circuit 16 Delay value calculation circuit 18, 22a, 22b, 22c, 22d Flip-flop 20 Clock delay circuit 24 0,1 discrimination circuit 26a, 26b, 26c, 26d Delay element

Claims (2)

When the READ command is received, the change from the first level to the second level in the cycle of the clock signal from the inactive state and the subsequent change from the second level to the first level are repeated. A data strobe signal that returns to an inactive state through an active state is transmitted, and the READ command is transmitted to a synchronous memory that transmits data in synchronization with a level change of the data strobe signal, and the data strobe signal is A memory interface circuit for receiving and reading the data in synchronization with a level change of the data strobe signal;
A detection circuit for detecting a level change of the data strobe signal and controlling a timing of reading the data;
A read mask control circuit that generates a read mask signal that prohibits detection by the detection circuit except for a non-mask period;
A delay value calculation circuit for detecting a level change of the data strobe signal and calculating a delay value of the data strobe signal with respect to the clock signal;
The mask control circuit further includes a delay value calculation mask for prohibiting detection by the delay value calculation circuit except for a non-mask period including only a part of the active state after a predetermined time from the READ command transmission. Generating a read mask signal based on the delay value of the data strobe signal calculated by the delay value calculation circuit using the delay value calculation mask signal ,
The non-mask period of the delay value calculation mask signal is within an allowable range of the delay time from the transmission of the READ command to the reception of the data strobe signal. A memory interface circuit characterized by not including at least one of a change from the first first level to the second level and a level change from the last second level to the first level . The non-mask period of the delay value calculation mask signal is within an allowable range of the delay time from the transmission of the READ command to the reception of the data strobe signal. 2. The memory interface circuit according to claim 1, wherein both the change from the first first level to the second level and the level change from the last second level to the first level are not included. .

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