JP2012212385A - Memory interface control circuit and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory interface control circuit for eliminating a data strobe signal DQS having a denormalized wave form due to noise and the like so as to be capable of normal data access without an increase in a circuit scale.SOLUTION: A memory interface control circuit includes: a data strobe signal verification circuit for receiving a data strobe signal that makes a notification of a timing when a DDR SDRAM transfers data and, when an abnormal wave form is detected in the data strobe signal, outputting a data initialization signal; a holding circuit for holding a data signal output from the DDR SDRAM with the data strobe signal activated and, when the data initialization signal is received, performing initialization of the held data; and a FIFO circuit for temporarily taking in the data output by the holding circuit and outputting the taken data to the outside.

Description

  The present invention relates to a memory interface control circuit and a semiconductor integrated circuit. In particular, the present invention relates to a memory interface control circuit that performs access control to a DDR SDRAM (Double Data Rate Synchronous DRAM).

  In recent years, DDR SDRAM having a high-speed data transfer function called a double data rate mode has become widespread. In the double data rate mode, data can be read and written at the rising and falling edges of the clock, so that data can be input and output at high speed. Non-Patent Document 1 defines a standard for data reading and writing of DDR SDRAM.

  Here, data access between the DDR SDRAM and the system LSI defined in Non-Patent Document 1 will be described. FIG. 2 is an example of a timing chart showing an operation when data output from the DDR SDRAM is read out by the system LSI. At time T2 in FIG. 2, a read command is issued from the system LSI to the DDR SDRAM. The DDR SDRAM that has received the read command sets the data strobe signal DQS to the L level at time T7. The data strobe signal DQS is a signal output from the DDR SDRAM, and is a signal output to inform the system LSI of the data transfer timing.

  The period from when the DDR SDRAM receives the read command to when the data strobe signal DQS is set to the L level is called read latency. This read latency can be changed by setting the DDR SDRAM. The data strobe signal DQS set to L level at time T7 is maintained at L level until time T9. The period in which the L level is continued is called a preamble period. There is no definition for the data strobe terminal (input / output terminal of the data strobe signal DQS) before the preamble period, and it can be set to an arbitrary state. Therefore, a high impedance state can be set. After maintaining data strobe signal DQS at L level until time T9, the logical level of data strobe signal DQS changes alternately. The number of logical level changes coincides with the data length read from the DDR SDRAM by one read command. That is, the burst length in the burst transfer and the number of toggles of the data strobe signal DQS match. The burst length can also be changed by setting the DDR SDRAM. The data strobe signal DQS toggles the number of times corresponding to the burst length, and then goes to the L level (time T12). Thereafter, data strobe signal DQS is maintained at the L level until time T13. The period during which data strobe signal DQS is maintained at the L level is called a postamble period. Even after the postamble period, the data strobe terminal can be set to an arbitrary state. Of course, a high impedance state can also be set. The access procedure between the DDR SDRAM and the system LSI is defined as a standard by the JEDEC Semiconductor Technology Association. Therefore, a general-purpose DDR SDRAM is designed and produced according to this standard.

  Next, the read operation of the system LSI that controls the DDR SDRAM will be described. The system LSI is designed to capture the data signal DQ at the rising and falling edges of the data strobe signal DQS. However, as described above, the data strobe signal DQS can be set to an arbitrary state before the preamble period or after the post-amble period. Therefore, in a high impedance state, a pulse waveform (glitch noise) at a level that can be recognized by the system LSI may occur in the data strobe signal DQS due to the influence of noise. As a result, unnecessary data that is not to be captured in the system LSI is captured by the system LSI, which may cause malfunction of the system LSI. In order to solve this problem, the mask signal MASK is generated inside the system LSI, and the data strobe signal DQS is masked by the mask signal MASK during the period when the data strobe signal DQS is not required (the period when the DDR SDRAM is not accessed). Avoid the effects of noise. In FIG. 2, the level of the mask signal MASK is changed during the preamble period (time T7 to T9) and the post-preamble period (time T12 to T13), and the data strobe signal DQS is validated inside the system LSI. Only during the read period of FIG. 2, the masking of the data strobe signal DQS is cancelled.

  However, the design of the mask signal MASK has become difficult as the speed of the DDR SDRAM increases. This is because when the speed of the DDR SDRAM is increased, the period (preamble period and post-preamble period) in which the change of the mask signal MASK is allowed is shortened. In particular, the release of the mask signal MASK needs to be determined during the preamble period, but the mask release timing of the mask signal MASK during this period is determined based only on the known time (access timing) such as the read latency and the preamble period. It is not possible. This is because it is necessary to design the release timing of the mask signal MASK in consideration of individual differences in the mass-produced DDR SDRAM and variations in the resistance value of the wiring (transmission path) between the DDR SDRAM and the system LSI.

  Here, in Patent Document 1, a memory that individually measures the data strobe signal DQS output from the DDR SDRAM and the delay time of the data signal DQ, and optimally adjusts the change timing of the data strobe signal DQS based on the measurement result. An interface control circuit is disclosed. By adjusting the change timing of the data strobe signal DQS, the data strobe signal DQS can be accurately masked, and the glitch noise resistance of the data strobe signal DQS is improved. In addition, restrictions on the layout of the DDR SDRAM are eased by improving the glitch noise resistance.

Japanese Patent No. 4284527

JEDEC STANDARD DDR2 SDRAM Specification, JESD79-2F, November 2009, JEDEC SOLID STATE TECHNOLOGY ASSOCIATION

  Each disclosure of the above prior art document is incorporated herein by reference. The following analysis has been made from the viewpoint of the present invention.

  The memory interface control circuit disclosed in Patent Document 1 can release the mask signal at an appropriate timing, but has a problem that the circuit scale increases. In order to release the mask signal at an appropriate timing, a circuit (variable) that generates a delay equivalent to the delay value from when the system LSI issues a read command until the response of the data strobe signal DQS and the data signal DQ is returned. This is because it is necessary to provide a delay circuit in the memory interface control circuit.

  FIG. 3 of FIG. 3 of Non-Patent Document 1 is shown. FIG. 3 (FIG. 53 of Non-Patent Document 1) is a timing chart when data is read from the DDR SDRAM. As described above, the DDR SDRAM must be designed based on the standard described in Non-Patent Document 1. Therefore, the application of the technique disclosed in Patent Document 1 is verified with respect to a DDR SDRAM designed in accordance with this standard.

  FIG. 3 shows the access timing when the read latency is 4 clocks. Therefore, it is determined that the read latency is 4 clocks, and the delay amount required by the memory interface circuit disclosed in Patent Document 1 is calculated. In this case, if the basic clock is 200 MHz, the period of one clock is 5.0 ns, so that a delay amount of 20 ns (5.0 ns × 4) is required. Therefore, the memory interface circuit disclosed in Patent Document 1 needs to include an element that delays a signal by 20 ns. Furthermore, since the delay amount (delay time) needs to be designed so as not to be affected by changes in the ambient temperature and power supply voltage of the system LSI including the memory interface control circuit, the above-described variable delay circuit has several K to several The gate scale of about 10K is necessary, and the problem that the scale of the variable delay circuit increases occurs. Therefore, there is a demand for a memory interface control circuit and a semiconductor integrated circuit that eliminates the data strobe signal DQS having an irregular waveform due to the influence of noise or the like without increasing the circuit scale and enables normal data access. .

  According to a first aspect of the present invention, a data strobe signal notifying the timing at which the memory transfers data is received, and when an abnormal waveform is detected in the data strobe signal, a data initialization signal is output, When no abnormal waveform is detected in the data strobe signal, a data strobe signal verification circuit that outputs a data capture permission signal and an output while holding the data signal output from the memory when the data strobe signal is activated When the data initialization signal is received, a holding circuit that initializes the held data and the data output from the holding circuit are temporarily captured, and when the data initialization signal is received, the data is captured. If the data acquisition permission signal is received after initializing the data, the acquired data Memory interface control circuit comprising a FIFO circuit for outputting to the outside, is provided.

  According to a second aspect of the present invention, a semiconductor integrated circuit including the above-described memory interface control circuit is provided.

  According to each aspect of the present invention, a memory interface control circuit that eliminates the data strobe signal DQS having an irregular waveform due to the influence of noise or the like without increasing the circuit scale, and enables normal data access, and A semiconductor integrated circuit is provided.

It is a figure for demonstrating the outline | summary of embodiment of this invention. 6 is an example of a timing chart showing an operation when data output from a DDR SDRAM is read out by a system LSI. 6 is a timing chart at the time of data reading disclosed in Non-Patent Document 1. 1 is a diagram illustrating an example of a connection between a system LSI including a memory interface control circuit according to a first embodiment of the present invention and a DDR SDRAM. FIG. 3 is a diagram showing an example of an internal configuration of a memory interface control circuit according to the first embodiment of the present invention. FIG. 6 is a diagram showing an example of an internal configuration of a data strobe signal verification circuit shown in FIG. 5. It is a figure which shows an example of an internal structure of the waveform missing detection circuit shown in FIG. FIG. 7 is a diagram showing an example of an internal configuration of a redundant waveform detection circuit shown in FIG. 6. It is a figure which shows an example of an internal structure of the H pulse detection circuit shown in FIG. It is a figure which shows an example of an internal structure of the L pulse detection circuit shown in FIG. FIG. 7 is a diagram illustrating an example of an internal configuration of a DQS counter circuit illustrated in FIG. 6. 3 is an example of a timing chart showing an operation of the memory interface control circuit according to the first embodiment. 6 is an example of a timing chart showing another operation of the memory interface control circuit according to the first embodiment.

  First, the outline of the embodiment will be described with reference to FIG. Note that the reference numerals of the drawings attached to this summary are attached to the respective elements for convenience as an example for facilitating understanding, and are not intended to limit the present invention to the illustrated embodiment.

  As described above, the memory interface control circuit disclosed in Patent Document 1 requires a large-scale control circuit in order to obtain an accurate data strobe signal DQS. Therefore, it is desired to provide a memory interface control circuit that allows normal data access by eliminating the data strobe signal DQS having an irregular waveform due to the influence of noise or the like without increasing the circuit scale.

  Accordingly, the memory interface control circuit shown in FIG. 1 is provided as an example. The memory interface control circuit shown in FIG. 1 accepts a data strobe signal DQS that notifies the timing when the DDR SDRAM transfers data, and outputs a data initialization signal when an abnormal waveform is detected in the data strobe signal DQS. When an abnormal waveform is not detected in the data strobe signal DQS, the data strobe signal verification circuit that outputs a data capture permission signal and the data strobe signal DQS are activated (input of a rising edge after the preamble period has elapsed). A data signal output from the SDRAM is held, and when a data initialization signal is received, a holding circuit for initializing the held data, and data output from the holding circuit are temporarily fetched, and a data initialization signal is received. If accepted, the initial data And a FIFO circuit for outputting the fetched data to the outside when a data fetch permission signal is received.

  The data strobe signal verification circuit verifies the waveform of the input data strobe signal DQS from various angles, and outputs a data initialization signal if the data strobe signal DQS has a nonstandard waveform. The holding circuit holds the data signal DQ while the data strobe signal verification circuit verifies the validity of the data strobe signal DQS, and outputs data to the FIFO circuit at the next stage. The data strobe signal verification circuit outputs a data capture permission signal when the validity of the input data strobe signal DQS can be confirmed. When the FIFO circuit receives the data capture permission signal, it outputs the data captured from the holding circuit to the outside.

  By using such a memory interface control circuit, based on the data strobe signal DQS which is the input data strobe signal DQS and whose validity can be confirmed (not abnormal) without masking the data strobe signal DQS. Data can be read out.

[First Embodiment]
Next, the first embodiment of the present invention will be described in more detail with reference to the drawings. FIG. 4 is a diagram showing an example of the connection between the system LSI 1 including the memory interface control circuit 10 according to the present embodiment and the DDR SDRAM 2. In the data transfer system shown in FIG. 4, the DDR SDRAM 2 outputs a data signal DQ, a data strobe signal DQS indicating the timing for transferring the data signal DQ, and an inverted data strobe signal DQSB. On the other hand, the system LSI 1 outputs a memory clock CK that is a basic clock of the DDR SDRAM 2 and a command signal CMD for the DDR SDRAM 2. The operation mode (read mode, write mode, etc.) of the DDR SDRAM 2 is determined by the command signal CMD.

  The system LSI 1 is a semiconductor integrated circuit that incorporates a memory interface control circuit 10. The memory interface control circuit 10 controls the DDR SDRAM 2 and the above-described signals (DQ, DQS, DQSB, CK, CMD). In addition, the memory interface control circuit 10 has an inverted standby signal STBYB generated inside the system LSI 1, a read command signal READ, a system clock CLK that is a basic clock of the system LSI 1, and a frequency twice that of the system clock CLK. The system receives a double system clock X2CLK and a quadruple system clock X4CLK having a frequency four times that of the system clock CLK. The inverted standby signal STBYB will be described later.

  Further, the data read from the DDR SDRAM 2 to the internal circuit of the system LSI 1 from the memory interface control circuit 10 and read from the DDR SDRAM 2 and the even-numbered data output signal OUT_DATA_E which is the even-numbered read data in the burst transfer. Data output signal OUT_DATA_O that is odd-numbered read data.

  Next, the memory interface control circuit 10 will be described. FIG. 5 is a diagram illustrating an example of the internal configuration of the memory interface control circuit 10. The memory interface control circuit 10 shown in FIG. 5 includes IO buffers 11 and 12, an AND circuit AND01, a variable delay circuit 13, flip-flops FF01 to FF03, a FIFO circuit 14, and a data strobe signal verification circuit 15. Has been.

  The IO buffer 11 is an input buffer that receives the data signal DQ read from the DDR SDRAM 2. The IO buffer 12 is an input buffer that receives data strobe signals (DQS, DQSB) output from the DDR SDRAM 2. Note that the IO buffers 11 and 12 may have an output operation.

  The AND circuit AND01 receives a signal obtained by inverting the logic of the output signal of the IO buffer 12 and the data strobe detection signal DQS_OK output from the data strobe signal verification circuit 15. The data strobe detection signal DQS_OK is a signal indicating that the data strobe signal verification circuit 15 has detected a normal data strobe signal DQS. The operation result in the AND circuit AND01 is output to the variable delay circuit 13 and the data strobe signal verification circuit 15.

  The variable delay circuit 13 receives the output of the IO buffer 12 via the AND circuit AND01, and a data strobe signal DQS90 having a phase difference of 90 degrees with respect to the data strobe signal DQS and 270 degrees with respect to the data strobe signal DQS. A data strobe signal DQS 270 having a phase difference of is output.

  The flip-flops FF01 to F03 are flip-flops with a reset terminal. The data signal DQ is input via the IO buffer 11 to the data input of the flip-flop FF01. The data strobe signal DQS90 is input to the clock of the flip-flop FF01, and the read data reset signal DRST output from the data strobe signal verification circuit 15 is input to the reset terminal RB. The read data reset signal DRST is a signal for initializing data read from the DDR SDRAM 2. The data output of the flip-flop FF01 becomes the data input of the flip-flop FF03.

  The data strobe signal DQS270 is input to the clock of the flip-flop FF03, and the read data reset signal DRST is input to the reset terminal RB. The data output of the flip-flop FF03 is a DATA_O signal for the FIFO circuit.

  The data signal DQ is input to the data input of the flip-flop FF02 via the IO buffer 11. The data strobe signal DQS270 is input to the clock of the flip-flop FF02, and the read data reset signal DRST is input to the reset terminal RB. The data output of the flip-flop FF02 becomes a DATA_E signal for the FIFO circuit 14.

  The FIFO circuit 14 includes a data output (DATA_E) of the flip-flop FF02, a data output (DATA_O) of the flip-flop FF03, a data strobe signal DQS270, a read data reset signal DRST, a data strobe detection signal DQS_OK, and a system clock CLK. As an input signal. Furthermore, the FIFO circuit 14 outputs the even-numbered data output signal OUT_DATA_E and the odd-numbered data output signal OUT_DATA_O.

  The data strobe signal verification circuit 15 is a circuit that detects whether or not the received data strobe signal DQS is a normal signal. Specifically, the data strobe signal DQS input to the data strobe signal verification circuit 15 is not adopted as long as it violates the standard defined in Non-Patent Document 1 described above. For example, if the period in which the data strobe signal DQS input to the data strobe signal verification circuit 15 is to be maintained at the L level or H level is inconsistent with the standard, such a data strobe signal DQS is treated as a normal signal. Absent. The read data fetched according to the data strobe signal determined as such an abnormal data strobe signal DQS is discarded. A signal for this is the read data reset signal DRST.

  Read data taken in accordance with the data strobe signal DQS in which no abnormality is detected in the data strobe signal verification circuit 15 is output to the system LSI 1 as normal data. The signal for this is the data strobe detection signal DQS_OK. The activation and deactivation of the data strobe signal verification circuit 15 is determined by the inverted standby signal STBYB that is a signal generated inside the system LSI 1.

  FIG. 6 is a diagram illustrating an example of an internal configuration of the data strobe signal verification circuit 15. The data strobe signal verification circuit 15 includes inverters INV01 and INV02, AND circuits AND02 to AND04, a waveform missing detection circuit 100, a redundant waveform detection circuit 200, an H pulse detection circuit 300, an L pulse detection circuit 400, It consists of a DQS counter 500.

  The inverter INV01 receives the data strobe detection signal DQS_OK output from the DQS counter 500, and outputs an inverted signal to the AND circuit AND02.

  The AND circuit AND02 receives the data strobe detection signal DQS_OK and the inverted standby signal STBYB as input signals. The output signal of the AND circuit AND02 is output as a DSETB signal to each circuit of the waveform missing detection circuit 100, the redundant waveform detection circuit 200, the H pulse detection circuit 300, the L pulse detection circuit 400, and the AND circuit AND03.

  The DSETB signal and the data strobe signal DQS90 are input to the AND circuit AND03. The output signal of the AND circuit AND03 is output to the DQS counter 500 as a DQS90C signal.

  The missing waveform detection circuit 100 receives the data strobe signal DQS, the quadruple system clock X4CLK, and the DSETB signal. The waveform loss detection circuit 100 outputs an HFLG signal. The HFLG signal is a flag signal indicating that the waveform of the input data strobe signal DQS is missing.

  The redundant waveform detection circuit 200 receives the data strobe signal DQS, the quadruple system clock X4CLK, and the DSETB signal. The redundant waveform detection circuit 200 outputs an LFLG signal. The LFLG signal is a flag signal indicating that the waveform of the input data strobe signal DQS is redundant.

  To the H pulse detection circuit 300, the data strobe signal DQS, the double system clock X2CLK, the DSETB signal, and the data strobe signal DQS90 are input. An HPFLG signal is output from the H pulse detection circuit 300. The HPFLG signal is a flag signal indicating that the H level period of the input data strobe signal DQS is shorter than the standard value.

  The L pulse detection circuit 400 receives the data strobe signal DQS, the double system clock X2CLK, the DSETB signal, and the data strobe signal DQS90. The LPFLG signal is output from the L pulse detection circuit 400. The LPFLG signal is a flag signal indicating that the L level period of the input data strobe signal DQS is shorter than the standard value.

  When each of the above flag signals (HFLG signal, LFLG signal, HPFLG signal, LPFLG signal) is at an H level, each detection circuit does not detect an abnormal waveform, and each detection circuit has an L level flag signal. Means that an abnormal waveform of the data strobe signal DQS is detected.

  The AND circuit AND04 receives the above-described flag signals (HFLG signal, LFLG signal, HPFLG signal, LPFLG signal) as input signals. The AND circuit AND04 outputs the operation result to the DQS counter 500 and the inverter INV02 as an RSTB signal.

  The output signal of the inverter INV02 is output from the data strobe signal verification circuit 15 as the read data reset signal DRST.

  The DQS counter circuit 500 receives the RSTB signal output from the AND circuit AND04, the DQS90C signal output from the AND circuit AND03, and the read command signal READ. The DQS counter circuit 500 outputs a data strobe detection signal DQS_OK.

  As described above, the data strobe signal verification circuit 15 includes four detection circuits, and verifies the validity of the data strobe signal DQS input to each detection circuit. When an abnormality is detected in any of the detection circuits, a flag signal is output and is combined into a read data reset request (RSTB signal and DRST signal) in the AND circuit AND04.

  On the other hand, if each detection circuit does not detect an abnormality, the DQS counter 500 checks whether the data strobe signal DQS 90 has been toggled by the number of times corresponding to the burst length. As a result of the confirmation, when the data strobe signal DQS90 is toggled as many times as necessary, the data strobe detection signal DQS_OK is output.

  In accordance with the read data reset signal DRST and data strobe detection signal DQS_OK output from the data strobe signal verification circuit 15, the flip-flops FF01 to FF03 and the FIFO circuit 14 in FIG. 2 initialize the data or read the data read from the DDR SDRAM 2 into the system Transmit to the inside of the LSI 1.

  Next, each detection circuit and the DQS counter 500 will be described. FIG. 7 is a diagram illustrating an example of an internal configuration of the waveform loss detection circuit 100. The missing waveform detection circuit 100 includes an inverter INV03, an AND circuit AND05, an OR circuit OR01, and flip-flops FF04 to FF07. The flip-flop FF04 is a flip-flop with a reset terminal, and the flip-flops FF05 to FF07 are flip-flops with a set terminal.

  The inverter INV03 receives the data strobe signal DQS and outputs the inverted signal to the AND circuit AND05.

  The AND circuit AND05 receives the output signal of the inverter INV03 and the DSETB signal as input signals. The output signal of the AND circuit AND05 is input to each set terminal SB of the flip-flops FF05 to FF07.

  The data strobe signal DQS is input to the data input of the flip-flop FF04, and the data output is the data input of the flip-flop FF05. The DSETB signal is input to the reset terminal RB of the flip-flop FF04.

  The flip-flop FF05 uses the data output of the flip-flop FF04 as a data input. The data output of the flip-flop FF05 is used as the data input of the flip-flop FF06 and the output to the OR circuit OR01. The flip-flop FF06 uses the data output of the flip-flop FF05 as a data input. The data output of the flip-flop FF06 is used as the data input of the flip-flop FF07 and the output to the OR circuit OR01. The flip-flop FF07 uses the data output of the flip-flop FF06 as a data input. The data output of the flip-flop FF07 is used as an output for the OR circuit OR01. The quadruple system clock X4CLK is input to the clocks of the flip-flops FF04 to FF07.

  The data output of the flip-flops FF05 to FF07 is input to the OR circuit OR01, and the operation result is output as the HFLG signal.

  Next, the redundant waveform detection circuit 200 will be described. FIG. 8 is a diagram illustrating an example of an internal configuration of the redundant waveform detection circuit 200. The redundant waveform detection circuit 200 includes a logical product circuit AND06, a negative logical product circuit NAND01, and flip-flops FF08 to FF11. The flip-flops FF08 to FF11 are flip-flops with a reset terminal.

  The data strobe signal DQS and the DSETB signal are input to the AND circuit AND06. The output signal of the AND circuit AND06 is input to each reset terminal RB of the flip-flops FF09 to FF11.

  The data strobe signal DQS is input to the data input of the flip-flop FF08, and the data output is output to the data input of the flip-flop FF09. The DSETB signal is input to the reset terminal RB of the flip-flop FF08.

  The flip-flop FF09 uses the data output of the flip-flop FF08 as a data input. The data output of the flip-flop FF09 is used as the data input of the flip-flop FF10 and the output to the NAND circuit NAND01. The flip-flop FF10 uses the data output of the flip-flop FF09 as a data input. The data output of the flip-flop FF10 is used as the data input of the flip-flop FF11 and the output to the NAND circuit NAND01. The flip-flop FF11 uses the data output of the flip-flop FF10 as a data input. The data output of the flip-flop FF11 is used as an output for the NAND circuit NAND01. The quadruple system clock X4CLK is input to the clocks of the flip-flops FF08 to FF11.

  The NAND circuit NAND01 receives the data output of the flip-flops FF09 to FF11 and outputs the calculation result as an LFLG signal.

  Next, the H pulse detection circuit 300 will be described. FIG. 9 is a diagram illustrating an example of the internal configuration of the H pulse detection circuit 300. The H pulse detection circuit 300 includes an inverter INV04, an AND circuit AND07, and a flip-flop FF12. The flip-flop FF12 is a flip-flop with a set terminal.

  Inverter INV04 receives data strobe signal DQS and outputs an inverted signal to AND circuit AND07.

  The AND circuit AND07 receives the output of the inverter INV04 and the DSETB signal as input signals. The output of the AND circuit AND07 is input to the set terminal SB of the flip-flop FF12.

  The data strobe signal DQS is input to the data input of the flip-flop FF12, and the data strobe signal DQS90 is input to the clock. The data output of the flip-flop FF12 is output as an HPFLG signal.

  Next, the L pulse detection circuit 400 will be described. FIG. 10 is a diagram illustrating an example of an internal configuration of the L pulse detection circuit 400. The L pulse detection circuit 400 includes inverters INV05 and INV06, an AND circuit AND08, and a flip-flop FF13. The flip-flop FF13 is a flip-flop with a set terminal.

  The inverter INV05 receives the data strobe signal DQS and outputs an inverted signal to the data input of the flip-flop FF13.

  A data strobe signal DQS90 is input to the inverter INV06, and an inverted signal is output to the clock of the flip-flop FF13.

  The AND circuit AND08 receives the data strobe signal DQS and the DSETB signal as input signals. The output of the AND circuit AND08 is input to the set terminal SB of the flip-flop FF13.

  An inverted signal of the data strobe signal DQS is input to the data input of the flip-flop FF13, and an inverted signal of the data strobe signal DQS90 is input to the clock. The data output of the flip-flop FF13 is output as an LPFLG signal.

  Next, the DQS counter circuit 500 will be described. FIG. 11 is a diagram showing an example of the internal configuration of the DQS counter circuit 500. As shown in FIG. The DQS counter circuit 500 includes inverters INV07 and INV08, an AND circuit AND09, an exclusive OR circuit XOR01, and flip-flops FF14 and FF15. Note that the flip-flops FF14 and FF15 are flip-flops with a reset terminal.

  A read command signal READ is input to the inverter INV07, and an inverted signal is input to the AND circuit AND09. The output signal of the inverter INV07 and the RSTB signal are input to the AND circuit AND09.

  The output of the AND circuit AND09 is input to the reset terminals RB of the flip-flops FF14 and FF15. The output signal of the inverter INV08 is input to the data input of the flip-flop FF14.

  The data output of the flip-flop FF14 is input to the inverter INV08 and the exclusive OR circuit XOR01.

  The exclusive OR circuit XOR01 receives the data outputs of the flip-flops FF14 and FF15, and outputs the operation result to the data input of the flip-flop FF15.

  The output of the exclusive OR circuit XOR01 is input to the data input of the flip-flop FF15, and the data output is output as the data strobe detection signal DQS_OK. The data strobe signal DQS90C is inverted and input to the clocks of the flip-flops FF14 and F15.

  Next, the operation of the memory interface control circuit 10 will be described. FIG. 12 is an example of a timing chart showing the operation of the memory interface control circuit 10 according to the present embodiment. FIG. 12 shows an operation when the captured data is initialized by detecting the abnormality of the input data strobe signal DQS by the waveform loss detection circuit 100 and then data of a predetermined burst length is captured. FIG. 12 is a timing chart when the burst length is 4.

  At time T2 in FIG. 12, the data strobe signal verification circuit 15 sets the data strobe detection signal DQS_OK to L level immediately after receiving the read command signal READ. In addition, after the read command signal READ becomes active, the H level inverted standby signal STBYB is input to the data strobe signal verification circuit 15 at time T5, whereby the data strobe signal verification circuit 15 is activated. Thereafter, when the data strobe signal DQS is input within the period of time T5 and T6, the flip-flop FF01 of the interface control circuit 10 takes in the state DX of the data signal DQ at the rising edge of the data strobe signal DQS90. Further, at time T7, the flip-flops FF02 and FF03 capture the data signal DQ at the rising edge of the data strobe signal DQS270, respectively.

  However, according to the DDR SDRAM standard, the data strobe signal DQS needs to rise within the period of time T7 and T8, but it remains at the L level. Therefore, the waveform loss detection circuit 100 sets the HFLG signal to L level on the assumption that there is an abnormality in the input data strobe signal DQS. As a result, an H level read data reset signal DRST is output from the data strobe signal verification circuit 15 (time T8). In response to the read data reset signal DRST, the flip-flops FF01 to FF03 initialize the stored data.

  Next, at time T9, the rising edge of the data strobe signal DQS is input again to the data strobe signal verification circuit 15, and the data strobe signal verification circuit 15 sets the read data reset signal DRST to the L level. The flip-flop FF01 whose reset is released takes in the state D1 of the data signal DQ at the rising edge of the data strobe signal DQS90. Further, the flip-flop FF02 takes in the state D2 of the data signal DQ at the rising edge of the data strobe signal DQS270. Further, the flip-flop FF03 accepts the input of data taken in by the flip-flop FF01 at the rising edge of the data strobe signal DQS270. Through the above operation, the DATA_E signal output from the flip-flop FF02 and the DATA_O signal output from the flip-flop FF03 are simultaneously output.

  The FIFO circuit 14 takes in the DATA_O signal and the DATA_E signal while maintaining the data order.

  Next, the rising edge of the second data strobe signal DQS is input to the data strobe signal verification circuit 15 at time T11, and the states D3 and D4 of the data signal DQ are input to the FIFO circuit 14 as in the operation at time T9. It is captured. Since the second data strobe signal DQS is input at time T11, the waveform loss detection circuit 100 does not detect any abnormality. At the same time, the abnormality of the data strobe signal DQS is not detected by other detection circuits (redundant waveform detection circuit 200, H pulse detection circuit 300, L pulse detection circuit 400). This is because the input data strobe signal DQS has a waveform according to the standard.

  When the falling edge of the data strobe signal DQS90C is counted twice in the DQS counter circuit 500, the data strobe detection signal DQS_OK is output from the data strobe signal verification circuit 15 at the rising edge of the quadruple system clock X4CLK immediately after time T12. . When this data strobe detection signal DQS_OK is output, the FIFO circuit 14 synchronizes the state (D1 to D4) of the data signal DQ taken in with the system clock CLK, and the data output signal OUT_DATA_E and the data output signal for the odd number of times. Output to the system LSI 1 as OUT_DATA_O. The data strobe signal verification circuit 15 receives the inverted standby signal STBYB and transitions to an inactive state (time T20).

  Next, operations of the redundant waveform detection circuit 200, the H pulse detection circuit 300, and the L pulse detection circuit 400 will be described. FIG. 13 is an example of a timing chart when the detection circuits of the redundant waveform detection circuit 200, the H pulse detection circuit 300, and the L pulse detection circuit 400 detect an abnormality in the data strobe signal DQS.

  In the period from time T1 to time T6 in FIG. 13, the input of the data strobe signal DQS is detected, but the data strobe signal DQS is not input thereafter, and the data held in the flip-flops FF01 to FF03 by the read data reset signal DRST. Has been destroyed. That is, this is an operation when the waveform loss detection circuit 100 detects an abnormality in the data strobe signal DQS. Since this operation is already described with reference to FIG. In the period from time T1 to time T6, each of the detection circuits of the redundant waveform detection circuit 200, the H pulse detection circuit 300, and the L pulse detection circuit 400 does not detect an abnormal waveform.

  A period from time T6 to time T9 in FIG. 13 is a timing chart when the redundant waveform detection circuit 200 detects an abnormality in the input data strobe signal DQS. The data strobe signal DQS transits to H level at time T6, but does not transit to L level even at time T7. Since the period during which the H level of the data strobe signal DQS continues exceeds the standard value, the redundant waveform detection circuit 200 detects an abnormality. As a result, the redundant waveform detection circuit 200 outputs the L level as the LFLG signal, and immediately after that, the data strobe signal verification circuit 15 outputs the read data reset signal DRST. Note that the read data reset signal DRST continues to be at the H level until the data strobe signal DQS is input.

  Next, the operation when the H pulse detection circuit 300 detects an abnormality in the input data strobe signal DQS will be described. Times T9 to T12 in FIG. 13 are timing charts when the H pulse detection circuit 300 detects an abnormality. Since the H level period of the data strobe signal DQS input at time T9 has a length according to the standard, the data strobe signal verification circuit 15 does not detect an abnormality. However, since the H level period of the data strobe signal DQS input at time T11 is half of the standard value, the H pulse detection circuit 300 detects an abnormality. As a result, the H pulse detection circuit 300 sets the HPFLG signal to the L level and outputs it. Thereafter, the data strobe signal verification circuit 15 outputs a read data reset signal DRST. The data strobe signal verification circuit 15 continues the H level of the read data reset signal DRST until the data strobe signal DQS is input at time T14.

  Next, an operation when the abnormality of the input data strobe signal DQS is detected by the L pulse detection circuit 400 will be described. Times T14 to T18 in FIG. 13 are timing charts when the L pulse detection circuit 400 detects an abnormality. Since the data strobe signal DQS input at time T14 is normal, the data strobe signal verification circuit 15 does not detect an abnormality. However, since the L level period of the data strobe signal DQS existing between time T15 and T16 is half of the standard value, the L pulse detection circuit 400 detects an abnormality. As a result, the L pulse detection circuit 400 sets the LPFLG signal to the L level and outputs it. Thereafter, the data strobe signal verification circuit 15 outputs a read data reset signal DRST. Note that the H level of the read data reset signal DRST is continued until the data strobe signal DQS is input.

  As described above, in the data strobe signal verification circuit 15, each detection circuit (the waveform missing detection circuit 100, the redundant waveform detection circuit 200, the H pulse detection circuit 300, the L pulse detection circuit 400) detects an abnormality in the data strobe signal DQS. To do. If an abnormality is detected, the read data taken up to that point is initialized. In addition, when an abnormal waveform other than the abnormal waveforms of the four data strobe signals DQS is present, an abnormal detection circuit is added to the data strobe signal verification circuit 15 to cope with different abnormal waveforms. It becomes possible.

  The memory interface control circuit 10 according to the present embodiment has a function of initializing data captured before the data strobe signal verification circuit 15 detects an abnormal data strobe signal DQS. Therefore, it is not necessary to mask the data strobe signal DQS, and there is no need to adjust the mask release timing in detail unlike the memory interface control circuit disclosed in Patent Document 1. Therefore, the memory interface control circuit disclosed in Patent Document 1 requires a gate scale of about several K to several tens of K, whereas the memory interface control circuit 10 according to this embodiment has a circuit scale of only a few tens of gates. Thus, it is possible to capture a normal data strobe signal DQS.

  It should be noted that the disclosures of the above patent documents and the like are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiment can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

1 System LSI
2 DDR SDRAM
10 memory interface control circuit 11, 12 IO buffer 13 variable delay circuit 14 FIFO circuit 15 data strobe signal verification circuit 100 waveform missing detection circuit 200 redundant waveform detection circuit 300 H pulse detection circuit 400 L pulse detection circuit 500 DQS counter AND01 to AND09 logic Product circuits FF01 to FF15 Flip-flops INV01 to INV08 Inverter NAND01 NAND circuit OR01 OR circuit XOR01 Exclusive OR circuit

Claims (10)

When a memory receives a data strobe signal for notifying the timing of data transfer, an abnormal waveform is detected in the data strobe signal, a data initialization signal is output, and an abnormal waveform is not detected in the data strobe signal Is a data strobe signal verification circuit that outputs a data capture enable signal;
When the data strobe signal is activated, a holding circuit that outputs and holds the data signal output from the memory, and initializes the held data when the data initialization signal is received;
The data output from the holding circuit is temporarily fetched. When the data initialization signal is received, the fetched data is initialized. When the data fetch permission signal is accepted, the fetched data is transferred to the outside. An output FIFO circuit;
A memory interface control circuit comprising: The holding circuit includes a first holding circuit that holds data transferred by the memory, and a second holding circuit that holds data different from the first holding circuit among data transferred by the memory. ,
The memory interface control circuit according to claim 1, wherein the FIFO circuit captures data output from the second holding circuit after capturing data output from the first holding circuit. The data strobe signal verification circuit includes an abnormal waveform detection circuit for verifying a waveform of the data strobe signal;
The number of changes in the logic level of the data strobe signal is counted, the data strobe signal changes the number of times corresponding to a predetermined read data length, and an abnormal waveform of the data strobe signal is detected in the abnormal waveform detection circuit. A DQS counter circuit that outputs the data capture enable signal when it is not detected;
A memory interface control circuit according to claim 1 or 2.   The memory interface control circuit according to claim 3, wherein the abnormal waveform detection circuit includes a waveform missing detection circuit that detects that the data strobe signal is not continuously input a specified number of times.   5. The redundant waveform detection circuit according to claim 3, wherein the abnormal waveform detection circuit includes a redundant waveform detection circuit that detects that a first logic level different from a logic level in a preamble period of the data strobe signal has continued for a period longer than a standard value. Memory interface control circuit.   6. The memory interface according to claim 3, wherein the abnormal waveform detection circuit includes a first pulse detection circuit that detects that a period of the first logic level of the data strobe signal is shorter than a standard value. Control circuit.   7. The abnormal pulse detection circuit includes a second pulse detection circuit that detects that a period of a second logic level that is the same as a logic level of a preamble period of the data strobe signal is shorter than a standard value. The memory interface control circuit according to claim 1.   The memory interface control circuit according to claim 1, wherein the memory is a DDR SDRAM.   9. The memory interface control circuit according to claim 8, wherein the DQS counter circuit outputs the data capture permission signal when the change in the logic level of the data strobe signal is counted a number of times corresponding to a burst length of a DDR SDRAM.   A semiconductor integrated circuit comprising the memory interface control circuit according to claim 1.

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