JP5441094B2 - Semiconductor substrate manufacturing method and semiconductor substrate - Google Patents

Description

  The present invention relates to a semiconductor substrate manufacturing method and a semiconductor substrate, and more particularly to a semiconductor substrate manufacturing method and a semiconductor substrate in which a group III-V semiconductor layer is directly bonded on a silicon carbide substrate.

  Group III-V semiconductors have some excellent characteristics compared to silicon, and are applied to optical devices, high-speed, high-power devices and the like by utilizing these characteristics. However, III-V semiconductors have poor thermal conductivity compared to silicon, for example, silicon has a thermal conductivity of 130 W / mK at room temperature, whereas gallium arsenide has a thermal conductivity of 45 W at room temperature. / MK, 68 W / mK for indium phosphide. For this reason, when a high output device is produced using a III-V group semiconductor, for example, improvement in heat dissipation characteristics becomes a problem.

In order to solve such problems, a III-V group semiconductor layer is epitaxially grown on a Si substrate or a sapphire substrate with good thermal conductivity, such as SOI, GaN on sapphire, and GaAs on on Si. Alternatively, a composite substrate is proposed in which a III-V group semiconductor substrate is bonded to a Si substrate or a sapphire substrate (see, for example, Patent Document 1).
JP 2007-300166 A

  However, for example, when a group III-V semiconductor layer is epitaxially grown on a Si substrate, it is difficult to form an epitaxial layer with good crystallinity because both have different lattice constants. For this reason, in the semiconductor element produced in the III-V group semiconductor layer, good element characteristics could not be obtained.

  In addition, when a III-V group semiconductor substrate is bonded onto a Si substrate, the thermal expansion coefficients of the two are different, and thus there is a problem that peeling or cracking occurs during the bonding process when the two are heat bonded. Further, when both are bonded at room temperature, there is a problem that the bonding strength is low and peeling occurs in the element manufacturing process and the like.

  Accordingly, an object of the present invention is to provide a semiconductor substrate in which a group III-V semiconductor layer such as gallium arsenide is formed in a good bonding state on a silicon carbide substrate having good thermal conductivity.

  The present invention is a method of manufacturing a semiconductor substrate having a group III-V semiconductor layer provided on a silicon carbide substrate, the steps of preparing a group III-V semiconductor substrate and a silicon carbide substrate each having a front surface and a back surface; A polishing step of attaching a back surface of the III-V semiconductor substrate to a polishing plate and polishing the III-V semiconductor substrate from the surface to make a thin layer; a surface of the III-V semiconductor substrate and a silicon carbide substrate; An application step of applying an organic solvent to at least one of the surfaces, an overlaying step of superimposing the surface of the III-V semiconductor substrate and the surface of the silicon carbide substrate to form a bonding surface, and a III-V semiconductor substrate and a silicon carbide substrate And heating in a state of being pressurized toward the bonding surface to form a group III-V semiconductor layer by directly bonding the group III-V semiconductor substrate to the surface of the silicon carbide substrate. Characteristic semiconductor It is a method of manufacturing a substrate.

The present invention is also a semiconductor substrate including a silicon carbide substrate and a group III-V semiconductor layer stacked on the silicon carbide substrate, wherein the group III-V semiconductor layer is directly bonded on the silicon carbide substrate. It is a semiconductor substrate characterized by being made.
Here, “directly bonded” means a bonded state in which no other bonding material such as an adhesive is used.

  Thus, according to the present invention, it is possible to provide a semiconductor substrate in which a group III-V semiconductor layer is formed on a silicon carbide substrate having good thermal conductivity without causing peeling or cracking.

  In addition, according to the present invention, the III-V group semiconductor layer is directly bonded onto the silicon carbide substrate without using a bonding material such as an adhesive, so that strong bonding can be obtained at low cost.

  Moreover, according to this invention, the semiconductor substrate which has the III-V group semiconductor layer excellent in thermal conductivity can be obtained.

Embodiment 1 FIG.
FIG. 1 is a perspective view of a semiconductor substrate according to a first embodiment of the present invention, the whole being represented by 100. FIG. The semiconductor substrate 100 has a structure in which a GaAs (gallium arsenide) layer 25 is bonded to a 6H—SiC (silicon carbide) substrate 10. The SiC substrate 10 and the GaAs layer 25 are directly bonded. That is, the SiC substrate 10 and the GaAs layer 25 are directly bonded without using another adhesive material such as an adhesive.

  Next, a method for manufacturing the semiconductor substrate 100 according to the first embodiment will be described with reference to FIG. This manufacturing method includes the following steps 1 to 4.

  Step 1: As shown in FIG. 2A, a GaAs substrate 20 that is a group III-V semiconductor is attached to a polishing plate 40 using a wax 30. The thickness of the GaAs substrate 20 is, for example, about 300 to 400 μm, and any of n-type, p-type, and i-type conductivity types may be used. As the polishing plate 30, for example, an alumina plate or a stainless steel (SUS) plate is used. The film thickness of the wax that joins the GaAs substrate 20 and the polishing plate 40 is preferably 10 μm or less.

  Step 2: As shown in FIG. 2B, the GaAs substrate 20 is polished. By the polishing process, the film thickness of the GaAs substrate 20 is reduced from, for example, 300 μm to 100 μm or less, preferably from 2 μm to 15 μm, and more preferably about 3 μm. The polishing step is performed so that, for example, polishing is performed using SiC abrasive grains and then chemical polishing is performed using an acid or alkali solution so that the polishing surface becomes a mirror surface. The polished surface (bonding surface) of the GaAs substrate 20 is preferably a Ga surface (Group III surface).

  Here, when the film thickness after polishing of the GaAs substrate 20 is examined, when the SiC substrate 10 and the GaAs substrate 20 are joined and a temperature change is applied, cracking or peeling occurs due to a difference in thermal expansion between the two substrates. Table 1 shows a comparison of the thermal expansion coefficient and the thermal expansion coefficient between SiC, Si, GaAs, and InP.

  In particular, when the thickness of the GaAs substrate 20 is thick, as shown in FIG. 3A (before the heating step) and FIG. 3B (after the heating step), the SiC substrate 10 is cracked or peeled between the SiC substrate 10 and the GaAs substrate 20. Occurs. FIG. 3B shows the SiC substrate 10 cracked in the heating process. It is considered that this is because the substrate is warped due to the difference in thermal expansion coefficient, and the SiC substrate 10 having low toughness is cracked by mechanical bending.

  In general, the amount of warpage of a laminated structure when a stress is applied to the laminated structure including a substrate (support substrate) and a thin layer (surface layer) provided on the surface is expressed by the following equation (1). (For example, described in JP-A-10-19893).

δ = 3σ · (1−v) · Tf · l ² / (Es · ts ² ) (1)

However,
δ: Warpage amount σ: Stress v: Substrate Poisson's ratio Tf: Surface layer thickness l: Substrate diameter Es: Young's modulus of substrate ts: Substrate thickness

At this time, the thermal stress generated in the joint portion of materials having different linear expansion coefficients is expressed by the following formula (2) (described in Japanese Patent Application Laid-Open No. 61-26227).
σ = (4 / ts) · Tf · Ef · ∫ ^Th _Tl (αs−αf) dT (2)
However,
σ: Thermal stress Ef: Young's modulus of the formation layer on the substrate αs: Linear expansion coefficient of the substrate αf: Linear expansion coefficient of the formation layer on the substrate Th: Temperature at which the substrate and the formation layer are joined Tl: Temperature after temperature change

Therefore, when the linear expansion coefficient is constant, the relationship between the film thickness Tf of the GaAs layer (surface layer) and the warpage δ of the composite structure is expressed by the following equation (3) from the equations (1) and (2). Is done.
δ =
{12 · Ef / Es · (αs−αf) · ΔT · (1-v) · l ² / Ts ³ } · Tf ²
.... (3)

  From equation (3), it can be seen that if the thickness of the substrate is constant, the amount of warpage δ of the composite structure is proportional to the square of the product of the film thickness Tf of the surface layer and the diameter l of the substrate.

The Young's modulus of SiC is 400 GPa, the Young's modulus of GaAs is 83 GPa, the difference in thermal expansion coefficient between them is 1.2 × 10 ⁻⁶ / deg, the Poisson's ratio of SiC is 0.45, and the aperture is 2 When a laminated structure using SiC having a thickness of 300 μm in inches, 3 inches, and 4 inches as a supporting substrate is cooled from 800 ° C. to 30 ° C., the thickness of the surface GaAs and the amount of warpage of the supporting substrate The relationship is as shown in FIG.

  In FIG. 4, the horizontal axis indicates the thickness of the surface GaAs layer, the vertical axis indicates the amount of warpage of the substrate, and the wafer diameters are 50.8 mm (2 inches), 76.2 mm (3 inches), and 100 mm (4 inches). ).

  Although it depends on the surface roughness and the end face shape, the SiC substrate is a double-sided polished product in a three-point support crack test, compared to a 2-inch 300 μm thick substrate whose end surface is ground with a # 600 diamond wheel. Some experimental results have been obtained that some cracks occur when a bending of about 20 μm is forcibly applied, and that all of them break when 100 μm is bent.

  In addition, for the same 300 μm thick substrate, the result is that the fracture start bending amount is almost proportional to the diameter of the substrate, and for the 3 inch substrate and the 4 inch substrate, the bending start bending amount is 30 μm, respectively. The amount of bending at which the total number was destroyed was 40 μm and 150 μm and 200 μm, respectively.

  From these results, the allowable value of the thickness of the GaAs layer bonded to the SiC substrate (the thickness at which destruction does not occur) is 28.8 μm or less for a 2-inch substrate, preferably 12.9 μm or less, preferably for a 3-inch substrate. 19.2 μm or less, preferably 8.6 μm or less, and for a 4-inch substrate, it is 14.6 μm or less, preferably 6.5 μm or less.

Step 3: The Si surface (bonding surface) side of the SiC substrate 10 is subjected to chemical mechanical polishing using colloidal silica. Polishing is preferably performed so that atomic steps are observed on the surface of SiC substrate 10. Subsequently, the polished surface is washed with an organic solvent such as isopropyl alcohol. On the other hand, the polished surface of the GaAs substrate 20 polished in step 2 is similarly cleaned using an organic solvent. As the organic solvent, in addition to isopropyl alcohol, alcohols such as methyl alcohol and ethyl alcohol and other organic solvents are used.
The surface of SiC substrate 10 can also be cleaned only without being polished.

  Next, as shown in FIG. 2C, bonding is performed through an organic solvent so that the polished surface of the GaAs substrate 20 and the polished surface of the SiC substrate 10 are in contact with each other. The contact surfaces of both substrates become the bonding surfaces. In this case, the polishing surface may be bonded with the organic solvent applied, or may be bonded after the polishing surface is washed with the organic solvent and then dried at room temperature, for example.

  The bonding of the GaAs substrate 20 and the SiC substrate 10 is preferably performed, for example, by pressing the polishing plate 40 and the SiC substrate 10 toward the bonding surface. In this case, in order to prevent the SiC substrate 10 and the GaAs substrate 20 from cracking in the pressurizing step, it is preferable to pressurize through a buffer material such as a graphite sheet. As the buffer material, for example, Nika film manufactured by Nippon Carbon Co., Ltd., permafoil or graph foil manufactured by Toyo Tanso Co., Ltd. is used. The bonded SiC substrate 10 and GaAs substrate 20 are not easily peeled off.

  Next, in a state where the SiC substrate 10 and the GaAs substrate 20 are bonded together, the substrate is heated in a heating furnace or the like. The heating condition is, for example, at a heating rate of 200 ° / hour or less, preferably 150 ° / hour, up to a holding temperature of about 800 ° C. and held at this temperature for at least 1 hour, preferably about 12 hours. . Thereafter, the temperature is lowered at a rate of 100 ° / hour or less, preferably 70 ° / hour.

  When the temperature is increased at a rate faster than 200 ° / hour, cracks occur in the substrate at a temperature of 350 ° C. or higher. On the other hand, when the temperature is raised at a rate of 200 ° / hour or less, particularly 150 ° / hour or less, the substrate does not crack.

  If the film thickness of the GaAs substrate 20 is 10 μm or less, cracks, cracks, peeling, etc. do not occur even if the temperature is raised and lowered at 500 ° / hour. Furthermore, when the film thickness of the GaAs substrate 20 is 3 μm or less, no cracks, cracks, etc. occur even when the temperature is raised and lowered at 1000 ° / hour.

  The holding temperature is at least higher than 500 ° C, preferably about 800 ° C. The holding temperature is preferably higher than the temperature of the semiconductor element manufacturing process performed later.

  The heating process may be performed in a state where the SiC substrate 10 and the GaAs substrate 20 are pressurized toward the bonding surface.

Further, for example, the temperature may be increased to 300 ° C. without applying pressure, and the pressure may be increased at 300 ° C. In this case, even if the SiC substrate 10 and the GaAs substrate 20 are peeled off at a part of the bonding surface, the SiC substrate 10 and the GaAs substrate 20 can be bonded again by applying pressure. At 300 ° C., the bonding surfaces can be bonded more easily than at room temperature. This is probably because the substrate is softened by heating.
On the other hand, when the substrate temperature reaches 350 ° C. or higher, it becomes difficult to re-join the peeled joint surfaces even if the substrate is pressurized. This is presumably because the substrate surface at the peeled portion is oxidized. Therefore, in order to rejoin the peeled joint surface, it is necessary to pressurize at 350 ° C. or less, preferably about 300 ° C.

  By performing such heating and pressurizing steps, the SiC substrate 10 and the GaAs substrate 20 can be directly bonded with sufficient strength.

  Step 4: As shown in FIG. 2D, the wax 30 is dissolved with an organic solvent or the like, and the polishing plate 40 and the GaAs substrate 20 are separated. Through the above steps, the semiconductor substrate 100 in which the GaAs layer 25 made of the thinned GaAs substrate 20 is laminated on the SiC substrate 10 can be obtained.

  Thus, by using the manufacturing method according to the present embodiment, it is possible to provide the semiconductor substrate 100 in which the GaAs layer 25 is formed on the SiC substrate 10 having good thermal conductivity without causing peeling or cracking. it can.

  Further, by using the manufacturing method according to the present embodiment, the GaAs layer 25 is directly bonded onto the SiC substrate 10 without using a bonding material such as an adhesive. Even if heated, the joint surface is difficult to peel off, and a strong joint can be obtained. In addition, the process of applying the adhesive material is unnecessary, and the semiconductor substrate can be obtained at low cost without complicating the manufacturing process.

  Moreover, in this Embodiment, the semiconductor substrate 100 which has the GaAs layer 25 excellent in thermal conductivity can be obtained. That is, the thermal conductivity of single crystal SiC is 490 Wm / K, which is twice that of polycrystalline SiC, three times that of Si, and ten times that of GaAs. By using a single crystal SiC substrate, it was overwhelmingly superior. A heat dissipation effect can be obtained.

  Further, since SiC has a wider transmission wavelength range than III-V group semiconductors such as Si and GaAs, an effect of thermal diffusion due to radiation can be expected. In particular, since the SiC substrate and the GaAs layer are directly joined without using an adhesive material such as metal or adhesive, good thermal diffusion can be obtained without being affected by the thermal resistance or contact thermal resistance of inclusions. Can do.

  In addition, single crystal SiC can be controlled in conductivity (P type, N type), and the semiconductor substrate according to the present embodiment using an SiC substrate has a horizontal single-sided electrode element structure and a vertical conductive element structure. Etc. can be applied. Furthermore, since either the P-type or the N-type can be selected to form a bonding surface, an element structure with the highest thermal diffusion efficiency can be selected.

Embodiment 2. FIG.
FIG. 5 is a perspective view of the semiconductor substrate according to the second embodiment of the present invention, the whole being represented by 200. FIG. In the semiconductor substrate 200, a GaAs layer 25 is stacked on the SiC substrate 20.
The SiC substrate 10 and the GaAs substrate 20 are bonded so that the (1-100) plane of the SiC substrate 10 and the (110) plane of the GaAs substrate constituting the GaAs layer 25 are parallel to each other. The two cleavage planes are preferably arranged in the same plane.

  The (1-100) plane of the SiC substrate 10 and the (110) plane of the GaAs substrate 20 may be determined by measuring with high accuracy using X-rays or the like, but in practice, it is preferable to use a cleavage plane. Both the (1-100) plane of the SiC substrate 10 and the (110) plane of the GaAs substrate 20 can be formed by cleaving with relatively high accuracy.

  The manufacturing process of the semiconductor substrate is substantially the same as the processes 1 to 4 described in the first embodiment. In the substrate bonding step shown in step 3, the two substrates are formed so that the (1-100) cleavage surface of the SiC substrate 10 and the (110) cleavage surface of the GaAs substrate 20 formed at the edge of the substrate are parallel to each other. Paste together. The cleavage plane is preferably arranged on the same plane. In this case, since it is difficult to align the position and direction in a high temperature state, it is preferable to perform the bonding while confirming that the two cleavage planes are parallel at room temperature.

  In order to arrange the (1-100) cleavage surface of the SiC substrate 10 and the (110) cleavage surface of the GaAs substrate 20 on the same plane, two cleavage surfaces are provided on a jig having a plane perpendicular to the surface of the SiC substrate 10. It is only necessary to place and paste them together. The accuracy for arranging the cleavage planes in parallel is preferably such that the parallelism can be confirmed when observed with an optical microscope or magnification projector having a magnification of 100 times.

  Thus, in the semiconductor substrate 200 bonded so that the cleavage planes of the SiC substrate 10 and the GaAs substrate 20 are parallel, and preferably the cleavage plane is the same plane, the (1-100) plane of the SiC substrate 10 and the GaAs substrate. The (110) plane of 20 (GaAs layer 25) can be simultaneously cleaved. This is useful when the semiconductor substrate 200 is used for manufacturing an optical semiconductor element and the element is divided or a cleavage plane is used as a laser resonance surface.

  Note that the (1-100) plane of the SiC substrate 10 and the (110) plane of the GaAs substrate 20 (GaAs layer 25) do not necessarily have to be in the same plane. If the line of intersection with the (1-100) surface of the substrate 10 and the bonding surface coincide with the (110 surface) of the GaAs substrate 20 (GaAs layer 25), the SiC substrate 10 and the GaAs substrate 20 are simultaneously cleaved. It becomes possible to do.

Embodiment 3 FIG.
In the above-described first and second embodiments, the heating process of the process 3 is performed using a heating furnace or an annealing furnace. May be heated.
When such laser heating is used, the bonding surfaces can be locally heated and bonded, and peeling of the bonding surfaces in the heating process can be reduced.

  In the first to third embodiments, the case where the GaAs substrate 20 is bonded onto the SiC substrate 10 has been described. However, the same applies to the case where other III-V group semiconductor substrates such as InP, GaN, and AlGaAs are used. Can be joined.

1 is a perspective view of a semiconductor substrate according to a first embodiment of the present invention. It is the schematic of the manufacturing process of the semiconductor substrate concerning Embodiment 1 of this invention. It is a GaAs / SiC substrate before a heating process. It is a GaAs / SiC substrate in which cracking occurred after the heating process. This is the relationship between the thickness of the GaAs layer and the warpage of the substrate. It is a perspective view of the semiconductor substrate concerning Embodiment 2 of this invention.

Explanation of symbols

  10 SiC substrate, 20 GaAs substrate, 25 GaAs layer, 30 wax, 40 polishing plate, 100, 200 semiconductor substrate.

Claims (11)

A method for manufacturing a semiconductor substrate in which a group III-V semiconductor layer is provided on a silicon carbide substrate,
Preparing a group III-V semiconductor substrate and a silicon carbide substrate each having a front surface and a back surface;
A polishing step of attaching the back surface of the III-V semiconductor substrate to a polishing plate, polishing the III-V semiconductor substrate from the surface, and reducing the film thickness to 30 μm or less ;
An application step of applying an organic solvent to at least one of the surface of the III-V group semiconductor substrate and the surface of the silicon carbide substrate;
An overlaying step of superposing the surface of the III-V semiconductor substrate and the surface of the silicon carbide substrate to form a bonding surface;
The III-V semiconductor substrate and the silicon carbide substrate are heated at a rate slower than 200 ° C./hour in a state of being pressurized toward the bonding surface, and the III-V substrate is formed on the surface of the silicon carbide substrate. And a heating step of directly joining the group semiconductor substrate to form a group III-V semiconductor layer.   The manufacturing method according to claim 1, wherein the polishing step is a step of reducing the film thickness of the group III-V semiconductor substrate to 2 μm or more and 15 μm or less.   The manufacturing method according to claim 1, wherein the coating step includes a step of drying the surface coated with the organic solvent at room temperature after coating the organic solvent.   The manufacturing method according to claim 1, wherein the heating step is a step of increasing the temperature at a rate slower than 150 ° C./hour.   The heating step is a step of pressurizing the III-V group semiconductor substrate and the silicon carbide substrate toward the bonding surface at a temperature of at least 300 ° C. and heating in the pressurized state. The manufacturing method according to claim 1.   The heating step includes a step of heating the III-V group semiconductor substrate and the silicon carbide substrate to a holding temperature lower than the melting point of the group III-V semiconductor at 300 ° C. or higher and holding at the holding temperature. The manufacturing method of Claim 1 characterized by the above-mentioned. The manufacturing method according to claim 6 , wherein the holding temperature is 800 ° C. The III-V group semiconductor substrate and the silicon carbide substrate each have a cleavage plane on a side wall surface between the front surface and the back surface,
The overlapping step is a step of overlapping the group III-V semiconductor substrate and the silicon carbide substrate such that the cleavage plane of the group III-V semiconductor substrate and the silicon carbide substrate are in the same plane. The manufacturing method according to claim 1. 9. The manufacturing method according to claim 8 , wherein the cleavage plane of the III-V group semiconductor substrate is a (110) plane, and the cleavage plane of the silicon carbide substrate is a (1-100) plane. The group III-V semiconductors, the production method according to any one of claims 1 to 9, characterized in that a gallium arsenide. A semiconductor substrate comprising a silicon carbide substrate and a group III-V semiconductor layer laminated on the silicon carbide substrate,
The semiconductor substrate manufactured by the manufacturing method according to claim 1 , wherein the group III-V semiconductor layer is directly bonded onto the silicon carbide substrate.